Communication synchronization method and device and computer storage medium

Abstract

The invention provides a communication synchronization method and device and a computer storage medium, and is applied to the technical field of communication, and the method comprises the steps: sequentially obtaining N power delay spectrums PDP of a target channel according to a measurement time interval; determining a first clock skew value according to the target relative time delay of the first PDP in the N PDPs, the target relative time delay of the Nth PDP and the time interval between the first PDP and the Nth PDP; according to the first clock deviation value, the relative time delay in each PDP is corrected; and controlling the transmitting end and the receiving end of the target channel to perform communication synchronization based on the corrected relative time delay. According to the method, the relative time delay in each acquired PDP is corrected based on the calculated first clock deviation value within a period of time, so that the accurate relative time delay is obtained, the communication synchronization of the transmitting end and the receiving end is realized, and the synchronization precision of the communication synchronization method is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a communication synchronization method, device and computer storage medium. Background Art

[0002] With the development of communication technology, terahertz communication is being used more and more widely. In the method of terahertz communication transmission and reception synchronization, a communication synchronization source is applied, that is, one (two in total) communication synchronization source that can send a trigger signal is introduced at the transmitting end and the receiving end of the communication system, but there will be a certain synchronization error after using two separate communication synchronization sources, so that the delay at the maximum power of the power delay profile (PDP) measured by the channel will decay uniformly over time, resulting in the relative delay measured to be offset, so the synchronization accuracy of the existing terahertz communication synchronization method is low. Summary of the invention

[0003] The embodiments of the present application provide a communication synchronization method, device and computer storage medium to solve the problem of low synchronization accuracy in existing communication synchronization methods.

[0004] In order to solve the above technical problems, this application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a communication synchronization method. The method includes:

[0006] According to the measurement time interval, N power delay profiles PDP of the target channel are obtained in sequence;

[0007] Determine a first clock deviation value according to a target relative delay of a first PDP and a target relative delay of an Nth PDP among the N PDPs, and a time interval between the first PDP and the Nth PDP;

[0008] Correcting the relative delay in each of the PDPs according to the first clock deviation value;

[0009] Based on the corrected relative delay, the transmitting end and the receiving end of the target channel are controlled to perform communication synchronization, where N is a positive integer greater than or equal to 2.

[0010] Optionally, sequentially acquiring N power delay profiles PDP of the target channel according to the measurement time interval includes:

[0011] Determine a first difference in sequence according to the measurement time interval, where the first difference is the difference between the target relative delays of the PDP in every two adjacent time intervals;

[0012] In a case where the number of target first difference values ​​is greater than a preset value, the N PDPs are determined, the target first difference value is a first difference value whose value is not equal to zero, and the preset value is determined according to the bandwidth.

[0013] Optionally, the target relative delay of each of the PDPs is a relative delay corresponding to the maximum power in its corresponding PDP.

[0014] Optionally, the target relative delay of each of the PDPs includes m sub-target relative delays, the m sub-target relative delays are relative delays corresponding to the m target powers in the PDP, and the m target powers are first m powers of all powers in the PDP arranged in descending order;

[0015] Determining a first clock deviation value according to a target relative delay of a first PDP among the N PDPs and the target relative delay of an N-th PDP, and a time interval between the first PDP and the N-th PDP, comprises:

[0016] Determine m second clock deviation values ​​accordingly according to the m sub-target relative delays of the first PDP among the N PDPs and the m sub-target relative delays of the N-th PDP, and the time interval between the first PDP and the N-th PDP;

[0017] An average value of the m second clock deviation values ​​is determined as the first clock deviation value.

[0018] Optionally, sequentially acquiring N power delay profiles PDP of the target channel according to the measurement time interval includes:

[0019] According to the measurement time interval, the transmission data of the target channel is subjected to cyclic correlation processing to obtain the N PDPs.

[0020] Optionally, before sequentially acquiring N power delay profiles PDP of the target channel in the measurement time sequence, the method further includes:

[0021] Set the period of the clock synchronization source trigger signal of the target channel.

[0022] In a second aspect, an embodiment of the present application further provides a communication synchronization device. The communication synchronization device includes:

[0023] A first acquisition module is used to sequentially acquire N power delay profiles PDP of the target channel according to the measurement time interval;

[0024] A first determining module, configured to determine a first clock deviation value according to a target relative delay of a first PDP and a target relative delay of an Nth PDP among the N PDPs, and a time interval between the first PDP and the Nth PDP;

[0025] A first correction module, configured to correct the relative delay in each of the PDPs according to the first clock deviation value;

[0026] The first control module is used to control the sending end and the receiving end of the target channel to perform communication synchronization based on the corrected relative delay, where N is a positive integer greater than or equal to 2.

[0027] Optionally, the first acquisition module includes:

[0028] A first determining unit, configured to determine a first difference in sequence according to a measurement time interval, wherein the first difference is a difference between the target relative delays of the PDP in every two adjacent time intervals;

[0029] The second determining unit is configured to determine the N PDPs when the number of target first difference values ​​is greater than a preset value, the target first difference value being a first difference value not equal to zero, and the preset value being determined according to bandwidth.

[0030] Optionally, the target relative delay of each of the PDPs is a relative delay corresponding to the maximum power in its corresponding PDP.

[0031] Optionally, the target relative delay of each of the PDPs includes m sub-target relative delays, the m sub-target relative delays are relative delays corresponding to the m target powers in the PDP, and the m target powers are first m powers of all powers in the PDP arranged in descending order;

[0032] The first determining module includes:

[0033] A third determining unit, configured to determine m second clock deviation values ​​correspondingly according to the m sub-target relative delays of the first PDP among the N PDPs and the m sub-target relative delays of the N-th PDP, and the time interval between the first PDP and the N-th PDP;

[0034] The fourth determining unit is used to determine an average value of the m second clock deviation values ​​as the first clock deviation value.

[0035] Optionally, the first acquisition module includes:

[0036] The first acquisition unit is used to perform cyclic correlation processing on the transmission data of the target channel according to the measurement time interval to obtain the N PDPs.

[0037] Optionally, the device further comprises:

[0038] The first setting module is used to set the period of the clock synchronization source trigger signal of the target channel.

[0039] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the above-mentioned communication synchronization method when executed by the processor.

[0040] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned communication synchronization method are implemented.

[0041] The communication synchronization method of the embodiment of the present application includes sequentially acquiring N power delay profiles PDP of the target channel according to the measurement time interval; determining the first clock deviation value according to the target relative delay of the first PDP and the target relative delay of the Nth PDP among the N PDPs, and the time interval between the first PDP and the Nth PDP; correcting the relative delay in each of the PDPs according to the first clock deviation value; and controlling the transmitting end and the receiving end of the target channel to perform communication synchronization based on the corrected relative delay, where N is a positive integer greater than or equal to 2. The method corrects the relative delay in each PDP acquired based on the calculated first clock deviation value within a period of time, thereby obtaining an accurate relative delay, realizing communication synchronization between the transmitting end and the receiving end, and improving the synchronization accuracy of the communication synchronization method. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0043] Figure 1 It is one of the PDP schematic diagrams of the communication synchronization method provided in the embodiment of the present application;

[0044] Figure 2 It is one of the overall delay fading diagrams of the communication synchronization method provided in the embodiment of the present application;

[0045] Figure 3 This is the second overall delay fading diagram of the communication synchronization method provided in the embodiment of the present application;

[0046] Figure 4 This is the second PDP schematic diagram of the communication synchronization method provided in the embodiment of the present application;

[0047] Figure 5 is a flow chart of a communication synchronization method provided by an embodiment of the present application;

[0048] Figure 6 This is the third PDP schematic diagram of the communication synchronization method provided in the embodiment of the present application;

[0049] Figure 7 This is the third overall delay fading diagram of the communication synchronization method provided in the embodiment of the present application;

[0050] Figure 8 is a structural diagram of a communication synchronization device provided by another embodiment of the present application;

[0051] Fig. 9 It is a structural diagram of an electronic device provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] In the existing communication method based on clock synchronization source, a clock synchronization source (two in total) that can trigger the signal is introduced at the transmitting end and the receiving end of the communication system. However, it is found in the communication that there will be a certain synchronization error after using two separate clock synchronization sources, which makes the delay at the maximum power of the power delay profile (PDP) measured by the channel evenly decay. Figure 1 The PDP diagram can reflect the delay of the multipath in the current channel and the power corresponding to the multipath. For a static channel, the delay of the multipath will not change with the length of the measurement time. Select the multipath with the largest power in the PDP for observation, where the maximum power point is the peak point as shown in the box. By recording the delay corresponding to the peak within a certain period of time, that is, the index of the horizontal axis, and plotting the delay value according to the observation time, the Figure 2 It can be found that the peak delay decays with time and is linearly distributed with time.

[0054] However, by zooming in on the overall fading graph, such as Figure 3 As shown in the figure, it can be seen that the decay rate of the peak delay is constant over a period of time. We use T as the time interval during which the peak delay remains constant.S In the case of terahertz communication, this offset is easy to be reflected on the PDP due to the large bandwidth, high sampling rate and large delay resolution of terahertz, causing errors. When the receiving end and the transmitting end are 6m apart, Figure 4 As shown in (a), when the bandwidth is 100MHz and the sampling rate is 100MHz, the delay resolution is 3m, and the corresponding delay X is 2. The PDP shows X as 2, and the small delay attenuation is not enough to be reflected in the PDP; Figure 4 As shown in (b), when the bandwidth is 1 GHz and the sampling rate is 1 GHz, when the delay resolution is 0.3 m, the corresponding delay X should be 20, but it is displayed as 19 in the PDP, which will show an error, making the relative delay inaccurate. Therefore, in the case of large-bandwidth terahertz communication, the embodiment of the present application provides a communication synchronization method. Figure 5 , Figure 5 is a flow chart of the communication synchronization method provided in an embodiment of the present application, such as Figure 5 As shown, the following steps are included:

[0055] Step 501: sequentially obtain N power delay profiles PDP of the target channel according to the measurement time interval;

[0056] In this step, the transmitting end of the target channel sends a pseudo-random sequence or other sequence with good autocorrelation, and the receiving end of the target channel collects the data transmitted by the target channel according to the measurement time interval. Each time the data is collected, a cyclic correlation process is performed to obtain a PDP. After the cyclic correlation process is performed on the collected data multiple times, N PDPs are obtained.

[0057] Step 502: Determine a first clock deviation value according to a target relative delay of a first PDP and a target relative delay of an Nth PDP among the N PDPs, and a time interval between the first PDP and the Nth PDP;

[0058] In this step, the target relative delay can be the relative delay corresponding to the maximum power in each PDP. In chronological order, according to the target relative delay τ1 of the first PDP and the target relative delay τ of the Nth PDP, N The difference is calculated by averaging the difference values ​​and the first clock deviation value is obtained in the N-1 time intervals. That is, the average delay attenuation value within a period of time. For example, 3600 PDPs are obtained, of which the first PDP is Figure 6 As shown in (a), the target relative delay τ1 = 958; the 3600th PDP is Figure 6 As shown in (b), the target relative delay τ 3600=1007, replace τ1=958 with τ 3600 =1007, and the difference is calculated by averaging the number of observed 3599 data time intervals to obtain the first clock deviation value.

[0059] Step 503: Correct the relative delay in each of the PDPs according to the first clock deviation value;

[0060] In this step, the PDP relative delay measured at the nth moment is taken as the standard relative delay of all PDPs, and the PDP at the mth moment is corrected (note that m here does not have to be less than the observation time T), and the shift amount is τ shift,m = Floor(Δτ·(mn)). The Floor(·) function indicates rounding down. This is because the calculated Δτ may not be an integer, and the resolution of the delay is limited by the sampling rate. Its accuracy may deviate from the calculation accuracy of Δτ, so it needs to be rounded down. For example, the 3600th PDP needs to perform τ shift,n = Floor (0.0136 · (3600-1)) = 49-bit correction, for the 4001th PDP, τ shift,n =Floor(0.0136·(4001-1))=54-bit correction, thereby obtaining the accurate relative delay.

[0061] Step 104: Based on the corrected relative delay, control the transmitting end and the receiving end of the target channel to perform communication synchronization, where N is a positive integer greater than or equal to 2.

[0062] In this step, communication synchronization between the transmitting end and the receiving end is achieved based on the accurate relative delay obtained after correction.

[0063] In the communication synchronization method of the embodiment of the present application, based on the calculated first clock deviation value within a period of time, the relative delay in each PDP is corrected to obtain an accurate relative delay, thereby achieving communication synchronization between the sending end and the receiving end, and improving the synchronization accuracy of the communication synchronization method.

[0064] Optionally, sequentially acquiring N power delay profiles PDP of the target channel according to the measurement time interval includes:

[0065] Determine a first difference in sequence according to the measurement time interval, where the first difference is the difference between the target relative delays of the PDP in every two adjacent time intervals;

[0066] In a case where the number of target first difference values ​​is greater than a preset value, the N PDPs are determined, the target first difference value is a first difference value whose value is not equal to zero, and the preset value is determined according to the bandwidth.

[0067] In the communication synchronization method of the embodiment of the present application, a target relative delay set S is defined. n , put the target relative delays in the first n PDPs measured into the set S n , S n ={τ1,τ2,...,τ n}, where τ n represents the target relative delay of the nth PDP. Through continuous measurement, the set S n Continuously expand the set S n Analysis can be performed to obtain T S , T S It is the maximum time period during which the relative delay remains constant.

[0068] First, for the set S n With S n+1 The target relative delay in is processed differentially to obtain the differential set, namely D n ={d1,d2,...,d n}={τ2-τ1,τ3-τ2,...,τ n+1 -τ n}, d n =τ n+1 -τ n , record D n The number of non-zero elements K and the serial number of non-zero elements in the set S. n With S n+1 The number of elements in D is also increasing. n The number of non-zero elements K in the matrix is ​​also increasing. When K = 2, the difference between the serial numbers of two non-zero elements is used to obtain the maximum time period T in which the relative delay remains unchanged. S , the results are as follows Figure 7 shown.

[0069] The measurement is continued until the number of target first differences is greater than a preset value, and then the measurement is stopped. The aforementioned target first differences are the non-zero elements in the difference set, and the number of target first differences is the number K of the aforementioned non-zero elements. It should be noted that T s Inversely proportional to the bandwidth, assuming that the bandwidths are B1 and B2 respectively, and the sampling is X times the bandwidth, the time periods for keeping the relative delay unchanged are T s 1. T s 2, then there exists: Therefore, the setting of the preset value here is related to the bandwidth. For example, when the bandwidth is greater than 50 MHz, the preset value can be set to 10; when the bandwidth is less than 50 MHz, the preset value can be set to 3. When the measurement is stopped, N PDPs can be obtained.

[0070] The communication synchronization method of the embodiment of the present application determines the number of target first differences according to the bandwidth, thereby determining the deadline for acquiring N PDPs, which is beneficial to shortening the time of the entire process of correcting the relative delay.

[0071] Optionally, the target relative delay of each of the PDPs is a relative delay corresponding to the maximum power in its corresponding PDP.

[0072] In the communication synchronization method of the embodiment of the present application, if the strongest path can be determined, that is, the paths corresponding to the maximum power of each PDP are the same, the target relative delay of each PDP is the relative delay corresponding to the maximum power in its corresponding PDP. Because the path corresponding to the maximum power is a direct path, it will not change basically. Correcting other relative delays in the PDP based on the first clock deviation value calculated from the relative delay corresponding to the maximum power in the PDP can improve the accuracy of the relative delay correction.

[0073] Optionally, the target relative delay of each of the PDPs includes m sub-target relative delays, the m sub-target relative delays are relative delays corresponding to the m target powers in the PDP, and the m target powers are first m powers of all powers in the PDP arranged in descending order;

[0074] Determining a first clock deviation value according to a target relative delay of a first PDP among the N PDPs and the target relative delay of an N-th PDP, and a time interval between the first PDP and the N-th PDP, comprises:

[0075] Determine m second clock deviation values ​​accordingly according to the m sub-target relative delays of the first PDP among the N PDPs and the m sub-target relative delays of the N-th PDP, and the time interval between the first PDP and the N-th PDP;

[0076] An average value of the m second clock deviation values ​​is determined as the first clock deviation value.

[0077] In the communication synchronization method of the embodiment of the present application, if the strongest path cannot be determined, that is, the paths with higher power in each PDP are different. For example, the first three powers in each PDP arranged in descending order can be taken, and the relative delays corresponding to the first three powers in each PDP are placed in the set In the embodiment, m second clock deviation values ​​are determined according to the determination method of the above embodiment. Then, an average value of the m second clock deviation values ​​is taken and determined as the first clock deviation value.

[0078] In the embodiment of the present application, when the strongest path cannot be determined, the first clock deviation value is determined according to the relative delays corresponding to the first m powers arranged in order from large to small in each PDP, which is conducive to improving the accuracy of subsequent relative delay correction.

[0079] Optionally, sequentially acquiring N power delay profiles PDP of the target channel according to the measurement time interval includes:

[0080] According to the measurement time interval, the transmission data of the target channel is subjected to cyclic correlation processing to obtain the N PDPs.

[0081] In the communication synchronization method of the embodiment of the present application, the generating end of the target channel sends a pseudo-random sequence or other sequence with good autocorrelation, and the receiving end of the target channel collects the data transmitted by the target channel according to the measurement time interval. Each time the data is collected, a cyclic correlation process is performed to obtain a PDP. After the multiple collected data are cyclically correlated, N PDPs are obtained. The embodiment of the present application obtains the PDP by performing cyclic correlation processing on the data obtained in each measurement, which is conducive to the subsequent determination of the target relative delay in the PDP.

[0082] Optionally, before sequentially acquiring N power delay profiles PDP of the target channel in the measurement time sequence, the method further includes:

[0083] Set the period of the clock synchronization source trigger signal of the target channel.

[0084] In the communication synchronization method of the embodiment of the present application, some preparatory work needs to be done before the measurement begins. For example, when setting up the transmitting end and the receiving end of the terahertz channel measurement system, first set the PN code, frequency, power, code rate, modulation mode, filter, and local oscillator signal frequency, power, etc. of the transmitted radio frequency signal, and at the same time set the clock synchronization source trigger signal period of the transmitting end and the receiving end respectively, so as to prepare for the subsequent acquisition of relatively synchronized data groups. Exemplarily, the specific steps can be as follows:

[0085] (1) The measurement modules are as follows: spectrum analyzer, vector network analyzer, up / down conversion local oscillator signal generator, amplifier, low noise amplifier, transceiver antenna, clock synchronization source. For the RF signal generator vector signal source at the transmitter, set the signal RF frequency to 6 GHz and the power to 0 dBm; the baseband signal uses the pseudo-random sequence PN9, the code rate is set to 600 MHz, BPSK modulation and raised cosine filtering with α of 1; set the frequency of the local oscillator signal in the local oscillator signal source at the transmitter and receiver to 21 GHz and the power to 10 dBm.

[0086] (2) The period of the impulse response sent by the clock synchronization source is set to a common multiple of 1 / 10 MHz of the baseband signal PN code period. The baseband signal period is 511 / 600 MHz. Therefore, the period of the impulse response sent by the clock synchronization source is set to 51.1 μs to ensure that the sampling rate is as fast as possible.

[0087] The embodiment of the present application sets the period of the clock synchronization source trigger signal of the target channel to facilitate the subsequent measurement process.

[0088] See also Figure 8 , Figure 8 It is a structural diagram of a communication synchronization device provided in yet another embodiment of the present application.

[0089] like Figure 8 As shown, the communication synchronization device 800 includes:

[0090] The first acquisition module 801 is used to sequentially acquire N power delay profiles PDP of the target channel according to the measurement time interval;

[0091] A first determining module 802 is used to determine a first clock deviation value according to a target relative delay of a first PDP and a target relative delay of an Nth PDP among the N PDPs, and a time interval between the first PDP and the Nth PDP;

[0092] A first correction module 803, configured to correct the relative delay in each of the PDPs according to the first clock deviation value;

[0093] The first control module is used to control the sending end and the receiving end of the target channel to perform communication synchronization based on the corrected relative delay, where N is a positive integer greater than or equal to 2.

[0094] Optionally, the first acquisition module includes:

[0095] A first determining unit, configured to determine a first difference in sequence according to a measurement time interval, wherein the first difference is a difference between the target relative delays of the PDP in every two adjacent time intervals;

[0096] The second determining unit is configured to determine the N PDPs when the number of target first difference values ​​is greater than a preset value, the target first difference value being a first difference value not equal to zero, and the preset value being determined according to bandwidth.

[0097] Optionally, the target relative delay of each of the PDPs is a relative delay corresponding to the maximum power in its corresponding PDP.

[0098] Optionally, the target relative delay of each of the PDPs includes m sub-target relative delays, the m sub-target relative delays are relative delays corresponding to the m target powers in the PDP, and the m target powers are first m powers of all powers in the PDP arranged in descending order;

[0099] The first determining module includes:

[0100] A third determining unit, configured to determine m second clock deviation values ​​correspondingly according to the m sub-target relative delays of the first PDP among the N PDPs and the m sub-target relative delays of the N-th PDP, and the time interval between the first PDP and the N-th PDP;

[0101] The fourth determining unit is used to determine an average value of the m second clock deviation values ​​as the first clock deviation value.

[0102] Optionally, the first acquisition module includes:

[0103] The first acquisition unit is used to perform cyclic correlation processing on the transmission data of the target channel according to the measurement time interval to obtain the N PDPs.

[0104] Optionally, the device further comprises:

[0105] The first setting module is used to set the period of the clock synchronization source trigger signal of the target channel.

[0106] See also Fig. 9 , Fig. 9 is a structural diagram of an electronic device provided in an embodiment of the present application, such as Fig. 9 As shown, the electronic device includes: a processor 900, a memory 920, and a program or instruction stored in the memory 920 and executable on the processor 900, the processor 900 is used to read the program or instruction in the memory 920; the electronic device also includes a bus interface and a transceiver 910.

[0107] The transceiver 910 is configured to receive and send data under the control of the processor 900 .

[0108] Among them, Fig. 9In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically linking various circuits of one or more processors represented by processor 900 and memory represented by memory 920. The bus architecture may also link various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface. The transceiver 910 may be a plurality of components, namely, a transmitter and a transceiver, providing a unit for communicating with various other devices on a transmission medium. The processor 900 is responsible for managing the bus architecture and general processing, and the memory 920 may store data used by the processor 900 when performing operations.

[0109] The processor 900 is used to read the program or instruction in the memory 920 and execute the following steps:

[0110] According to the measurement time interval, N power delay profiles PDP of the target channel are obtained in sequence;

[0111] Determine a first clock deviation value according to a target relative delay of a first PDP and a target relative delay of an Nth PDP among the N PDPs, and a time interval between the first PDP and the Nth PDP;

[0112] Correcting the relative delay in each of the PDPs according to the first clock deviation value;

[0113] Based on the corrected relative delay, the transmitting end and the receiving end of the target channel are controlled to perform communication synchronization, where N is a positive integer greater than or equal to 2.

[0114] Optionally, the processor 900 is configured to read a program or instruction in the memory 920 and perform the following steps:

[0115] Determine a first difference in sequence according to the measurement time interval, where the first difference is the difference between the target relative delays of the PDP in every two adjacent time intervals;

[0116] In a case where the number of target first difference values ​​is greater than a preset value, the N PDPs are determined, the target first difference value is a first difference value whose value is not equal to zero, and the preset value is determined according to the bandwidth.

[0117] Optionally, the target relative delay of each of the PDPs is a relative delay corresponding to the maximum power in its corresponding PDP.

[0118] Optionally, the target relative delay of each of the PDPs includes m sub-target relative delays, the m sub-target relative delays are relative delays corresponding to the m target powers in the PDP, and the m target powers are first m powers of all powers in the PDP arranged in descending order;

[0119] The processor 900 is used to read the program or instruction in the memory 920 and execute the following steps:

[0120] Determine m second clock deviation values ​​accordingly according to the m sub-target relative delays of the first PDP among the N PDPs and the m sub-target relative delays of the N-th PDP, and the time interval between the first PDP and the N-th PDP;

[0121] An average value of the m second clock deviation values ​​is determined as the first clock deviation value.

[0122] Optionally, the processor 900 is configured to read a program or instruction in the memory 920 and perform the following steps:

[0123] According to the measurement time interval, the transmission data of the target channel is subjected to cyclic correlation processing to obtain the N PDPs.

[0124] Optionally, the processor 900 is configured to read a program or instruction in the memory 920 and perform the following steps:

[0125] Set the period of the clock synchronization source trigger signal of the target channel.

[0126] The embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, each process of the above-mentioned communication synchronization method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0127] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0128] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0129] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A communication synchronization method, characterized in that: The method comprises: According to the measurement time interval, N power delay profiles PDP of the target channel are obtained in sequence; Determine a first clock deviation value according to a target relative delay of a first PDP and a target relative delay of an Nth PDP among the N PDPs, and a time interval between the first PDP and the Nth PDP; Correcting the relative delay in each of the PDPs according to the first clock deviation value; Based on the corrected relative delay, the transmitting end and the receiving end of the target channel are controlled to perform communication synchronization, where N is a positive integer greater than or equal to 2.

2. The communication synchronization method according to claim 1, characterized in that: The step of sequentially acquiring N power delay profiles PDP of the target channel according to the measurement time interval includes: Determine a first difference in sequence according to the measurement time interval, where the first difference is the difference between the target relative delays of the PDP in every two adjacent time intervals; In a case where the number of target first difference values ​​is greater than a preset value, the N PDPs are determined, the target first difference value is a first difference value whose value is not equal to zero, and the preset value is determined according to the bandwidth.

3. The communication synchronization method according to claim 1 or 2, characterized in that: The target relative delay of each of the PDPs is the relative delay corresponding to the maximum power in the corresponding PDP.

4. The communication synchronization method according to claim 1, characterized in that: The target relative delay of each of the PDPs includes m sub-target relative delays, where the m sub-target relative delays are relative delays corresponding to the m target powers in the PDP, and the m target powers are the first m powers of all powers in the PDP arranged in descending order; Determining a first clock deviation value according to a target relative delay of a first PDP among the N PDPs and the target relative delay of an N-th PDP, and a time interval between the first PDP and the N-th PDP, comprises: Determine m second clock deviation values ​​accordingly according to the m sub-target relative delays of the first PDP among the N PDPs and the m sub-target relative delays of the N-th PDP, and the time interval between the first PDP and the N-th PDP; An average value of the m second clock deviation values ​​is determined as the first clock deviation value.

5. The communication synchronization method according to claim 1, characterized in that: The step of sequentially acquiring N power delay profiles PDP of the target channel according to the measurement time interval includes: According to the measurement time interval, the transmission data of the target channel is subjected to cyclic correlation processing to obtain the N PDPs.

6. The communication synchronization method according to claim 5, characterized in that: Before sequentially acquiring N power delay profiles PDP of the target channel in the measurement time sequence, the method further includes: Set the period of the clock synchronization source trigger signal of the target channel.

7. A communication synchronization device, characterized in that: The device comprises: A first acquisition module is used to sequentially acquire N power delay profiles PDP of the target channel at equal measurement time intervals; A first determining module, configured to determine a first clock deviation value according to a target relative delay of a first PDP among the N PDPs and the target relative delay of an N-th PDP, and a time interval between the first PDP and the N-th PDP; A first correction module, configured to correct the relative delay in each of the PDPs according to the first clock deviation value; The first control module is used to control the sending end and the receiving end of the target channel to perform communication synchronization based on the corrected relative delay, where N is a positive integer greater than or equal to 2.

8. The communication device according to claim 7, characterized in that The first acquisition module includes: A first determining unit, configured to determine, in sequence, a plurality of first difference values ​​at equal measurement time intervals, wherein the first difference value is a difference between the target relative delays of the PDPs at every two adjacent time intervals; The second determining unit is configured to determine the N PDPs when the number of target first difference values ​​is greater than a preset value, the target first difference value being a first difference value not equal to zero, and the preset value being determined according to bandwidth.

9. An electronic device, characterized in that: The method comprises a processor, a memory and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the communication synchronization method according to any one of claims 1 to 6 when executed by the processor.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the communication synchronization method according to any one of claims 1 to 6 are implemented.

Images