Split packet router for time sensitive networking

Abstract

The invention discloses a split packet router for time sensitive networking. A network interface device for implementing scheduling for time-sensitive networking, comprising a network interface device comprising medium access control (MAC) circuitry, the MAC circuitry comprising: a priority router to parse packet payloads to determine priority values; determining a corresponding traffic category based on a priority value from the packet payload; and routing the packet payload to one of a plurality of traffic category-based packet buffers based on the traffic category; and a packet router to: retrieve packet payloads from a plurality of traffic category based packet buffers based on traffic categories; and placing the packet payload in a queue for direct memory access (DMA) circuitry to store the packet payload in the main memory.

Description

Technical Field

[0001] Embodiments described herein relate generally to data communication systems, and in particular, to split packet routers for time-sensitive networking. Background Art

[0002] Currently, network cards transmit and receive data packets. As network usage grows and additional systems come online to serve more data to more end users, data communication services need to become faster and more efficient. At the network card level, efficient and deterministic packet processing is needed to reduce latency and increase throughput in the network. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals with different letter suffixes may represent different instances of similar components. Some embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which:

[0004] Figure 1 is a schematic diagram illustrating an operating environment according to an embodiment;

[0005] Figure 2 is a schematic diagram illustrating a transmitter circuit system in a network interface device (NID) for time sensitive networking (TSN) according to an embodiment;

[0006] Figure 3 is a schematic diagram illustrating receiver circuitry in a NID for time-sensitive networking (TSN) according to an embodiment;

[0007] Figure 4 is a block diagram illustrating a mapping of a priority code point (PCP) to a traffic class (TC) according to an embodiment;

[0008] Figure 5 is a block diagram illustrating an Ethernet frame with a virtual local area network (VLAN) tag according to an embodiment;

[0009] Figure 6 is a flow chart illustrating a method for scheduling at a network interface device according to an embodiment;

[0010] Figure 7is a flow chart illustrating a method for processing a packet received at a network interface device according to an embodiment; and

[0011] Figure 8 is a block diagram illustrating an example machine on which any one or more of the techniques (eg, methodologies) discussed herein may be performed, according to an example embodiment. DETAILED DESCRIPTION

[0012] In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of some example embodiments. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without these specific details.

[0013] Emerging standards (e.g., IEEE standards) for deterministic networking, collectively referred to as time-sensitive networking (TSN), provide extremely precise data transmission across networks. As a result, embedded designs in the industrial and automotive sectors are increasingly integrating TSN controllers. The inevitable convergence of information technology (IT) and operational technology (OT), workload consolidation, and the need for seamless communication across many connected devices require the transmission of various types of data traffic through network interface controllers (NICs) without sacrificing the latency of hard real-time applications. As application logic is refactored into a network of interactive microservices, this latency sensitivity extends well beyond the latency sensitivity of hard real-time applications, because control of response time at the application level requires strict control of the accumulation of latency across each of the many network interactions between clients and servers.

[0014] To address these different types of traffic, the IEEE 802.1Q standard defines eight traffic classes with corresponding priorities. To support these eight traffic classes, the current generation of NICs implements eight transmit (Tx) queues and eight receive (Rx) queues, with each pair of transmit and receive queues dedicated to one of the eight traffic classes.

[0015] Although the PCP (priority code point) priority field defined in the Ethernet packet header is intended to provide QoS for data traffic of different criticalities, current TSN network controllers rarely use this field to route data within hardware. This is because many of today's network controller architectures focus on high data throughput rather than low latency. For example, some NICs simply add traffic categories on top of existing architectures without optimizing packet routing. In these unoptimized architectures, packets received from the network are first stored in huge buffers (usually hundreds of KB) in the order in which they are received. These packets are then retrieved from internal memory to be processed by a packet router (e.g., a flow director), which parses and filters the packets before redirecting them to different traffic class buffers. The main disadvantage of this type of architecture is that time-critical packets after the best-effort packets will be stored in memory behind the best-effort packets. Due to back pressure at the packet router, these time-critical packets will stay in memory for a long duration until the best-effort packets arriving before them are processed. With additional and more complex filtering and parsing rules, packet routers will experience higher back pressure, and time-critical packets will stay in memory for longer periods of time. This therefore adds considerable undesirable waiting time.

[0016] Alternatively, other types of architectures solve the latency problem by performing parsing and filtering as soon as they receive a packet before redirecting it to a traffic class packet buffer. Although this type of architecture solves the latency problem, it is not scalable for high-speed NICs (e.g., 10Gbps and above). This is because the packet router needs to parse and filter the packets within the inter-packet-gap (IPG) before the next packet arrives. The higher the speed, the smaller the IPG becomes. For example, at a speed of 10Gbps, the IPG is 9.6ns. The situation is even worse at a speed of 25Gbs, where the IPG is only 3.84ns. This is simply not enough time to perform packet parsing and filtering. To address this problem, some packet routers are designed for parallel parsing and filtering. However, the cost of this architecture is large area overhead and increased power requirements, which directly affects the silicon die area and cost of the product.

[0017] What is needed is a mechanism for handling time-sensitive networking in a high-throughput network. The systems and mechanisms described herein can reduce both latency and area overhead by splitting (e.g., separating, bifurcating) a packet router into two parts: a priority-based router and a receiving packet router. By splitting the operations of priority-based routing and writing packets to main memory, the split packet router is fast enough for high-speed NICs and minimizes die area usage and corresponding costs.

[0018] When receiving a packet, the priority-based router analyzes the priority field (e.g., PCP field) of the packet and quickly routes the packet to a receive buffer based on the traffic class based on the priority value. In the case of PCP, because the PCP field is 3 bits, the packet filtering portion of the packet router can be executed quickly and requires only a small area. Once the packet is routed to a different traffic class buffer based on the PCP field, the receiving packet router (e.g., the second portion of the packet router) routes the packet to the corresponding software queue using a dedicated DMA channel.

[0019] When transmitting a packet, the priority router analyzes the priority field of the outgoing packet before routing the packet to a transmit buffer based on the traffic class. The packet is retrieved from the transmit buffer based on the traffic class of the packet and the rules used by the scheduler when the packet is to be transmitted. The split architecture is scalable, incurs very low latency, and is highly area efficient. Additional details are provided below.

[0020] Figure 11 is a schematic diagram illustrating an operating environment 100 according to an embodiment. The operating environment 100 may be a server computer, a desktop computer, a laptop computer, a wearable device, a hybrid device, an onboard vehicle system, a network switch, a network router, or other computing devices capable of receiving and processing network traffic. The operating environment 100 includes a network interface device (NID) 102. The NID 102 includes electronic circuits for supporting a data link layer and a physical layer. Specifically, the NID 102 can receive data using an interconnect 104 or a radio 106. The interconnect 104 is arranged to receive signals through a physical medium, wherein the signals are arranged into some supported L2 framing, and interpret the incoming signal stream as a bit stream organized into L2 units referred to as "frames". For example, the interconnect 104 may be an Ethernet port. The radio 106 is capable of sending and receiving radio frequency (RF) data and is used to communicate via a wireless protocol (such as Wi-Fi, Bluetooth, Zigbee, cellular communications, etc.). Other types of communication interfaces may be supported by the NID 102, such as Gigabit Ethernet, Asynchronous Transfer Mode (ATM), High-Speed ​​Serial Interface (HSSI), Packet over SONET (POS), Fiber Distributed Data Interface (FDDI), Fiber to the Home (FTTH), etc. In these cases, appropriate ports may be provided in the NID architecture. The NID 102 may also take the form of an expansion card, and thus may be referred to as a network interface card or network interface controller (NIC).

[0021] NID 102 includes circuitry such as packet parser 108 and scheduler circuit 110. Packet parser 108 and scheduler circuit 110 may use NID memory 112 or main memory 114 for various operations such as queuing packets, saving state data, storing historical data, supporting neural networks, and so forth.

[0022] NID 102 also includes direct memory access (DMA) circuitry 122 and media access control (MAC) circuitry 124 (also referred to as media access control (MAC)). DMA circuitry 122 may be used to communicate with a plurality of NIDs through a structure (e.g., System-on-Chip Architecture On-Chip System Fabric, IOSF)) accesses the main memory 114. The DMA circuit 122 provides an interface to the MAC circuit 124 to prepare frames for transmission. The MAC circuit 124 is capable of performing: frame delimitation and identification; addressing of the destination station (both as an individual station and as a group of stations), transmission of source station addressing information, providing transparent data transmission of LLC PDU or equivalent information in the Ethernet sublayer, generally protecting against errors by generating and checking the frame check sequence, and controlling access to the physical transmission medium. In the case of Ethernet, the functions required by the MAC circuit 124 are: receiving / transmitting normal frames; providing half-duplex retransmission and backoff functions; attaching / checking FCS (frame check sequence); strengthening inter-frame gaps; discarding malformed frames; adding (tx) / removing (rx) preambles, SFD (start frame delimiter) and padding in front; and providing half-duplex compatibility: attaching (tx) / removing (rx) MAC addresses.

[0023] The packet parser 108, the scheduler circuit 110, the DMA circuit 122, and the MAC circuit 124 may be implemented using a CPU 111 on the NID, an ASIC, an FPGA, or other types of computing units on the NID 102. Further, portions of the packet parser 108, the scheduler circuit 110, the DMA circuit 122, and the MAC circuit 124 may be incorporated into a common circuit system on the same die, or virtualized. It should be understood that various arrangements of these components may be used depending on available power, area, design, or other factors.

[0024] Operating environment 100 also includes central processing unit (CPU) cores 150A, 150B, 150C, and 150N (collectively 150A-N). Figure 1 Four cores are shown in the figure, but it should be understood that there may be more or fewer cores in a particular CPU architecture. Additionally, there may be multiple CPUs that are logically grouped together to create a CPU complex. The mechanism described herein can be used for a single-core CPU, a multi-core CPU, or multiple CPUs that work in synergy.

[0025] NID 102 can communicate with cores 150A-N, main memory 114, or other parts of operating environment 100 via a suitable interconnect channel, such as a Peripheral Component Interconnect Express (PCIe) connector 116. PCIe connector 116 can have any width (e.g., x1, x4, x12, x16, or x32). Other interconnect channels include On-Chip System Fabric (IOSF), Quick Path Interconnect (QPI) and Primary Scalable Fabric (PSF).

[0026] The NID 102 may communicate with the cores 150A-N via a bus such as a PCIe bus. The PCIe client 115 controls the bus, and the PCIe connector 116 in the NID 102 provides an interface to the bus controller 118. The PCIe client 115 may perform additional functions, such as controlling the allocation of internal resources to virtual domains, supporting various forms of I / O virtualization (e.g., single root input / output virtualization (SR-IOV)), and other functions. The PCIe bus controller 118 may be incorporated into the same die that includes the cores 150A-N. The platform controller hub may include a PCIe bus controller 118, a memory management unit (MMU) 120, a serial ATA controller, a Universal Serial Bus (USB) controller, a clock controller, a trusted platform module (TPM), a serial-peripheral interface (SPI), and other components in the processor die.

[0027] Modern processor architectures have multiple levels in the cache hierarchy before entering main memory. In many designs, the outermost level of cache is shared by all cores on the same physical chip (e.g., in the same package), while the innermost cache level is per-core.

[0028] exist Figure 1In the example illustrated in , each CPU core 150A-N includes a corresponding L1 cache, which is separated into an L1 instruction cache 152A, 152B, 152C, 152N (collectively referred to as 152A-N) and an L1 data cache 154A, 154B, 154C, 154N (collectively referred to as 154A-N). The cores 150A-N also each include an L2 cache 156A, 156B, 156C, 156N (collectively referred to as 156A-N). The size of the L1 cache and the L2 cache varies depending on the processor design. For L1 cache size (e.g., 16KB instructions and 16KB data, or 32KB instructions and 32KB data), the conventional size ranges from 32KB to 64KB; and for L2 cache size, the conventional size ranges from 256KB to 512KB. The L3 cache size can vary from 8MB to 12MB, or larger.

[0029] Figure 2 2 is a schematic diagram illustrating a transmitter circuit system in a NID 200 for time-sensitive networking (TSN) according to an embodiment. The NID 200 includes a DMA engine 210 and a MAC circuit system 220 to transmit packets in a time-sensitive network environment. The DMA engine 210 is a multi-channel DMA engine and includes transmit (tx) channel registers 211. These registers 211 are used for data transmission from a main memory 260 (e.g., DDR) to packet buffers 240A-C in the network interface device 200. For example, the tx channel registers 211 may include a head pointer register and a tail pointer register required to access a transmit descriptor buffer for DMA operations. The MAC circuit system 220 includes a Precision Time Protocol (PTP) timer 221, a scheduler 222 based on a gate control list (GCL), a priority router 223, a packet processor 224, and a first-in-first-out (FIFO) queue 225.

[0030] For packet transmission, once the tail pointers of all available queues in the TRB (transmit ring buffer) (not shown) are advanced, the DMA engine 210 first obtains the descriptors of all available queues. A ring buffer is a data structure in the application or middleware memory space and is used to store packets of a data stream. Each ring buffer uses a head pointer and a tail pointer to indicate the beginning and end of a queue. Packets are copied from the ring buffer to the transmit packet buffer (for transmission) or from the receive packet buffer to the ring buffer (when receiving). All descriptors are usually obtained on the VC0 virtual channel. Channel-based routing can be used to map time-critical channels to virtual channel VC1. The channel-based router 270 is used to handle the communication between the DMA engine 210 and the memory 260 using the virtual channels (e.g., VC0 and VC1) established between the host and the NID 200.

[0031] The obtained descriptors are stored in a descriptor cache 230 based on traffic categories. The transmit descriptor cache 230 includes a separate queue for each channel. In an embodiment, 64 transmit channels and 64 receive channels are supported by the DMA engine 210. It should be understood that there may be more or fewer transmit channels and receive channels. Each DMA channel processes a circular buffer, and each circular buffer is mapped to one of eight traffic categories (TC0-TC7) defined by the user. The channel-based router 270 provides the channel number to the DMA engine 210 based on the virtual channel used. Descriptors are pre-fetched and stored in the descriptor cache 230 to reduce end-to-end transmit latency. Each channel has an associated descriptor pre-fetch cache 231A, 231B, ..., 231N (collectively referred to as 231A-N).

[0032] The DMA engine 210 parses the descriptor and retrieves the packet payload, which is stored in a first-in, first-out (FIFO) queue 225. The retrieved packet payload is parsed by the priority router 223 for field decoding. The priority router 223 may use any priority-based routing mechanism, such as a mechanism that examines the L2, L3, or L4 priority field and routes the packet based on the selected priority field. An example priority field includes a priority code point (PCP) field. Since the PCP field is only 3 bits, parsing the packet is straightforward. Based on this field encoding, the MAC circuit system 220 pushes the packet into the corresponding traffic class-based transmit packet buffer 240A-N. The encoding of the PCP to the traffic class is described in Figure 4 For example, a high priority express packet is pushed into the TC7 packet queue.

[0033] These packets will be fetched by the MAC scheduler 222 based on the start time of the packets. The GCL based scheduler 222 uses the gate control list 250 to determine from which ring buffer to read and transmit the packet. Because the ring buffers are associated with traffic classes, the GCL based scheduler 222 effectively schedules for each traffic class from several ring buffers.

[0034] There are several IEEE 802.1 standards that can be used as scheduling algorithms implemented in the MAC circuit system 220. For example, 802.1Qbv defines a gate-based schedule where specific queue packets are pre-fetched from the packet buffer and transmitted based on the gate opening time slot. The packet processor 224 is used for additional packet processing, such as (Virtual Local Area Network) VLAN tag insertion or replacement. This packet processing is done after reading the packet from the packet buffer 240A-N, thereby eliminating latency bubbles caused by back pressure of packet processing.

[0035] The PTP timer 221 is used to synchronize the clock for packet scheduling. The gating cycle is a period and is used to cycle through the active categories in the gating control list 250. The cycle time is the duration of the gating cycle. The cycle time used in these examples is 100 μs; however, it should be understood that any duration can be used as the cycle time.

[0036] Figure 3 3 is a schematic diagram illustrating a receiver circuit system in a NID 300 for time-sensitive networking (TSN) according to an embodiment. NID 300 can be merged with NID 200 so that the composite NID can provide both transmitter circuit system and receiver circuit system. Similar to NID 200, NID 300 includes a DMA engine 310 and a MAC circuit system 320 to receive packets in a time-sensitive network environment. DMA engine 310 is a multi-channel DMA engine and includes a receive (rx) channel register 311. MAC circuit system 320 includes a priority router 323, a packet router 324, a first-in-first-out (FIFO) queue 325, and a VLAN filter register 321.

[0037] The packet router 324 can be implemented as a packet distributor or a packet distribution mechanism that the network interface controller uses to route packets to and from a buffer in a host memory or a memory on the NIC. Thus, the packet router 324 can be implemented in various forms, such as a flow director, a receive side scaling (RSS) mechanism, or a receive packet steering (RPS) mechanism. RSS is a network driver technology that enables efficient distribution of network receive processing across multiple CPUs in a multiprocessor system. RPS uses a hashing algorithm based on the packet IP address and port to distribute received network traffic across multiple cores.

[0038] Packets received from the line are routed to priority-based packet buffers 340A, 340B, ..., 340N (collectively 340A-N) by priority router 323 using field encodings in the packets (e.g., PCP field encodings). The driver allocates a certain number of descriptors (not shown) in main memory 360 and stores each packet buffer address in a descriptor receive ring buffer (RRB). The start location address of the RBB, the length of the RBB, and the head and tail locations in the RBB are programmed in rx channel register 311. Using the RRB, NID 300 is able to know which descriptors are available, and thereby which packet buffers in main memory 360 pointed to by those descriptors are available.

[0039] When the software forwards the tail pointer, the MAC circuit system 320 pre-fetches available descriptors from the RRB. Based on strict priority, the MAC circuit system 320 pre-fetches rx packet descriptors. When the MAC circuit system 320 receives a packet, the MAC circuit system 320 (e.g., packet router 324) initiates a DMA write from the packet buffer 340A-N to the memory 360. These rx packet descriptors contain address pointers to the location where the received data will be written to the main memory 360. The MAC circuit system 320 utilizes the appropriate DMA channel based on the packet router rules and the VLAN filter register 321. These rules are defined using several exact or hash-based filters. For example, Figure 5 The VLAN filter register 560 illustrated in FIG. 5 provides rules whereby packets belonging to a specific VLAN tag (VID) are mapped to a specific DMA channel and thereby to an application queue in the memory 360 .

[0040] The traffic class based router 370 is used to handle the communication between the DMA engine 310 and the memory 360 using the virtual channels (eg, VC0 and VC1 ) established between the host and the NID 300 .

[0041] Because packets are routed using priority router 323 as soon as they arrive, critical packets are not delayed behind best-effort packets, thereby eliminating latency associated with waiting for packet processing used in previous systems. Figure 4 and Figure 5 The figure shows the packet format and PCP field priority defined by the 802.1Q standard. Receive (rx) register 311 stores the mapping of VLAN tags to specific channels for both transmit and receive operations. Similar parsing and filtering can be performed on L2, L3 or L4 headers.

[0042] Figure 4 4 is a block diagram illustrating a mapping 400 of priority code points (PCP) to traffic classes (TCs) according to an embodiment. In a VLAN tag, there is a 3-bit PCP field. With three bits, there are a total of eight possible values ​​for the PCP value. Each of these PCP values ​​(PCP0...PCP7) is mapped to a TC (TC0...TC8). A traffic type description is provided in mapping 400. It should be understood that this is an example of a PCP to TC mapping and that any other mapping may be used. Further, it should be understood that traffic types may be referred to as traffic classes and that their definitions and descriptions may be set by an administrator, a standards body, an organization, or by another entity.

[0043] Figure 5 1 is a block diagram illustrating an Ethernet frame 500 with a virtual local area network (VLAN) tag according to an embodiment. The Ethernet frame 500 includes a 7-byte (54-bit) preamble 502, a one-byte (8-bit) start frame delimiter (SFD) field 504, a 6-byte (48-bit) destination MAC address 506, a 6-byte (48-bit) source MAC address 508, a 4-byte (32-bit) VLAN tag 510, a 2-byte (16-bit) Ethernet type field 512, a variable length payload field 514, and a 4-byte (32-bit) cyclic redundancy check (CRC) field 516.

[0044] The payload field 514 is a variable length field having a minimum size governed by the minimum 64-byte Ethernet frame transmission size. Thus, with the header fields (preamble 502, SFD field 504, destination MAC address 506, and source MAC address 508) and CRC field 516, the minimum payload field size is 42 bytes when a single VLAN tag 510 is used. If nested VLAN tags 510 are used, the minimum payload field size is reduced by four bytes (32 bits). Similarly, the maximum payload field size is governed by the maximum allowable Ethernet frame transmission size.

[0045] The VLAN tag 510 includes a 2-byte (16-bit) tag protocol identifier (TPID) field 520 and a 2-byte (16-bit) tag control information (TCI) field 522. The TCI field 522 is further divided into subfields, including a 3-bit priority code point (PCP) field 530, a 1-bit discard eligibility indicator (DEI) field 532, and a 12-bit VLAN identifier (VID) field 534. The TPID field 520 is used to indicate that the frame has a VLAN tag. The PCP field 530 depicts the priority level of the frame. Different PCP values ​​are used to correspond to different traffic classes. The DEI field 532 is used to indicate frames that are eligible to be discarded when congestion exists. The VID field 534 is used to specify the VLAN to which the frame belongs. There may be certain VID values ​​that are reserved or have special meanings.

[0046] Figure 5 Another example of a PCP to traffic type mapping 540 is also illustrated. The mapping 540 is used to create control and VID fields in a transmit VLAN register 550 and a receive VLAN filter register 560. The transmit VLAN register 550 has a format of a 2-byte (16-bit) control field 552 and a 2-byte (16-bit) VID field 554. The transmit VLAN register 550 is used to insert a VLAN tag into a transmit packet. The VID field 554 in the transmit VLAN register 550 may include the same information as the VID field 534 in the 802.1Q tag 510. In an embodiment, the 16-bit control field 552 is used to indicate an internal VLAN or an external VLAN, whether to add a VLAN, whether to overwrite an existing VLAN, or other options.

[0047] The receive VLAN filter register 560 has a format of a 10-bit control field 562, a 6-bit channel number field 564, and a 2-byte (16-bit) VID field 566. The receive VLAN filter register 560 stores rules and is used to route packets to specific DMA channels within the same traffic category. There may be multiple DMA channels mapped to the same traffic category. In other words, there may be multiple data streams that can be mapped to the same traffic category. In an embodiment, the 6-bit channel number field 564 of the receive VLAN filter register 560 is used to guide the received packet to a specific DMA channel. In an embodiment, there are 64 DMA receive channels, and thus, 6 bits are used to specify a specific one of the 64 channels. The 10-bit control field 562 is used for internal VLAN or external VLAN filtering, removing VLAN tags from received data, or other options. The VID field 566 may include the same information as the VID field 534 in the 802.1Q tag 510.

[0048] Figure 6 is a flow chart illustrating a method 600 for scheduling at a network interface device according to an embodiment. At 602, the method 600 includes reading a packet descriptor from a descriptor cache.

[0049] At 604, method 600 includes reading a packet payload corresponding to the packet descriptor from main memory.

[0050] At 606, method 600 includes parsing the packet payload to determine a priority value. In an embodiment, parsing the packet payload to determine the priority value includes decoding a 3-bit priority code point (PCP) field in a virtual local area network (VLAN) tag. In a further embodiment, the VLAN tag is an IEEE 802.1Q tag.

[0051] At 608, method 600 includes determining a corresponding traffic class based on a priority value from the packet payload. In an embodiment, determining a corresponding traffic class based on a priority value from the packet payload includes performing a lookup in a PCP to traffic class mapping.

[0052] At 610, at 608, method 600 includes routing the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class.

[0053] At 612, method 600 includes scheduling packets from a plurality of traffic class-based packet buffers for transmission.

[0054] In an embodiment, the method 600 includes: modifying the packet payload prior to transmission. In another embodiment, the method 600 includes: inserting a VLAN tag into a packet header of the packet payload. In another embodiment, the method 600 includes: inserting an IEEE 802.1Q tag into a packet header of the packet payload. In another embodiment, the method 600 includes: replacing an existing VLAN tag in a packet header of the packet payload with a different VLAN tag.

[0055] Figure 7 is a flow chart illustrating a method 700 for processing a packet received at a network interface device, according to an embodiment. At 702, the method 700 includes parsing a packet payload to determine a priority value.

[0056] In an embodiment, parsing the packet payload to determine the priority value comprises decoding a 3-bit Priority Code Point (PCP) field in a Virtual Local Area Network (VLAN) tag. In a further embodiment, the VLAN tag is an IEEE 802.1Q tag.

[0057] At 704, method 700 includes determining a corresponding traffic class based on a priority value from a packet payload. In an embodiment, determining a corresponding traffic class based on a priority value from a packet payload includes performing a lookup in a PCP to traffic class mapping.

[0058] At 706, method 700 includes routing the packet payload to a packet buffer of a plurality of traffic class-based packet buffers based on the traffic class.

[0059] At 708, method 700 includes retrieving packet payloads from a plurality of traffic class-based packet buffers based on the traffic class. In an embodiment, retrieving packet payloads from a plurality of traffic class-based packet buffers based on the traffic class includes retrieving packet payloads in descending order of priority.

[0060] At 710, method 700 includes placing the packet payload in a queue for direct memory access (DMA) circuitry to store the packet payload in main memory. In an embodiment, storing the packet payload in main memory includes transmitting high priority packets through a different channel than lower priority packets using a channel-based router. Hardware Platform

[0061] The embodiments may be implemented in one or a combination of hardware, firmware, and software. The embodiments may also be implemented as instructions stored on a machine-readable storage device, which may be read and executed by at least one processor to perform the operations described herein. The machine-readable storage device may include any non-transitory mechanism for storing information in a form that can be read by a machine (e.g., a computer). For example, a machine-readable storage device may include a read-only memory (ROM), a random-access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory device, and other storage devices and media.

[0062] The processor subsystem may be used to execute instructions on a machine-readable medium. The processor subsystem may include one or more processors, each processor having one or more cores. Additionally, the processor subsystem may be disposed on one or more physical devices. The processor subsystem may include one or more special-purpose processors, such as a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), or a fixed-function processor.

[0063] Examples as described herein may include logic or several components, modules or mechanisms, or may operate on logic or several components, modules or mechanisms. Each module may be hardware, software or firmware that is communicatively coupled to one or more processors to implement the operations described herein. Each module may be a hardware module, and thus, the module may be considered as a tangible entity that can perform a specified operation and may be configured or arranged in a certain manner. In an example, a circuit (e.g., internally or relative to an external entity such as other circuits) may be arranged as a module in a specified manner. In an example, all or part of one or more computer systems (e.g., independent client or server computer systems) or one or more hardware processors may be configured by firmware or software (e.g., instructions, application parts, or applications) to operate a module for performing a specified operation. In an example, the software may reside on a machine-readable medium. In an example, the software, when executed by the underlying hardware of the module, causes the hardware to perform a specified operation. Thus, the term hardware module is understood to encompass a tangible entity that is physically constructed, specifically configured (e.g., hardwired), or temporarily (e.g., transiently) configured (e.g., programmed) to operate in a specified manner or to perform part or all of any operation described herein. Considering examples where modules are temporarily configured, each of these modules does not need to be instantiated at any one time. For example, in the case where a module includes a general-purpose hardware processor configured using software, the general-purpose hardware processor can be configured as corresponding different modules at different times. The software can configure the hardware processor accordingly, for example, so as to construct a specific module at one time instance and construct different modules at different time instances. Modules can also be software or firmware modules that operate to perform the methods described herein.

[0064] As used in this document, circuitry or circuits may include, alone or in any combination, for example: hardwired circuitry; programmable circuitry, such as a computer processor including one or more separate instruction processing cores; state machine circuitry; and / or firmware storing instructions executed by the programmable circuitry. The circuits, circuitry, or modules may be embodied together or alone as circuitry that forms part of a larger system, such as an integrated circuit (IC), a system on-chip (SoC), a desktop computer, a laptop computer, a tablet computer, a server, a smart phone, etc.

[0065] Figure 8It is a block diagram illustrating a machine in the example form of a computer system 800 according to an example embodiment, in which a set of instructions or a sequence of instructions can be executed to make the machine perform any of the methods discussed herein. In an alternative embodiment, the machine operates as a standalone device, or can be connected (e.g., networked) to other machines. In a networked deployment, the machine can operate as a server or client machine in a server-client network environment, or it can act as a peer in a peer (or distributed) network environment. The machine can be a wearable device, a personal computer (personal computer, PC), a tablet PC, a hybrid tablet, a personal digital assistant (personal digital assistant, PDA), a mobile phone, or any machine capable of executing instructions (sequentially or otherwise) specifying actions to be taken by the machine. In addition, although only a single machine is shown, the term "machine" should also include any collection of machines that execute a set (or multiple sets) of instructions individually or collectively to perform any one or more of the methods discussed herein. Similarly, the term "processor-based system" shall be taken to include any collection of one or more machines controlled or operated by a processor (e.g., a computer) to individually or jointly execute instructions to perform any one or more of the methodologies discussed herein.

[0066] The example computer system 800 includes at least one processor 802 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or both, a processor core, a computing node, etc.), at least one coprocessor 803 (e.g., an FPGA, a dedicated GPU, an ASIC, etc.), a main memory 803, and a static memory 806, which communicate with each other via a link 808 (e.g., a bus). The computer system 800 may further include a video display unit 810, an alphanumeric input device 812 (e.g., a keyboard), and a user interface (UI) navigation device 814 (e.g., a mouse). In one embodiment, the video display unit 810, the input device 812, and the UI navigation device 814 are incorporated into a touch screen display. The computer system 800 may additionally include a storage device 816 (e.g., a drive unit), a signal generating device 818 (e.g., a speaker), a network interface device 820, and one or more sensors (not shown), such as a global positioning system (GPS) sensor, a compass, an accelerometer, a gyroscope, a magnetometer, or other sensors.

[0067] The storage device 816 includes a machine-readable medium 822 having stored thereon one or more sets of data structures and instructions 824 (e.g., software) that embody or are utilized by any one or more of the methodologies or functions described herein. The instructions 824 may also reside, completely or at least partially, within the main memory 804, within the static memory 806, and / or within the processor 802 during execution of the instructions 824 by the computer system 800, wherein the main memory 804, the static memory 806, and the processor 802 also constitute machine-readable media.

[0068] Although the machine-readable medium 822 is illustrated as a single medium in the example embodiment, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) storing one or more instructions 824. The term "machine-readable medium" should also be considered to include any tangible medium that is capable of storing, encoding, or carrying instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure, or the tangible medium is capable of storing, encoding, or carrying data structures utilized by or associated with such instructions. The term "machine-readable medium" should accordingly be considered to include, but is not limited to, solid-state memory and optical and magnetic media. Specific examples of machine-readable media include non-volatile memory, including, by way of example, but not limited to: semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0069] The instructions 820 may be further transmitted or received over a communication network 826 using a transmission medium, via a network interface device 824, using any of a number of well-known transmission protocols (e.g., HTTP). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), the Internet, a mobile phone network, a plain old telephone (POTS) network, and a wireless data network (e.g., Bluetooth, Wi-Fi, 3G and 4G LTE / LTE-A or WiMAX networks). The term "transmission medium" shall be deemed to include any intangible medium that is capable of storing, encoding or carrying instructions to be executed by a machine, and includes digital or analog communication signals or other intangible media used to facilitate communication of such software.

[0070] The network interface device 820 may be configured or programmed to implement the methods described herein. Specifically, the network interface device 820 may provide various aspects of packet inspection, aggregation, queuing, and processing. The network interface device 820 may also be configured or programmed to communicate with a memory management unit (MMU), a processor 802, a main memory 804, a static memory 806, or other components of the system 800 via a link 808. The network interface device 820 may query various components of the system 800 or otherwise provide interfaces to various components of the system 800 to inspect cache memory; trigger or stop the operation of a virtual machine, a process, or other processing element; or otherwise interact with various computing units or processing elements in or outside the system 800. Additional notes and examples:

[0071] Example 1 is a network interface device, which includes: a media access control (MAC) circuit system, which includes: a priority router, which is used to: parse a packet payload to determine a priority value; determine a corresponding traffic class based on the priority value from the packet payload; and route the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class; and a packet router, which is used to: retrieve the packet payload from the plurality of traffic class-based packet buffers based on the traffic class; and place the packet payload in a queue for a direct memory access (DMA) circuit system to store the packet payload in a main memory.

[0072] In Example 2, the subject matter of Example 1 includes, wherein to parse the packet payload to determine the priority value, the priority router is to decode a 3-bit priority code point (PCP) field in a virtual local area network (VLAN) tag.

[0073] In Example 3, the subject matter of Example 2 includes, wherein the VLAN tag is an IEEE 802.1Q tag.

[0074] In Example 4, the subject matter of Examples 1-3 includes, wherein to determine the corresponding traffic class based on the priority value from the packet payload, the priority router is to perform a lookup in the PCP to traffic class mapping.

[0075] In Example 5, the subject matter of Examples 1-4 includes, wherein to retrieve the packet payloads from the plurality of traffic class-based packet buffers based on the traffic class, the packet router is to retrieve the packet payloads in descending order of priority.

[0076] In Example 6, the subject matter of Examples 1-5 includes where, to store the packet payload in the main memory, the DMA circuitry is to use a channel-based router to transmit high priority packets through a different channel than lower priority packets.

[0077] Example 7 is a method for operating a network interface device, the method comprising: parsing a packet payload to determine a priority value; determining a corresponding traffic class based on the priority value from the packet payload; routing the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class; retrieving the packet payload from the plurality of traffic class-based packet buffers based on the traffic class; and placing the packet payload in a queue for a direct memory access (DMA) circuit system to store the packet payload in a main memory.

[0078] In Example 8, the subject matter of Example 7 includes, wherein parsing the packet payload to determine the priority value includes decoding a 3-bit priority code point (PCP) field in a virtual local area network (VLAN) tag.

[0079] In Example 9, the subject matter of Example 8 includes, wherein the VLAN tag is an IEEE 802.1Q tag.

[0080] In Example 10, the subject matter of Examples 7-9 includes, wherein determining the corresponding traffic class based on the priority value from the packet payload includes performing a lookup in a priority code point (PCP) to traffic class mapping.

[0081] In Example 11, the subject matter of Examples 7-10 includes, wherein retrieving the packet payloads from the plurality of traffic class-based packet buffers based on the traffic class includes retrieving the packet payloads in descending order of priority.

[0082] In Example 12, the subject matter of Examples 7-11 includes, wherein storing the packet payload in the main memory comprises: using a channel-based router to transmit the high priority packets through a different channel than lower priority packets.

[0083] Example 13 is at least one machine-readable medium, which includes instructions that, when executed by a network interface device, cause the network interface device to perform operations including: parsing a packet payload to determine a priority value; determining a corresponding traffic class based on the priority value from the packet payload; routing the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class; retrieving the packet payload from a plurality of traffic class-based packet buffers based on the traffic class; and placing the packet payload in a queue for a direct memory access (DMA) circuit system to store the packet payload in a main memory.

[0084] In Example 14, the subject matter of Example 13 includes, wherein parsing the packet payload to determine the priority value includes decoding a 3-bit priority code point (PCP) field in a virtual local area network (VLAN) tag.

[0085] In Example 15, the subject matter of Example 14 includes, wherein the VLAN tag is an IEEE 802.1Q tag.

[0086] In Example 16, the subject matter of Examples 13-15 includes, wherein the instructions for determining the corresponding traffic class based on the priority value from the packet payload include instructions for performing a lookup in a priority code point (PCP) to traffic class mapping.

[0087] In Example 17, the subject matter of Examples 13-16 includes, wherein the instructions for retrieving packet payloads from a plurality of traffic class-based packet buffers based on traffic class include instructions for retrieving the packet payloads in descending order of priority.

[0088] In Example 18, the subject matter of Examples 13-17 includes, wherein the instructions for storing the packet payload in the main memory include instructions for using a tunnel-based router to transmit high priority packets through a different tunnel than lower priority packets.

[0089] Example 19 is a network interface device, which includes: a direct memory access (DMA) circuit system, which is used to read a packet descriptor from a descriptor cache and read a packet payload corresponding to the packet descriptor from a main memory; and a media access control (MAC) circuit system, which includes: a priority router, which is used to: parse the packet payload to determine a priority value; determine a corresponding traffic class based on the priority value from the packet payload; and route the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class; and a scheduling circuit system, which is used to schedule packets from a plurality of traffic class-based packet buffers for transmission.

[0090] In Example 20, the subject matter of Example 19 includes, wherein to parse the packet payload to determine the priority value, the priority router is to decode a 3-bit priority code point (PCP) field in a virtual local area network (VLAN) tag.

[0091] In Example 21, the subject matter of Example 20 includes, wherein the VLAN tag is an IEEE 802.1Q tag.

[0092] In Example 22, the subject matter of Examples 19-21 includes, wherein to determine the corresponding traffic class based on the priority value from the packet payload, the priority router is to perform a lookup in a priority code point (PCP) to traffic class mapping.

[0093] In Example 23, the subject matter of Examples 19-22 includes, wherein the network interface device further comprises a packet processor to modify the packet payload prior to transmission.

[0094] In Example 24, the subject matter of Example 23 includes, wherein the packet processor is to insert the VLAN tag into a packet header of the packet payload.

[0095] In Example 25, the subject matter of Examples 23-24 includes, wherein the packet processor is to insert the IEEE 802.1Q tag into a packet header of the packet payload.

[0096] In Example 26, the subject matter of Examples 23-25 ​​includes, wherein the packet processor is to replace an existing VLAN tag in a packet header of the packet payload with a different VLAN tag.

[0097] Example 27 is a method for operating a network interface device, the method comprising: reading a packet descriptor from a descriptor cache; reading a packet payload corresponding to the packet descriptor from a main memory; parsing the packet payload to determine a priority value; determining a corresponding traffic class based on the priority value from the packet payload; routing the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class; and scheduling packets from the plurality of traffic class-based packet buffers for transmission.

[0098] In Example 28, the subject matter of Example 27 includes, wherein parsing the packet payload to determine the priority value includes: decoding a 3-bit priority code point (PCP) field in a virtual local area network (VLAN) tag.

[0099] In Example 29, the subject matter of Example 28 includes, wherein the VLAN tag is an IEEE 802.1Q tag.

[0100] In Example 30, the subject matter of Examples 27-29 includes, wherein determining the corresponding traffic class based on the priority value from the packet payload includes performing a lookup in a priority code point (PCP) to traffic class mapping.

[0101] In Example 31, the subject matter of Examples 27-30 includes modifying the packet payload prior to transmission.

[0102] In Example 32, the subject matter of Example 31 includes inserting the VLAN tag into a packet header of the packet payload.

[0103] In Example 33, the subject matter of Examples 31-32 includes inserting an IEEE 802.1Q tag into a packet header of a packet payload.

[0104] In Example 34, the subject matter of Examples 31-33 includes replacing an existing VLAN tag in a packet header of a packet payload with a different VLAN tag.

[0105] Example 35 is at least one machine-readable medium, which includes instructions that, when executed by a network interface device, cause the network interface device to perform operations comprising: reading a packet descriptor from a descriptor cache; reading a packet payload corresponding to the packet descriptor from a main memory; parsing the packet payload to determine a priority value; determining a corresponding traffic class based on the priority value from the packet payload; routing the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class; and scheduling packets from the plurality of traffic class-based packet buffers for transmission.

[0106] In Example 36, the subject matter of Example 35 includes, wherein the instructions for parsing the packet payload to determine the priority value include: instructions for decoding a 3-bit priority code point (PCP) field in a virtual local area network (VLAN) tag.

[0107] In Example 37, the subject matter of Example 36 includes, wherein the VLAN tag is an IEEE 802.1Q tag.

[0108] In Example 38, the subject matter of Examples 35-37 includes, wherein the instructions for determining the corresponding traffic class based on the priority value from the packet payload include instructions for performing a lookup in a priority code point (PCP) to traffic class mapping.

[0109] In Example 39, the subject matter of Examples 35-38 includes instructions for modifying a packet payload prior to transmission.

[0110] In Example 40, the subject matter of Example 39 includes instructions for inserting a VLAN tag into a packet header of a packet payload.

[0111] In Example 41, the subject matter of Examples 39-40 comprises instructions for inserting an IEEE 802.1Q tag into a packet header of a packet payload.

[0112] In Example 42, the subject matter of Examples 39-41 includes instructions for replacing an existing VLAN tag in a packet header of a packet payload with a different VLAN tag.

[0113] Example 43 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-42.

[0114] Example 44 is an apparatus comprising means for implementing any of Examples 1-42.

[0115] Example 45 is a system for implementing any of Examples 1-42.

[0116] Example 46 is a method for implementing any of Examples 1-42.

[0117] Example 43 is an edge computing system comprising a plurality of edge computing nodes configured with the subject matter of any one of Examples 1-42.

[0118] Example 44 is an edge computing node capable of operating in an edge computing system, the edge computing node comprising a processing circuit system configured to implement any of Examples 1-42.

[0119] Example 45 is an edge computing node capable of operating as a server in an edge computing system, the edge computing node being configured to perform any one of Examples 1-42.

[0120] Example 46 is an edge computing node capable of operating as a client in an edge computing system, the edge computing node being configured to perform any one of Examples 1-42.

[0121] Example 47 is an edge computing node that can operate as an aggregation node, a network hub node, a gateway node, or a core data processing node in a layer of an edge computing network, and the edge computing node is configured to perform any one of Examples 1-42.

[0122] Example 48 is an edge computing network comprising networking components and processing components configured to provide or operate a communication network to enable the edge computing system to implement any of Examples 1-42.

[0123] Example 49 is an access point comprising networking components and processing components configured to provide or operate a communication network to enable an edge computing system to implement any of Examples 1-42.

[0124] Example 50 is a base station comprising networking components and processing components configured to provide or operate a communication network to enable an edge computing system to implement any of Examples 1-42.

[0125] Example 51 is a roadside unit comprising a networking component configured to provide or operate a communication network to enable an edge computing system to implement any of Examples 1-42.

[0126] Example 52 is an on-premise server capable of operating in a private communication network different from a public edge computing network, the server being configured to enable an edge computing system to implement any of Examples 1-42.

[0127] Example 53 is a 3GPP 4G / LTE mobile wireless communication system, comprising a networking component and a processing component, wherein the networking component and the processing component are configured with the subject matter of any one of Examples 1-42.

[0128] Example 54 is a 5G network mobile wireless communication system, comprising a networking component and a processing component, which are configured with the subject matter of any one of Examples 1-42.

[0129] Example 55 is a user equipment device comprising a networking circuit system and a processing circuit system, wherein the networking circuit system and the processing circuit system are configured to connect to an edge computing system, and the edge computing system is configured to implement any one of Examples 1-42.

[0130] Example 56 is a client computing device comprising a processing circuit system configured to coordinate computing operations with an edge computing system configured to implement any of Examples 1-42.

[0131] Example 57 is an edge supply node capable of operating in an edge computing system configured to implement any one of Examples 1-42.

[0132] Example 58 is a service orchestration node operable in an edge computing system configured to implement any one of Examples 1-42.

[0133] Example 59 is an application orchestration node capable of operating in an edge computing system configured to implement any one of Examples 1-42.

[0134] Example 60 is a multi-tenant management node capable of operating in an edge computing system configured to implement any of Examples 1-42.

[0135] Example 61 is an edge computing system comprising a processing circuit system configured to operate one or more functions and services to implement any of Examples 1-42.

[0136] Example 62 is a networked hardware having network functionality implemented thereon, the networked hardware being operable within an edge computing system configured with the subject matter of any of Examples 1-42.

[0137] Example 63 is an acceleration hardware having an acceleration function implemented thereon, the acceleration hardware being operable in an edge computing system, the acceleration function being configured to implement any one of Examples 1-42.

[0138] Example 64 is storage hardware having storage capabilities implemented thereon, the storage hardware being operable in an edge computing system, the storage hardware being configured to implement any one of Examples 1-42.

[0139] Example 65 is computing hardware having computing capabilities implemented thereon, the computing hardware being operable in an edge computing system, the computing hardware being configured to implement any one of Examples 1-42.

[0140] Example 66 is an edge computing system suitable for supporting vehicle-to-vehicle (V2V), vehicle-to-everything (V2X), or vehicle-to-infrastructure (V2I) scenarios, and the edge computing system is configured to implement any one of Examples 1-42.

[0141] Example 67 is an edge computing system suitable for operating in accordance with one or more European Telecommunications Standards Institute (ETSI) Multi-Access Edge Computing (MEC) specifications, and the edge computing system is configured to implement any one of Examples 1-42.

[0142] Example 68 is an edge computing system suitable for operating one or more multi-access edge computing (MEC) components, which MEC components are provided according to the European Telecommunications Standards Institute (ETSI) multi-access edge computing (MEC) configuration from one or more of the following: a MEC agent, a MEC application orchestrator, a MEC application, a MEC platform or a MEC service, and the MEC component is configured to implement any one of Examples 1-42.

[0143] Example 69 is an edge computing system configured as an edge mesh, the edge computing system being provided with a microservice cluster, a microservice cluster with a sidecar, or a linked microservice cluster with a sidecar, the edge computing system being configured to implement any one of Examples 1-42.

[0144] Example 70 is an edge computing system comprising one or more isolation environments provided between dedicated hardware, virtual machines, containers, and virtual machines on containers, the edge computing system being configured to implement any one of Examples 1-42.

[0145] Example 71 is an edge computing server configured to operate as an enterprise server, a roadside server, a street cabinet server, or a telecommunications server, the edge computing server being configured to implement any one of Examples 1-42.

[0146] Example 72 is an edge computing system configured to implement any of Examples 1-42 utilizing use cases provided by one or more of the following: compute migration, data caching, video processing, network function virtualization, radio access network management, augmented reality, virtual reality, autonomous driving, vehicle assistance, vehicle communications, industrial automation, retail services, manufacturing operations, smart buildings, energy management, Internet of Things operations, object detection, speech recognition, healthcare applications, gaming applications, or accelerated content processing.

[0147] Example 73 is an edge computing system comprising computing nodes operated by multiple owners at different geographic locations, the edge computing system configured to implement any of Examples 1-42.

[0148] Example 74 is a cloud computing system, comprising a data server operating a corresponding cloud service, the corresponding cloud service being configured to coordinate with an edge computing system to implement any one of Examples 1-42.

[0149] Example 75 is a server comprising hardware for operating a micro-cloud, micro-edge, or micro-application service configured to coordinate with an edge computing system to implement any of Examples 1-42.

[0150] Example 76 is an edge node in an edge computing system, comprising one or more devices having at least one processor and a memory to implement any of Examples 1-42.

[0151] Example 77 is an edge node in an edge computing system, which operates one or more services provided from among: a management console service, a telemetry service, a provisioning service, an application or service orchestration service, a virtual machine service, a container service, a function deployment service, or a compute deployment service, or an acceleration management service, wherein the one or more services are configured to implement any one of Examples 1-42.

[0152] Example 78 is a set of distributed edge nodes distributed among network layers of an edge computing system, the network layers including near edge, local edge, enterprise edge, owned edge, close edge, intermediate edge, or far edge network layers, and this set of distributed edge nodes is configured to implement any one of Examples 1-42.

[0153] Example 79 is an edge computing system device, comprising: one or more processors, and one or more computer-readable media comprising instructions, which, when executed by the one or more processors, cause the one or more processors to execute any one of Examples 1-42.

[0154] Example 80 is one or more computer-readable storage media, comprising instructions for causing an electronic device of an edge computing system to perform any one of Examples 1-42 when the instructions are executed by one or more processors of the electronic device.

[0155] Example 81 is a communication signal transmitted in an edge computing system, the communication signal being used to perform any of Examples 1-42.

[0156] Example 82 is a data structure transmitted in an edge computing system, the data structure comprising a datagram, a packet, a frame, a fragment, a protocol data unit (PDU), or a message, and the data structure is used to perform any one of Examples 1-42.

[0157] Example 83 is a signal transmitted in an edge computing system, the signal being encoded with a datagram, packet, frame, fragment, protocol data unit (PDU), message, or data, the signal being used to perform any of Examples 1-42.

[0158] Example 84 is an electromagnetic signal transmitted in an edge computing system, the electromagnetic signal carrying computer-readable instructions, wherein execution of the computer-readable instructions by one or more processors causes the one or more processors to perform any one of Examples 1-42.

[0159] Example 85 is a computer program for use in an edge computing system, the computer program comprising instructions, wherein execution of the program by a processing element in the edge computing system causes the processing element to perform any one of Examples 1-42.

[0160] Example 86 is a device of an edge computing system, the device comprising means for performing any of Examples 1-42.

[0161] Example 87 is a device of an edge computing system, the device comprising logic, modules, or circuit systems for performing any of Examples 1-42.

[0162] Example 88 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-87.

[0163] Example 89 is an apparatus comprising means for implementing any of Examples 1-87.

[0164] Example 90 is a system for implementing any of Examples 1-87.

[0165] Example 91 is a method for implementing any of Examples 1-87.

[0166] The above detailed description includes references to the attached drawings, which form part of the detailed description. The drawings illustrate specific embodiments that can be implemented by way of illustration. These embodiments are also referred to as "examples" in this article. Such examples may include elements other than those shown or described. However, examples including the elements shown or described are also contemplated. Moreover, examples using any combination or arrangement of those elements shown or described (or one or more aspects thereof) are also contemplated, or with reference to the specific examples shown or described in this article (or one or more aspects thereof), or with reference to other examples shown or described in this article (or one or more aspects thereof).

[0167] Publications, patents, and patent documents cited in this document are incorporated herein by reference in their entirety, as if individually incorporated by reference. In the event of inconsistent usages between this document and those documents incorporated by reference, the usage in the incorporated reference(s) is supplemental to that of this document; for irreconcilable inconsistencies, the usage in this document controls.

[0168] In this document, as is common in patent documents, the terms "a" and "an" are used to include one or more than one, independent of any other instance or usage of "at least one" or "one or more". In this document, unless otherwise indicated, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B", "B but not A", and "A and B". In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein". In addition, in the appended claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article or process that includes elements other than those listed after such terms in a claim is still deemed to fall within the scope of that claim. In addition, in the appended claims, the terms "first", "second", and "third", etc. are used only as labels and are not intended to indicate the numerical order of their objects.

[0169] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in conjunction with other examples. Other embodiments may be used by those of ordinary skill in the art after carefully reading the above description. The abstract allows the reader to quickly determine the nature of the present technology disclosure. The abstract is submitted, and it is understood that the abstract will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the above specific embodiments, various features may be grouped together to simplify the present disclosure. However, the claims may not state each feature disclosed herein, because the embodiments may characterize a subset of the features. Further, the embodiments may include fewer features than those disclosed in a particular example. Therefore, the attached claims are thus incorporated into the specific embodiments, and one of the claims is independently a separate embodiment. The scope of the embodiments disclosed herein should be determined with reference to the attached claims together with the full scope of equivalents to which such claims are entitled.

Claims

1. A network interface device, comprising: A medium access control MAC circuit system, wherein the medium access control MAC circuit system comprises: A priority router, the priority router being used for: Parsing the packet payload to determine a priority value; determining a corresponding traffic class based on the priority value from the packet payload; and routing the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class; and A packet router, the packet router being configured to: retrieving packet payloads from the plurality of traffic class-based packet buffers based on the traffic class; and The packet payload is placed in a queue for direct memory access (DMA) circuitry to store the packet payload in main memory.

2. The network interface device according to claim 1, wherein: In order to parse the packet payload to determine the priority value, the priority router is used to decode the 3-bit priority code point PCP field in the virtual local area network VLAN tag.

3. The network interface device according to claim 2, wherein: The VLAN tag is an IEEE 802.1Q tag.

4. The network interface device according to claim 1, wherein: To determine the corresponding traffic class based on the priority value from the packet payload, the priority router is configured to perform a lookup in a priority code point PCP to traffic class mapping.

5. The network interface device according to claim 1, wherein: To retrieve the packet payloads from the plurality of traffic class-based packet buffers based on the traffic class, the packet router is configured to retrieve the packet payloads in descending order of priority.

6. The network interface device according to claim 1, wherein: The DMA circuitry is operable to use a channel-based router to transmit high priority packets through a different channel than lower priority packets in order to store the packet payload in main memory.

7. A method for operating a network interface device, the method comprising: Parsing the packet payload to determine a priority value; determining a corresponding traffic class based on the priority value from the packet payload; routing the packet payload to a packet buffer of a plurality of traffic class-based packet buffers based on the traffic class; retrieving packet payloads from the plurality of traffic class-based packet buffers based on the traffic class; as well as The packet payload is placed in a queue for direct memory access (DMA) circuitry to store the packet payload in main memory.

8. The method of claim 7, wherein: Parsing the packet payload to determine the priority value includes decoding a 3-bit priority code point (PCP) field in a virtual local area network (VLAN) tag.

9. The method of claim 8, wherein: The VLAN tag is an IEEE 802.1Q tag.

10. The method of claim 7, wherein: Determining a corresponding traffic class based on the priority code point PCP value from the packet payload includes performing a lookup in a priority code point PCP to traffic class mapping.

11. The method of claim 7, wherein: Retrieving the packet payloads from the plurality of traffic class-based packet buffers based on the traffic class includes retrieving packet payloads in descending order of priority.

12. The method of claim 7, wherein: Storing the packet payload in main memory includes using a tunnel-based router to transmit high priority packets through a different tunnel than lower priority packets.

13. A network interface device, comprising: direct memory access DMA circuitry for reading a packet descriptor from a descriptor buffer and a packet payload corresponding to the packet descriptor from main memory; as well as A medium access control MAC circuit system, wherein the medium access control MAC circuit system comprises: A priority router, the priority router being used for: parsing the packet payload to determine a priority value; determining a corresponding traffic class based on the priority value from the packet payload; and routing the packet payload to one of a plurality of traffic class-based packet buffers based on the traffic class; and Scheduling circuitry for scheduling packets from the plurality of traffic class-based packet buffers for transmission.

14. The network interface device of claim 13, wherein: In order to parse the packet payload to determine the priority value, the priority router is used to decode the 3-bit priority code point PCP field in the virtual local area network VLAN tag.

15. The network interface device of claim 14, wherein: The VLAN tag is an IEEE 802.1Q tag.

16. The network interface device of claim 13, wherein: To determine the corresponding traffic class based on the priority value from the packet payload, the priority router is configured to perform a lookup in a priority code point PCP to traffic class mapping.

17. The network interface device of claim 13, wherein: The network interface device further comprises a packet processor for modifying the packet payload prior to transmission.

18. The network interface device of claim 17, wherein: The packet processor is used to insert a VLAN tag into a packet header of the packet payload.

19. The network interface device of claim 17, wherein: The packet processor is used to insert an IEEE 802.1Q tag into a packet header of the packet payload.

20. The network interface device of claim 17, wherein: The packet processor is configured to replace an existing VLAN tag in a packet header of the packet payload with a different VLAN tag.

21. At least one machine-readable medium comprising instructions that, when executed by a machine, cause the machine to perform the operations of any one of the methods of claims 7-12.

22. A device, comprising: means for parsing the packet payload to determine a priority value; means for determining a corresponding traffic class based on said priority value from said packet payload; means for routing the packet payload to a packet buffer of a plurality of traffic class-based packet buffers based on the traffic class; means for retrieving packet payloads from said plurality of traffic class-based packet buffers based on said traffic class; as well as Means for placing the packet payload in a queue for direct memory access (DMA) circuitry to store the packet payload in main memory.

Images