Accelerator, data processing method and related equipment
By designing a communication scheduling engine and computing scheduling engine in the accelerator, and using intermediate representations to perform communication and computing tasks in parallel, the problem of low utilization of collective communication resources in distributed computing is solved, and the computing efficiency is improved.
Patent Information
- Application Number
- CN202311093637.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-25
- Publication Date
- 2025-02-25
AI Technical Summary
The current collective communication method in distributed computing has the problem of low resource utilization, resulting in low computing efficiency.
An accelerator is designed, including a communication scheduling engine, a communication unit, a computing scheduling engine and a computing unit. Through the intermediate representation calling the communication unit and the computing unit, the communication operator and the computing operator are executed in parallel, so as to realize the parallelism of communication and computing.
The resource utilization rate of the accelerator is improved, and the efficiency of distributed computing is improved by processing communication and computing tasks in parallel.
Smart Images
Figure CN119512732A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of data processing, and in particular to an accelerator, a data processing method and related equipment. Background Art
[0002] With the development of high performance computing (HPC) and artificial intelligence (AI) technology, the scale of data that computing devices need to process is also increasing. In order to solve the problem of large-scale data computing, distributed computing has emerged. In the current distributed computing field, distributed computing assigns computing tasks to multiple computing devices for execution. In the process of distributed computing, data interaction will be involved between various computing devices. Collective communication has a large number of important applications in distributed computing. For example, collective communication methods such as allreduce and allgather are common methods for realizing data interaction between multiple computing devices in distributed computing. However, the current collective communication method has the problem of low resource utilization. Summary of the invention
[0003] The present application provides an accelerator, a data processing method and related equipment, which can improve the resource utilization of the accelerator and improve the efficiency of distributed computing.
[0004] In a first aspect, the present application provides an accelerator, which includes a communication scheduling engine, a communication unit, a computing scheduling engine and a computing unit. The communication scheduling engine is used to obtain an intermediate representation corresponding to a model reasoning task or a model training task, and then call the communication unit to execute a first communication operator among multiple communication operators included in a communication task according to the intermediate representation, and call the computing unit to execute the computing operator in the communication task, or notify the computing scheduling engine so that the computing scheduling engine calls the computing unit to execute the computing operator in the communication task. The above-mentioned intermediate representation includes the above-mentioned communication task, and the communication task indicates the execution of a collective communication.
[0005] The communication task for implementing collective communication includes both communication operators for implementing sending / receiving data and computing operators for computing. In the process of executing the communication task through the above-mentioned accelerator, when the accelerator calls the communication unit to execute the communication operator through the communication scheduling engine, it can call the computing unit to execute the computing operator in the communication task through the communication scheduling engine or the computing scheduling engine, so that the accelerator executes the computing operator to calculate the data while executing the communication operator to send data, thereby realizing the parallelism of communication and computing, avoiding the computing unit being in an idle state when executing the communication operator, and improving the resource utilization of the accelerator, thereby improving the efficiency of distributed computing.
[0006] In a possible implementation, the intermediate representation also includes a computing task, and the computing scheduling engine is used to call the computing unit to execute the computing task according to the intermediate representation. The intermediate representation is used to implement model reasoning tasks or model training tasks. The tasks corresponding to the intermediate representation include computing tasks and communication tasks. The computing tasks are executed by the computing unit to generate data to be transmitted. The communication tasks are used to collectively communicate the data generated by the computing tasks to achieve data aggregation between different accelerators.
[0007] In a possible implementation, the communication scheduling engine is further used to send notification information to the computing scheduling engine after executing the communication task; the computing scheduling engine is further used to execute the computing task after the communication task in the intermediate representation when receiving the notification information.
[0008] In a possible implementation, the computing scheduling engine is further used to send notification information to the communication scheduling engine after executing the computing task; the communication scheduling engine is further used to execute the communication task after the computing task in the intermediate representation when receiving the notification information.
[0009] The communication scheduling engine is used to execute communication tasks, and the computing scheduling engine is used to execute computing tasks. After the communication scheduling engine and the computing scheduling engine have completed their respective tasks, they will send notification information to the other scheduling engine to notify the other scheduling engine to execute the corresponding task.
[0010] In a possible implementation, the communication task in the intermediate representation is generated by a processor calling a first function, and the input of the first function is a collective communication identifier, such as a name of the collective communication.
[0011] In a possible implementation, the communication task is a global reduction allreduce or a global collection allgather.
[0012] In a possible implementation, when the communication task is allreduce, the computing operator includes a quantization operator and a dequantization operator; wherein each quantization operator indicates to perform a quantization operation on part of the data in the accelerator.
[0013] In a possible implementation, when the communication task is allgather, the above-mentioned calculation operator includes a matrix multiplication operator.
[0014] In one possible implementation, the accelerator is a graphics processing unit (GPU), a neural network processor (NPU), a tensor processing unit (TPU) or a dedicated AI processing chip.
[0015] In a second aspect, the present application provides a data processing method, which is applied to a computing device, the computing device includes a communication scheduling engine, a communication unit, a computing scheduling engine and a computing unit, and the method includes: the communication scheduling engine obtains an intermediate representation corresponding to a model reasoning task or a model training task, and then calls the communication unit to execute a first communication operator among multiple communication operators included in a communication task according to the intermediate representation, and calls the computing unit to execute the computing operator in the communication task, or notifies the computing scheduling engine so that the computing scheduling engine calls the computing unit to execute the computing operator in the communication task. The above-mentioned intermediate representation includes the above-mentioned communication task, and the communication task indicates the execution of a collective communication.
[0016] In a possible implementation, the intermediate representation further includes a computing task, and the method further includes: a computing scheduling engine calling a computing unit to execute the computing task according to the intermediate representation.
[0017] In one possible implementation, the computing scheduling engine calls the computing unit to execute the computing task according to the intermediate representation, including: the communication scheduling engine sends a notification message to the computing scheduling engine after executing the communication task; and the computing scheduling engine executes the computing task after the communication task in the intermediate representation after receiving the notification message.
[0018] In a possible implementation, the method further includes: the computing scheduling engine sends notification information to the communication scheduling engine when the computing task is completed; and the communication scheduling engine executes the communication task after the computing task described in the intermediate representation when receiving the notification information.
[0019] In a possible implementation, the communication task in the intermediate representation is generated by a processor calling a first function, and the input of the first function is a collective communication identifier.
[0020] In a possible implementation, the communication task is a global reduction allreduce or a global collection allgather.
[0021] In a possible implementation, when the communication task is allreduce, the computing operator includes a quantization operator and a dequantization operator; wherein each quantization operator indicates to perform a quantization operation on part of the data in the accelerator.
[0022] In a possible implementation, when the communication task is allgather, the above-mentioned calculation operator includes a matrix multiplication operator.
[0023] In one possible implementation, the computing device includes an accelerator, and the computing unit and the communication unit are located in the accelerator; the accelerator is a GPU, an NPU, a TPU or a dedicated artificial intelligence AI processing chip.
[0024] In a third aspect, the present application provides a computing device comprising a processor, an accelerator and a memory, the memory being used to store instructions, the processor being used to execute the instructions, and when the processor executes the instructions, the accelerator is called to implement the method described in the second aspect or any possible implementation of the second aspect.
[0025] In a fourth aspect, the present application provides a computer program product, which, when executed on a server, enables the server to execute the method described in the second aspect or any possible implementation manner of the second aspect.
[0026] In a fifth aspect, the present application provides a computer-readable storage medium, which stores instructions. When the instructions are executed on a server, the server executes the method described in the second aspect or any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0028] Figure 1 is a schematic diagram of a computing device provided in an embodiment of the present application;
[0029] Figure 2 is a schematic diagram of a data processing method provided in an embodiment of the present application;
[0030] Figure 3 is a schematic diagram of a ring-allreduce execution process provided in an embodiment of the present application;
[0031] Figure 4 is a schematic diagram of another ring-allreduce execution process provided in an embodiment of the present application;
[0032] Figure 5is a schematic diagram of another ring-allreduce execution process provided in an embodiment of the present application;
[0033] Figure 6 is a schematic diagram of an allgather execution process provided by an embodiment of the present application;
[0034] Figure 7 is a schematic diagram of another allgather execution process provided in an embodiment of the present application;
[0035] Figure 8 is a schematic diagram of an accelerator provided in an embodiment of the present application;
[0036] Fig. 9 It is a schematic diagram of another computing device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0037] The technical solution in this application will be described below in conjunction with the accompanying drawings.
[0038] In the current distributed computing field, computing tasks are assigned to one or more computing devices for execution. For example, a computing device includes multiple accelerators, and computing tasks are performed by multiple accelerators of a computing device; or computing tasks are assigned to multiple computing devices, each of which includes multiple accelerators, and computing tasks are completed by the accelerators included in multiple computing devices. In the process of distributed computing, multiple accelerators of a computing device and multiple accelerators of multiple computing devices will involve data interaction. Collective communication is a common method for data interaction between different accelerators in distributed computing, such as collective communication methods such as global reduce (allreduce) and global gather (allgather). Users can interact with data by calling the allreduce or allgather interface.
[0039] In current distributed computing, users usually use the collective communication functions provided by the message passing interface (MPI) library to implement collective communication, such as MPI_reduce, MPI_allgather, etc. Users only need to call the corresponding interface function, and the computing device can implement the corresponding operation according to a fixed process, and users do not need to pay attention to the underlying implementation logic. However, there is a problem of low resource utilization when implementing collective communication in current distributed computing.
[0040] The present application provides a data processing method, which is applied to Figure 1The computing device comprises one or more general-purpose processors and one or more accelerators. The general-purpose processor may be a central processing unit (CPU), and the accelerator may be a graphics processing unit (GPU), a neural network processor (NPU), a tensor processing unit (TPU) or a dedicated AI processing chip.
[0041] The computing device receives a script file of a task input by a user, such as a script file of a model training task or a script file of a model reasoning task. The CPU converts the script file into an intermediate representation (IR) through a training framework, and the intermediate representation includes a communication task. Among them, the communication task is used to indicate the execution of a collective communication, and the communication task includes multiple communication operators and multiple computing operators. The accelerator executes the communication operator to implement the data sending or receiving operation, and the accelerator executes the computing operator to implement the data calculation.
[0042] The CPU sends the intermediate representation to an accelerator, such as Figure 1 As shown, the accelerator includes a communication scheduling engine, a communication unit, a computing scheduling engine and a computing unit. In the process of executing the intermediate representation, when the accelerator executes the communication task, since the communication task includes multiple communication operators and multiple computing operators, when the accelerator executes the communication operator, the accelerator calls the communication unit through the communication scheduling engine to execute the communication operator. When the communication scheduling engine calls the communication unit to execute the communication operator, it can also call the computing unit to execute the computing operator in the communication task, or the communication scheduling engine notifies the computing scheduling engine so that the computing scheduling engine calls the computing unit to execute the computing operator in the communication task. For example, when the communication scheduling engine calls the communication unit to execute the first communication operator among multiple communication operators, it also calls the computing unit to execute the computing operator after the first communication operator, or when the communication scheduling engine calls the communication unit to execute the first communication operator among multiple communication operators, it notifies the computing scheduling engine so that the computing scheduling engine calls the computing unit to execute the computing operator after the first communication operator.
[0043] In the embodiment of the present application, the intermediate representation also includes a computing task. The accelerator can generate data that needs to be sent by the communication task by executing the computing task. For example, in the model training task, the computing task includes a computing task for implementing forward propagation and a computing task for implementing reverse propagation. After the accelerator completes the computing task corresponding to the reverse propagation, it can generate the gradient data that needs to be sent by the communication task.
[0044] When the accelerator executes the computing task in the intermediate representation, it calls the computing unit to execute the computing task through the computing scheduling engine. When the communication task is executed according to the intermediate representation, the computing scheduling engine sends notification information to the communication scheduling engine. After receiving the notification information, the communication scheduling engine executes the communication task after the above computing task in the intermediate representation. Since a communication task includes multiple communication operators and multiple computing operators, when it is necessary to execute the first communication operator in the communication operator, the communication scheduling engine calls the communication unit to execute the first communication operator, and calls the computing unit to execute the computing operator included in the communication task, or the communication scheduling engine notifies the computing scheduling engine, so that the computing scheduling engine calls the computing unit to execute the computing operator included in the communication task. After executing the above communication task, the communication scheduling engine sends notification information to the computing scheduling engine. After receiving the notification information, the computing scheduling engine executes the computing task after the above communication task in the intermediate representation.
[0045] The above communication task can be allreduce or allgather, etc. When the communication task is allreduce, the computing operator includes a quantization operator and a dequantization operator, etc. Each quantization operator is used to perform a quantization operation on part of the data in the accelerator to obtain quantized data; the dequantization operator is used to dequantize the quantized data received from other accelerators. When the communication task is allgather, the computing operator includes a matrix multiplication operator, which is used to implement the multiplication operation of two matrices.
[0046] In the process of the accelerator executing a communication task, when the accelerator calls the communication unit to execute the communication operator through the communication scheduling engine, it can call the computing unit to execute the computing operator in the communication task through the communication scheduling engine or the computing scheduling engine, thereby realizing the parallelism of communication and computing, avoiding the computing unit being idle when executing the communication operator, and improving the resource utilization of the accelerator, thereby improving the efficiency of distributed computing.
[0047] The following is combined with the above Figure 1 The accelerator shown in the present application provides a data processing method, which is applied to Figure 1 The data processing method provided by the present application is described below in conjunction with the accompanying drawings. Figure 2 As shown, Figure 2 It is a flow chart of a data processing method provided in an embodiment of the present application.
[0048] S201. The computing device obtains a script file and converts the script file into an intermediate representation through a general processor.
[0049] The script file is a file that implements model training tasks or model inference tasks. The script file includes the code for processing input data and model parameters. The model parameters include the model's network structure, learning rate, optimizer type, loss function, etc.
[0050] After obtaining the script file, the computing device converts the script file into an intermediate representation through the training framework running on the processor, that is, the intermediate representation is used to represent the model reasoning task or the model training task. The intermediate representation includes a communication task, and a communication task is used to indicate the execution of a collective communication. Among them, the communication task can be a task that implements collective communication such as allreduce or allgather. For example, when performing model training in a data-parallel manner, data aggregation needs to be achieved between multiple accelerators through allreduce. The above-mentioned training framework can be a deep learning framework such as TensorFlow or PyTorch, which is not specifically limited in the embodiments of the present application.
[0051] The above intermediate representation also includes computing tasks. The computing device can generate the data that needs to be sent by the communication task by executing the computing tasks. For example, in the process of implementing the model training task through data parallelism, the computing tasks include computing tasks for implementing forward propagation and computing tasks for implementing reverse propagation. After the accelerator completes the reverse propagation computing task, it generates the gradient data that needs to be sent by the communication task.
[0052] In an embodiment of the present application, the above-mentioned communication task includes a communication operator and a computing operator, the communication operator is used to implement the operation of sending or receiving data, and the computing operator is used to implement the calculation of data. For example, if the communication task is allreduce, the computing operator includes a quantization operator and an inverse quantization operator, each quantization operator is used to perform a quantization operation on part of the data in the accelerator, and the inverse quantization operator is used to inversely quantize the quantized data sent by other accelerators. For example, in the case where the communication task is ring-allreduce, if there are three accelerators that need to perform collective communication of ring-allreduce, the data that needs to participate in the collective communication in each accelerator will be divided into 3 parts. For any accelerator, first, one of the data is quantized by executing a quantization operator on the data through the computing unit to obtain the quantized data, and then the quantized data is sent to another accelerator by executing a communication operator through the communication unit. While sending the quantized data to another accelerator, the computing operator is executed by the computing unit to quantize the other part of the data.
[0053] When the communication task is allgather, the computing operator includes a matrix multiplication operator for implementing a multiplication operation of two matrices.
[0054] In a possible implementation, the communication task is generated by the computing device calling the first function through the processor, and the input of the first function is a collective communication identifier, which indicates a collective communication method, such as allreduce, ring-allreduce, allgather or alltoall. That is, the script file includes the first function, and after obtaining the script file, the computing device runs the script file and executes the first function in the script file to obtain the communication task in the intermediate representation.
[0055] It should be understood that the above intermediate representation includes multiple computing tasks and multiple communication tasks. Each computing task includes multiple computing operators, and each communication task includes multiple computing operators and multiple communication operators, that is, the above intermediate representation includes multiple operators. Each operator includes an operator identifier, an operator (operator, op) type, and input data. For communication operators, the above operator types include a send operator or a receive operator, and the communication operator also includes attribute information. In the case where the operator type is a sending operator, the attribute information includes the offset and length of the data to be sent, wherein the offset indicates the starting position of the data to be sent in the input data, and the length indicates the length of the data to be sent; in the case where the operator type is a receiving operator, the attribute information includes the identifier of the source accelerator of the received data. The following is an example of a communication operator:
[0056]
[0057] The communication operator is identified as "send_0", the operator type is a sending operator, and the input data of the communication operator is "comp_0". The communication operator indicates that 100 data are sent to the destination accelerator from the starting position of the input data "comp_0", or 100 bytes of data are sent to the destination accelerator.
[0058] For calculation operators, operator types include addition operators, matrix multiplication operators, multiplication operators, activation operators, quantization operators, dequantization operators, etc. The calculation operator also includes attribute information and the identifier of the pre-dependent operator. The attribute information indicates the offset and length of the data to be calculated. Among them, the offset indicates the starting position of the data to be calculated in the input data, and the length indicates the number of data to be calculated. The following is an example of a calculation operator:
[0059]
[0060] The name of the calculation operator is "add_0", the operator type is an addition operator, the input data of the calculation operator is "variable_0", and the preceding dependent operator is an operator named "send_0". The calculation operator indicates to perform an addition operation on the input data "variable_0" and the first 100 data obtained from the preceding dependent operator "send_0".
[0061] S202. The computing device sends the intermediate representation to the accelerator, and the accelerator executes the intermediate representation.
[0062] After the computing device obtains the above intermediate representation through the training framework running in the processor, the intermediate representation is sent to the accelerator. The accelerator calls the computing unit through the computing scheduling engine to execute the computing task in the intermediate representation. After the computing unit completes a computing task, if the next task of the computing task is a communication task, the computing scheduling engine sends a notification message to the communication scheduling engine. The notification message is used to notify the communication scheduling engine to execute the next communication task. For example, the notification message includes a communication task identifier, which is used to indicate the communication task that the communication scheduling engine needs to execute.
[0063] After receiving the notification information sent by the computing scheduling engine, the communication scheduling engine calls the communication unit to execute the communication operator in the communication task. When executing the communication operator, the communication scheduling engine can also call the computing unit to execute the computing operator in the communication task, or the communication scheduling engine notifies the computing scheduling engine to make the computing scheduling engine call the computing unit to execute the computing operator in the communication task. For example, when it is necessary to execute the first communication operator in the communication operator, the communication scheduling engine calls the communication unit to execute the first communication operator, and calls the computing unit to execute the computing operator after the first communication operator, or the communication scheduling engine notifies the computing scheduling engine to make the computing scheduling engine call the computing unit to execute the computing operator after the first communication operator.
[0064] After the communication scheduling engine completes the communication task by calling the communication unit and the computing unit, if the next task of the communication task is a computing task, the communication scheduling engine sends a notification message to the computing scheduling engine, and the notification message is used to instruct the computing scheduling engine to execute the next computing task. For example, the communication message includes a computing task identifier, and the computing task identifier is used to indicate the computing task that the computing scheduling engine needs to execute. After receiving the notification message sent by the communication scheduling engine, the computing scheduling engine calls the computing unit to execute the corresponding computing task.
[0065] The following uses ring-allreduce and allgather as examples to introduce the process of implementing collective communication through the accelerator and data processing method provided by this application.
[0066] First, taking ring-allreduce, a collective communication method used in distributed computing, as an example, the process of implementing ring-allreduce through the accelerator and data processing method provided in this application is introduced.
[0067] See also Figure 3 , Figure 3 This is a schematic diagram of the current ring-allreduce execution process provided by an embodiment of the present application. Taking the distributed computing including three accelerators as an example, accelerator 0 includes three copies of data, namely a0, b0 and c0, accelerator 1 includes three copies of data, namely a1, b1 and c1, and accelerator 2 includes three copies of data, namely a2, b2 and c2. The process of data interaction between the current accelerators through ring-allreduce is as follows:
[0068] Step 1:
[0069] Accelerator 0 quantizes a0, b0, and c0 to obtain qa0, qb0, and qc0;
[0070] Accelerator 1 quantizes a1, b1, and c1 to obtain qa1, qb1, and qc1;
[0071] Accelerator 2 quantizes a2, b2, and c2 to obtain qa2, qb2, and qc2.
[0072] Step 2:
[0073] Accelerator 0 sends qa0 to accelerator 1 and receives qc2 sent by accelerator 2;
[0074] Accelerator 1 sends qb1 to accelerator 2 and receives qa0 sent by accelerator 0;
[0075] Accelerator 2 sends qc2 to accelerator 0 and receives qb1 sent by accelerator 1.
[0076] Step 3:
[0077] Accelerator 0 executes qc0+qc2 to get qc02;
[0078] Accelerator 1 executes qa0+qa1 and obtains qa01;
[0079] Accelerator 2 executes qb1+qb2 and obtains qb12.
[0080] Step 4:
[0081] Accelerator 0 sends qc02 to accelerator 1 and receives qb12 sent by accelerator 2;
[0082] Accelerator 1 sends qa01 to accelerator 2 and receives qc02 sent by accelerator 0;
[0083] Accelerator 2 sends qb12 to accelerator 0 and receives qa01 sent by accelerator 1.
[0084] Step 5:
[0085] Accelerator 0 executes qb0+qb12 and gets qb;
[0086] Accelerator 1 executes qc0+qc02 to get qc;
[0087] Accelerator 2 executes qa01+qa2 and obtains qa.
[0088] Step 6:
[0089] Accelerator 0 sends qb to accelerator 1 and receives qa sent by accelerator 2;
[0090] Accelerator 1 sends qc to accelerator 2 and receives qb sent by accelerator 0;
[0091] Accelerator 2 sends qa to accelerator 0 and receives qc sent by accelerator 1.
[0092] Step 7:
[0093] Accelerator 0 sends qa to accelerator 1 and receives qc sent by accelerator 2;
[0094] Accelerator 1 sends qb to accelerator 2 and receives qa sent by accelerator 0;
[0095] Accelerator 2 sends qc to accelerator 0 and receives qb sent by accelerator 1.
[0096] Step 8:
[0097] Accelerator 0 dequantizes qa, qb and qc respectively to obtain dqa, dqb and dqc;
[0098] Accelerator 1 dequantizes qa, qb and qc respectively to obtain dqa, dqb and dqc;
[0099] Accelerator 2 dequantizes qa, qb and qc respectively to obtain dqa, dqb and dqc.
[0100] When you need to use ring-allreduce to communicate collectively, you only need to call the ring-allreduce interface, and the underlying layer can complete the above process. Figure 2As shown in , in the above process, the accelerator can only perform computing operations or can only perform sending / receiving operations at each step. When performing computing operations, the bandwidth between accelerators will be idle, and when performing sending / receiving operations, the computing resources of the accelerators are idle. Therefore, this method does not fully utilize bandwidth resources and computing resources, affecting computing efficiency.
[0101] See also Figure 4 , Figure 4 It is a schematic diagram of a ring-allreduce execution process provided by an embodiment of the present application. Taking distributed computing including three accelerators as an example, based on the intermediate representation, after the computing scheduling engine of each accelerator obtains the data to be transmitted by executing the computing task, the computing scheduling engine sends a notification message to the communication scheduling engine. After the communication scheduling engine receives the notification message, it executes the communication task through the computing unit and the communication unit. Among them, accelerator 0 includes three copies of data, namely a0, b0 and c0, accelerator 1 includes three copies of data, namely a1, b1 and c1, and accelerator 2 includes three copies of data, namely a2, b2 and c2. The process of data interaction between accelerators through ring-allreduce includes the following 8 steps.
[0102] Step 1:
[0103] Accelerator 0 performs quantization on a0 to obtain qa0;
[0104] Accelerator 1 performs quantization on b1 to obtain qb1;
[0105] Accelerator 2 performs quantization on c2 to obtain qc2.
[0106] Step 2:
[0107] Accelerator 0 sends qa0 to accelerator 1, and at the same time performs quantization on c0 to obtain qc0, and receives qc2 sent by accelerator 2 to obtain qc0 and qc2;
[0108] Accelerator 1 sends qb1 to accelerator 2, and at the same time performs quantization on a1 to obtain qa1, and receives qa0 sent by accelerator 0 to obtain qa0 and qa1;
[0109] Accelerator 2 sends qc2 to accelerator 0, and at the same time performs quantization on b2 to obtain qb2, and receives qb1 sent by accelerator 1 to obtain qb1 and qb2.
[0110] Step 3:
[0111] Accelerator 0 executes qc0+qc2 to get qc02;
[0112] Accelerator 1 executes qa0+qa1 and obtains qa01;
[0113] Accelerator 2 executes qb1+qb2 and obtains qb12.
[0114] Step 4:
[0115] Accelerator 0 sends qc02 to accelerator 1, and performs quantization on b0 to obtain qb0; it receives qb12 sent by accelerator 2 and obtains qb0 and qb12;
[0116] Accelerator 1 sends qa01 to accelerator 2, and at the same time performs quantization on c1 to obtain qc1; it receives qc02 sent by accelerator 0 and obtains qc1 and qc02;
[0117] Accelerator 2 sends qb12 to accelerator 0, and at the same time performs quantization on a2 to obtain qa2; it receives qa01 sent by accelerator 1 and obtains qa01 and qa2.
[0118] Step 5:
[0119] Accelerator 0 calculates qb0+qb12 and obtains qb;
[0120] Accelerator 1 calculates qc1+qc02 and obtains qc;
[0121] Accelerator 2 calculates qa01+qa2 and obtains qa.
[0122] Step 6:
[0123] Accelerator 0 sends qb to accelerator 1, and performs dequantization on qb to obtain dqb; it receives qa sent by accelerator 2 and obtains qa;
[0124] Accelerator 1 sends qc to accelerator 2, and performs dequantization on qc to obtain dqc; it receives qb sent by accelerator 0 and obtains qb;
[0125] Accelerator 2 sends qa to accelerator 0, and at the same time performs dequantization on qa to obtain dqa; it receives qc sent by accelerator 1 and obtains qc.
[0126] Step 7:
[0127] Accelerator 0 sends qa to accelerator 1, and performs dequantization on qa to obtain dqa; it receives qc sent by accelerator 2 to obtain qc;
[0128] Accelerator 1 sends qb to accelerator 2, and performs dequantization on qb to obtain dqb; it receives qa sent by accelerator 0 and obtains qa;
[0129] Accelerator 2 sends qc to accelerator 0, and at the same time performs dequantization on qc to obtain dqc; it receives qb sent by accelerator 1 and obtains qb.
[0130] Step 8:
[0131] Accelerator 0 performs dequantization on qc to obtain dqc;
[0132] Accelerator 1 performs dequantization on qa to obtain dqa;
[0133] Accelerator 2 performs inverse quantization on qb to obtain dqb.
[0134] It should be noted that Figure 4 In each step of the corresponding embodiment, the quantization operation performed by the accelerator is implemented by the communication scheduling engine or the computing scheduling engine calling the computing unit to execute the quantization operator in the communication task; the sending operation performed by the accelerator is implemented by the communication scheduling engine calling the communication unit to execute the communication operator in the communication task; the inverse quantization operation performed by the accelerator is implemented by the communication scheduling engine or the computing scheduling engine calling the computing unit to execute the inverse quantization operator in the communication task. Among them, when the accelerator performs both the sending operation and the computing operation in one step, the communication scheduling engine of the accelerator calls the communication unit to execute the communication operator while the communication scheduling engine calls the computing unit to execute the computing operator, or the communication scheduling engine notifies the computing scheduling engine to call the computing unit to execute the computing operator.
[0135] By comparing the above Figure 3 , Figure 4 and a description of the steps involved, Figure 3 and Figure 4 Each accelerator sends data the same number of times and the length of each transmission is the same, but Figure 4 In the corresponding process, the quantization or dequantization operation of a large amount of data is completed in multiple times, so that the calculation operation can be performed while sending the data, which improves the utilization rate of the accelerator resources and makes Figure 4 In the corresponding embodiment, the length of the data to be quantized in step 1 is smaller, and the length of the data to be dequantized in step 8 is smaller, so Figure 4 The corresponding process takes less time and can improve the efficiency of distributed computing.
[0136] See also Figure 5 , Figure 5 1 is a schematic diagram of another ring-allreduce execution process provided by an embodiment of the present application. The process of data exchange between accelerators through ring-allreduce is as follows:
[0137] Step 1:
[0138] Accelerator 0, performs quantization on a0 to obtain qa0;
[0139] Accelerator 1 performs quantization on b1 to obtain qb1;
[0140] Accelerator 2 performs quantization on c2 to obtain qc2.
[0141] Step 2:
[0142] Accelerator 0 sends qa0 to accelerator 1, and at the same time performs quantization on b0 to obtain qb0, and receives qc2 sent by accelerator 2 to obtain c0 and qc2;
[0143] Accelerator 1 sends qb1 to accelerator 2, and at the same time performs quantization on c1 to obtain qc1, and receives qa0 sent by accelerator 0 to obtain a1 and qa0;
[0144] Accelerator 2 sends qc2 to accelerator 0, and at the same time performs quantization on a2 to obtain qa2, and receives qb1 sent by accelerator 1 to obtain b2 and qb1.
[0145] Step 3:
[0146] Accelerator 0 sends qb0 to accelerator 1, and performs dequantization on qc2 at the same time, calculates c0 and the dequantization result to obtain c02, receives qa2 sent by accelerator 2, and obtains qa0 and qa2;
[0147] Accelerator 1 sends qc1 to accelerator 2, and performs dequantization on qa0 at the same time, calculates a1 and the dequantization result to obtain a01, receives qb0 sent by accelerator 0, and obtains qb0 and qb1;
[0148] Accelerator 2 sends qa2 to accelerator 0, and at the same time performs dequantization on qb1, calculates b2 and the dequantization result to obtain b12, receives qc1 sent by accelerator 1, and obtains qc1 and qc2.
[0149] Step 4:
[0150] Accelerator 0 performs quantization on c02 to obtain qc02;
[0151] Accelerator 1 performs quantization on a01 to obtain qa01;
[0152] Accelerator 2 performs quantization on b12 to obtain qb12.
[0153] Step 5:
[0154] Accelerator 0 sends qc02 to accelerator 1, receives qb12 sent by accelerator 2, and obtains qb0 and qb12;
[0155] Accelerator 1 sends qa01 to accelerator 2, receives qc02 sent by accelerator 0, and obtains qc1 and qc02;
[0156] Accelerator 2 sends qb12 to accelerator 0, receives qa01 sent by accelerator 1, and obtains qa01 and qa2.
[0157] Step 6:
[0158] Accelerator 0, calculate qb0+qb12, get qb;
[0159] Accelerator 1, calculates qc1+qc02 and obtains qc;
[0160] Accelerator 2 calculates qa01+qa2 and obtains qa.
[0161] Step 7:
[0162] Accelerator 0 sends qb to accelerator 1 and performs dequantization on qb to obtain dqb; it receives qa sent by accelerator 2 and obtains qa;
[0163] Accelerator 1 sends qc to accelerator 2, and performs dequantization on qc to obtain dqc; receives qb sent by accelerator 0 to obtain qb;
[0164] Accelerator 2 sends qa to accelerator 0, and at the same time performs dequantization on qa to obtain dqa; it receives qc sent by accelerator 1 and obtains qc.
[0165] Step 8:
[0166] Accelerator 0 sends qa to accelerator 1 and performs dequantization on qa to obtain dqa; it receives qc sent by accelerator 2 and obtains qc;
[0167] Accelerator 1 sends qb to accelerator 2, and performs dequantization on qb to obtain dqb; receives qa sent by accelerator 0 to obtain qa;
[0168] Accelerator 2 sends qc to accelerator 0, and at the same time performs dequantization on qc to obtain dqc; receives qb sent by accelerator 1 to obtain qb.
[0169] Step 9:
[0170] Accelerator 0 performs dequantization on qc to obtain dqc;
[0171] Accelerator 1 performs dequantization on qa to obtain dqa;
[0172] Accelerator 2 performs dequantization on qb to obtain dqb.
[0173] It should be noted that Figure 5In each step of the corresponding embodiment, the quantization operation performed by the accelerator is implemented by the communication scheduling engine or the computing scheduling engine calling the computing unit to execute the quantization operator in the communication task; the sending operation performed by the accelerator is implemented by the communication scheduling engine calling the communication unit to execute the communication operator in the communication task; the inverse quantization operation performed by the accelerator is implemented by the communication scheduling engine or the computing scheduling engine calling the computing unit to execute the inverse quantization operator in the communication task. Among them, when the accelerator performs both the sending operation and the computing operation in one step, the communication scheduling engine of the accelerator calls the communication unit to execute the communication operator while the communication scheduling engine calls the computing unit to execute the computing operator, or the communication scheduling engine notifies the computing scheduling engine to call the computing unit to execute the computing operator.
[0174] By comparing the above Figure 3 , Figure 5 and a description of the steps involved, Figure 3 and Figure 5 Each accelerator sends data the same number of times and the length of each transmission is the same, but Figure 5 In the corresponding process, the quantization or dequantization operation of a large amount of data is completed in multiple times, so that the calculation operation can be performed while sending the data, which improves the utilization rate of the accelerator resources and makes Figure 5 In the corresponding embodiment, the length of the data to be quantized in step 1 is smaller, and the length of the data to be dequantized in step 9 is smaller, so Figure 5 The corresponding process takes less time and can improve the efficiency of distributed computing.
[0175] Next, taking the collective communication mode used in distributed computing as AllGather, that is, the above-mentioned communication task as AllGather as an example, the process of implementing AllGather through the accelerator and data processing method provided in this application is introduced.
[0176] See also Figure 6 , Figure 6 This is a schematic diagram of an allgather execution process provided by an embodiment of the present application. Taking the distributed computing including two accelerators as an example, accelerator 3 includes matrix D0 and matrix E0, and accelerator 4 includes matrix D1 and matrix E1; the process of data interaction between the current accelerators through allgather is as follows:
[0177] Step 1:
[0178] Accelerator 3 sends matrix D0 to accelerator 4, receives matrix D1 sent by accelerator 4, and obtains matrix D;
[0179] Accelerator 4 sends matrix D1 to accelerator 3, receives matrix D0 sent by accelerator 3, and obtains matrix D;
[0180] Step 2:
[0181] Accelerator 3 calculates [D0, D1]*E0 and obtains the matrix [F00, F10];
[0182] Accelerator 4 calculates [D0, D1]*E1 and obtains the matrix [G01, G11];
[0183] When allgathering, you only need to call the allgather interface, and the bottom layer can complete the above process. Figure 6 As shown in , in the above process, the accelerator can only perform computing operations or can only perform sending / receiving operations at each step. When performing computing operations, the bandwidth between accelerators will be idle, and when performing sending / receiving operations, the computing resources of the accelerators are idle. Therefore, this method does not fully utilize bandwidth resources and computing resources, affecting computing efficiency.
[0184] See also Figure 7 , Figure 7 It is a schematic diagram of another allgather execution process provided by an embodiment of the present application. Based on the intermediate representation, after the computing scheduling engine of each accelerator obtains the data to be transmitted by executing the computing task, the computing scheduling engine sends a notification message to the communication scheduling engine, and the communication scheduling engine executes the communication task through the computing unit and the communication unit. Among them, accelerator 3 includes matrix D0 and matrix E0, and accelerator 4 includes matrix D1 and matrix E1. Based on the intermediate representation, the process of data interaction between accelerators through allgather is as follows:
[0185] Step 1:
[0186] Accelerator 3 sends matrix D0 to accelerator 4, and at the same time calculates matrix D0 multiplied by matrix E0 to obtain matrix F00, and receives matrix D1 sent by accelerator 4;
[0187] Accelerator 4 sends matrix D1 to accelerator 3, and at the same time calculates matrix D1 multiplied by matrix E1 to obtain matrix G11, and receives matrix D0 sent by accelerator 3;
[0188] Step 2:
[0189] Accelerator 3 calculates matrix D1 and multiplies matrix E0 to obtain matrix F10;
[0190] Accelerator 4 calculates matrix D0 and multiplies matrix E1 to obtain matrix G01;
[0191] Step 3:
[0192] Accelerator 3 merges matrix F00 and matrix F10 to obtain matrix [F00, F10];
[0193] Accelerator 3 merges matrix F11 and matrix F01 to obtain matrix [G01, G11].
[0194] It should be noted that Figure 7 In each step of the corresponding embodiment, the matrix multiplication operation performed by the accelerator is implemented by the communication scheduling engine or the computing scheduling engine calling the computing unit to execute the matrix multiplication operator in the communication task; the sending operation performed by the accelerator is implemented by the communication scheduling engine calling the communication unit to execute the communication operator in the communication task. Among them, when the accelerator performs both the sending operation and the computing operation in one step, the communication scheduling engine of the accelerator calls the communication unit to execute the communication operator while the communication scheduling engine calls the computing unit to execute the computing operator, or the communication scheduling engine notifies the computing scheduling engine to call the computing unit to execute the computing operator.
[0195] By comparing the above Figure 6 , Figure 7 and a description of the steps involved, Figure 6 and Figure 7 Each accelerator sends data the same number of times and the length of each transmission is the same, but Figure 7 In the corresponding process, the accelerator completes the multiplication calculation of some matrices while sending data, realizing the execution of calculation operations while sending data, improving the utilization rate of the accelerator's resources and making Figure 7 In the corresponding embodiment, the amount of data that needs to be matrix multiplied after the data is sent is less, so Figure 7 The corresponding process takes less time and can improve the efficiency of distributed computing.
[0196] For the above method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described order of actions. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the present invention. Other reasonable step combinations that can be thought of by those skilled in the art based on the above description also fall within the scope of protection of the present invention.
[0197] The present application also provides an accelerator, such as Figure 8 As shown, Figure 8800 includes a communication scheduling engine 810, a communication unit 820, a computing scheduling engine 830, a computing unit 840, and a storage unit 850. The storage unit 850 is used to store data or instructions, such as storing an intermediate representation obtained from a processor, storing data calculated by the computing unit 840, and storing data received from other accelerators. For another example, in the case where the above-mentioned intermediate representation is an intermediate representation corresponding to a model training task, the storage unit 850 can store model parameters and training data for training the model.
[0198] The operations performed by the communication scheduling engine 810, the communication unit 820, the computing scheduling engine 830, and the computing unit 840 in the accelerator 800 can refer to the above Figure 1 or Figure 2 The relevant descriptions in the corresponding embodiments are not repeated here.
[0199] The present application also provides a computing device, such as Fig. 9 As shown, Fig. 9 9 is a schematic diagram of a computing device provided in an embodiment of the present application. The computing device 900 includes one or more processors 910, one or more accelerators 800, a communication interface 920, and a memory 930, wherein the processor 910, one or more accelerators 800, the communication interface 920, and the memory 930 are interconnected via a bus 940, wherein:
[0200] The processor 910 may be a CPU, and the accelerator 800 may be a GPU, NPU, TPU, or a dedicated AI processing chip. The operations performed by the processor 910 may refer to the above Figure 1 or Figure 2 The operations performed by the general processor in the corresponding embodiment and the operations performed by the accelerator 800 can refer to the above Figure 1 or Figure 2 The operations performed by the accelerator in the corresponding embodiment will not be described in detail here.
[0201] The communication interface 920 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface.
[0202] The memory 930 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 930 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).
[0203] The memory 930 may also be used to store program codes and data, so that the processor 910 calls the program instructions stored in the memory 930 to execute the operation steps performed by the general processor in the above method embodiment. Fig. 9 Show more or fewer components, or have different component configurations.
[0204] The bus 940 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus 940 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 9 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.
[0205] Specifically, the specific implementation of the above-mentioned computing device 900 to perform various operations can refer to the above-mentioned Figure 1 or Figure 2 The specific operations performed in the corresponding embodiments are not described in detail here.
[0206] An embodiment of the present application also provides a computer-readable storage medium, in which instructions are stored. When the computer-readable storage medium is executed on a processor, the method steps implemented by the evaluation device in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations of the above method embodiment, which will not be repeated here.
[0207] An embodiment of the present application also provides a computer-readable storage medium, in which instructions are stored. When the computer-readable storage medium is executed on a processor, the method steps implemented by the management device in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations of the above method embodiment, which will not be repeated here.
[0208] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0209] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium, or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.
[0210] The steps in the method of the embodiment of the present application can be adjusted in order, combined or deleted according to actual needs; the modules in the device of the embodiment of the present application can be divided, combined or deleted according to actual needs.
[0211] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of the present application. At the same time, for general technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
[0212] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the protection scope of the technical solutions of the embodiments of the present invention.
Claims
1. An accelerator, characterized in that: It includes a communication scheduling engine, a communication unit, a computing scheduling engine and a computing unit, wherein: The communication scheduling engine is used to obtain an intermediate representation, where the intermediate representation is used to represent a model reasoning task or a model training task, where the intermediate representation includes a communication task, where the communication task indicates to perform a collective communication, and where the communication task includes a plurality of communication operators and a plurality of computing operators; The communication scheduling engine is also used to call the communication unit to execute the first communication operator among the multiple communication operators according to the intermediate representation, and call the computing unit to execute the computing operator in the communication task or notify the computing scheduling engine so that the computing scheduling engine schedules the computing unit to execute the computing operator in the communication task.
2. The accelerator according to claim 1, characterized in that The intermediate representation also includes computational tasks, The computing scheduling engine is used to call the computing unit to execute the computing task according to the intermediate representation.
3. The accelerator according to claim 2, characterized in that The communication scheduling engine is further configured to send notification information to the computing scheduling engine when the communication task is completed; The computing scheduling engine is further configured to execute the computing task following the communication task in the intermediate representation upon receiving the notification information.
4. The accelerator according to claim 2, characterized in that: The computing scheduling engine is further configured to send notification information to the communication scheduling engine when the computing task is completed; The communication scheduling engine is further configured to execute the communication task following the computing task in the intermediate representation upon receiving the notification information.
5. The accelerator according to any one of claims 1 to 4, characterized in that: The communication task in the intermediate representation is generated by a processor calling a first function, where the input of the first function is a collective communication identifier.
6. The accelerator according to any one of claims 1 to 5, characterized in that: The communication task is a global reduction allreduce or a global collection allgather.
7. The accelerator according to claim 6, characterized in that When the communication task is allreduce, the computing operator includes a quantization operator and a dequantization operator; wherein each quantization operator is used to perform a quantization operation on part of the data in the accelerator.
8. The accelerator according to claim 6, characterized in that When the communication task is allgather, the calculation operator includes a matrix multiplication operator.
9. The accelerator according to any one of claims 1 to 8, characterized in that: The accelerator is a graphics processor GPU, a neural network processor NPU, a tensor processor TPU or a dedicated artificial intelligence AI processing chip.
10. A data processing method, characterized in that: Applied to a computing device, the computing device includes a communication scheduling engine, a communication unit, a computing scheduling engine and a computing unit, the method includes: The communication scheduling engine obtains an intermediate representation, where the intermediate representation is used to represent an inference task or a model training task, where the intermediate representation includes a communication task, where the communication task indicates to perform a collective communication, and where the communication task includes a plurality of communication operators and a plurality of computing operators; The communication scheduling engine calls the communication unit to execute the first communication operator among the multiple communication operators according to the intermediate representation, and calls the computing unit to execute the computing operator in the communication task or notifies the computing scheduling engine so that the computing scheduling engine schedules the computing unit to execute the computing operator in the communication task.
11. The method according to claim 10, characterized in that The intermediate representation also includes a computing task, and the method further includes: The computing scheduling engine calls the computing unit to execute the computing task according to the intermediate representation.
12. The method according to claim 11, characterized in that The computing scheduling engine calls the computing unit to execute the computing task according to the intermediate representation, including: The communication scheduling engine sends notification information to the computing scheduling engine when the communication task is completed; Upon receiving the notification information, the computing scheduling engine executes the computing task following the communication task in the intermediate representation.
13. The method according to claim 11, characterized in that The method further comprises: The computing scheduling engine sends notification information to the communication scheduling engine when the computing task is completed; Upon receiving the notification information, the communication scheduling engine executes the communication task following the computing task in the intermediate representation.
14. The method according to any one of claims 10 to 13, characterized in that: The communication task in the intermediate representation is generated by a processor calling a first function, where the input of the first function is a collective communication identifier.
15. The method according to any one of claims 10 to 14, characterized in that: The communication task is a global reduction allreduce or a global collection allgather.
16. The method according to claim 15, characterized in that When the communication task is allreduce, the computing operator includes a quantization operator and a dequantization operator; wherein each quantization operator is used to perform a quantization operation on part of the data in the accelerator.
17. The method according to claim 15, characterized in that When the communication task is allgather, the calculation operator includes a matrix multiplication operator.
18. The method according to any one of claims 10 to 17, characterized in that: The computing device includes an accelerator, and the computing unit and the communication unit are located in the accelerator; the accelerator is a graphics processor GPU, a neural network processor NPU, a tensor processor TPU or a dedicated artificial intelligence AI processing chip.
19. A computing device, characterized in that The computing device includes a processor, an accelerator and a memory, the memory is used to store instructions, the processor is used to execute the instructions, and when the processor executes the instructions, the accelerator is called to implement the method according to any one of claims 10 to 18.
20. A computer-readable storage medium, characterized in that: The method comprises computer program instructions, which, when executed by a computing device, causes the computing device to perform the method as claimed in any one of claims 10 to 18.