Display panel

Abstract

This application discloses a display panel that displays a first display screen and a second display screen that are displayed continuously. The display panel includes multiple sub-pixels, multiple scan lines, multiple data lines, and a compensation module. The polarity of the first data voltage input to the sub-pixel during the display period of the first display screen is opposite to the polarity of the second data voltage input to the sub-pixel during the display period of the second display screen. The compensation module is electrically connected to one end of the multiple data lines. The compensation module is used to input a first compensation voltage to the sub-pixel during the blank period of the first display screen and to input a second compensation voltage to the sub-pixel during the blank period of the second display screen. The polarity of the first compensation voltage is the same as the polarity of the first data voltage, and the polarity of the second compensation voltage is the same as the polarity of the second data voltage. The first compensation voltage is not zero, and the second compensation voltage is not zero, so as to alleviate the problem of display panel flicker.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel. Background Technology

[0002] In existing display panels, the polarity of the data voltage input to the sub-pixels is opposite in two consecutive displayed frames. Due to leakage current at the source and drain of the switching transistor, the brightness of the sub-pixel gradually decreases after the first frame scan ends. Upon entering the second frame, the input of data voltage of opposite polarity to the sub-pixel increases the voltage difference between the source and drain of the switching transistor, accelerating the leakage rate and causing the sub-pixel brightness to continue decreasing until a significant increase in brightness occurs after the next scan. Therefore, the brightness variation of the display panel between two consecutive displayed frames is significant, leading to a flickering problem. Summary of the Invention

[0003] This application provides a display panel that can solve the problem of flickering caused by large brightness changes in two consecutively displayed frames.

[0004] On one hand, embodiments of this application provide a display panel, the display panel displaying a first display screen and a second display screen displayed continuously. The display panel includes: multiple sub-pixels, multiple scan lines, multiple data lines, and a compensation module. The multiple scan lines are arranged along a first direction and are electrically connected to the multiple sub-pixels respectively. The multiple data lines are arranged along a second direction, the first direction intersecting the second direction, and are electrically connected to the multiple sub-pixels respectively. The data lines input a first data voltage to the sub-pixels during the display period of the first display screen. The polarity of the voltage input to the sub-pixel during the display period of the second display screen is opposite to the polarity of the second data voltage input to the sub-pixel by the data line during the display period of the second display screen. The compensation module is electrically connected to one end of the multiple data lines. The compensation module is used to input a first compensation voltage to the sub-pixel during the blank period of the first display screen and a second compensation voltage to the sub-pixel during the blank period of the second display screen. The polarity of the first compensation voltage is the same as the polarity of the first data voltage, and the polarity of the second compensation voltage is the same as the polarity of the second data voltage. The first compensation voltage is not zero, and the second compensation voltage is not zero.

[0005] Optionally, in some embodiments of this application, the compensation module includes a compensation voltage output terminal, which is electrically connected to one end of the plurality of data lines. The compensation voltage output terminal is used to output the first compensation voltage and the second compensation voltage; the absolute value of the first compensation voltage is less than or equal to the absolute value of the first data voltage, and the absolute value of the second compensation voltage is greater than or equal to the absolute value of the second data voltage.

[0006] Optionally, in some embodiments of this application, the compensation module includes a plurality of switching transistors, the gates of the plurality of switching transistors being electrically connected to a global control signal terminal; one of the source and drain of the switching transistors being electrically connected to the compensation voltage output terminal, and the other of the source and drain of the switching transistors being electrically connected to one end of the data line.

[0007] Optionally, in some embodiments of this application, during the blank period, the on-time of the switching transistor is greater than or equal to the off-time.

[0008] Optionally, in some embodiments of this application, the plurality of data lines include a plurality of first data lines and a plurality of second data lines, with the plurality of first data lines and the plurality of second data lines alternately arranged along the second direction; the first data voltage includes a first positive data voltage and a first negative data voltage, and during the display period of the first display screen, the data voltage input to the sub-pixel by the first data line is the first positive data voltage, and the data voltage input to the sub-pixel by the second data line is the first negative data voltage; the second data voltage includes a second positive data voltage and a second negative data voltage, and during the display period of the second display screen, the data voltage input to the sub-pixel by the first data line is the second negative data voltage, and the data voltage input to the sub-pixel by the second data line is the second positive data voltage.

[0009] Optionally, in some embodiments of this application, the compensation module includes a first compensation voltage output terminal and a second compensation voltage output terminal. The first compensation voltage output terminal is electrically connected to the first data line. The first compensation voltage includes a first positive compensation voltage and a first negative compensation voltage. The first positive compensation voltage is less than or equal to the first positive data voltage, and the first negative compensation voltage is greater than or equal to the first negative data voltage. The second compensation voltage output terminal is electrically connected to the second data line. The second compensation voltage includes a second positive compensation voltage and a second negative compensation voltage. The second positive compensation voltage is less than or equal to the second positive data voltage, and the second negative compensation voltage is greater than or equal to the second negative data voltage.

[0010] Optionally, in some embodiments of this application, the compensation module includes a plurality of first switching transistors and a plurality of second switching transistors, wherein the gates of the plurality of first switching transistors and the gates of the plurality of second switching transistors are electrically connected to a global control signal terminal; one of the source and drain of the first switching transistor is electrically connected to the first compensation voltage output terminal, and the other of the source and drain of the first switching transistor is electrically connected to one end of the first data line; one of the source and drain of the second switching transistor is electrically connected to the second compensation voltage output terminal, and the other of the source and drain of the second switching transistor is electrically connected to one end of the second data line.

[0011] Optionally, in some embodiments of this application, the first switching transistor and the second switching transistor are turned off during the display period and turned on during the blank period.

[0012] Optionally, in some embodiments of this application, the blank period includes a first blank sub-period and a second blank sub-period, the first blank sub-period and the second blank sub-period being adjacent; wherein, the first switching transistor and the second switching transistor are turned on in the first blank sub-period and turned off in the second blank sub-period; or, the first switching transistor and the second switching transistor are turned on in the second blank sub-period and turned off in the first blank sub-period.

[0013] Optionally, in some embodiments of this application, the compensation module includes a plurality of first switching transistors and a plurality of second switching transistors. The gates of the plurality of first switching transistors are electrically connected to a first control signal terminal, and the gates of the plurality of second switching transistors are electrically connected to a second control signal terminal. One of the source and drain of the first switching transistor is electrically connected to the first compensation voltage output terminal, and the other of the source and drain of the first switching transistor is electrically connected to one end of the first data line. One of the source and drain of the second switching transistor is electrically connected to the second compensation voltage output terminal, and the other of the source and drain of the second switching transistor is electrically connected to one end of the second data line.

[0014] Optionally, in some embodiments of this application, the blank period includes a first blank sub-period, a second blank sub-period, and a third blank sub-period, wherein the second blank sub-period is located between the first blank sub-period and the third blank sub-period; the first switching transistor is turned on in the first blank sub-period and the second blank sub-period, and the first switching transistor is turned off in the third blank sub-period; the second switching transistor is turned on in the second blank sub-period and the third blank sub-period, and the second switching transistor is turned off in the first blank sub-period.

[0015] Optionally, in some embodiments of this application, the blank period includes a plurality of first blank sub-periods and a plurality of second blank sub-periods, the first blank sub-periods and the second blank sub-periods alternating; wherein, the first switching transistor is turned on in a plurality of first blank sub-periods, the first switching transistor is turned off in a plurality of second blank sub-periods, the second switching transistor is turned on in a plurality of second blank sub-periods, and the second switching transistor is turned off in a plurality of first blank sub-periods.

[0016] Optionally, in some embodiments of this application, during the blank period, the on-time of the first switching transistor and the second switching transistor is greater than the off-time.

[0017] The display panel provided in this application is electrically connected to one end of multiple data lines via a compensation module. During the blank periods of the first and second consecutively displayed frames, a first compensation voltage is input to the sub-pixels, and a second compensation voltage is input to the sub-pixels during the blank periods of the second frame. This reduces the voltage difference between the source and drain of the sub-pixels during the blank periods, stabilizing the sub-pixel potential, mitigating leakage, and alleviating the problem of significant brightness fluctuations in the display panel between two consecutively displayed frames due to severe leakage between the end of one scan and the beginning of the next scan, which causes flickering. This improves the display effect. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the display panel provided in the first embodiment of this application;

[0019] Figure 2 This is a first driving timing diagram of a display panel provided in an embodiment of this application;

[0020] Figure 3 This is a second driving timing diagram of a display panel provided in an embodiment of this application;

[0021] Figure 4This is a schematic diagram of the display panel provided in the second embodiment of this application;

[0022] Figure 5 This is a third driving timing diagram of the display panel provided in the embodiments of this application;

[0023] Figure 6 This is a fourth driving timing diagram of the display panel provided in the embodiments of this application;

[0024] Figure 7 This is a fifth driving timing diagram of a display panel provided in an embodiment of this application;

[0025] Figure 8 This is a schematic diagram of the display panel provided in the third embodiment of this application;

[0026] Figure 9 This is a sixth driving timing diagram of a display panel provided in an embodiment of this application;

[0027] Figure 10 This is a seventh driving timing diagram of a display panel provided in an embodiment of this application;

[0028] Figure 11 This is a schematic diagram of the display panel provided in the fourth embodiment of this application. Detailed Implementation

[0029] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0030] The various embodiments provided in this application are similar, and the features in different embodiments are combined with each other.

[0031] like Figure 1 As shown, an embodiment of this application provides a display panel 100, wherein the display panel 100 displays a first display screen and a second display screen displayed sequentially. The display panel 100 includes: a plurality of sub-pixels 10, a plurality of scan lines 20, a plurality of data lines 30, and a compensation module 40. The plurality of scan lines 20 are arranged along a first direction Y, and the plurality of scan lines 20 are electrically connected to the plurality of sub-pixels 10 respectively. The plurality of data lines 30 are arranged along a second direction X, the first direction Y intersects the second direction X, the plurality of scan lines 20 are electrically connected to the plurality of sub-pixels 10 respectively, and the polarity of the first data voltage input by the data lines 30 to the sub-pixels 10 during the display period of the first display screen is opposite to the polarity of the second data voltage input by the data lines 30 to the sub-pixels 10 during the display period of the second display screen.

[0032] The compensation module 40 is electrically connected to one end of multiple data lines 30. The compensation module 40 is used to input a first compensation voltage to the sub-pixel 10 during the blank period of the first display screen and to input a second compensation voltage to the sub-pixel 10 during the blank period of the second display screen. The polarity of the first compensation voltage is the same as the polarity of the first data voltage, and the polarity of the second compensation voltage is the same as the polarity of the second data voltage. The first compensation voltage is not zero, and the second compensation voltage is not zero.

[0033] The display panel 100 is electrically connected to one end of multiple data lines 30 via a compensation module 40. During the blank period of the first display screen in the continuously displayed first and second display screens, a first compensation voltage is input to the sub-pixel 10, and a second compensation voltage is input to the sub-pixel 10 during the blank period of the second display screen. This keeps the potential of the sub-pixel 10 stable and improves the problem of the display panel flickering due to the significant brightness change between two continuously displayed frames caused by the severe leakage of the sub-pixel 10 after the end of the scan and before the next scan, followed by a significant increase in brightness after the next scan.

[0034] In an embodiment of this application, the compensation module 40 includes a compensation voltage output terminal V0, which is electrically connected to one end of a plurality of data lines 30. The compensation voltage output terminal V0 is used to output a first compensation voltage and a second compensation voltage. The absolute value of the first compensation voltage is less than or equal to the absolute value of the first data voltage, and the absolute value of the second compensation voltage is greater than or equal to the absolute value of the second data voltage.

[0035] Specifically, when the first data voltage is a positive polarity data voltage, for example, the first data voltage is 2 volts, then the first compensation voltage is greater than 0 volts and less than or equal to 2 volts, for example, the first compensation voltage is 1.5 volts. When the first data voltage is a negative polarity data voltage, for example, the first data voltage is -2 volts, then the first compensation voltage is less than 0 volts and greater than or equal to -2 volts, for example, the first compensation voltage is -1.5 volts.

[0036] The absolute value of the first compensation voltage is equal to the absolute value of the second compensation voltage.

[0037] In embodiments of this application, the compensation module 40 includes a plurality of switching transistors T0, the gates of which are electrically connected to the global control signal terminal GAS0. One of the source and drain of the switching transistor T0 is electrically connected to the compensation voltage output terminal V0, and the other of the source and drain of the switching transistor T0 is electrically connected to one end of the data line 30.

[0038] In embodiments of this application, the display panel further includes a gate driving circuit 50 and a source driving circuit 60. The gate driving circuit 50 is electrically connected to multiple scan lines 20 and is used to provide scan signals to the sub-pixels 10. The source driving circuit 60 is electrically connected to the other end of multiple data lines 30 and is used to provide data voltage to the sub-pixels 10.

[0039] In the embodiments of this application, during the blank period, the on-time of the switching transistor T0 is greater than or equal to the off-time.

[0040] like Figure 1 and Figure 2 As shown, during the display period t01, the global control signal terminal GAS0 receives a low-level global control signal gas0. During the blank period t02, the global control signal terminal GAS0 receives a high-level global control signal gas0. The switching transistor T0 remains on during the blank period t02.

[0041] like Figure 1 and Figure 3 As shown, during the display period t01, the global control signal terminal GAS0 receives a low-level global control signal gas0. During a portion of the blank period t02, the global control signal terminal GAS0 receives a high-level global control signal gas0. The switching transistor T0 is turned on under the control of the high-level global control signal gas0. The portion of the blank period t02 includes any period within the blank period t02.

[0042] like Figure 4 As shown, an embodiment of this application provides a display panel 200. The difference between display panel 200 and display panel 100 is that the multiple data lines 30 include multiple first data lines 31 and multiple second data lines 32. The compensation module 40 includes a first compensation voltage output terminal V1, a second compensation voltage output terminal V2, multiple first switching transistors T1, and multiple second switching transistors T2. The first compensation voltage output terminal V1 is electrically connected to the first switching transistors T1 and the first data lines 31, and the second compensation voltage output terminal V2 is electrically connected to the second switching transistors T2 and the second data lines 32.

[0043] Specifically, the display panel 200 displays a first display screen and a second display screen that are displayed consecutively. The display panel 200 includes multiple sub-pixels 10, multiple scan lines 20, multiple data lines 30, and a compensation module 40. The multiple scan lines 20 are arranged along a first direction Y and are electrically connected to the multiple sub-pixels 10 respectively. The multiple data lines 30 are arranged along a second direction X, where the first direction Y intersects with the second direction X. The multiple scan lines 20 are electrically connected to the multiple sub-pixels 10 respectively. The polarity of the first data voltage input by the data lines 30 to the sub-pixels 10 during the display period of the first display screen is opposite to the polarity of the second data voltage input by the data lines 30 to the sub-pixels 10 during the display period of the second display screen.

[0044] The multiple data lines 30 include multiple first data lines 31 and multiple second data lines 32, which are alternately arranged along a second direction X. The first data voltage includes a first positive data voltage and a first negative data voltage. During the display period of the first display screen, the data voltage input to the sub-pixel 10 by the first data line 31 is the first positive data voltage, and the data voltage input to the sub-pixel 10 by the second data line 32 is the first negative data voltage. The second data voltage includes a second positive data voltage and a second negative data voltage. During the display period of the second display screen, the data voltage input to the sub-pixel 10 by the first data line 31 is the second negative data voltage, and the data voltage input to the sub-pixel 10 by the second data line 32 is the second positive data voltage.

[0045] In embodiments of this application, the compensation module 40 includes a first compensation voltage output terminal V1 and a second compensation voltage output terminal V2. The first compensation voltage output terminal V1 is electrically connected to the first data line 31. The first compensation voltage includes a first positive compensation voltage and a first negative compensation voltage. The first positive compensation voltage is less than or equal to the first positive data voltage, and the first negative compensation voltage is greater than or equal to the first negative data voltage. For example, if the first positive data voltage is 2 volts, then the first positive compensation voltage is greater than 0 volts and less than or equal to 2 volts; for example, the first positive compensation voltage is 1.5 volts. If the first negative data voltage is -2 volts, then the first negative compensation voltage is less than 0 volts and greater than or equal to -2 volts; for example, the first negative compensation voltage is -1.5 volts.

[0046] The second compensation voltage output terminal V2 is electrically connected to the second data line 32. The second compensation voltage includes a second positive compensation voltage and a second negative compensation voltage. The second positive compensation voltage is less than or equal to the second positive data voltage, and the second negative compensation voltage is greater than or equal to the second negative data voltage.

[0047] For example, if the second positive data voltage is 2 volts, then the second positive compensation voltage is greater than 0 volts and less than or equal to 2 volts; for example, the second positive compensation voltage is 1 volt. If the second negative data voltage is -2 volts, then the second negative compensation voltage is less than 0 volts and greater than or equal to -2 volts; for example, the second negative compensation voltage is -1 volt.

[0048] In embodiments of this application, the compensation module 40 includes a plurality of first switching transistors T1 and a plurality of second switching transistors T2. The gates of the plurality of first switching transistors T1 and the gates of the plurality of second switching transistors T2 are all electrically connected to the global control signal terminal GAS0. One of the source and drain of the first switching transistor T1 is electrically connected to the first compensation voltage output terminal V1, and the other of the source and drain of the first switching transistor T1 is electrically connected to one end of the first data line 31. One of the source and drain of the second switching transistor T2 is electrically connected to the second compensation voltage output terminal V2, and the other of the source and drain of the second switching transistor T2 is electrically connected to one end of the second data line 32.

[0049] In the embodiments of this application, the first switching transistor T1 and the second switching transistor T2 are turned off during the display period, and the first switching transistor T1 and the second switching transistor T2 are turned on during the blank period.

[0050] like Figure 5 As shown, the global control signal terminal GAS0 receives a low-level global control signal gas0 during the display period t01, and the first switching transistor T1 and the second switching transistor T2 are turned off. The blank period t02 includes a first blank sub-period t001 and a second blank sub-period t002, which are adjacent and have the same duration. During the first blank sub-period t001, the global control signal terminal GAS0 receives a high-level global control signal gas0, and the first switching transistor T1 and the second switching transistor T2 are turned on. During the second blank sub-period t002, the global control signal terminal GAS0 receives a low-level global control signal gas0, and the first switching transistor T1 and the second switching transistor T2 are turned off.

[0051] like Figure 6As shown, the global control signal terminal GAS0 receives a low-level global control signal gas0 during the display period t01, and the first switching transistor T1 and the second switching transistor T2 are turned off. The blank period t02 includes a first blank sub-period t001 and a second blank sub-period t002, which are adjacent and have the same duration. During the first blank sub-period t001, the global control signal terminal GAS0 receives a low-level global control signal gas0, and the first switching transistor T1 and the second switching transistor T2 are turned off. During the second blank sub-period t002, the global control signal terminal GAS0 receives a high-level global control signal gas0, and the first switching transistor T1 and the second switching transistor T2 are turned on.

[0052] like Figure 7 As shown, during the blank period t02, the on-time of the first switching transistor T1 and the second switching transistor T2 is longer than their off-time. This ensures that the duration of the compensation voltage received by the sub-pixel on the data line electrically connected to the first switching transistor T1 is long enough, thereby improving the stability of the sub-pixel potential, and the duration of the compensation voltage received by the sub-pixel on the data line electrically connected to the second switching transistor T2 is long enough, thereby improving the stability of the sub-pixel potential.

[0053] Specifically, the blank period t02 includes a first blank sub-period t001 and a second blank sub-period t002, which are adjacent to each other. The duration of the first blank sub-period t001 is longer than the duration of the second blank sub-period t002.

[0054] In the embodiments of this application, the global control signal terminal GAS0 receives a low-level global control signal gas0 during the display period t01, and the first switching transistor T1 and the second switching transistor T2 are turned off. The blank period includes a first blank sub-period t001 and a second blank sub-period t002, which are adjacent. During the first blank sub-period t001, the global control signal terminal GAS0 receives a high-level global control signal gas0, and the first switching transistor T1 and the second switching transistor T2 are turned on during the first blank sub-period t001. During the second blank sub-period t002, the global control signal terminal GAS0 receives a low-level global control signal gas0, and the first switching transistor T1 and the second switching transistor T2 are turned off during the second blank sub-period t002.

[0055] Alternatively, if the duration of the second blank sub-period t002 is greater than the duration of the first blank sub-period t001, then both the first switching transistor T1 and the second switching transistor T2 are turned on in the second blank sub-period t002 and turned off in the first blank sub-period t001.

[0056] like Figure 8 As shown, an embodiment of this application provides a display panel 300. The difference between the display panel 300 and the display panel 200 is that the gates of a plurality of first switching transistors T1 are electrically connected to a first control signal terminal GAS1, and the gates of a plurality of second switching transistors T2 are electrically connected to a second control signal terminal GAS2.

[0057] Specifically, the compensation module 40 includes multiple first switching transistors T1 and multiple second switching transistors T2. The gates of the multiple first switching transistors T1 are electrically connected to a first control signal terminal GAS1, and the gates of the multiple second switching transistors T2 are electrically connected to a second control signal terminal GAS2. One of the source and drain of the first switching transistor T1 is electrically connected to a first compensation voltage output terminal V1, and the other of the source and drain of the first switching transistor T1 is electrically connected to one end of a first data line 31. One of the source and drain of the second switching transistor T2 is electrically connected to a second compensation voltage output terminal V2, and the other of the source and drain of the second switching transistor T2 is electrically connected to one end of a second data line 32.

[0058] The other structures of display panel 300 are the same as those of display panel 200.

[0059] like Figure 8 As shown, the first switching transistor T1 and the second switching transistor T2 are of the same type, and the first switching transistor T1 is an N-type transistor.

[0060] like Figure 9 As shown, the blank period includes multiple first blank sub-periods t001 and multiple second blank sub-periods t002. The first blank sub-periods t001 and the second blank sub-periods t002 alternate. The first switching transistor T1 is turned on in multiple first blank sub-periods t001, and the second switching transistor T2 is turned on in multiple second blank sub-periods t002.

[0061] Specifically, during the display period, the first control signal terminal GAS1 receives a low-level first control signal gas1, and the first switching transistor T1 is turned off. During the display period, the second control signal terminal GAS2 receives a low-level second control signal gas2, and the second switching transistor T2 is turned off. During multiple first blank sub-periods t001, the first control signal terminal GAS1 receives a high-level first control signal gas1, and the first switching transistor T1 is turned on during these multiple blank sub-periods t001. During multiple second blank sub-periods t002, the first control signal terminal GAS1 receives a low-level first control signal gas1, and the first switching transistor T1 is turned off during these multiple blank sub-periods t002. During multiple second blank sub-periods t002, the second control signal terminal GAS2 receives a high-level second control signal gas2, and the second switching transistor T2 is turned on during these multiple blank sub-periods t002. During multiple first blank sub-periods t001, the second switching transistor T2 is turned off during these multiple blank sub-periods t001.

[0062] like Figure 10 As shown, the blank time period includes a first blank sub-time period t001, a second blank sub-time period t002, and a third blank sub-time period t003, with the second blank sub-time period t002 located between the first blank sub-time period t001 and the third blank sub-time period t003. The first switching transistor T1 is turned on in both the first blank sub-time period t001 and the second blank sub-time period t002, and the second switching transistor T2 is turned on in both the second blank sub-time period t002 and the third blank sub-time period t003.

[0063] Specifically, during the display period, the first control signal terminal GAS1 receives a low-level first control signal gas1, and the second control signal terminal GAS2 receives a low-level second control signal gas2. The first switching transistor T1 and the second switching transistor T2 are turned off. During the first blank sub-period t001 and the second blank sub-period t002, the first control signal terminal GAS1 receives a high-level first control signal gas1, and the first switching transistor T1 is turned on. During the third blank sub-period t003, the first control signal terminal GAS1 receives a low-level first control signal gas1, and the first switching transistor T1 is turned off. During the first blank sub-period t001, the second control signal terminal GAS2 receives a low-level second control signal gas2, and the second switching transistor T2 is turned off. During the second blank sub-period t002 and the third blank sub-period t003, the second switching transistor T2 is turned on.

[0064] like Figure 11As shown, an embodiment of this application provides a display panel 400. The difference between display panel 400 and display panel 300 is that one of the first switching transistor T1 and the second switching transistor T2 is an N-type transistor, and the other of the first switching transistor T1 and the second switching transistor T2 is a P-type transistor. This allows for greater diversity in the circuit configuration of the compensation module 40. For example, the first switching transistor T1 and the second switching transistor T2 can be electrically connected to the first control signal terminal GAS1 and the second control signal terminal GAS2 respectively, or they can be electrically connected to the same control signal terminal, thereby reducing the space occupied by the compensation module 40 and the number of signal lines.

[0065] The other structures of display panel 400 are the same as those of display panel 300.

[0066] An embodiment of this application also provides a display device, which includes a display panel and a frame, with the display panel disposed within the frame.

[0067] The above provides a detailed description of a display panel provided by the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the core ideas of this application, and the above description should not be construed as a limitation on the scope of protection of this application.

Claims

1. A display panel, characterized in that, The display panel displays images including a first display image and a second display image displayed consecutively. The display panel includes: Multiple sub-pixels; Multiple scan lines are arranged along a first direction, and each scan line is electrically connected to a plurality of sub-pixels. Multiple data lines are arranged along a second direction, the first direction intersects the second direction, and the multiple data lines are electrically connected to multiple sub-pixels respectively. The polarity of the first data voltage input by the data lines to the sub-pixels during the display period of the first display screen is opposite to the polarity of the second data voltage input by the data lines to the sub-pixels during the display period of the second display screen. A compensation module is electrically connected to one end of the plurality of data lines. The compensation module is used to input a first compensation voltage to the sub-pixel during the blank period of the first display screen and to input a second compensation voltage to the sub-pixel during the blank period of the second display screen. The polarity of the first compensation voltage is the same as the polarity of the first data voltage, and the polarity of the second compensation voltage is the same as the polarity of the second data voltage. Wherein, the first compensation voltage is not zero, and the second compensation voltage is not zero; The compensation module includes a compensation voltage output terminal, which is electrically connected to one end of the plurality of data lines. The compensation voltage output terminal is used to output the first compensation voltage and the second compensation voltage. The absolute value of the first compensation voltage is less than or equal to the absolute value of the first data voltage, and the absolute value of the second compensation voltage is greater than or equal to the absolute value of the second data voltage.

2. The display panel according to claim 1, characterized in that, The compensation module includes multiple switching transistors, and the gates of the multiple switching transistors are electrically connected to the global control signal terminal; One of the source and drain of the switching transistor is electrically connected to the compensation voltage output terminal, and the other of the source and drain of the switching transistor is electrically connected to one end of the data line.

3. The display panel according to claim 2, characterized in that, During the blank period, the on-time of the switching transistor is greater than or equal to the off-time.

4. The display panel according to claim 1, characterized in that, The multiple data lines include multiple first data lines and multiple second data lines, with the multiple first data lines and multiple second data lines alternately arranged along the second direction; The first data voltage includes a first positive data voltage and a first negative data voltage. During the display period of the first display screen, the data voltage of the sub-pixel input by the first data line is the first positive data voltage, and the data voltage of the sub-pixel input by the second data line is the first negative data voltage. The second data voltage includes a second positive data voltage and a second negative data voltage. During the display period of the second display screen, the first data line inputs the second negative data voltage to the sub-pixel, and the second data line inputs the second positive data voltage to the sub-pixel.

5. The display panel according to claim 4, characterized in that, The compensation module includes a first compensation voltage output terminal and a second compensation voltage output terminal. The first compensation voltage output terminal is electrically connected to the first data line. The first compensation voltage includes a first positive compensation voltage and a first negative compensation voltage. The first positive compensation voltage is less than or equal to the first positive data voltage, and the first negative compensation voltage is greater than or equal to the first negative data voltage. The second compensation voltage output terminal is electrically connected to the second data line. The second compensation voltage includes a second positive compensation voltage and a second negative compensation voltage. The second positive compensation voltage is less than or equal to the second positive data voltage, and the second negative compensation voltage is greater than or equal to the second negative data voltage.

6. The display panel according to claim 5, characterized in that, The compensation module includes multiple first switching transistors and multiple second switching transistors, and the gates of the multiple first switching transistors and the multiple second switching transistors are electrically connected to the global control signal terminal. One of the source and drain of the first switching transistor is electrically connected to the first compensation voltage output terminal, and the other of the source and drain of the first switching transistor is electrically connected to one end of the first data line. One of the source and drain of the second switching transistor is electrically connected to the second compensation voltage output terminal, and the other of the source and drain of the second switching transistor is electrically connected to one end of the second data line.

7. The display panel according to claim 6, characterized in that, The first and second switching transistors are turned off during the display period and turned on during the blank period.

8. The display panel according to claim 7, characterized in that, The blank period includes a first blank sub-period and a second blank sub-period, wherein the first blank sub-period and the second blank sub-period are adjacent; Wherein, the first switching transistor and the second switching transistor are turned on during the first blank sub-period, and the first switching transistor and the second switching transistor are turned off during the second blank sub-period; or... The first switching transistor and the second switching transistor are turned on during the second blank sub-period, and the first switching transistor and the second switching transistor are turned off during the first blank sub-period.

9. The display panel according to claim 5, characterized in that, The compensation module includes a plurality of first switching transistors and a plurality of second switching transistors. The gates of the plurality of first switching transistors are electrically connected to a first control signal terminal, and the gates of the plurality of second switching transistors are electrically connected to a second control signal terminal. One of the source and drain of the first switching transistor is electrically connected to the first compensation voltage output terminal, and the other of the source and drain of the first switching transistor is electrically connected to one end of the first data line. One of the source and drain of the second switching transistor is electrically connected to the second compensation voltage output terminal, and the other of the source and drain of the second switching transistor is electrically connected to one end of the second data line.

10. The display panel according to claim 9, characterized in that, The blank period includes a first blank sub-period, a second blank sub-period, and a third blank sub-period, with the second blank sub-period located between the first blank sub-period and the third blank sub-period; The first switching transistor is turned on during the first blank sub-period and the second blank sub-period, and the first switching transistor is turned off during the third blank sub-period. The second switching transistor is turned on during the second blank sub-period and the third blank sub-period, and the second switching transistor is turned off during the first blank sub-period.

11. The display panel according to claim 9, characterized in that, The blank period includes multiple first blank sub-periods and multiple second blank sub-periods, with the first blank sub-periods and the second blank sub-periods alternating; In this configuration, the first switching transistor is turned on during multiple first blank sub-periods, the first switching transistor is turned off during multiple second blank sub-periods, the second switching transistor is turned on during multiple second blank sub-periods, and the second switching transistor is turned off during multiple first blank sub-periods.

12. The display panel according to any one of claims 8 to 11, characterized in that, During the blank period, the on-time of the first switching transistor and the second switching transistor is greater than the off-time.

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