Data verification and decoding method, verification circuit, JESD204C interface and analog-to-digital converter

Abstract

The invention discloses a data verification and decoding method, a verification circuit, a JESD204C interface and an analog-to-digital converter, and the coding method comprises the steps: receiving to-be-coded data which is one or more of a plurality of data blocks; and according to a data coding demand, coding the to-be-coded data based on a cyclic redundancy check method to obtain a coding sequence. On the basis of a traditional 64B / 66B coding check circuit, the advantages of the coding check circuit are reserved, and the problem that in the traditional circuit, the delay of a check code is large in actual work is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a data verification and decoding method, a verification circuit, a JESD204C interface, and an analog-to-digital converter. Background Art

[0002] In the JESD204C protocol, 64B / 66B encoding is not an encoding of the scrambled data to improve DC balance, but an error monitoring mechanism and means of establishing a data link. The protocol specifies three error monitoring methods, including: cyclic redundancy check CRC3 (hereinafter referred to as CRC3 encoding), cyclic redundancy check CRC12 (hereinafter referred to as CRC12 encoding), and forward error correction code FEC (hereinafter referred to as FEC encoding). The characteristics of CRC3 encoding are low hardware consumption and low latency, but the error detection effect is relatively poor compared to CRC12 encoding and FEC encoding, and it is generally not used. Forward error correction code FEC is an optional option that can greatly improve accuracy in scenarios with relatively high accuracy requirements. Compared with FEC encoding, CRC12 encoding has low latency, is easy to implement, and has a command channel interface, so it is widely used.

[0003] The 64B / 66B encoding process can be mainly divided into two parts: calculating the CRC12 checksum and generating the frame header stream. Figure 1 As shown. Figure 1 In the encoding process shown, 32 blocks in the traditional 64B / 66B encoding check circuit multi-block MB_N enter the CRC calculation circuit in sequence. After all 32 blocks are moved into the circuit, a 12-bit check code is obtained, and then it is encoded into the frame header stream of the next multi-block MB_N+1. In this way, a large delay will be generated when it is necessary to determine the check code of the first data block or decode the code. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present application provides a data verification and decoding method, a verification circuit, a JESD204C interface and an analog-to-digital converter to solve at least one defect in the prior art.

[0005] To achieve the above objectives and other objectives, the present application provides a data verification method, the encoding method comprising:

[0006] Receiving data to be encoded, wherein the data to be encoded is one or more of a plurality of data blocks;

[0007] According to the data encoding requirements, the encoded data is checked based on the cyclic redundancy check method to obtain a check code sequence.

[0008] In an embodiment of the present invention, the plurality of data blocks in the to-be-encoded data are continuous data blocks.

[0009] In one embodiment of the present invention, the check code sequence includes: a 12-bit CRC12 check code, a command signal, multiple block stop bits and a fixed combination of "0" and "1", totaling 32 bits of data.

[0010] In an embodiment of the present invention, when the data to be encoded is one of a plurality of data blocks, the data block is the first data block.

[0011] In one embodiment of the present invention, when the data to be encoded is all data blocks in a plurality of data blocks, the plurality of data blocks are sequentially input into a data encoding module, and the data encoding module verifies the plurality of data blocks based on a cyclic redundancy check method to obtain a check code sequence.

[0012] In one embodiment of the present invention, the method also includes: encoding the verified data and outputting a coding sequence, the coding sequence having multiple data blocks, each of the data blocks including a two-bit frame header and data to be encoded, the two-bit frame header being one of a 12-bit CRC12 check code, a command signal, a multi-block termination bit and a fixed "0" or "1" combination, and the two-bit frame header of each data block is different.

[0013] To achieve the above purpose and other purposes, the present application provides a data decoding method, which includes: decoding the coding sequence.

[0014] To achieve the above objectives and other objectives, the present application provides a data verification circuit, including:

[0015] A data receiving module, used for receiving data to be encoded, wherein the data to be encoded is one or more of a plurality of data blocks;

[0016] The data verification module is used to verify the encoded data based on the cyclic redundancy check method according to the data encoding requirements to obtain a verification code sequence.

[0017] To achieve the above objectives and other objectives, the present application provides a JESD204C interface, including the verification circuit.

[0018] To achieve the above objectives and other objectives, the present application provides an analog-to-digital converter, including the JESD204C interface.

[0019] Beneficial effects of this application:

[0020] The present application discloses a data encoding method, the encoding method comprising: receiving data to be encoded, the data to be encoded being one or more of a plurality of data blocks; encoding the data to be encoded based on a cyclic redundancy check method to obtain a coding sequence according to data encoding requirements. The present invention retains the advantages of the coding verification circuit on the basis of the traditional 64B / 66B coding verification circuit, and solves the problem of large delay of the verification code in the traditional circuit in actual work.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0023] Figure 1 It is a schematic diagram of 64B / 66B encoding in the prior art;

[0024] Figure 2 This is a schematic diagram of 64B / 66B encoding according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0026] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application, and thus the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0027] Although the terms "first", "second", "A", and "B", etc. may be used herein to describe various elements, these elements should not be limited by these terms and are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the following technology. The term "and / or" includes a combination of multiple related items or any of the multiple related items.

[0028] As used herein, unless the context indicates otherwise, the singular form is intended to include the plural form, and it will be understood that the term "comprising" means the presence of stated features, quantities, steps, operations, elements, or combinations thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0029] Before the detailed description, it is intended to clarify that the division of components in this specification is divided only by the main function of each component. That is, two or more components to be described below can be combined into one component, or can be divided into two or more components according to more detailed functions. In addition to the main function of the component, each component to be described below can also perform some or all of the functions of other components, and some of the main functions of each component can be exclusively performed by other components.

[0030] In the JESD204C protocol, 64B / 66B encoding is not an encoding of the scrambled data to improve DC balance, but an error monitoring mechanism and means of establishing a data link. The protocol specifies three error monitoring methods, including: cyclic redundancy check CRC3 (hereinafter referred to as CRC3 encoding), cyclic redundancy check CRC12 (hereinafter referred to as CRC12 encoding), and forward error correction code FEC (hereinafter referred to as FEC encoding). The characteristics of CRC3 encoding are low hardware consumption and low latency, but the error detection effect is relatively poor compared to CRC12 encoding and FEC encoding, and it is generally not used. Forward error correction code FEC is an optional option that can greatly improve accuracy in scenarios with relatively high accuracy requirements. Compared with FEC encoding, CRC12 encoding has low latency, is easy to implement, and has a command channel interface, so it is widely used.

[0031] The 64B / 66B encoding process can be mainly divided into two parts: calculating the CRC12 checksum and generating the frame header stream. Figure 1As shown, the encoder inputs a 64B data stream, and every 32 64-bit scrambled data blocks form multiple data blocks MB_N. Blocks MB_N_Block0...MB_N_Block31 enter the CRC calculation circuit in turn. After 64 frame clock cycles, a 12-bit CRC12 check code CRC[0]...CRC

[11] can be obtained. In addition, the protocol stipulates that before each multi-block in the CRC calculation circuit, the shift register should be set to "0". The CRC check code, command signal (CMD), multi-block end bit (EoEMB) and fixed "0" and "1" are 32 bits in total, and each bit is encoded as a two-bit frame header. The encoder outputs a 2-bit frame header and the 64-bit data of the next multi-block MB_N+1 in parallel to form a 66B data stream.

[0032] exist Figure 1 In the encoding process shown, the 32 blocks in the traditional 64B / 66B encoding check circuit multi-block MB_N enter the CRC calculation circuit in sequence. After all 32 blocks are moved into the circuit, a 12-bit check code is obtained, and then it is encoded into the frame header stream of the next multi-block MB_N+1. During the decoding process, the minimum delay of CRC-12 to detect a bit error in the first scrambled data bit of the multi-block is 46 blocks.

[0033] In order to reduce this delay, the present invention proposes a 64B / 66B encoding method in the JESD204C interface link layer for high-speed ADC. The encoding circuit principle is as follows: Figure 2 The present application provides a data verification method, the encoding method comprising:

[0034] Receiving data to be encoded, wherein the data to be encoded is one or more of a plurality of data blocks;

[0035] According to the data encoding requirements, the encoded data is checked based on the cyclic redundancy check method to obtain a check code sequence.

[0036] According to data encoding requirements, the present invention can input a data block into the encoding circuit. On the basis of the traditional 64B / 66B encoding verification circuit, the advantages of the encoding verification circuit are retained and the problem of large delay of the verification code in the traditional circuit in actual work is solved.

[0037] It should be noted that the present invention is implemented based on CRC12 encoding, and the CRC12 generating polynomial is: 12 +x 9 +x 8 +x 3 +x 2 +x+1.

[0038] It should be noted that the data encoding requirement may refer to the speed of processing data. If the processing data rate requirement is not too fast, multiple data blocks can be input into the data encoding module in sequence. If the processing data rate requirement is high, the first data block can be input into the data encoding module.

[0039] like Figure 2 As shown, the data to be encoded includes one or more data blocks. When the data to be encoded includes one data block, the data block is the first data block among the multiple data blocks. When the data blocks to be encoded are all the data blocks among the multiple data blocks, the multiple data blocks are sequentially input into the data encoding module (i.e. Figure 2 In the encoding circuit in the embodiment, a data encoding module verifies multiple data blocks based on a cyclic redundancy check method to obtain a check code sequence.

[0040] When the data to be encoded includes multiple data blocks, for example, data blocks MB_N_Block0 ... MB_N_Block31, the multiple data blocks enter sequentially. Figure 2 The CRC calculation circuit in the CRC calculation circuit can obtain the 12-bit CRC12 check code CRC[0]...CRC

[11] after 64 frame clock cycles. When the first data block is checked in this way, 32 data blocks enter the CRC calculation circuit in sequence. After all 32 blocks are moved into the circuit, the 12-bit check code corresponding to the first data block is obtained. The 32-block delay will be generated by reading in 32 data blocks and then calculating the check code.

[0041] For scenarios where data needs to be processed quickly, only the first data block can be checked to obtain the corresponding check code, that is, the first data block is input into the CRC calculation circuit, and the first data block is checked by the CRC12 algorithm. In this way, it can be quickly determined whether there is a problem with the data transmission, without waiting until all data blocks are input before checking. In this way, no 32-block delay is generated during the data transmission process, thereby improving the efficiency of data processing.

[0042] In the embodiment of the present application, the check code sequence includes: a 12-bit CRC12 check code, a command signal, multiple block termination bits and a fixed combination of "0" and "1", totaling 32 bits of data.

[0043] After the data block is CRC-checked, a 12-bit CRC12 check code CRC[0]…CRC

[11] can be generated. In addition, the protocol stipulates that before each data block in the CRC calculation circuit, the shift register should be set to "0". The check code sequence includes the CRC check code, the command signal (CMD), the end-of-multiple-block bit (EoEMB) and a fixed combination of "0" and "1", totaling 32 bits of data, namely, CRC[0], CRC[1], CRC[2], CRC[3], CRC[4], CRC[5], CRC[6], CRC[7], CRC[8], CRC[9], CRC

[10] , CRC

[11] , CMD[0], CMD[1], CMD[2], CMD[3], CMD[4], CMD[5], CMD[6], 01, 10, etc.

[0044] In an embodiment of the present application, the method also includes: encoding the verified data and outputting a coding sequence, the coding sequence having multiple data blocks, each of the data blocks including a two-bit frame header and data to be encoded, the two-bit frame header being one of a 12-bit CRC12 check code, a command signal, a multi-block termination bit and a fixed "0" or "1" combination, and the two-bit frame header of each data block is different.

[0045] like Figure 2 As shown, for a data block, the two-bit frame header can be one of 10, 01, etc., or one of CRC[0], CRC[1], CRC[2], CRC[3], CRC[4], CRC[5], CRC[6], CRC[7], CRC[8], CRC[9], CRC

[10] , CRC

[11] . For example, the two-bit frame header is CRC[0], CRC[0], or CRC[1], CRC[1], or CRC[2], CRC[2], or CRC[3], CRC[3], or CRC[4], CRC[4], or CRC[ 5], CRC[5], or CRC[6], CRC[6], or CRC[7], CRC[7], or CRC[8], CRC[8], or CRC[9], CRC[9], or CRC

[10] , CRC

[10] , or CRC

[11] , CRC

[11] , or CMD[0], CMD[0], or CMD[1], CMD[1], or CMD[2], CMD[2], or CMD[3], CMD[3], or CMD[4], CMD[4], or CMD[5], CMD[5], or CMD[6], CMD[6]. The data to be encoded is MB_N_BLOCK0, MB_N_BLOCK1, ....., MB_N_BLOCK31.

[0046] It should be noted that the next data to be encoded is the data adjacent to the current data to be encoded. For example, if the current data to be encoded is N, the next data to be encoded is N+1. For another example, if the current data to be encoded is: MB_N_BLOCK0, MB_N_BLOCK1, ....., MB_N_BLOCK31, the next data to be encoded is: MB_N+1_BLOCK0, MB_N+1_BLOCK1, ....., MB_N+1_BLOCK31. When the data to be encoded includes multiple data blocks, the verified data is encoded and the 2-bit frame header and the 64-bit data of the next data to be encoded MB_N+1 are output in parallel to form a 66B data stream.

[0047] The present application provides a data verification circuit, comprising:

[0048] A data receiving module, used for receiving data to be encoded, wherein the data to be encoded is one or more of a plurality of data blocks;

[0049] The data verification module is used to verify the encoded data based on the cyclic redundancy check method according to the data encoding requirements to obtain a verification code sequence.

[0050] It should be noted that the data verification circuit provided in the above embodiment and the data verification method provided in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs operations has been described in detail in the method embodiment and will not be repeated here.

[0051] In one embodiment, the present application provides a data decoding method, the decoding method comprising: decoding the coding sequence.

[0052] In one embodiment, the present application provides a JESD204C interface, including the verification circuit.

[0053] In one embodiment, the present application provides an analog-to-digital converter, comprising the JESD204C interface.

[0054] Compared with the 32 block delays caused by the need to read in 32 data blocks and then calculate the check code in the traditional circuit, the present invention can only encode the first data block of multiple data blocks according to the CRC calculation rule, so that the delay of 32 data blocks can be avoided. In addition, since the traditional circuit needs to send the CRC check code of the previous data to be encoded into the first 12 data blocks of the next data to be encoded for transmission and generate 12 block delays, the present invention can directly transmit in the first data block after calculating the check code of the first data block, eliminating the 46 block delays caused by the check coding circuit in the traditional circuit.

[0055] The 64B / 66B check circuit in the JESD204C interface link layer for high-speed ADC proposed in this invention can solve the problem of large delay of the check code in the traditional circuit in actual work without affecting the performance of the traditional coding check circuit, and completely eliminate the original 46 delay blocks, effectively expanding the application scope of the JESD204C circuit.

[0056] The above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A data verification method, characterized in that: The encoding method comprises: Receiving data to be encoded, wherein the data to be encoded is one or more of a plurality of data blocks; According to the data encoding requirements, the encoded data is checked based on the cyclic redundancy check method to obtain a check code sequence.

2. The data verification method according to claim 1, characterized in that: The multiple data blocks in the data to be encoded are continuous data blocks.

3. The data verification method according to claim 2, characterized in that: The check code sequence includes: a 12-bit CRC12 check code, a command signal, multiple block termination bits and a fixed combination of "0" and "1", totaling 32 bits of data.

4. The data verification method according to claim 2, characterized in that: When the data to be encoded is one of a plurality of data blocks, the data block is the first data block.

5. The data verification method according to claim 2, characterized in that: When the data to be encoded is all data blocks in a plurality of data blocks, the plurality of data blocks are sequentially input into a data encoding module, and the data encoding module verifies the plurality of data blocks based on a cyclic redundancy check method to obtain a check code sequence.

6. The data verification method according to claim 4 or 5, characterized in that: The method also includes: encoding the verified data and outputting a coding sequence, wherein the coding sequence has multiple data blocks, each of which includes a two-bit frame header and data to be encoded, wherein the two-bit frame header is one of a 12-bit CRC12 check code, a command signal, a multi-block termination bit and a fixed combination of "0" and "1", and the two-bit frame header of each data block is different.

7. A data decoding method, characterized in that: The decoding method comprises: Decoding the coding sequence of claim 6.

8. A data verification circuit, characterized in that: include: A data receiving module, used for receiving data to be encoded, wherein the data to be encoded is one or more of a plurality of data blocks; The data verification module is used to verify the encoded data based on the cyclic redundancy check method according to the data encoding requirements to obtain a verification code sequence.

9. A JESD204C interface, characterized in that: The verification circuit comprises the verification circuit described in any one of claims 1 to 7.

10. An analog-to-digital converter, characterized in that: Includes the JESD204C interface as described in claim 9.

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