Real-time optimization method for data stream calculation bandwidth

Abstract

The invention discloses a method for real-time optimization of a data stream calculation bandwidth, and relates to the field of high-performance calculation of computers, and the method comprises the following steps: recording the write-in times and write-in time of each type of operation instruction through a counter in an annular buffer area, and transmitting the write-in times and the write-in time to a bandwidth judgment device for initial bandwidth judgment; recording the output times and the output time of each type of operation instruction through a counter in the register, and transmitting the output times and the output time to a bandwidth judgment device for secondary bandwidth judgment; adjusting a bandwidth allocation strategy in real time in combination with the proportion of the operation instruction type; and transmitting the operation instruction to the corresponding operation unit based on the adjusted bandwidth allocation strategy, and executing the corresponding operation instruction. According to the invention, the annular buffer area is adopted to cache the data, so that frequent memory allocation operation is avoided, the overhead of memory management is reduced, and the utilization efficiency and security of the memory are improved.

Description

Technical Field

[0001] The present invention relates to the field of high performance computing of computers, and in particular to a method for real-time optimization of data flow computing bandwidth. Background Art

[0002] High-performance computing aims to process multiple tasks, instructions or data items at the same time. Its implementation relies on high-performance computer systems that organize thousands of processors in a specific way through network connections. This organization not only involves the interconnection topology and communication protocols of the network, but also covers operating systems and middleware software. The core goal of high-performance computing is to provide computing speeds that exceed traditional computers and solve complex problems that traditional computers cannot handle.

[0003] In the computing model of computer architecture, control flow and data flow are two main categories. Control flow computers, namely von Neumann computers, are the mainstream system, following the instruction sequence to drive operations, and the data operation participation depends on the needs of the current instructions. In contrast, the data flow computing model adopts a data-driven approach, where the execution of instructions depends on the completeness of the required operands, and the execution results further drive the execution of subsequent instructions.

[0004] Data flow computing systems are usually composed of multiple computing nodes, each of which has powerful computing capabilities, but relatively weak control capabilities and low complexity. These nodes contain multiple fixed-point arithmetic units and floating-point arithmetic units, corresponding to fixed-point arithmetic pipelines and floating-point arithmetic pipelines respectively. In each clock cycle, the pipeline selects one instruction from the prepared instructions to execute. However, the ratio of fixed-point instructions to floating-point instructions varies in different computing applications, which directly affects the demand for fixed-point and floating-point arithmetic bandwidth.

[0005] In the nodes of data flow computing, the instruction issuance mechanism plays a key role, such as Figure 3 As shown in the figure, the instruction queue is used to store the real-time execution information of the instructions, while the instruction issuance logic is responsible for selecting and issuing instructions to the corresponding operation unit. However, the traditional instruction issuance method has certain limitations: when the proportion of fixed-point instructions is high and the floating-point instructions are small, the calculation pipeline of the floating-point operation unit may be idle, while the bandwidth of the fixed-point pipeline may be tight. This fixed and unadjustable hardware bandwidth allocation method not only reduces the execution efficiency of the calculation, but also may cause insufficient bandwidth when the amount of data is too large, thereby affecting the normal transmission of data and the timely response of operation requests, and ultimately reducing the operation processing speed.

[0006] Currently, no effective solution has been proposed for the problems in the related technologies. Summary of the invention

[0007] In view of the problems in the related art, the present invention proposes a method for real-time optimization of data stream computing bandwidth to overcome the above technical problems existing in the existing related art.

[0008] To this end, the specific technical solution adopted by the present invention is as follows:

[0009] A method for real-time optimization of data flow computing bandwidth, the method comprising:

[0010] S1, extracting operation instructions from the instruction queue of the data stream, and recording the number of writes and the write time of each type of operation instruction through the counter in the ring buffer, and transmitting the number of writes and the write time to the bandwidth determiner for initial bandwidth determination;

[0011] S2, transferring the operation instructions in the ring buffer to the register, and recording the output times and output time of each type of operation instructions through the counter in the register, and transferring the output times and output time to the bandwidth determiner for secondary bandwidth determination;

[0012] S3, the processor component adjusts the bandwidth allocation strategy in real time according to the results of the initial and secondary bandwidth judgments and the proportion of the operation instruction types, and the processor component includes a data processor and a bandwidth allocator;

[0013] S4. Based on the adjusted bandwidth allocation strategy, the operation instruction is transmitted to the corresponding operation unit to execute the corresponding operation instruction.

[0014] Further, extracting operation instructions from the instruction queue of the data stream, and recording the number of writes and the write time of each type of operation instruction through the counter in the ring buffer, and transmitting the number of writes and the write time to the bandwidth determiner for initial bandwidth determination includes:

[0015] S11, obtaining the instruction queue of the data stream, and assigning the instruction queue to the operation pipeline, the operation pipeline includes a fixed-point operation pipeline and a floating-point operation pipeline;

[0016] S12, extracting fixed-point operation instructions and floating-point operation instructions from the fixed-point operation pipeline and the floating-point operation pipeline respectively;

[0017] S13, storing the extracted fixed-point operation instructions and floating-point operation instructions in corresponding ring buffers respectively, and using a counter in the ring buffer to record the number of writes and the write time, the number of writes includes the number of fixed-point writes and the number of floating-point writes, and the write time includes the fixed-point write time and the floating-point write time;

[0018] S14: The recorded number of write times and write time are transmitted to a bandwidth determiner, and the bandwidth determiner is used to perform an initial bandwidth determination.

[0019] Further, the instruction queue of the data stream is obtained, and the instruction queue is assigned to the operation pipeline, the operation pipeline includes a fixed-point operation pipeline and a floating-point operation pipeline including:

[0020] S111, obtaining the instruction queue of the data stream, and checking the status of the instructions in the instruction queue;

[0021] S112, based on the instructions after the inspection is completed, obtaining and determining the states of the fixed-point operation pipeline and the floating-point operation pipeline;

[0022] S113, based on the determination results of the fixed-point operation pipeline and the floating-point operation pipeline, transmitting the instructions in the instruction queue to the instruction issuing logic;

[0023] S114, the instruction issuing logic selects a corresponding pipeline according to the type of the instruction, removes the corresponding instruction from the instruction queue, and distributes it to the selected pipeline;

[0024] S115 , the fixed-point operation pipeline and the floating-point operation pipeline respectively receive and execute the assigned instructions, and update the state of the instruction issuance logic based on the execution results.

[0025] Further, the recorded number of write times and write time are transmitted to a bandwidth determiner, and the bandwidth determiner is used to perform initial bandwidth determination, including:

[0026] S141, transmitting the recorded fixed-point writing times, floating-point writing times, fixed-point writing time and floating-point writing time to a bandwidth determiner;

[0027] S142: Based on the transmission result, the bandwidth determiner calculates the total write bandwidth using a bandwidth formula;

[0028] S143: Compare the calculated total write bandwidth with the node bandwidth to perform an initial bandwidth determination.

[0029] Furthermore, the bandwidth formula is:

[0030]

[0031] In the formula, Z represents the total write bandwidth value;

[0032] w1 represents the number of fixed-point writes;

[0033] t1 represents the fixed-point writing time;

[0034] w2 represents the number of floating point writes;

[0035] t2 represents the floating point writing time.

[0036] Furthermore, the calculated total write bandwidth is compared with the node bandwidth, and the initial bandwidth judgment includes:

[0037] If the total written bandwidth is less than or equal to the node bandwidth, the bandwidth determiner does not send an adjustment instruction to the clock adjuster;

[0038] If the total write bandwidth is greater than the node bandwidth, the bandwidth determiner sends an instruction to the clock adjuster and increases the clock cycle according to a preset cycle.

[0039] Further, the operation instructions in the ring buffer are transferred to the register, and the output times and output time of each type of operation instructions are recorded by the counter in the register, and the output times and output time are transferred to the bandwidth determiner for secondary bandwidth determination, including:

[0040] S21, reading fixed-point arithmetic instructions and floating-point arithmetic instructions from the ring buffer, and transferring the fixed-point arithmetic instructions and floating-point arithmetic instructions to corresponding registers;

[0041] S22, using the counter in the register to record the output times and output time, the output times include the fixed-point output times and the floating-point output times, and the output time includes the fixed-point output time and the floating-point output time;

[0042] S23, feeding back the recorded output times and output time to the bandwidth determiner, and using the bandwidth determiner to perform secondary bandwidth determination.

[0043] Furthermore, the recorded output times and output times are fed back to the bandwidth determiner, and the bandwidth determiner is used to perform secondary bandwidth determination, including:

[0044] S231, feeding back the recorded fixed-point output times, floating-point output times, fixed-point output time and floating-point output time to the bandwidth determiner;

[0045] S232, based on the feedback result, the bandwidth determiner calculates the output total bandwidth using the bandwidth formula;

[0046] S233: Compare the calculated total output bandwidth with the node bandwidth to perform secondary bandwidth judgment.

[0047] Furthermore, the calculated total output bandwidth is compared with the node bandwidth, and a secondary bandwidth judgment is performed including:

[0048] If the total output bandwidth is less than or equal to the node bandwidth, the bandwidth determiner does not send an adjustment instruction to the clock adjuster;

[0049] If the total output bandwidth is greater than the node bandwidth, the bandwidth determiner sends an instruction to the clock adjuster and increases the clock cycle according to a preset cycle.

[0050] Furthermore, the processor component adjusts the bandwidth allocation strategy in real time according to the results of the primary and secondary bandwidth judgments and the proportion of the operation instruction types. The processor component includes a data processor and a bandwidth allocator including:

[0051] S31, transmitting the initial bandwidth determination result and the secondary bandwidth determination result from the register to the data processor;

[0052] S32, the data processor receives and processes the fixed-point operation instructions and floating-point operation instructions in the initial bandwidth determination result and the secondary bandwidth determination result, obtains the fixed-point processing result and the floating-point processing result, and transmits the fixed-point processing result and the floating-point processing result to the bandwidth allocator;

[0053] S33. The bandwidth allocator adjusts the bandwidth allocation strategy according to the ratio of the received fixed-point processing result to the received floating-point processing result.

[0054] The beneficial effects of the present invention are:

[0055] 1. The present invention avoids frequent memory allocation operations by caching data in a ring buffer, reduces the overhead of memory management, and improves the utilization efficiency and security of memory; at the same time, the ring buffer plays the role of data buffering and temporary storage, effectively alleviating the problem of insufficient bandwidth caused by excessive data volume, avoiding data backlog and slow processing, and improving the fluency and real-time performance of data processing.

[0056] 2. The present invention adjusts the proportion of bandwidth occupied by fixed-point operations and floating-point operations in real time through the ratio of the number of register output times, fully utilizing bandwidth resources and improving bandwidth utilization; in addition, the total bandwidth required for the current instruction is determined by the number of writes to the ring buffer to ensure that the bandwidth can be reasonably allocated when processing a large amount of data, avoiding data overflow and low computing efficiency caused by insufficient bandwidth.

[0057] 3. The present invention effectively solves the problem of low computing efficiency caused by tight bandwidth allocation in the data flow architecture by optimizing bandwidth allocation from two dimensions: time and space. By dynamically adjusting the bandwidth allocation strategy, the efficient operation of the system is ensured and the waste of bandwidth resources is avoided. In addition, the real-time optimization method can flexibly respond to different computing tasks and data flows, thereby improving the adaptability and robustness of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 is a flow chart of a method for real-time optimization of data stream computing bandwidth according to an embodiment of the present invention;

[0060] Figure 2 It is a schematic diagram of the instruction emission structure of the data flow architecture in a method for real-time optimization of data flow computing bandwidth according to an embodiment of the present invention;

[0061] Figure 3 It is a schematic diagram of the instruction emission structure of a traditional data flow architecture in a method for real-time optimization of data flow computing bandwidth according to an embodiment of the present invention. DETAILED DESCRIPTION

[0062] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention and are mainly used to illustrate the embodiments. They can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, ordinary technicians in this field should be able to understand other possible implementation methods and advantages of the present invention.

[0063] According to an embodiment of the present invention, a method for real-time optimization of data stream computing bandwidth is provided.

[0064] The present invention is further described with reference to the accompanying drawings and specific embodiments. Figure 1 As shown, according to a method for real-time optimization of data stream computing bandwidth according to an embodiment of the present invention, the method includes:

[0065] S1. Extract operation instructions from the instruction queue of the data stream, and record the number of writes and the write time of each type of operation instruction through the counter in the ring buffer, and transmit the number of writes and the write time to the bandwidth determiner for initial bandwidth determination.

[0066] Specifically, extracting operation instructions from the instruction queue of the data stream, and recording the number of writes and the write time of each type of operation instruction through the counter in the ring buffer, and transmitting the number of writes and the write time to the bandwidth determiner for initial bandwidth determination includes:

[0067] S11, obtaining the instruction queue of the data stream, and assigning the instruction queue to the operation pipeline, the operation pipeline includes a fixed-point operation pipeline and a floating-point operation pipeline.

[0068] Specifically, the instruction queue of the data stream is obtained, and the instruction queue is assigned to the operation pipeline, the operation pipeline includes a fixed-point operation pipeline and a floating-point operation pipeline including:

[0069] S111, obtaining the instruction queue of the data stream, and checking the status of the instructions in the instruction queue;

[0070] S112, based on the instructions after the inspection is completed, obtaining and determining the states of the fixed-point operation pipeline and the floating-point operation pipeline;

[0071] S113, based on the determination results of the fixed-point operation pipeline and the floating-point operation pipeline, transmitting the instructions in the instruction queue to the instruction issuing logic;

[0072] S114, the instruction issuing logic selects a corresponding pipeline according to the type of the instruction, removes the corresponding instruction from the instruction queue, and distributes it to the selected pipeline;

[0073] S115 , the fixed-point operation pipeline and the floating-point operation pipeline respectively receive and execute the assigned instructions, and update the state of the instruction issuance logic based on the execution results.

[0074] S12, extracting fixed-point operation instructions and floating-point operation instructions from the fixed-point operation pipeline and the floating-point operation pipeline respectively.

[0075] S13. Store the extracted fixed-point operation instructions and floating-point operation instructions into corresponding ring buffers respectively, and use the counter in the ring buffer to record the number of writes and the write time, where the number of writes includes the number of fixed-point writes and the number of floating-point writes, and the write time includes the fixed-point write time and the floating-point write time.

[0076] S14: The recorded number of write times and write time are transmitted to a bandwidth determiner, and the bandwidth determiner is used to perform an initial bandwidth determination.

[0077] Specifically, the recorded number of write times and write time are transmitted to the bandwidth determiner, and the initial bandwidth determination using the bandwidth determiner includes:

[0078] S141, transmitting the recorded fixed-point writing times, floating-point writing times, fixed-point writing time and floating-point writing time to a bandwidth determiner.

[0079] S142: Based on the transmission result, the bandwidth determiner calculates the total write bandwidth using a bandwidth formula.

[0080] Specifically, the bandwidth formula is:

[0081]

[0082] In the formula, Z represents the total write bandwidth value;

[0083] w1 represents the number of fixed-point writes;

[0084] t1 represents the fixed-point writing time;

[0085] w2 represents the number of floating point writes;

[0086] t2 represents the floating point writing time.

[0087] S143: Compare the calculated total write bandwidth with the node bandwidth to perform an initial bandwidth determination.

[0088] Specifically, the calculated total write bandwidth is compared with the node bandwidth, and the initial bandwidth judgment includes:

[0089] If the total written bandwidth is less than or equal to the node bandwidth, the bandwidth determiner does not send an adjustment instruction to the clock adjuster;

[0090] If the total write bandwidth is greater than the node bandwidth, the bandwidth determiner sends an instruction to the clock adjuster and increases the clock cycle according to a preset cycle.

[0091] It should be noted that the number of fixed-point writes and floating-point writes in the counter result are passed to the bandwidth judge, and the total bandwidth of the fixed-point operation and floating-point operation is judged through calculation whether it is greater than the actual node bandwidth. If so, the bandwidth judge issues an instruction, the clock regulator responds, and the clock cycle increases continuously in units of T cycles. If not, the bandwidth judge does not issue an instruction and the clock regulator does not respond.

[0092] S2. The operation instructions in the ring buffer are transferred to the register, and the output times and output time of each type of operation instructions are recorded through the counter in the register, and the output times and output time are transferred to the bandwidth determiner for secondary bandwidth determination.

[0093] Specifically, the operation instructions in the ring buffer are transferred to the register, and the output times and output time of each type of operation instructions are recorded by the counter in the register, and the output times and output time are transferred to the bandwidth determiner for secondary bandwidth determination, including:

[0094] S21, reading fixed-point operation instructions and floating-point operation instructions from the ring buffer, and transferring the fixed-point operation instructions and floating-point operation instructions to corresponding registers.

[0095] It should be additionally explained that the speed at which the fixed-point operation instructions and the floating-point operation instructions are cached in the ring buffer is faster than the speed at which their data are obtained from the ring buffer.

[0096] S22. Use the counter in the register to record the output times and output time. The output times include the fixed-point output times and the floating-point output times. The output time includes the fixed-point output time and the floating-point output time.

[0097] S23, feeding back the recorded output times and output time to the bandwidth determiner, and using the bandwidth determiner to perform secondary bandwidth determination.

[0098] Specifically, the recorded output times and output time are fed back to the bandwidth determiner, and the bandwidth determiner is used to perform secondary bandwidth determination, including:

[0099] S231, feeding back the recorded fixed-point output times, floating-point output times, fixed-point output time and floating-point output time to the bandwidth determiner;

[0100] S232, based on the feedback result, the bandwidth determiner calculates the output total bandwidth using the bandwidth formula;

[0101] S233: Compare the calculated total output bandwidth with the node bandwidth to perform secondary bandwidth judgment.

[0102] Specifically, the calculated total output bandwidth is compared with the node bandwidth, and the secondary bandwidth judgment includes:

[0103] If the total output bandwidth is less than or equal to the node bandwidth, the bandwidth determiner does not send an adjustment instruction to the clock adjuster;

[0104] If the total output bandwidth is greater than the node bandwidth, the bandwidth determiner sends an instruction to the clock adjuster and increases the clock cycle according to a preset cycle.

[0105] It should be noted that the initial clock cycle of the register is very small, and the delay time of the data in the register is negligible. If the clock regulator is running, the register clock cycle will continue to increase with the T cycle, and its delay will also gradually increase.

[0106] S3. The processor component adjusts the bandwidth allocation strategy in real time according to the results of the primary and secondary bandwidth judgments and the proportion of the operation instruction types. The processor component includes a data processor and a bandwidth allocator.

[0107] Specifically, the processor component adjusts the bandwidth allocation strategy in real time according to the results of the primary and secondary bandwidth judgments and the proportion of the operation instruction types. The processor component includes a data processor and a bandwidth allocator including:

[0108] S31 , transmitting the initial bandwidth determination result and the secondary bandwidth determination result from the register to the data processor.

[0109] It should be additionally explained that the fixed-point operation instructions, floating-point operation instructions, fixed-point output times, and floating-point output times in the register are transmitted to the data processor.

[0110] S32: The data processor receives and processes the fixed-point operation instructions and floating-point operation instructions in the primary bandwidth determination result and the secondary bandwidth determination result, obtains the fixed-point processing result and the floating-point processing result, and transmits the fixed-point processing result and the floating-point processing result to the bandwidth allocator.

[0111] S33. The bandwidth allocator adjusts the bandwidth allocation strategy according to the ratio of the received fixed-point processing result to the received floating-point processing result.

[0112] S4. Based on the adjusted bandwidth allocation strategy, the operation instruction is transmitted to the corresponding operation unit to execute the corresponding operation instruction.

[0113] It should be noted that after each group of instruction queues is processed, each counter is cleared and the clock regulator is reset to wait for the next group of instruction queues.

[0114] In a specific embodiment, the instruction queue is used to store the real-time execution information of the instruction, and a group of instruction queues are waiting for operation. The queue enters the instruction emission logic, and the instruction emission logic is used to select the instruction and emit it to the corresponding operation pipeline. In each clock cycle, the instruction emission logic selects an instruction from the prepared instructions and emits it to the corresponding pipeline for execution. The ratio of fixed-point operation instructions to floating-point operation instructions in different computing applications is also different.

[0115] like Figure 2 As shown in the figure, two operation pipelines are set, namely fixed-point operation pipeline and floating-point operation pipeline. The instruction issuance logic first determines whether the status of each instruction in the instruction queue is ready, and whether each operation pipeline can receive and execute new instructions. If it is determined to be, the instructions in the instruction queue are assigned to the corresponding pipeline for execution.

[0116] The instructions of the fixed-point operation pipeline enter the ring buffer 1, and the instructions of the floating-point operation pipeline enter the ring buffer 2; counters counter1 and counters counter2 are set at the data writing locations of the ring buffer 1 and the ring buffer 2 respectively, and all the fixed-point operation instructions and floating-point operation instructions are written into the ring buffer, and their counting results are w1 and w2 respectively, and the time taken is t1 and t2 respectively; the counter sends the counting results w1 and w2 to the bandwidth judge, and the bandwidth judge makes a judgment, where the operation bandwidth of this node is B.

[0117] If w1 / t1+w2 / t2<=B, the bandwidth determiner determines that it is negative, does not send a command, and the clock adjuster does not operate; the following descriptions all occur under this condition.

[0118] Fixed-point operation instructions and floating-point operation instructions are read out from ring buffer 1 and ring buffer 2 respectively and enter register 1 and register 2; wherein, ring buffer 1 and ring buffer 2, register 1 and register 2 are of the same type, and the speed of caching the data in the ring buffer is faster than the speed of obtaining the data from the ring buffer, so as to avoid data congestion in the ring buffer and speed up data transmission efficiency; the initial clock cycle T0 of the register is very small, and the delay of data in the register is negligible.

[0119] Counters counter3 and counter4 are set at the output positions of registers 1 and 2, and all fixed-point operation instructions and floating-point operation instructions enter the data processor from the registers, and their counting results are O1 and O2 respectively, and the time taken is t3 and t4 respectively; O1 and O2 data are sent to the data processor, and the processing data results are O1 / t3 and O2 / t4; the initial values ​​of the bandwidth of the fixed-point operation unit and the bandwidth of the floating-point operation unit are both B / 2; the processing results are sent to the bandwidth allocator, and the allocator allocates the bandwidth in advance at the ratio of O1 / t3:O2 / t4; the fixed-point operation instructions and floating-point operation instructions enter the fixed-point operation unit and the floating-point operation unit respectively, and perform data operation processing; when the next group of instruction queues arrives, all counters are set to 0, the register clock cycle is reset to the initial value, and the bandwidth of the fixed-point operation unit and the floating-point operation unit is also reset.

[0120] If w1 / t1+w2 / t2>B, the bandwidth determiner determines yes, sends an instruction, the clock regulator responds, and the register cycle is adjusted to T1. O1 / (t3+T1)+O2 / (t3+T1)<=B, and T1 can be obtained. The following descriptions all occur under this condition.

[0121] Fixed-point operation instructions and floating-point operation instructions are read out from ring buffer 1 and ring buffer 2 respectively, and enter register 1 and register 2; at this time, the clock regulator is in a responsive state, the register cycle is adjusted to T1, counter3 and counter4 output O1 and O2; at the same time, O1 and O2 data are sent to the data processor, and the processing data results are O1 / t3 and O2 / t4; the processing results are sent to the bandwidth allocator, and the allocator allocates the bandwidth in advance at the ratio of O1 / t3:O2 / t4; the fixed-point operation instructions and floating-point operation instructions enter the fixed-point operation unit and the floating-point operation unit for data operation processing.

[0122] In addition, for fixed-point numbers, the decimal point is not fixed, such as int, where the decimal point is at the end of the number. The more decimal places there are, the higher the precision of the number. If there are n places after the decimal point, the precision is 1 / (2 n ); The more integer digits there are, the larger the maximum value that can be represented. The calculation formula for fixed-point numbers is:

[0123]

[0124] In the formula, n represents a decimal number; fc represents the length of the decimal place; bw represents the fixed-point number width; i represents the index; and Bi represents the value of the i-th place.

[0125] Floating point numbers, numbers with unfixed decimal points, such as float and double, have completely different representation logic from unsigned integers such as int and char. Floating point numbers cannot be shifted because the bits are in different fields and have different meanings, for example:

[0126]

[0127] In the formula, V represents a floating point number; S represents the sign bit, which takes a value of 0 or 1 and determines the sign of a number, 0 represents positive and 1 represents negative; M represents the mantissa, which is expressed as a decimal, for example, 1.234*10 0 , 1.234 is the mantissa; R represents the base, which is 10 for decimal numbers and 2 for binary numbers; E represents the exponent, which is expressed as an integer, such as 10 -1 , -1 is the exponent.

[0128] If you want to use a floating point number to represent a number in a computer, you only need to confirm these variables.

[0129] In summary, with the help of the above technical solution of the present invention, by using the ring buffer to cache data, frequent memory allocation operations are avoided, the memory management overhead is reduced, and the memory utilization efficiency and security are improved; at the same time, the ring buffer plays the role of data buffering and temporary storage, effectively alleviating the problem of insufficient bandwidth caused by excessive data volume, avoiding data backlog and slow processing, and improving the fluency and real-time performance of data processing. The bandwidth proportion occupied by fixed-point operations and floating-point operations is adjusted in real time by the ratio of the number of register output times, making full use of bandwidth resources and improving bandwidth utilization; in addition, the total bandwidth required for the current instruction is determined by the number of writes to the ring buffer, ensuring that the bandwidth can be reasonably allocated when processing a large amount of data, avoiding data overflow and low computing efficiency caused by insufficient bandwidth. By optimizing bandwidth allocation from the two dimensions of time and space, the problem of low computing efficiency caused by tight bandwidth allocation in the data flow architecture is effectively solved, and by dynamically adjusting the bandwidth allocation strategy, the efficient operation of the system is ensured, and the waste of bandwidth resources is avoided; in addition, the real-time optimization method can flexibly respond to different computing tasks and data flows, improving the adaptability and robustness of the system.

[0130] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for real-time optimization of data flow computing bandwidth, characterized in that: The method includes: S1, extracting operation instructions from the instruction queue of the data stream, and recording the number of writes and the write time of each type of operation instruction through the counter in the ring buffer, and transmitting the number of writes and the write time to the bandwidth determiner for initial bandwidth determination; S2, transferring the operation instructions in the ring buffer to the register, and recording the output times and output time of each type of operation instructions through the counter in the register, and transferring the output times and output time to the bandwidth determiner for secondary bandwidth determination; S3, the processor component adjusts the bandwidth allocation strategy in real time according to the results of the initial and secondary bandwidth judgments and the proportion of the operation instruction types, and the processor component includes a data processor and a bandwidth allocator; S4. Based on the adjusted bandwidth allocation strategy, the operation instruction is transmitted to the corresponding operation unit to execute the corresponding operation instruction.

2. A method for real-time optimization of data flow computing bandwidth according to claim 1, characterized in that: The extracting operation instructions from the instruction queue of the data stream, recording the number of writes and the write time of each type of operation instruction through a counter in the ring buffer, and transmitting the number of writes and the write time to the bandwidth determiner for initial bandwidth determination includes: S11, obtaining an instruction queue of a data stream, and assigning the instruction queue to a calculation pipeline, wherein the calculation pipeline includes a fixed-point calculation pipeline and a floating-point calculation pipeline; S12, extracting fixed-point operation instructions and floating-point operation instructions from the fixed-point operation pipeline and the floating-point operation pipeline respectively; S13, storing the extracted fixed-point operation instructions and floating-point operation instructions in corresponding ring buffers respectively, and using a counter in the ring buffer to record the number of writes and the write time, wherein the number of writes includes the number of fixed-point writes and the number of floating-point writes, and the write time includes the fixed-point write time and the floating-point write time; S14: The recorded number of write times and write time are transmitted to a bandwidth determiner, and the bandwidth determiner is used to perform an initial bandwidth determination.

3. A method for real-time optimization of data flow computing bandwidth according to claim 2, characterized in that: The instruction queue of the data stream is obtained, and the instruction queue is allocated to the operation pipeline, wherein the operation pipeline includes a fixed-point operation pipeline and a floating-point operation pipeline, including: S111, obtaining the instruction queue of the data stream, and checking the status of the instructions in the instruction queue; S112, based on the instructions after the inspection is completed, obtaining and determining the states of the fixed-point operation pipeline and the floating-point operation pipeline; S113, based on the determination results of the fixed-point operation pipeline and the floating-point operation pipeline, transmitting the instructions in the instruction queue to the instruction issuing logic; S114, the instruction issuing logic selects a corresponding pipeline according to the type of the instruction, removes the corresponding instruction from the instruction queue, and distributes it to the selected pipeline; S115 , the fixed-point operation pipeline and the floating-point operation pipeline respectively receive and execute the assigned instructions, and update the state of the instruction issuance logic based on the execution results.

4. A method for real-time optimization of data flow computing bandwidth according to claim 3, characterized in that: The step of transmitting the recorded number of write times and write time to the bandwidth determiner and using the bandwidth determiner to perform initial bandwidth determination includes: S141, transmitting the recorded fixed-point writing times, floating-point writing times, fixed-point writing time and floating-point writing time to a bandwidth determiner; S142: Based on the transmission result, the bandwidth determiner calculates the total write bandwidth using a bandwidth formula; S143: Compare the calculated total write bandwidth with the node bandwidth to perform an initial bandwidth determination.

5. A method for real-time optimization of data flow computing bandwidth according to claim 4, characterized in that: The bandwidth formula is: In the formula, Z represents the total write bandwidth value; w1 represents the number of fixed-point writes; t1 represents the fixed-point writing time; w2 represents the number of floating point writes; t2 represents the floating point writing time.

6. A method for real-time optimization of data flow computing bandwidth according to claim 5, characterized in that: The step of comparing the calculated total write bandwidth with the node bandwidth to perform initial bandwidth determination includes: If the total written bandwidth is less than or equal to the node bandwidth, the bandwidth determiner does not send an adjustment instruction to the clock adjuster; If the total write bandwidth is greater than the node bandwidth, the bandwidth determiner sends an instruction to the clock adjuster and increases the clock cycle according to a preset cycle.

7. A method for real-time optimization of data flow computing bandwidth according to claim 1, characterized in that: The method of transmitting the operation instructions in the ring buffer to the register, recording the output times and output time of each type of operation instructions by the counter in the register, and transmitting the output times and output time to the bandwidth determiner for secondary bandwidth determination includes: S21, reading fixed-point arithmetic instructions and floating-point arithmetic instructions from the ring buffer, and transferring the fixed-point arithmetic instructions and floating-point arithmetic instructions to corresponding registers; S22, using a counter in a register to record the number of outputs and the output time, the number of outputs includes the number of fixed-point outputs and the number of floating-point outputs, and the output time includes the fixed-point output time and the floating-point output time; S23, feeding back the recorded output times and output time to the bandwidth determiner, and using the bandwidth determiner to perform secondary bandwidth determination.

8. A method for real-time optimization of data flow computing bandwidth according to claim 7, characterized in that: Feeding back the recorded output times and output time to the bandwidth determiner, and using the bandwidth determiner to perform secondary bandwidth determination includes: S231, feeding back the recorded fixed-point output times, floating-point output times, fixed-point output time and floating-point output time to the bandwidth determiner; S232, based on the feedback result, the bandwidth determiner calculates the output total bandwidth using the bandwidth formula; S233: Compare the calculated total output bandwidth with the node bandwidth to perform secondary bandwidth judgment.

9. A method for real-time optimization of data flow computing bandwidth according to claim 1, characterized in that: The step of comparing the calculated total output bandwidth with the node bandwidth and performing secondary bandwidth determination includes: If the total output bandwidth is less than or equal to the node bandwidth, the bandwidth determiner does not send an adjustment instruction to the clock adjuster; If the total output bandwidth is greater than the node bandwidth, the bandwidth determiner sends an instruction to the clock adjuster and increases the clock cycle according to a preset cycle.

10. The method for real-time optimization of data flow computing bandwidth according to claim 1, characterized in that: The processor component adjusts the bandwidth allocation strategy in real time according to the results of the primary and secondary bandwidth judgments and the proportion of the operation instruction types. The processor component includes a data processor and a bandwidth allocator including: S31, transmitting the initial bandwidth determination result and the secondary bandwidth determination result from the register to the data processor; S32, the data processor receives and processes the fixed-point operation instructions and floating-point operation instructions in the initial bandwidth determination result and the secondary bandwidth determination result, obtains the fixed-point processing result and the floating-point processing result, and transmits the fixed-point processing result and the floating-point processing result to the bandwidth allocator; S33. The bandwidth allocator adjusts the bandwidth allocation strategy according to the ratio of the received fixed-point processing result to the received floating-point processing result.

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