A gate driving circuit and a display device

Abstract

This invention provides a gate driving circuit and a display device. The gate driving circuit includes multiple gate driving units, each of which includes a pre-charge module, a pull-down module, a stabilization module, and an output module. The output module is connected to the pre-charge module at a first node and includes a first switching element, a pre-output unit, and a first pull-down stabilization unit. The first control terminal of the first switching element is connected to the first node, the first path terminal is connected to a third node, and the second path terminal is connected to the output terminal. The pre-output unit charges the third node according to the previous stage gate output signal and the first clock signal of the current stage. The first pull-down stabilization unit is used to pull the third node down to a low level according to the second clock signal of the current stage during the stabilization phase. The high-level time period of the second clock signal of the current stage does not overlap with the high-level time period of the first clock signal of the current stage. This invention can effectively reduce circuit noise, improve high-temperature resistance, and enable the display device to be used in more application scenarios.

Description

Technical Field

[0001] This invention relates to the field of display driving technology, and in particular to a gate driving circuit and a display device. Background Technology

[0002] Display devices, such as liquid crystal displays (LCDs), have gradually replaced traditional cathode ray tube displays due to their numerous advantages, including being lightweight, energy-efficient, and radiation-free. They are widely used in electronic devices such as high-definition digital televisions, desktop computers, personal digital assistants, laptops, mobile phones, and digital cameras.

[0003] The display device can be configured with a gate drive circuit to provide a gate output signal to the gate line. Changes in the high and low levels of the gate output signal can activate or deactivate the thin-film transistor connected to the gate line, thereby controlling the switching of pixels and achieving image display. For example... Figure 1 As shown, each stage of the gate driving circuit in the prior art includes a pre-charge module, a pull-down module, a stabilization module, and an output module. The output module has a switching element T, whose control terminal is connected to a node. One path of the switching element receives a clock signal CLK, and the other path is connected to an output terminal V to connect to the corresponding gate line. This is used to output the gate clock signal of this stage based on the high level at the node and the high level of the clock signal CLK during the output phase. However, during the stabilization phase, the clock signal CLK maintains a periodic switching between high and low levels, causing periodic noise to be generated at both the node and the output terminal V through the switching element. This circuit noise reduces the circuit's high-temperature resistance and may even prevent the display device from coping with high-temperature operating scenarios. Therefore, it is necessary to provide an improved technical solution to overcome the above-mentioned technical problems existing in the prior art. Summary of the Invention

[0004] In view of this, the present invention provides a gate driving circuit and a display device that can effectively reduce circuit noise, improve high temperature resistance, and enable the display device to be used in more application scenarios.

[0005] This invention provides a gate driving circuit, which includes multiple gate driving units. Each gate driving unit includes a pre-charge module, a pull-down module, a stabilization module, and an output module. The output module is connected to the pre-charge module at a first node. The output module includes a first switching element, a pre-output unit, and a first pull-down stabilization unit. The first switching element includes a first control terminal, a first path terminal, and a second path terminal. The first control terminal of the first switching element is connected to the first node, the first path terminal of the first switching element is connected to a third node, and the second path terminal of the first switching element is connected to the output terminal and is used to output the gate output signal of this stage. The pre-output unit is connected to the third node and charges the third node according to the previous stage gate output signal and the first clock signal of this stage. The first pull-down stabilization unit is connected to the third node and is used to pull the third node down to a low level according to the second clock signal of this stage during the stabilization phase. The high-level time period of the second clock signal of this stage does not overlap with the high-level time period of the first clock signal of this stage.

[0006] Specifically, the pre-output unit includes a second switching element and a third switching element. The second switching element includes a second control terminal, a third path terminal, and a fourth path terminal. The second control terminal of the second switching element is connected to the fourth node. The third path terminal of the second switching element receives the first clock signal of this stage, and the fourth path terminal of the second switching element is connected to the third node. The third switching element includes a third control terminal, a fifth path terminal, and a sixth path terminal. The third control terminal of the third switching element receives the gate output signal of the previous stage. The fifth path terminal of the third switching element receives a first high-level signal, and the sixth path terminal of the third switching element is connected to the fourth node.

[0007] Specifically, the first pull-down stabilization unit includes a fourth switching element and a fifth switching element; the fourth switching element includes a fourth control terminal, a seventh path terminal, and an eighth path terminal, the fourth control terminal of the fourth switching element receives the second clock signal of this stage, the seventh path terminal of the fourth switching element is connected to the third node, and the eighth path terminal of the fourth switching element receives a low-level signal; the fifth switching element includes a fifth control terminal, a ninth path terminal, and a tenth path terminal, the fifth control terminal of the fifth switching element receives the second clock signal of this stage, the ninth path terminal of the fifth switching element is connected to the fourth node, and the tenth path terminal of the fifth switching element receives a low-level signal.

[0008] Specifically, the output module further includes a first capacitor, the first end of which is connected to the fourth node, and the second end of which is connected to the third node.

[0009] Specifically, the pre-charge module includes a sixth switching element, which includes a sixth control terminal, an eleventh path terminal, and a twelfth path terminal. The sixth control terminal of the sixth switching element receives the output signal from the front-stage gate, the eleventh path terminal of the sixth switching element receives the third clock signal of this stage, and the twelfth path terminal of the sixth switching element is connected to the first node.

[0010] And / or, the pull-down module includes a seventh switching element, the seventh switching element including a seventh control terminal, a thirteenth path terminal and a fourteenth path terminal, the seventh control terminal of the seventh switching element receiving the gate output signal of the subsequent stage, the thirteenth path terminal of the seventh switching element being connected to the first node, and the fourteenth path terminal of the seventh switching element receiving the fourth clock signal of this stage;

[0011] And / or, the stabilization module includes an eighth switching element, a ninth switching element, a tenth switching element, an eleventh switching element, and a twelfth switching element; the eighth switching element includes an eighth control terminal, a fifteenth path terminal, and a sixteenth path terminal, the eighth control terminal of the eighth switching element receiving the second clock signal of this stage, the fifteenth path terminal of the eighth switching element being connected to the output terminal, and the sixteenth path terminal of the eighth switching element receiving a low-level signal; the ninth switching element includes a ninth control terminal, a seventeenth path terminal, and an eighteenth path terminal, the ninth control terminal of the ninth switching element being connected to the second node, the seventeenth path terminal of the ninth switching element being connected to the first node, and the eighteenth path terminal of the ninth switching element receiving the low-level signal; the tenth switching element includes a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal, the tenth control terminal of the tenth switching element... The tenth switching element is connected to the first node, and its nineteenth path is connected to the second node. The twentieth path of the tenth switching element receives the low-level signal. The eleventh switching element includes an eleventh control terminal, a twenty-first path terminal, and a twenty-second path terminal. The eleventh control terminal of the eleventh switching element is connected to the second node, and its twenty-first path terminal is connected to the output terminal. The twenty-second path terminal of the eleventh switching element receives the low-level signal. The twelfth switching element includes a twelfth control terminal, a twenty-third path terminal, and a twenty-fourth path terminal. The twelfth control terminal of the twelfth switching element receives a second high-level signal. The twenty-third path terminal of the twelfth switching element is connected to the twelfth control terminal of the twelfth switching element, and the twenty-fourth path terminal of the twelfth switching element is connected to the second node.

[0012] Specifically, the duty cycle of the third clock signal, the first clock signal, the fourth clock signal, and the second clock signal of this level are all 50%, the clock periods are all equal, and they are sequentially spaced one-quarter of a clock period apart.

[0013] Specifically, the first high-level signal received at the fifth path terminal of the third switching element is replaced by the second clock signal of this stage.

[0014] Specifically, the output module further includes a second pull-down stabilizing unit, which is connected to the output terminal and pulls the output terminal down to a low level according to the gate output signal of the subsequent stage.

[0015] Specifically, the second pull-down stabilizing unit includes a thirteenth switching element; the thirteenth switching element includes a thirteenth control terminal, a twenty-fifth path terminal, and a twenty-sixth path terminal. The thirteenth control terminal of the thirteenth switching element receives the output signal from the gate of the subsequent stage, the twenty-fifth path terminal of the thirteenth switching element is connected to the output terminal, and the twenty-sixth path terminal of the thirteenth switching element receives a low-level signal.

[0016] This invention also provides a display device including the gate driving circuit described above.

[0017] The present invention provides a gate driving circuit and a display device. The gate driving circuit includes multiple gate driving units, each of which includes a pre-charge module, a pull-down module, a stabilization module, and an output module. The output module is connected to the pre-charge module at a first node and includes a first switching element, a pre-output unit, and a first pull-down stabilization unit. The first control terminal of the first switching element is connected to the first node, the first path terminal is connected to the third node, and the second path terminal is connected to the output terminal. The pre-output unit charges the third node according to the previous stage gate output signal and the first clock signal of the current stage. The first pull-down stabilization unit is used to pull the third node down to a low level according to the second clock signal of the current stage during the stabilization phase. The high-level time period of the second clock signal of the current stage does not overlap with the high-level time period of the first clock signal of the current stage. Therefore, this gate driving circuit can be used to generate gate driving signals, effectively reduce circuit noise during the stabilization phase, improve high-temperature resistance, and enable the display device to be used in more application scenarios.

[0018] In order to make the above and other objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a partial connection diagram of the gate drive circuit in the prior art.

[0020] Figure 2This is a circuit connection diagram of a gate driving circuit according to an embodiment of the present invention.

[0021] Figure 3 This is a timing diagram of a set of clock signals received by the gate driving circuit according to an embodiment of the present invention.

[0022] Figure 4 This is a circuit connection diagram of the gate driving circuit according to another embodiment of the present invention. Detailed Implementation

[0023] To further illustrate the technical means and effects of the present invention in order to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, describes the specific implementation methods, steps, structures, features and effects of the gate driving circuit and display device proposed according to the present invention.

[0024] Figure 2 This is a circuit connection diagram of a gate driving circuit according to an embodiment of the present invention. Please refer to [link / reference]. Figure 2 The gate driving circuit of this embodiment includes a multi-stage gate driving unit. Each stage of the gate driving unit includes a pre-charge module 10, a pull-down module 20, a stabilization module 30, and an output module 40. The output module 40 is connected to the pre-charge module 10 at the first node Q1. The output module 40 includes a first switching element T1, a pre-output unit 41, and a first pull-down stabilization unit 42. The first switching element T1 includes a first control terminal, a first path terminal, and a second path terminal. The first control terminal of the first switching element T1 is connected to the first node Q1, the first path terminal of the first switching element T1 is connected to the third node Q3, and the second path terminal of the first switching element T1 is connected to the output terminal V and is used to output the gate output signal Gn of this stage. The pre-output unit 41 is connected to the third node Q3 and charges the third node Q3 according to the previous stage gate output signal Gn-4 and the first clock signal CLK3 of this stage. The first pull-down stabilizing unit 42 is connected to the third node Q3 and is used to pull the third node Q3 to a low level according to the second clock signal CLK7 of this stage during the stabilization phase. The high level period of the second clock signal CLK7 of this stage does not overlap with the high level period of the first clock signal CLK3 of this stage.

[0025] The pre-charge module 10 is connected to the first node Q1 and charges the first node Q1 according to the gate output signal Gn-4 of the preceding stage and the third clock signal CLK1 of this stage. The pull-down module 20 is connected to the first node Q1 and the pre-charge module 10, and pulls the first node Q1 down to a low level according to the gate output signal Gn+4 of the following stage and the fourth clock signal CLK5 of this stage. The stabilization module 30 is connected to the first node Q1 and the output terminal V. The stabilization module 30 is used to maintain the first node Q1 and the output terminal V at a low level when the first node Q1 is pulled down to a low level.

[0026] In embodiments of the present invention, the gate driving units can be connected sequentially or sequentially with intervals between them. Figure 2 In the example, the gate driving units are connected sequentially at intervals. For example, the nth gate driving unit is connected to the (n-4)th and (n+4)th gate driving units respectively. Then, the gate output signal Gn of the nth gate driving unit can be represented by Gn, the gate output signal Gn-4 of the previous stage received by the nth gate driving unit can be represented by Gn-4, and the gate output signal of the next stage received by the nth gate driving unit can be represented by Gn+4.

[0027] It is worth noting that if the nth-stage gate drive unit at the beginning of the circuit is not connected to a preceding gate drive unit, then an external signal circuit needs to provide a preceding gate output signal Gn-4. This preceding gate output signal Gn-4 can be provided directly by the timing control circuit or via a source drive circuit to provide the corresponding enable signal STV1. If the nth-stage gate drive unit at the end of the circuit is not connected to a following gate drive unit, then an external signal circuit needs to provide a following gate output signal Gn+4. This following gate output signal Gn+4 can be provided directly by the timing control circuit or via a source drive circuit to provide the corresponding pull-down signal STV2.

[0028] In one embodiment of the present invention, such as Figure 2 As shown, the pre-output unit 41 includes a second switching element T2 and a third switching element T3. The second switching element T2 includes a second control terminal, a third path terminal, and a fourth path terminal. The second control terminal of the second switching element T2 is connected to the fourth node Q4. The third path terminal of the second switching element T2 receives the first clock signal CLK3 of this stage, and the fourth path terminal of the second switching element T2 is connected to the third node Q3. The third switching element T3 includes a third control terminal, a fifth path terminal, and a sixth path terminal. The third control terminal of the third switching element T3 receives the gate output signal Gn-4 from the previous stage. The fifth path terminal of the third switching element T3 receives the first high-level signal DCH, and the sixth path terminal of the third switching element T3 is connected to the fourth node Q4. However, the present invention is not limited to this. For example, in another embodiment, only the second switching element T2 can be provided. The second control terminal of the second switching element T2 receives the gate output signal Gn-4 from the previous stage, the third path terminal of the second switching element T2 receives the first clock signal CLK3 of this stage, and the fourth path terminal of the second switching element T2 is connected to the third node Q3.

[0029] In one embodiment of the present invention, such as Figure 2As shown, the first pull-down stabilizing unit 42 includes a fourth switching element T4 and a fifth switching element T5. The fourth switching element T4 includes a fourth control terminal, a seventh path terminal, and an eighth path terminal. The fourth control terminal of the fourth switching element T4 receives the second clock signal CLK7 of this stage. The seventh path terminal of the fourth switching element T4 is connected to the third node Q3. The eighth path terminal of the fourth switching element T4 receives a low-level signal VGL. The fifth switching element T5 includes a fifth control terminal, a ninth path terminal, and a tenth path terminal. The fifth control terminal of the fifth switching element T5 receives the second clock signal CLK7 of this stage. The ninth path terminal of the fifth switching element T5 is connected to the fourth node Q4. The tenth path terminal of the fifth switching element T5 receives a low-level signal VGL. However, the present invention is not limited to this. For example, in another embodiment, only the fourth switching element T4 may be provided to pull down the third node Q3 to a low level according to the second clock signal CLK7 of this stage.

[0030] In one embodiment of the present invention, such as Figure 2 As shown, the output module 40 also includes a first capacitor C1. The first terminal of the first capacitor C1 is connected to the fourth node Q4, and the second terminal of the first capacitor C1 is connected to the third node Q3. In one embodiment, the first capacitor C1 may be, but is not limited to, an external capacitor between the fourth node Q4 and the third node Q3. By utilizing the coupling effect of the capacitor, the voltage pull-up effect of the fourth node Q4 can be improved.

[0031] In one embodiment of the present invention, such as Figure 2 As shown, the output module 40 also includes a second capacitor C2. The first end of the second capacitor C2 is connected to the first node Q1, and the second end of the first capacitor C1 is connected to the output terminal V. In one embodiment, the second capacitor C2 may be, but is not limited to, an external capacitor between the first node Q1 and the output terminal V. By utilizing the coupling effect of the capacitor, the voltage pull-up effect of the first node Q1 can be improved.

[0032] In one embodiment of the present invention, such as Figure 2 As shown, the pre-charge module 10 includes a sixth switching element T6, which includes a sixth control terminal, an eleventh path terminal, and a twelfth path terminal. The sixth control terminal of the sixth switching element T6 receives the gate output signal Gn-4 from the previous stage, the eleventh path terminal of the sixth switching element T6 receives the third clock signal CLK1 of this stage, and the twelfth path terminal of the sixth switching element T6 is connected to the first node Q1.

[0033] In one embodiment of the present invention, such as Figure 2As shown, the pull-down module 20 includes a seventh switching element T7, which includes a seventh control terminal, a thirteenth path terminal, and a fourteenth path terminal. The seventh control terminal of the seventh switching element T7 receives the gate output signal Gn+4 from the subsequent stage. The thirteenth path terminal of the seventh switching element T7 is connected to the first node Q1. The fourteenth path terminal of the seventh switching element T7 receives the fourth clock signal CLK5 of this stage.

[0034] In one embodiment of the present invention, such as Figure 2 As shown, the stabilization module 30 includes an eighth switching element T8, a ninth switching element T9, a tenth switching element T10, an eleventh switching element T11, and a twelfth switching element T12. The eighth switching element T8 includes an eighth control terminal, a fifteenth path terminal, and a sixteenth path terminal. The eighth control terminal of the eighth switching element T8 receives the second clock signal CLK7 of this stage. The fifteenth path terminal of the eighth switching element T8 is connected to the output terminal V, and the sixteenth path terminal of the eighth switching element T8 receives a low-level signal VGL. The ninth switching element T9 includes a ninth control terminal, a seventeenth path terminal, and an eighteenth path terminal. The ninth control terminal of the ninth switching element T9 is connected to the second node Q2, the seventeenth path terminal of the ninth switching element T9 is connected to the first node Q1, and the eighteenth path terminal of the ninth switching element T9 receives a low-level signal VGL. The tenth switching element T10 includes a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal. The tenth control terminal is connected to the first node Q1, the nineteenth path terminal of the tenth switching element T10 is connected to the second node Q2, and the twentieth path terminal of the tenth switching element T10 receives a low-level signal VGL; the eleventh switching element T11 includes an eleventh control terminal, a twenty-first path terminal, and a twenty-second path terminal. The eleventh control terminal of the eleventh switching element T11 is connected to the second node Q2, the twenty-first path terminal of the eleventh switching element T11 is connected to the output terminal V, and the twenty-second path terminal of the eleventh switching element T11 receives a low-level signal VGL; the twelfth switching element T12 includes a twelfth control terminal, a twenty-third path terminal, and a twenty-fourth path terminal. The twelfth control terminal of the twelfth switching element T12 receives a second high-level signal DC, the twenty-third path terminal of the twelfth switching element T12 is connected to the twelfth control terminal of the twelfth switching element T12, and the twenty-fourth path terminal of the twelfth switching element T12 is connected to the second node Q2.

[0035] In one embodiment of the present invention, the first switching element T1 to the twelfth switching element T12 may be, but is not limited to, an N-type TFT, an NMOS transistor, or an N-type transistor. The corresponding first control terminal to the twelfth control terminal of the first switching element T1 to the twelfth switching element T12 are all gates. The corresponding pass terminals of the first switching element T1 to the twelfth switching element T12 are drains or sources.

[0036] Figure 3 This is a timing diagram of a set of clock signals received by a gate driving circuit according to an embodiment of the present invention. The set of clock signals received by the gate driving circuit consists of N phase difference clocks, and the phase difference between two adjacent phase difference clocks is one-Nth of a period, where N can be 8, etc. The first clock signal CLK3, the second clock signal CLK7, the third clock signal CLK1, and the fourth clock signal CLK5 received by any gate driving unit can be provided by this set of clock signals. Figure 3 In this example, the clock signals consist of eight phase-difference clocks, CLK1 to CLK8, with the phase difference between any two adjacent phase-difference clocks being one-eighth of a period. The first clock signal CLK3, the second clock signal CLK7, the third clock signal CLK1, and the fourth clock signal CLK5 received by any gate driving unit can be provided by this set of clock signals. The phase difference between the first clock signal CLK3 received by any gate driving unit and the first clock signal CLK3 received by an adjacent gate driving unit is one-eighth of a period. The phase difference between the second clock signal CLK7 received by any gate driving unit and the second clock signal CLK7 received by the adjacent gate driving unit is one-eighth of a period. The phase difference between the third clock signal CLK1 received by any gate driving unit and the third clock signal CLK1 received by the adjacent gate driving unit is one-eighth of a period. The phase difference between the fourth clock signal CLK5 received by any gate driving unit and the fourth clock signal CLK5 received by the adjacent gate driving unit is one-eighth of a period.

[0037] In one embodiment of the present invention, the duty cycles of the third clock signal CLK1, the first clock signal CLK3, the fourth clock signal CLK5, and the second clock signal CLK7 are all 50%, and their clock periods are all equal, with a quarter-clock period interval between them. However, the present invention does not limit the duty cycle of each clock signal to this; the duty cycle can be, for example, 37.5% to 50%, etc., all of which fall within the protection scope of the present invention.

[0038] Specifically, with Figure 2 and Figure 3 For example, the operation of the gate drive unit in a gate drive circuit includes four stages: pre-charge stage, output stage, pull-down stage, and stabilization stage.

[0039] Pre-charging phase:

[0040] When the front-stage gate output signal Gn-4 transitions from low to high, the pre-charge module 10 controls the first node Q1 to receive the high-level front-stage gate output signal Gn-4, and the first node Q1 begins charging.

[0041] In one embodiment, when the front-stage gate output signal Gn-4 transitions from low to high, the sixth switching element T6 receives the high-level front-stage gate output signal Gn-4 through its sixth control terminal and becomes on. Then, the first node Q1 receives the third clock signal CLK1 through the on-state sixth switching element T6. When the third clock signal CLK1 transitions from low to high, the first node Q1 begins charging. Thus, the pre-charging module 10 charges the first node Q1.

[0042] In one embodiment, when the front-stage gate output signal Gn-4 transitions from low to high, the rear-stage gate output signal Gn+4 is at a low level. The seventh switching element T7 receives the low-level rear-stage gate output signal Gn+4 through its seventh control terminal, indicating it is in an off state. Therefore, the pull-down module 20 does not enter the working state.

[0043] In one embodiment, when the first node Q1 is charged and pulled up to a high level, the first switching element T1 receives a high level through the first control terminal connected to the first node Q1 and becomes on. Simultaneously, the front-stage gate output signal Gn-4 transitions from low to high, and the third switching element T3 receives the high-level front-stage gate output signal Gn-4 through the third control terminal and becomes on. The fourth node Q4 receives the first high-level signal DCH through the on-state third switching element T3 and begins charging. When the fourth node Q4 is charged to a high level, the second switch receives a high level through the second control terminal connected to the fourth node Q4 and becomes on. Then, the third node Q3 receives the low-level first clock signal CLK3 through the on-state second switching element T2, and the third node Q3 does not charge. Therefore, the output module 40 does not enter the working state, the third node Q3 is not charging, and the output terminal V does not output the current-stage gate output signal Gn.

[0044] In one embodiment, when the first node Q1 is charged and pulled up to a high level, the tenth control terminal of the tenth switching element T10 connected to the first node Q1 becomes high, and the tenth switching element T10 becomes on. Consequently, the second node Q2, connected to the nineteenth path terminal of the tenth switching element T10, receives a low-level signal VGL through the on-state tenth switching element T10, and thus the second node Q2 becomes low. The ninth switching element T9 then becomes off-state by receiving a low level through its ninth control terminal connected to the second node Q2, and the tenth switching element T10 becomes off-state by receiving a low level through its tenth control terminal connected to the second node Q2. Therefore, the stabilization module 30 does not pull down the first node Q1, but pulls the second node Q2 down to a low level.

[0045] Output phase:

[0046] The first node Q1 has been pulled up to a high level, and the first clock signal CLK3 of this stage has changed from a low level to a high level. Based on the high level of the first node Q1 and the high level of the first clock signal CLK3 of this stage, the output module 40 outputs a high-level gate output signal Gn at the output terminal V.

[0047] In one embodiment, the fourth node Q4 has been pulled up to a high level, so the second switching element T2 is in a conducting state. Simultaneously, the first clock signal CLK3 of this stage transitions from a low level to a high level. The third node Q3 receives the high-level first clock signal CLK3 through the conducting second switching element T2, and the third node Q3 is charged to a high level. Meanwhile, the first node Q1 has been pulled up to a high level, so the first switching element T1 is in a conducting state. The output terminal V is connected to the third node Q3 through the conducting first switching element T1, so the output terminal V is at a high level. Therefore, the output module 40 operates, the third node Q3 is pulled up to a high level, and the output terminal V outputs a high-level gate output signal Gn of this stage. In one embodiment, the fourth node Q4 is also pulled up by the first capacitor C1 (charge pump), further increasing the level of the fourth node Q4 and fully opening the second switching element T2. In one embodiment, the first node Q1 is further boosted by the second capacitor C2, thereby raising the level of the first node Q1 and fully opening the first switching element T1.

[0048] Drop-down phase:

[0049] When the gate output signal Gn+4 of the subsequent stage jumps from low level to high level, the pull-down module 20 controls the first node Q1 to receive the fourth clock signal CLK5 of this stage. Then, when the fourth clock signal CLK5 of this stage jumps from high level to low level, the first node Q1 is stably pulled down to low level.

[0050] In one embodiment, when the gate output signal Gn+4 of the subsequent stage transitions from low to high, the seventh switching element T7 receives the high-level gate output signal Gn+4 through its seventh control terminal and becomes on. Consequently, the first node Q1, connected to the thirteenth path terminal of the seventh switching element T7, receives the fourth clock signal CLK5 of this stage through the on-state seventh switching element T7. When the fourth clock signal CLK5 transitions from high to low, the first node Q1 is stably pulled down to a low level. Thus, the pull-down module 20 pulls the first node Q1 down to a low level.

[0051] In one embodiment, when the subsequent gate output signal Gn+4 transitions from low to high, the preceding gate output signal Gn-4 is at a low level. The sixth switching element T6 receives the low-level preceding gate output signal Gn-4 through its sixth control terminal and is in an off state. Therefore, the pre-charge module 10 does not enter the working state.

[0052] In one embodiment, when the first node Q1 is pulled down to a low level, the first control terminal of the first switching element T1 connected to the first node Q1 becomes low, and the first switching element T1 becomes disconnected. Simultaneously, the second clock signal CLK7 of this stage transitions from low to high. The fifth switching element T5 receives the high-level second clock signal CLK7 through its fifth control terminal and becomes on. The fourth node Q4 receives the low-level signal VGL through the on-state fifth switching element T5, and the fourth node Q4 is pulled down to a low level. Since the fourth node Q4 is connected to the second control terminal of the second switching element T2, the second switching element T2 is disconnected. Furthermore, the fourth switching element T4 receives the high-level second clock signal CLK7 through its fourth control terminal and becomes on. The third node Q3 receives the low-level signal VGL through the on-state fourth switching element T4, and the third node Q3 is pulled down to a low level. Therefore, the output module 40 can be used to pull down the third node Q3 to a low level during the pull-down phase, and the output terminal V stops outputting the gate output signal Gn of this stage.

[0053] In one embodiment, when the first node Q1 is pulled down to a low level, the tenth control terminal of the tenth switching element T10 connected to the first node Q1 becomes low, and the tenth switching element T10 becomes disconnected. Consequently, the second node Q2 receives the second high-level signal DC through the conducting twelfth switch, i.e., the second node Q2 becomes high. The twelfth switching element T12 remains in a conducting state because it receives the second high-level signal DC through its twelfth control terminal. Then, the ninth switching element T9 becomes conducting because it receives a high level through its ninth control terminal connected to the second node Q2. The first node Q1 receives a low-level signal VGL through the conducting ninth switching element T9, and the first node Q1 is pulled down to a low level. Simultaneously, the tenth switching element T10 becomes conducting because it receives a high level through its tenth control terminal connected to the second node Q2. The output terminal V receives a low-level signal VGL through the conducting tenth switching element T10, and the output terminal V is pulled down to a low level. Simultaneously, the eighth switching element T8 can receive the high-level second clock signal CLK7 from the eighth control terminal and become conductive. The output terminal V can receive the low-level signal VGL through the conductive eighth switching element T8, and the output terminal V is pulled down to a low level. Thus, the stabilization module 30 can be used to achieve a stable low-level effect between the first node Q1 and the output terminal V.

[0054] Stable phase:

[0055] In other words, during the time period excluding the first three stages, if the pre-charge module 10 receives a low-level front-stage gate output signal Gn-4, then the pre-charge module 10 is not in operation. Simultaneously, if the pull-down module 20 receives a low-level rear-stage gate output signal Gn+4, then the pull-down module 20 is not in operation. Therefore, the pre-charge module 10 and the pull-down module 20 have no effect on the first node Q1. The stabilization module 30 can be used to maintain the first node Q1 and the output terminal V at a low level, and the first pull-down stabilization unit 42 in the output module 40 can be used to maintain the third node Q3 at a low level.

[0056] In one embodiment, during the stabilization phase, the front-stage gate output signal Gn-4 is at a low level, and the sixth switching element T6 receives the low-level front-stage gate output signal Gn-4 through the sixth control terminal and is in an off state. Therefore, the pre-charge module 10 does not enter the working state.

[0057] In one embodiment, during the stabilization phase, the downstream gate output signal Gn+4 is at a low level, and the seventh switching element T7 receives the low-level downstream gate output signal Gn+4 through its seventh control terminal, indicating it is in an off state. Therefore, the pull-down module 20 is not in operation.

[0058] In one embodiment, during the stabilization phase, the first node Q1 is pulled down to a low level, and the tenth control terminal of the tenth switching element T10 connected to the first node Q1 becomes low, thus the tenth switching element T10 becomes disconnected. Consequently, the second node Q2 receives the second high-level signal DC through the conducting twelfth switch, i.e., the second node Q2 becomes high. The twelfth switching element T12 remains in a conducting state by receiving the second high-level signal DC through its twelfth control terminal. Then, the ninth switching element T9 becomes conducting by receiving a high level through its ninth control terminal connected to the second node Q2, and the first node Q1 receives a low-level signal VGL through the conducting ninth switching element T9, pulling the first node Q1 down to a low level. Simultaneously, the tenth switching element T10 becomes conducting by receiving a high level through its tenth control terminal connected to the second node Q2, and the output terminal V receives a low-level signal VGL through the conducting tenth switching element T10, pulling the output terminal V down to a low level. Simultaneously, the eighth switching element T8 can receive the high-level second clock signal CLK7 from the eighth control terminal and become conductive. The output terminal V can receive the low-level signal VGL through the conductive eighth switching element T8, and the output terminal V is pulled down to a low level. Thus, the stabilization module 30 can be used to achieve a stable low-level effect between the first node Q1 and the output terminal V.

[0059] In one embodiment, during the stabilization phase, the first node Q1 is pulled down to a low level, and the second control terminal of the second switching element T2 connected to the first node Q1 is at a low level, thus the second switching element T2 is in an off state. Simultaneously, whenever the second clock signal CLK7 transitions from a low level to a high level, the fifth switching element T5 receives the high-level second clock signal CLK7 through its fifth control terminal and becomes on. Then, the fourth node Q4 receives the low-level signal VGL through the on-state fifth switching element T5, and the fourth node Q4 is pulled down to a low level. Since the fourth node Q4 is connected to the second control terminal of the second switching element T2, the second switching element T2 is in an off state. Furthermore, when the fourth switching element T4 receives the high-level second clock signal CLK7 through its fourth control terminal and becomes on, the third node Q3 receives the low-level signal VGL through the on-state fourth switching element T4, and the third node Q3 is pulled down to a low level. Therefore, the output module 40 can be used to periodically pull down the third node Q3 to a low level during the stable phase. The first clock signal CLK3 of this stage will switch between high and low levels periodically, which will generate noise in the third node Q3. This effectively reduces the noise of the first node Q1 and the output terminal V. Furthermore, the periodic pull-down of the third node Q3 to a low level can prevent the noise of the third node Q3 from accumulating to a high level under the noise of the first clock signal CLK3 of this stage. This can maintain the low level state of the third node Q3, effectively reduce the noise of the first node Q1 and the output terminal V, improve the high temperature resistance, and make it suitable for more application scenarios such as high temperature.

[0060] Figure 4 This is a circuit connection diagram of a gate driving circuit according to another embodiment of the present invention. Please refer to [link / reference]. Figure 4 This embodiment provides a gate driving circuit, whose basic structure, principle and technical effects are the same as those of the previous embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the previous embodiment.

[0061] In one embodiment of the present invention, such as Figure 4As shown, the first high-level signal DCH received at the fifth path terminal of the third switching element T3 is replaced by the second clock signal CLK7 of this stage. That is, the third control terminal of the third switching element T3 receives the gate output signal Gn-4 from the previous stage, the fifth path terminal of the third switching element T3 receives the second clock signal CLK7 of this stage, and the sixth path terminal of the third switching element T3 is connected to the fourth node Q4. Specifically, if the first high-level signal DCH is replaced by the second clock signal CLK7 of this stage, the fourth node Q4 can still be charged during the pre-charge phase by receiving the high-level second clock signal CLK7 of this stage through the conducting third switching element T3. In other phases, the third switching element T3 is in the off state, so it has no effect on the signal on the fifth path terminal. Therefore, in the fifth path of the third switching element T3, the first high-level signal DCH can be replaced by the second clock signal CLK7 of this stage, which can avoid the leakage current at the fifth path terminal of the third switching element T3, as well as the resulting energy loss and heat generation.

[0062] In one embodiment of the present invention, such as Figure 4 As shown, the output module 40 also includes a second pull-down stabilizing unit, which is connected to the output terminal V and pulls the output terminal V down to a low level according to the gate output signal Gn+4 of the subsequent stage.

[0063] In one embodiment of the present invention, such as Figure 4 As shown, the second pull-down stabilizing unit includes a thirteenth switching element T13; the thirteenth switching element T13 includes a thirteenth control terminal, a twenty-fifth path terminal, and a twenty-sixth path terminal. The thirteenth control terminal of the thirteenth switching element T13 receives the gate output signal Gn+4 from the subsequent stage, the twenty-fifth path terminal of the thirteenth switching element T13 is connected to the output terminal V, and the twenty-sixth path terminal of the thirteenth switching element T13 receives the low-level signal VGL.

[0064] Specifically, when the gate output signal Gn+4 transitions from low to high, the thirteenth switching element T13 is in the on state. The output terminal V can be quickly pulled down to low level through the on-state thirteenth switching element T13, which can effectively reduce the falling edge time of the gate output signal without increasing the clock load and improve the image quality of the product.

[0065] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the gate driving circuit as provided in the above embodiments, for providing gate output signals to the gate lines of the display panel. Implementation of this display device can refer to the embodiments of the gate driving circuit described above; repeated details will not be repeated.

[0066] The present invention discloses a multi-stage output gate driving circuit and a display device. The gate driving circuit includes multiple stages of gate driving units. Each stage of the gate driving unit includes a pre-charge module, a pull-down module, a stabilization module, and an output module. The output module is connected to the pre-charge module at a first node and includes a first switching element, a pre-output unit, and a first pull-down stabilization unit. The first control terminal of the first switching element is connected to the first node, the first path terminal is connected to the third node, and the second path terminal is connected to the output terminal. The pre-output unit charges the third node according to the previous stage gate output signal and the first clock signal of the current stage. The first pull-down stabilization unit is used to pull the third node down to a low level according to the second clock signal of the current stage during the stabilization phase. The high-level time period of the second clock signal of the current stage does not overlap with the high-level time period of the first clock signal of the current stage. Therefore, this gate driving circuit can be used to generate gate driving signals, effectively reduce circuit noise during the stabilization phase, improve high-temperature resistance, and enable the display device to be used in more application scenarios.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the invention without departing from the scope of the invention shall still fall within the scope of the present invention.

Claims

1. A gate driving circuit, characterized in that, include: A multi-stage gate driving unit, each stage of which includes a pre-charge module (10), a pull-down module (20), a stabilization module (30), and an output module (40); the output module (40) is connected to the pre-charge module (10) at a first node (Q1), and the output module (40) includes a first switching element (T1), a pre-output unit (41), and a first pull-down stabilization unit (42); The first switching element (T1) includes a first control terminal, a first path terminal and a second path terminal. The first control terminal of the first switching element (T1) is connected to the first node (Q1), the first path terminal of the first switching element (T1) is connected to the third node (Q3), and the second path terminal of the first switching element (T1) is connected to the output terminal (V) and is used to output the gate output signal (Gn) of this stage. The pre-output unit (41) is connected to the third node (Q3) and charges the third node (Q3) according to the front gate output signal (Gn-4) and the first clock signal (CLK3) of this stage; The first pull-down stabilizing unit (42) is connected to the third node (Q3) and is used to pull the third node (Q3) to a low level according to the second clock signal (CLK7) of this stage during the stabilization phase. The high level time period of the second clock signal (CLK7) of this stage does not overlap with the high level time period of the first clock signal (CLK3) of this stage. The pre-output unit (41) includes a second switching element (T2) and a third switching element (T3). The second switching element (T2) includes a second control terminal, a third path terminal, and a fourth path terminal. The second control terminal of the second switching element (T2) is connected to the fourth node (Q4). The third path terminal of the second switching element (T2) receives the first clock signal (CLK3) of this stage. The fourth path terminal of the second switching element (T2) is connected to the third node (Q3). The third switching element (T3) includes a third control terminal, a fifth path terminal, and a sixth path terminal. The third control terminal of the third switching element (T3) receives the gate output signal (Gn-4) of the previous stage. The fifth path terminal of the third switching element (T3) receives the first high-level signal (DCH). The sixth path terminal of the third switching element (T3) is connected to the fourth node (Q4).

2. The gate driving circuit according to claim 1, characterized in that, The first pull-down stabilizing unit (42) includes a fourth switching element (T4) and a fifth switching element (T5); the fourth switching element (T4) includes a fourth control terminal, a seventh path terminal and an eighth path terminal, the fourth control terminal of the fourth switching element (T4) receives the second clock signal (CLK7) of this stage, the seventh path terminal of the fourth switching element (T4) is connected to the third node (Q3), and the eighth path terminal of the fourth switching element (T4) receives a low-level signal (VGL); the fifth switching element (T5) includes a fifth control terminal, a ninth path terminal and a tenth path terminal, the fifth control terminal of the fifth switching element (T5) receives the second clock signal (CLK7) of this stage, the ninth path terminal of the fifth switching element (T5) is connected to the fourth node (Q4), and the tenth path terminal of the fifth switching element (T5) receives the low-level signal (VGL).

3. The gate driving circuit according to claim 1, characterized in that, The output module (40) further includes a first capacitor (C1), the first end of which is connected to the fourth node (Q4), and the second end of which is connected to the third node (Q3).

4. The gate driving circuit according to claim 1, characterized in that, The pre-charge module (10) includes a sixth switching element (T6), which includes a sixth control terminal, an eleventh path terminal, and a twelfth path terminal. The sixth control terminal of the sixth switching element (T6) receives the front-stage gate output signal (Gn-4), the eleventh path terminal of the sixth switching element (T6) receives the third clock signal (CLK1) of this stage, and the twelfth path terminal of the sixth switching element (T6) is connected to the first node (Q1). And / or, the pull-down module (20) includes a seventh switching element (T7), the seventh switching element (T7) includes a seventh control terminal, a thirteenth path terminal and a fourteenth path terminal, the seventh control terminal of the seventh switching element (T7) receives the gate output signal (Gn+4) of the subsequent stage, the thirteenth path terminal of the seventh switching element (T7) is connected to the first node (Q1), and the fourteenth path terminal of the seventh switching element (T7) receives the fourth clock signal (CLK5) of this stage; And / or, the stabilization module (30) includes an eighth switching element (T8), a ninth switching element (T9), a tenth switching element (T10), an eleventh switching element (T11), and a twelfth switching element (T12); the eighth switching element (T8) includes an eighth control terminal, a fifteenth path terminal, and a sixteenth path terminal. The eighth control terminal of the eighth switching element (T8) receives the second clock signal (CLK7) of this stage. The fifteenth path terminal of the eighth switching element (T8) is connected to the output terminal (V). The sixteenth path terminal of the eighth switching element (T8)... The circuit terminal receives a low-level signal (VGL); the ninth switching element (T9) includes a ninth control terminal, a seventeenth path terminal, and an eighteenth path terminal. The ninth control terminal of the ninth switching element (T9) is connected to the second node (Q2), the seventeenth path terminal of the ninth switching element (T9) is connected to the first node (Q1), and the eighteenth path terminal of the ninth switching element (T9) receives the low-level signal (VGL); the tenth switching element (T10) includes a tenth control terminal, a nineteenth path terminal, and a twentieth path terminal. The tenth control terminal is connected to the first node (Q1), and the nineteenth path terminal of the tenth switching element (T10) is connected to the second node (Q2). The twentieth path terminal of the tenth switching element (T10) receives the low-level signal (VGL). The eleventh switching element (T11) includes an eleventh control terminal, a twenty-first path terminal, and a twenty-second path terminal. The eleventh control terminal of the eleventh switching element (T11) is connected to the second node (Q2), and the twenty-first path terminal of the eleventh switching element (T11) is connected to the output terminal (V). The eleventh switching element (T11) receives the low-level signal (VGL) at its twentieth channel terminal; the twelfth switching element (T12) includes a twelfth control terminal, a twentieth-third channel terminal, and a twenty-fourth channel terminal. The twelfth control terminal of the twelfth switching element (T12) receives a second high-level signal (DC). The twentieth channel terminal of the twelfth switching element (T12) is connected to the twelfth control terminal of the twelfth switching element (T12), and the twenty-fourth channel terminal of the twelfth switching element (T12) is connected to the second node (Q2).

5. The gate driving circuit according to claim 4, characterized in that, The duty cycle of the third clock signal (CLK1), the first clock signal (CLK3), the fourth clock signal (CLK5), and the second clock signal (CLK7) of this stage are all 50%, and their clock periods are all equal, and they are successively spaced one-quarter of a clock period apart.

6. The gate driving circuit according to claim 1, characterized in that, The first high-level signal (DCH) received at the fifth path terminal of the third switching element (T3) is replaced by the second clock signal (CLK7) of this stage.

7. The gate driving circuit according to claim 1, characterized in that, The output module (40) further includes a second pull-down stabilizing unit, which is connected to the output terminal (V) and pulls the output terminal (V) down to a low level according to the gate output signal (Gn+4).

8. The gate driving circuit according to claim 7, characterized in that, The second pull-down stabilizing unit includes a thirteenth switching element (T13); the thirteenth switching element (T13) includes a thirteenth control terminal, a twenty-fifth path terminal, and a twenty-sixth path terminal. The thirteenth control terminal of the thirteenth switching element (T13) receives the gate output signal (Gn+4) of the subsequent stage, the twenty-fifth path terminal of the thirteenth switching element (T13) is connected to the output terminal (V), and the twenty-sixth path terminal of the thirteenth switching element (T13) receives a low-level signal (VGL).

9. A display device, characterized in that, Includes the gate drive circuit as described in any one of claims 1 to 8.

Images