Low-noise operational amplifier with wide common-mode input range

Abstract

The invention belongs to the field of analog integrated circuits, and particularly relates to a low-noise operational amplifier with a wide common-mode input range. The amplifier comprises an input bias current adjusting unit, a differential input stage unit, an intermediate gain stage unit and a buffer output stage unit which are connected in sequence, the input bias current adjusting unit is used for sampling input-stage current and adjusting the magnitude and temperature drift of input bias current; the differential input stage unit is used for signal acquisition and adopts a rail-to-rail input type common-emitter common-base differential pair structure; the intermediate gain stage unit amplifies a signal received by the differential input stage unit, and the buffer output stage unit provides enough output current to ensure the current driving capability of the operational amplifier; according to the operational amplifier, the equivalent input voltage noise can be reduced by controlling the working current of the input geminate transistors and the load resistance, the operational amplifier can be ensured to have low input offset voltage by trimming the load resistance, and the requirements of the operational amplifier in low-noise and high-precision application scenes are met.

Description

Technical Field

[0001] The invention belongs to the field of analog integrated circuits, and in particular relates to a low-noise operational amplifier with a wide common-mode input range. Background Art

[0002] The operational amplifier is one of the basic units in the analog signal processing system. It has functions such as signal amplification, active filtering, analog-to-digital conversion (DAC), and digital-to-analog conversion (ADC), and can realize signal processing and transmission. Due to the trade-off relationship between the performance indicators of the operational amplifier, such as speed and power consumption, stability and bandwidth, noise and power consumption, it is difficult to design an operational amplifier with "perfect" indicators in all aspects. The selection of operational amplifiers is usually based on the characteristics of the application scenario, and the design of operational amplifiers has gradually improved key indicators in a targeted manner according to different application scenarios.

[0003] In application systems with high precision requirements or processing weak signals, the large noise of the operational amplifier will seriously affect the performance of the system. In order to meet the growing demand for low-noise performance, it is necessary to design the noise of the operational amplifier specifically to ensure the normal operation of the system. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention proposes a low-noise operational amplifier with a wide common-mode input range, the amplifier comprising: an input bias current adjustment unit, a differential input stage unit, an intermediate gain stage unit and a buffer output stage unit; the input bias current adjustment unit, the differential input stage unit, the intermediate gain stage unit and the buffer output stage unit are connected in sequence;

[0005] The input bias current adjustment unit is used for input stage current sampling and adjusting the input bias current size and its temperature drift. The differential input stage unit is used for signal acquisition and adopts a rail-to-rail input common emitter common base differential pair structure. The intermediate gain stage unit amplifies the signal received by the differential input stage unit. The buffer output stage unit provides sufficient output current to ensure the current driving capability of the operational amplifier.

[0006] Preferably, the input bias current regulating unit includes 11 NPN transistors, 5 PNP transistors, 2 diodes and 5 resistors; the collector of the NPN transistor Q1, one end of the resistors R1 to R3 and the input end of the diode D1 are all connected to the positive electrode of the power supply, the base of the NPN transistor Q1 is connected to the emitter of the NPN transistor Q10, the base of the PNP transistor Q2 and the emitter of the PNP transistor Q13, the emitter of the NPN transistor Q1 is connected to the emitter of the PNP transistor Q2, the base of the PNP transistor Q11 and the base of the NPN transistor Q12; the collector of the PNP transistor Q2 is connected to the base of the NPN transistor Q4 The base, the base of NPN transistor Q5 and the collector of NPN transistor Q3; the emitter of NPN transistor Q3, the emitter of NPN transistor Q6, one end of resistors R4~R6 and the output end of diode D2 are all connected to the negative electrode of the power supply, the base of NPN transistor Q3 is connected to the base of NPN transistor Q6 and the collector of NPN transistor Q6; the collector of NPN transistor Q4 is connected to the differential input stage unit, the emitter of NPN transistor Q4 is connected to the emitter of NPN transistor Q5 and the collector of NPN transistor Q6; the collector of NPN transistor Q5 is connected to the differential input stage unit; the emitter of PNP transistor Q7 The other end of the resistor R1 is connected, the base of the PNP transistor Q7 is connected to the base of the PNP transistor Q8, the collector of the PNP transistor Q7 and the collector of the NPN transistor Q10; the emitter of the PNP transistor Q8 is connected to the other end of the resistor R2, the collector of the PNP transistor Q8 is connected to the base of the PNP transistor Q9 and the differential input stage unit; the collector of the PNP transistor Q9 is connected to the emitter of the PNP transistor Q11; the base of the NPN transistor Q10 is connected to the differential input stage unit; the collector of the PNP transistor Q11 is connected to the input end of the diode D2; the collector of the NPN transistor Q12 is connected to the input The output end, the emitter of the NPN transistor Q12 is connected to the collector of the NPN transistor Q16; the base of the PNP transistor Q13 is connected to the differential input stage unit, the collector of the PNP transistor Q13 is connected to the collector of the NPN transistor Q14, the base of the NPN transistor Q14 and the base of the NPN transistor Q15; the emitter of the NPN transistor Q14 is connected to the other end of the resistor R4; the collector of the NPN transistor Q15 is connected to the base of the NPN transistor Q16 and the differential input stage unit, the emitter of the NPN transistor Q15 is connected to the other end of the resistor R5; the emitter of the NPN transistor Q16 is connected to the other end of the resistor R6.

[0007] Preferably, the differential input stage unit includes 15 NPN transistors, 15 PNP transistors, 14 resistors and 2 capacitors; one end of resistors R7-R9 and resistors R13-R15 are all connected to the positive electrode of the power supply; the base of NPN transistor Q18 is connected to the base of PNP transistor Q10 and the collector of NPN transistor Q4 in the input bias current adjustment unit, the collector of NPN transistor Q18 is connected to the other end of resistor R1, the collector of NPN transistor Q23 and the emitter of PNP transistor Q35, the emitter of NPN transistor Q18 is connected to the emitter of NPN transistor Q19, the collector of NPN transistor Q22 and the base of PNP transistor Q13 in the input bias current adjustment unit; PNP transistor The emitter of transistor Q17 is connected to the other end of resistor R8, the base of PNP transistor Q17 is connected to the base of PNP transistor Q33, the collector of PNP transistor Q33 and the base of PNP transistor Q9 in the input bias current adjustment unit, the collector of PNP transistor Q17 is connected to the emitter of PNP transistor Q20, the emitter of PNP transistor Q21 and the base of NPN transistor Q10 in the input bias current adjustment unit; the collector of NPN transistor Q19 is connected to one end of resistor R9, the collector of NPN transistor Q24 and the emitter of PNP transistor Q34, the base of NPN transistor Q19 is connected to the base of PNP transistor Q21 and NPN transistor Q5 in the input bias current adjustment unit. The collector of the PNP transistor Q20 is connected to one end of the resistor R10, the collector of the PNP transistor Q27 and the emitter of the NPN transistor Q43; the collector of the PNP transistor Q21 is connected to one end of the resistor R22, the collector of the PNP transistor Q28 and the emitter of the NPN transistor Q42; the base of the NPN transistor Q22 is connected to the base of the NPN transistor Q46, the collector of the NPN transistor Q46 and the base of the NPN transistor Q16 in the input bias current adjustment unit; the emitter of the NPN transistor Q22 is connected to one end of the resistor R11; the base of the NPN transistor Q23 is connected to the collector of the PNP transistor Q31, the base of the NPN transistor Q24 and the base of the PNP transistor Q2 5, the emitter of the NPN transistor Q23 is connected to the emitter of the PNP transistor Q27 and one end of the capacitor C1; the emitter of the NPN transistor Q24 is connected to the other end of the capacitor C2 and the emitter of the PNP transistor Q28; the collector of the PNP transistor Q25 is connected to the collector of the NPN transistor Q29, the base of the PNP transistor Q25, the base of the NPN transistor Q29, the collector of the PNP transistor Q26 and the collector of the NPN transistor Q30; the emitter of the PNP transistor Q26 is connected to the collector of the PNP transistor Q32, and the base of the PNP transistor Q26 is connected to the base of the NPN transistor Q30, the collector of the PNP transistor Q36 and the collector of the NPN transistor Q41;The base of the PNP transistor Q27 is connected to the emitter of the NPN transistor Q30 and the collector of the NPN transistor Q45; the base of the PNP transistor Q28 is connected to the emitter of the NPN transistor Q29 and the collector of the NPN transistor Q44; the emitter of the PNP transistor Q31 is connected to the other end of the resistor R13, and the base of the PNP transistor Q31 is connected to the base of the PNP transistor Q32; the emitter of the PNP transistor Q32 is connected to the other end of the resistor R14; the emitter of the PNP transistor Q33 is connected to the other end of the resistor R15; The base of the P transistor Q34 is connected to the base of the PNP transistor Q35, the collector of the PNP transistor Q34 and the emitter of the PNP transistor Q36; the collector of the PNP transistor Q35 is connected to the base of the PNP transistor Q36, the collector of the NPN transistor Q38 and the intermediate gain stage unit; the collector of the NPN transistor Q37 is connected to the collector of the PNP transistor Q33, the base of the NPN transistor Q37 is connected to one end of the capacitor C2 and the base of the NPN transistor Q38, and the emitter of the NPN transistor Q37 is connected to the end of the resistor R19. The emitter of the PNP transistor Q39 is connected to one end of the resistor R19; the emitter of the NPN transistor Q38 is connected to the emitter of the resistor R20, and the other end of the resistor R20 is connected to the emitter of the PNP transistor Q40; the base of the PNP transistor Q39 is connected to the other end of the capacitor C2 and the base of the PNP transistor Q40; the collector of the PNP transistor Q39 is connected to the collector of the NPN transistor Q46; the collector of the PNP transistor Q40 is connected to the base of the NPN transistor Q41, the collector of the NPN transistor Q43 and the intermediate gain stage Unit; the emitter of NPN transistor Q41 is connected to the collector of NPN transistor Q42, the base of NPN transistor Q42 and the base of NPN transistor Q43; the emitter of NPN transistor Q44 is connected to one end of resistor R16, and the base of NPN transistor Q44 is connected to the base of NPN transistor Q45; the emitter of NPN transistor Q45 is connected to one end of resistor R17; the emitter of NPN transistor Q46 is connected to one end of resistor R18; the other ends of resistors R10~R13 and resistors R16~R18 are all connected to the negative electrode of the power supply. ;

[0008] Preferably, the intermediate gain stage unit includes 2 NPN transistors, 2 PNP transistors and 6 resistors; one end of the resistor R25 and the resistor R26 are both connected to the positive electrode of the power supply; the other end of the resistor R25 is connected to the emitter of the PNP transistor Q47, the base of the PNP transistor Q47 is connected to the collector of the PNP transistor Q47, one end of the resistor R21 and the buffer output stage unit; the emitter of the PNP transistor Q49 is connected to the other end of the resistor R21, the base of the PNP transistor Q49 is connected to the collector of the PNP transistor Q35 in the differential input stage unit, and the PNP transistor The collector of Q49 is connected to one end of the resistor R22; the collector of the NPN transistor Q50 is connected to the other end of the resistor R23, the base of the NPN transistor Q50 is connected to the collector of the PNP transistor Q40 in the differential input stage unit, and the emitter of the NPN transistor Q50 is connected to one end of the resistor R24; the collector of the NPN transistor Q51 is connected to the other end of the resistor R24, the base of the NPN transistor Q51 and the buffer output stage unit, and the emitter of the NPN transistor Q51 is connected to one end of the resistor R27; the other ends of the resistors R22 and R27 are both connected to the negative electrode of the power supply.

[0009] Preferably, the buffer output stage unit includes 3 NPN transistors, 3 PNP transistors and 4 resistors; one end of the resistor R26, the collector of the NPN transistor Q53 and the collector of the NPN transistor Q55 are all connected to the positive electrode of the power supply; the other end of the resistor R26 is connected to the emitter of the PNP transistor Q48, the base of the PNP transistor Q48 is connected to the base of the PNP transistor Q47 in the intermediate gain stage unit, the collector of the PNP transistor Q48 is connected to the emitter of the PNP transistor Q54 and the base of the NPN transistor Q55; the base of the NPN transistor Q53 is connected to the base of the PNP transistor Q54, and the base of the NPN transistor Q55 is connected to the base of the PNP transistor Q54. The emitter of transistor Q53 is connected to the collector of NPN transistor Q52 and the base of PNP transistor Q56; the base of NPN transistor Q52 is connected to the base of NPN transistor Q51 in the intermediate gain stage unit, and the emitter of NPN transistor Q52 is connected to one end of resistor R28; the emitter of NPN transistor Q55 is connected to one end of resistor R29, the other end of resistor R29 is connected to one end of resistor R30, and the other end of resistor R30 is connected to the emitter of PNP transistor Q56; the other end of resistor R28, the collector of PNP transistor Q54 and the collector of PNP transistor Q56 are all connected to the negative electrode of the power supply.

[0010] The beneficial effects of the present invention are as follows: the present invention adopts a rail-to-rail input common-emitter common-base differential pair structure, so that the operational amplifier has a wide common-mode input range, and the equivalent input voltage noise can be achieved below 1nV / √Hz by controlling the working current of the input pair tube and the load resistance. In addition, by adjusting the load resistance, the operational amplifier can be guaranteed to have a low input offset voltage, which is lower than 0.5mV, meeting the requirements of the operational amplifier in low noise, high precision, and wide common-mode input range application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the circuit structure of a low-noise operational amplifier with a wide common-mode input range in the present invention;

[0012] Figure 2 A schematic diagram of the equivalent input voltage noise of the operational amplifier in the present invention;

[0013] Figure 3 A schematic diagram of the input common mode range of the operational amplifier in the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] The present invention proposes a low noise operational amplifier with a wide common mode input range, such as Figure 1 As shown, the amplifier includes: an input bias current adjustment unit, a differential input stage unit, an intermediate gain stage unit and a buffer output stage unit; the input bias current adjustment unit, the differential input stage unit, the intermediate gain stage unit and the buffer output stage unit are connected in sequence;

[0016] The input bias current adjustment unit is used for sampling the input current and adjusting the input bias current and its temperature drift;

[0017] The differential input stage unit is used for signal acquisition and adopts a rail-to-rail input cascode differential pair structure, which can effectively improve the speed of the input differential pair while ensuring the gain;

[0018] The intermediate gain stage unit is mainly used to amplify the signal received by the input stage, has a very high output impedance, and can achieve a high open-loop gain (>60dB);

[0019] The buffer output stage unit is used to provide sufficient output current to ensure the current driving capability of the operational amplifier.

[0020] Preferably, the input bias current regulating unit includes 11 NPN transistors, 5 PNP transistors, 2 diodes and 5 resistors; the collector of the NPN transistor Q1, one end of the resistors R1 to R3 and the input end of the diode D1 are all connected to the positive electrode of the power supply, the base of the NPN transistor Q1 is connected to the emitter of the NPN transistor Q10, the base of the PNP transistor Q2 and the emitter of the PNP transistor Q13, the emitter of the NPN transistor Q1 is connected to the emitter of the PNP transistor Q2, the base of the PNP transistor Q11 and the base of the NPN transistor Q12; the collector of the PNP transistor Q2 is connected to the base of the NPN transistor Q4 The base, the base of NPN transistor Q5 and the collector of NPN transistor Q3; the emitter of NPN transistor Q3, the emitter of NPN transistor Q6, one end of resistors R4~R6 and the output end of diode D2 are all connected to the negative electrode of the power supply, the base of NPN transistor Q3 is connected to the base of NPN transistor Q6 and the collector of NPN transistor Q6; the collector of NPN transistor Q4 is connected to the differential input stage unit, the emitter of NPN transistor Q4 is connected to the emitter of NPN transistor Q5 and the collector of NPN transistor Q6; the collector of NPN transistor Q5 is connected to the differential input stage unit; the emitter of PNP transistor Q7 The other end of the resistor R1 is connected, the base of the PNP transistor Q7 is connected to the base of the PNP transistor Q8, the collector of the PNP transistor Q7 and the collector of the NPN transistor Q10; the emitter of the PNP transistor Q8 is connected to the other end of the resistor R2, the collector of the PNP transistor Q8 is connected to the base of the PNP transistor Q9 and the differential input stage unit; the collector of the PNP transistor Q9 is connected to the emitter of the PNP transistor Q11; the base of the NPN transistor Q10 is connected to the differential input stage unit; the collector of the PNP transistor Q11 is connected to the input end of the diode D2; the collector of the NPN transistor Q12 is connected to the input The output end, the emitter of the NPN transistor Q12 is connected to the collector of the NPN transistor Q16; the base of the PNP transistor Q13 is connected to the differential input stage unit, the collector of the PNP transistor Q13 is connected to the collector of the NPN transistor Q14, the base of the NPN transistor Q14 and the base of the NPN transistor Q15; the emitter of the NPN transistor Q14 is connected to the other end of the resistor R4; the collector of the NPN transistor Q15 is connected to the base of the NPN transistor Q16 and the differential input stage unit, the emitter of the NPN transistor Q15 is connected to the other end of the resistor R5; the emitter of the NPN transistor Q16 is connected to the other end of the resistor R6.

[0021] Preferably, the differential input stage unit includes 15 NPN transistors, 15 PNP transistors, 14 resistors and 2 capacitors; one end of resistors R7-R9 and resistors R13-R15 are all connected to the positive electrode of the power supply; the base of NPN transistor Q18 is connected to the base of PNP transistor Q10 and the collector of NPN transistor Q4 in the input bias current adjustment unit, the collector of NPN transistor Q18 is connected to the other end of resistor R1, the collector of NPN transistor Q23 and the emitter of PNP transistor Q35, the emitter of NPN transistor Q18 is connected to the emitter of NPN transistor Q19, the collector of NPN transistor Q22 and the base of PNP transistor Q13 in the input bias current adjustment unit; PNP transistor The emitter of transistor Q17 is connected to the other end of resistor R8, the base of PNP transistor Q17 is connected to the base of PNP transistor Q33, the collector of PNP transistor Q33 and the base of PNP transistor Q9 in the input bias current adjustment unit, the collector of PNP transistor Q17 is connected to the emitter of PNP transistor Q20, the emitter of PNP transistor Q21 and the base of NPN transistor Q10 in the input bias current adjustment unit; the collector of NPN transistor Q19 is connected to one end of resistor R9, the collector of NPN transistor Q24 and the emitter of PNP transistor Q34, the base of NPN transistor Q19 is connected to the base of PNP transistor Q21 and NPN transistor Q5 in the input bias current adjustment unit. The collector of the PNP transistor Q20 is connected to one end of the resistor R10, the collector of the PNP transistor Q27 and the emitter of the NPN transistor Q43; the collector of the PNP transistor Q21 is connected to one end of the resistor R22, the collector of the PNP transistor Q28 and the emitter of the NPN transistor Q42; the base of the NPN transistor Q22 is connected to the base of the NPN transistor Q46, the collector of the NPN transistor Q46 and the base of the NPN transistor Q16 in the input bias current adjustment unit; the emitter of the NPN transistor Q22 is connected to one end of the resistor R11; the base of the NPN transistor Q23 is connected to the collector of the PNP transistor Q31, the base of the NPN transistor Q24 and the base of the PNP transistor Q2 5, the emitter of the NPN transistor Q23 is connected to the emitter of the PNP transistor Q27 and one end of the capacitor C1; the emitter of the NPN transistor Q24 is connected to the other end of the capacitor C2 and the emitter of the PNP transistor Q28; the collector of the PNP transistor Q25 is connected to the collector of the NPN transistor Q29, the base of the PNP transistor Q25, the base of the NPN transistor Q29, the collector of the PNP transistor Q26 and the collector of the NPN transistor Q30; the emitter of the PNP transistor Q26 is connected to the collector of the PNP transistor Q32, and the base of the PNP transistor Q26 is connected to the base of the NPN transistor Q30, the collector of the PNP transistor Q36 and the collector of the NPN transistor Q41;The base of the PNP transistor Q27 is connected to the emitter of the NPN transistor Q30 and the collector of the NPN transistor Q45; the base of the PNP transistor Q28 is connected to the emitter of the NPN transistor Q29 and the collector of the NPN transistor Q44; the emitter of the PNP transistor Q31 is connected to the other end of the resistor R13, and the base of the PNP transistor Q31 is connected to the base of the PNP transistor Q32; the emitter of the PNP transistor Q32 is connected to the other end of the resistor R14; the emitter of the PNP transistor Q33 is connected to the other end of the resistor R15; The base of the P transistor Q34 is connected to the base of the PNP transistor Q35, the collector of the PNP transistor Q34 and the emitter of the PNP transistor Q36; the collector of the PNP transistor Q35 is connected to the base of the PNP transistor Q36, the collector of the NPN transistor Q38 and the intermediate gain stage unit; the collector of the NPN transistor Q37 is connected to the collector of the PNP transistor Q33, the base of the NPN transistor Q37 is connected to one end of the capacitor C2 and the base of the NPN transistor Q38, and the emitter of the NPN transistor Q37 is connected to the end of the resistor R19. The emitter of the PNP transistor Q39 is connected to one end of the resistor R19; the emitter of the NPN transistor Q38 is connected to the emitter of the resistor R20, and the other end of the resistor R20 is connected to the emitter of the PNP transistor Q40; the base of the PNP transistor Q39 is connected to the other end of the capacitor C2 and the base of the PNP transistor Q40; the collector of the PNP transistor Q39 is connected to the collector of the NPN transistor Q46; the collector of the PNP transistor Q40 is connected to the base of the NPN transistor Q41, the collector of the NPN transistor Q43 and the intermediate gain stage Unit; the emitter of NPN transistor Q41 is connected to the collector of NPN transistor Q42, the base of NPN transistor Q42 and the base of NPN transistor Q43; the emitter of NPN transistor Q44 is connected to one end of resistor R16, and the base of NPN transistor Q44 is connected to the base of NPN transistor Q45; the emitter of NPN transistor Q45 is connected to one end of resistor R17; the emitter of NPN transistor Q46 is connected to one end of resistor R18; the other ends of resistors R10~R13 and resistors R16~R18 are all connected to the negative electrode of the power supply. ;

[0022] The differential input stage unit is the core unit of the present invention. It uses NPN input pair transistors Q18-Q19 and PNN input pair transistors Q20-Q21 that can realize rail-to-rail input, which can make the common-mode input voltage range reach V CC -1.3V~V EE +1.3V, the emitter area ratio of transistors Q18: Q19: Q20: Q21 is 1:1:1:1. The NPN input pair and PNP input pair are large-size transistors. Their noise contribution mainly includes the thermal noise and flicker noise of transistors Q18 to Q21. The noise expression is:

[0023]

[0024] The input stage uses resistors R7, R9, R10, and R12 as loads, and the resistance ratio of resistors R7: R9: R10: R12 is 1:1:1:1. Using resistors as loads can avoid the low-frequency noise of transistors. The noise contribution of the load resistors is mainly thermal noise, and its equivalent noise current expression is:

[0025]

[0026] Converting the noise of the input pair tube and load to the input end, the equivalent input voltage noise expression is:

[0027]

[0028] in, represents the noise current of input transistors Q19 and Q21, k represents the Boltzmann constant, T represents the temperature, and r b19，21 represents the base resistance of input transistors Q19 and Q21, g m19，21 represents the transconductance of the input transistors Q19 and Q21, K' represents a fixed constant that is device-dependent, and I C19，21 represents the collector current of input transistors Q19 and Q21, f represents the frequency, represents the noise current of the load resistors R9 and R12, R 9，12 Represents the input stage load resistors R9 and R12, represents the equivalent input voltage noise, r b19 represents the base resistance of the NPN input transistor Q19, g m19 represents the transconductance of the NPN input transistor Q19, I C19 represents the collector current of NPN input transistor Q19, r o19 represents the output resistance of NPN input transistor Q19, r b21 represents the base resistance of the PNP input transistor Q21, g m21 represents the transconductance of the PNP input transistor Q21, r o21 represents the output resistance of the PNP input transistor Q21.

[0029] From the above expression, we can see that the main parameters affecting the equivalent input voltage noise of the operational amplifier include the base resistance r of the transistor. b , the operating current of the transistor I C And load resistance R. In the present invention, the input pair transistors Q18-Q21 use large-sized multi-finger transistors, which can effectively reduce the base resistance r of the transistor. b, increase the operating current of the transistor to the milliampere level, and increase the transconductance of the input to the tube. Reduce the load resistors R7, R9, R10, and R12 as much as possible, and finally achieve a value lower than At the same time, resistors R7 and R9 can be adjusted to make the input offset voltage of the operational amplifier lower than 0.5V, which has high precision.

[0030] Preferably, the intermediate gain stage unit includes 2 NPN transistors, 2 PNP transistors and 6 resistors; one end of the resistor R25 and the resistor R26 are both connected to the positive electrode of the power supply; the other end of the resistor R25 is connected to the emitter of the PNP transistor Q47, the base of the PNP transistor Q47 is connected to the collector of the PNP transistor Q47, one end of the resistor R21 and the buffer output stage unit; the emitter of the PNP transistor Q49 is connected to the other end of the resistor R21, the base of the PNP transistor Q49 is connected to the collector of the PNP transistor Q35 in the differential input stage unit, and the PNP transistor The collector of Q49 is connected to one end of the resistor R22; the collector of the NPN transistor Q50 is connected to the other end of the resistor R23, the base of the NPN transistor Q50 is connected to the collector of the PNP transistor Q40 in the differential input stage unit, and the emitter of the NPN transistor Q50 is connected to one end of the resistor R24; the collector of the NPN transistor Q51 is connected to the other end of the resistor R24, the base of the NPN transistor Q51 and the buffer output stage unit, and the emitter of the NPN transistor Q51 is connected to one end of the resistor R27; the other ends of the resistors R22 and R27 are both connected to the negative electrode of the power supply.

[0031] Preferably, the buffer output stage unit includes 3 NPN transistors, 3 PNP transistors and 4 resistors; one end of the resistor R26, the collector of the NPN transistor Q53 and the collector of the NPN transistor Q55 are all connected to the positive electrode of the power supply; the other end of the resistor R26 is connected to the emitter of the PNP transistor Q48, the base of the PNP transistor Q48 is connected to the base of the PNP transistor Q47 in the intermediate gain stage unit, the collector of the PNP transistor Q48 is connected to the emitter of the PNP transistor Q54 and the base of the NPN transistor Q55; the base of the NPN transistor Q53 is connected to the base of the PNP transistor Q54, and the base of the NPN transistor Q55 is connected to the base of the PNP transistor Q54. The emitter of transistor Q53 is connected to the collector of NPN transistor Q52 and the base of PNP transistor Q56; the base of NPN transistor Q52 is connected to the base of NPN transistor Q51 in the intermediate gain stage unit, and the emitter of NPN transistor Q52 is connected to one end of resistor R28; the emitter of NPN transistor Q55 is connected to one end of resistor R29, the other end of resistor R29 is connected to one end of resistor R30, and the other end of resistor R30 is connected to the emitter of PNP transistor Q56; the other end of resistor R28, the collector of PNP transistor Q54 and the collector of PNP transistor Q56 are all connected to the negative electrode of the power supply.

[0032] In the operational amplifier, the NPN differential input pair inputs a positive signal IN+, the PNP differential input pair inputs a negative signal IN-, and the output signal is between the resistor R29 and the resistor R30. The present invention can achieve the same level of low noise characteristics as foreign circuits by designing the input stage with low noise, such as Figure 2 As shown, the present invention can achieve an equivalent input voltage noise as low as 793pV / √Hz at a frequency of f=1kHz. At the same time, the present invention takes into account the common mode input range, such as Figure 3 As shown, when the positive and negative power supplies are 5V and -5V respectively, the common-mode input range can reach -3.7V to 3.7V.

[0033] In summary, the operational amplifier designed by the present invention includes a three-stage amplification structure, and the input stage adopts a folded common emitter and common base structure, including an NPN-type differential input pair of tubes (Q18, Q19) and a PNP-type differential input pair of tubes (Q20, Q21), so that the circuit has a wide common-mode input range, and uses passive device resistance as a load, which effectively reduces the low-frequency noise of the circuit, and at the same time sets a larger input pair of tubes (NPN pair of tubes, PNP pair of tubes) area and working current to achieve the low-noise characteristics of the circuit. The present invention can achieve an equivalent input voltage noise of less than 1nV / √Hz by controlling the working current of the input pair of tubes and the load resistance. In addition, by adjusting the load resistance, it can be ensured that the operational amplifier has a low input offset voltage of less than 0.5mV, which meets the requirements of the operational amplifier in low-noise, high-precision, and wide common-mode input range application scenarios.

[0034] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A low noise operational amplifier with a wide common mode input range, characterized in that: include: An input bias current adjustment unit, a differential input stage unit, an intermediate gain stage unit, and a buffer output stage unit; The input bias current adjustment unit, the differential input stage unit, the intermediate gain stage unit and the buffer output stage unit are connected in sequence; The input bias current adjustment unit is used for input stage current sampling and adjusting the input bias current size and its temperature drift; the differential input stage unit is used for signal acquisition and adopts a rail-to-rail input common emitter common base differential pair structure; the intermediate gain stage unit amplifies the signal received by the differential input stage unit, and the buffer output stage unit provides sufficient output current to ensure the current driving capability of the operational amplifier.

2. A low noise operational amplifier with a wide common mode input range according to claim 1, characterized in that: The input bias current regulating unit includes 11 NPN transistors, 5 PNP transistors, 2 diodes and 5 resistors; the collector of the NPN transistor Q1, one end of the resistors R1 to R3 and the input end of the diode D1 are all connected to the positive electrode of the power supply; the base of the NPN transistor Q1 is connected to the emitter of the NPN transistor Q10, the base of the PNP transistor Q2 and the emitter of the PNP transistor Q13; the emitter of the NPN transistor Q1 is connected to the emitter of the PNP transistor Q2, the base of the PNP transistor Q11 and the base of the NPN transistor Q12; the collector of the PNP transistor Q2 is connected to the base of the NPN transistor Q4 , the base of NPN transistor Q5 and the collector of NPN transistor Q3; the emitter of NPN transistor Q3, the emitter of NPN transistor Q6, one end of resistors R4~R6 and the output end of diode D2 are all connected to the negative electrode of the power supply, the base of NPN transistor Q3 is connected to the base of NPN transistor Q6 and the collector of NPN transistor Q6; the collector of NPN transistor Q4 is connected to the differential input stage unit, the emitter of NPN transistor Q4 is connected to the emitter of NPN transistor Q5 and the collector of NPN transistor Q6; the collector of NPN transistor Q5 is connected to the differential input stage unit; the emitter of PNP transistor Q7 is connected The other end of the resistor R1 is connected, the base of the PNP transistor Q7 is connected to the base of the PNP transistor Q8, the collector of the PNP transistor Q7 and the collector of the NPN transistor Q10; the emitter of the PNP transistor Q8 is connected to the other end of the resistor R2, the collector of the PNP transistor Q8 is connected to the base of the PNP transistor Q9 and the differential input stage unit; the collector of the PNP transistor Q9 is connected to the emitter of the PNP transistor Q11; the base of the NPN transistor Q10 is connected to the differential input stage unit; the collector of the PNP transistor Q11 is connected to the input end of the diode D2; the collector of the NPN transistor Q12 is connected to the input The output end, the emitter of the NPN transistor Q12 is connected to the collector of the NPN transistor Q16; the base of the PNP transistor Q13 is connected to the differential input stage unit, the collector of the PNP transistor Q13 is connected to the collector of the NPN transistor Q14, the base of the NPN transistor Q14 and the base of the NPN transistor Q15; the emitter of the NPN transistor Q14 is connected to the other end of the resistor R4; the collector of the NPN transistor Q15 is connected to the base of the NPN transistor Q16 and the differential input stage unit, the emitter of the NPN transistor Q15 is connected to the other end of the resistor R5; the emitter of the NPN transistor Q16 is connected to the other end of the resistor R6.

3. A low noise operational amplifier with a wide common mode input range according to claim 1, characterized in that: The differential input stage unit includes 15 NPN transistors, 15 PNP transistors, 14 resistors and 2 capacitors; one end of resistors R7-R9 and resistors R13-R15 are connected to the positive electrode of the power supply; the base of NPN transistor Q18 is connected to the base of PNP transistor Q10 and the collector of NPN transistor Q4 in the input bias current adjustment unit, the collector of NPN transistor Q18 is connected to the other end of resistor R1, the collector of NPN transistor Q23 and the emitter of PNP transistor Q35, the emitter of NPN transistor Q18 is connected to the emitter of NPN transistor Q19, the collector of NPN transistor Q22 and the base of PNP transistor Q13 in the input bias current adjustment unit; PNP transistor The emitter of Q17 is connected to the other end of the resistor R8, the base of the PNP transistor Q17 is connected to the base of the PNP transistor Q33, the collector of the PNP transistor Q33 and the base of the PNP transistor Q9 in the input bias current adjustment unit, the collector of the PNP transistor Q17 is connected to the emitter of the PNP transistor Q20, the emitter of the PNP transistor Q21 and the base of the NPN transistor Q10 in the input bias current adjustment unit; the collector of the NPN transistor Q19 is connected to one end of the resistor R9, the collector of the NPN transistor Q24 and the emitter of the PNP transistor Q34, the base of the NPN transistor Q19 is connected to the base of the PNP transistor Q21 and the base of the NPN transistor Q5 in the input bias current adjustment unit. collector; the collector of the PNP transistor Q20 is connected to one end of the resistor R10, the collector of the PNP transistor Q27 and the emitter of the NPN transistor Q43; the collector of the PNP transistor Q21 is connected to one end of the resistor R22, the collector of the PNP transistor Q28 and the emitter of the NPN transistor Q42; the base of the NPN transistor Q22 is connected to the base of the NPN transistor Q46, the collector of the NPN transistor Q46 and the base of the NPN transistor Q16 in the input bias current adjustment unit; the emitter of the NPN transistor Q22 is connected to one end of the resistor R11; the base of the NPN transistor Q23 is connected to the collector of the PNP transistor Q31, the base of the NPN transistor Q24 and the base of the PNP transistor Q25 The emitter of the NPN transistor Q23 is connected to the emitter of the PNP transistor Q27 and one end of the capacitor C1; the emitter of the NPN transistor Q24 is connected to the other end of the capacitor C2 and the emitter of the PNP transistor Q28; the collector of the PNP transistor Q25 is connected to the collector of the NPN transistor Q29, the base of the PNP transistor Q25, the base of the NPN transistor Q29, the collector of the PNP transistor Q26 and the collector of the NPN transistor Q30; the emitter of the PNP transistor Q26 is connected to the collector of the PNP transistor Q32, and the base of the PNP transistor Q26 is connected to the base of the NPN transistor Q30, the collector of the PNP transistor Q36 and the collector of the NPN transistor Q41;The base of the PNP transistor Q27 is connected to the emitter of the NPN transistor Q30 and the collector of the NPN transistor Q45; the base of the PNP transistor Q28 is connected to the emitter of the NPN transistor Q29 and the collector of the NPN transistor Q44; the emitter of the PNP transistor Q31 is connected to the other end of the resistor R13, and the base of the PNP transistor Q31 is connected to the base of the PNP transistor Q32; the emitter of the PNP transistor Q32 is connected to the other end of the resistor R14; the emitter of the PNP transistor Q33 is connected to the other end of the resistor R15; The base of the P transistor Q34 is connected to the base of the PNP transistor Q35, the collector of the PNP transistor Q34 and the emitter of the PNP transistor Q36; the collector of the PNP transistor Q35 is connected to the base of the PNP transistor Q36, the collector of the NPN transistor Q38 and the intermediate gain stage unit; the collector of the NPN transistor Q37 is connected to the collector of the PNP transistor Q33, the base of the NPN transistor Q37 is connected to one end of the capacitor C2 and the base of the NPN transistor Q38, and the emitter of the NPN transistor Q37 is connected to the end of the resistor R19. The emitter of the PNP transistor Q39 is connected to one end of the resistor R19; the emitter of the NPN transistor Q38 is connected to the emitter of the resistor R20, and the other end of the resistor R20 is connected to the emitter of the PNP transistor Q40; the base of the PNP transistor Q39 is connected to the other end of the capacitor C2 and the base of the PNP transistor Q40; the collector of the PNP transistor Q39 is connected to the collector of the NPN transistor Q46; the collector of the PNP transistor Q40 is connected to the base of the NPN transistor Q41, the collector of the NPN transistor Q43 and the intermediate gain stage Unit; the emitter of NPN transistor Q41 is connected to the collector of NPN transistor Q42, the base of NPN transistor Q42 and the base of NPN transistor Q43; the emitter of NPN transistor Q44 is connected to one end of resistor R16, and the base of NPN transistor Q44 is connected to the base of NPN transistor Q45; the emitter of NPN transistor Q45 is connected to one end of resistor R17; the emitter of NPN transistor Q46 is connected to one end of resistor R18; the other ends of resistors R10~R13 and resistors R16~R18 are all connected to the negative electrode of the power supply. ; 4. The low noise operational amplifier with a wide common mode input range according to claim 1, characterized in that: The intermediate gain stage unit includes 2 NPN transistors, 2 PNP transistors and 6 resistors; one end of the resistor R25 and the resistor R26 are both connected to the positive electrode of the power supply; the other end of the resistor R25 is connected to the emitter of the PNP transistor Q47, the base of the PNP transistor Q47 is connected to the collector of the PNP transistor Q47, one end of the resistor R21 and the buffer output stage unit; the emitter of the PNP transistor Q49 is connected to the other end of the resistor R21, the base of the PNP transistor Q49 is connected to the collector of the PNP transistor Q35 in the differential input stage unit, and the PNP transistor Q The collector of 49 is connected to one end of the resistor R22; the collector of the NPN transistor Q50 is connected to the other end of the resistor R23, the base of the NPN transistor Q50 is connected to the collector of the PNP transistor Q40 in the differential input stage unit, and the emitter of the NPN transistor Q50 is connected to one end of the resistor R24; the collector of the NPN transistor Q51 is connected to the other end of the resistor R24, the base of the NPN transistor Q51 and the buffer output stage unit, and the emitter of the NPN transistor Q51 is connected to one end of the resistor R27; the other ends of the resistors R22 and R27 are both connected to the negative electrode of the power supply.

5. The low noise operational amplifier with wide common mode input range according to claim 1, characterized in that: The buffer output stage unit includes 3 NPN transistors, 3 PNP transistors and 4 resistors; one end of the resistor R26, the collector of the NPN transistor Q53 and the collector of the NPN transistor Q55 are all connected to the positive electrode of the power supply; the other end of the resistor R26 is connected to the emitter of the PNP transistor Q48, the base of the PNP transistor Q48 is connected to the base of the PNP transistor Q47 in the intermediate gain stage unit, the collector of the PNP transistor Q48 is connected to the emitter of the PNP transistor Q54 and the base of the NPN transistor Q55; the base of the NPN transistor Q53 is connected to the base of the PNP transistor Q54, and the base of the NPN transistor Q55 is connected to the base of the PNP transistor Q54. The emitter of transistor Q53 is connected to the collector of NPN transistor Q52 and the base of PNP transistor Q56; the base of NPN transistor Q52 is connected to the base of NPN transistor Q51 in the intermediate gain stage unit, and the emitter of NPN transistor Q52 is connected to one end of resistor R28; the emitter of NPN transistor Q55 is connected to one end of resistor R29, the other end of resistor R29 is connected to one end of resistor R30, and the other end of resistor R30 is connected to the emitter of PNP transistor Q56; the other end of resistor R28, the collector of PNP transistor Q54 and the collector of PNP transistor Q56 are all connected to the negative electrode of the power supply.

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