Circuit structure and working method of a micro gas sensor array

Abstract

The application relates to a circuit structure and working method of a micro gas sensor array, and belongs to the technical field of integrated circuits. The circuit structure comprises a multiplexer (MUX), a programmable gain amplifier (PGA), a low-pass filter (LPF), a driver (Drive), a successive approximation register analog-to-digital converter (SAR ADC), a digital control module (Digital Control) and an IIC interface for communication. In view of the demand for high precision and strong robustness of sensor signals, a common-source common-gate floating reverse dynamic amplifier is adopted in a SAR ADC noise shaping circuit, so that the insensitivity of the circuit to process, voltage and temperature (PVT) changes is significantly improved; the number of voltage-controlled delays in a time domain comparator (COMP) is increased, so that input reference noise is reduced; a hundred-nanosecond-level super-long delay module (DELAY) is integrated after asynchronous SAR logic, so that SAR ADC sampling errors are effectively reduced, and the measurement precision of the whole system is improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically a circuit structure and working method of a micro gas sensor array. Background Technology

[0002] In the context of continuous advancements in science and technology, gas sensors have found applications in numerous aspects of daily life. With the continuous progress and improvement of Micro-Electro-Mechanical Systems (MEMS) technology, gas sensors are exhibiting a trend towards miniaturization and integration. The bulky back-end circuits and devices of the past can no longer meet current practical needs, making the integration of back-end circuits a new requirement. Therefore, designing a high-performance application-specific integrated circuit (ASIC) centered around a micro gas sensor array is extremely necessary.

[0003] The output signal of microarray gas sensor arrays is often affected by various interferences such as noise. Therefore, high-performance application-specific integrated circuits (ASICs) play a crucial role in improving the performance of microsensor arrays. However, traditional ASICs for micro gas sensors may lack robustness in extreme environments, affecting the reliability and accuracy of the sensors. Therefore, high-precision and robust ASICs for micro gas sensor arrays remain a hot research topic and a significant challenge. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a circuit structure and operating method for a micro gas sensor array. It employs a common-source, common-gate floating inverted dynamic amplifier, significantly improving the circuit's insensitivity to variations in process, voltage, and temperature (PVT). By increasing the number of voltage-controlled delays in the time-domain comparator (COMP), input reference noise is reduced. A 100-nanosecond-level ultra-long delay module (DELAY) is integrated after the asynchronous SAR logic, effectively reducing SAR ADC sampling errors and thus improving the overall system's measurement accuracy. This invention meets the current requirements for interface control circuits of micro gas sensor arrays and has strong application value and practicality.

[0005] The technical solution adopted in this invention is:

[0006] A circuit structure for a micro gas sensor array includes a multiplexer (MUX), a programmable gain amplifier (PGA), a low-pass filter (LPF), a driver (Drive), a successive approximation analog-to-digital converter (SAR ADC), a digital control module (Digital Control), and an IIC interface.

[0007] The multiplexer MUX is used to select an electrical signal from the electrical signals output by multiple sensors and transmit it to the subsequent signal processing unit;

[0008] The programmable gain amplifier (PGA) uses resistive feedback to achieve programmable gain amplification of the signal.

[0009] The output of the programmable gain amplifier (PGA) is connected to a low-pass filter (LPF), which is used to filter the signal output by the PGA.

[0010] The output of the low-pass filter LPF is connected to the driver Drive, which drives the approximation analog-to-digital converter (SAR ADC). The output of the driver Drive and the output of the reference voltage are connected to the SAR ADC, which converts the analog signal output by the gas sensor into a digital signal.

[0011] The successive approximation analog-to-digital converter (SAR ADC) circuit includes a sample-and-hold circuit (S / H), capacitor arrays DAC+ and DAC-, a capacitor array switch DAC SWITCH, a time-domain comparator COMP, asynchronous SAR logic, a nanosecond-level ultra-long delay module DELAY, and a noise shaping module. The noise shaping module includes a capacitor array DAC, a capacitor array switch DAC Switch, dynamic weighted average (DWA) logic, a cascode floating inverting dynamic amplifier, switches CLK1 and CLK1N, and an integrating capacitor CF. The sample-and-hold circuit S / H is connected to the input terminals VIP, VIN, clock control signal CLKS, capacitor arrays DAC+, DAC-, and DAC, respectively. DAC+ and DAC- are connected to the capacitor array switch DAC SWITCH. DAC+, DAC-, A1, and A2 are connected to the input terminals of the time-domain comparator COMP. The output terminal of the time-domain comparator COMP is connected to the asynchronous SAR logic, and the output terminal of the asynchronous SAR logic is connected to the capacitor array switch DAC. The SWITCH, the nanosecond-level ultra-long delay module DELAY, and the DWA logic are connected. The output of the nanosecond-level ultra-long delay module DELAY is connected to the time-domain comparator COMP. The output of the DWA logic is connected to the capacitor array switch DAC Switch. The capacitor array DAC is connected to the switch CLK1 and the capacitor array switch DAC Switch respectively. The switch CLK1 is connected to the switches CLK1N, A1, A2, the upper and lower plates of the integrating capacitor CF, and the non-inverting input, inverting input, non-inverting output, and inverting output of the common-source cascode floating inverting amplifier respectively. The switch CLK1N is connected to the common-mode voltage VCM.

[0012] Furthermore, the circuit of the cascode floating inverted dynamic amplifier includes switch CLKR, switch CLK1, and capacitor C. X Capacitor C RES、 MOSFETs MP1~MP4 and MN1~MN4;

[0013] The sources of MOSFETs MP1 and MP2 are connected to switch CLK1. The drain of MOSFET MP1 is connected to the source of MOSFET MP3. The gate of MOSFET MP1 is connected to the gate of MOSFET MN3 and voltage V. + And connected to switch CLKR, the drain of MOSFET MP2 is connected to the source of MOSFET MP4, and the gate of MOSFET MP2 is connected to the gate of MOSFET MN4 and voltage V. - And connected to switch CLKR, the gate of MOSFET MP3 is connected to the common-mode point V. CM The gate of MOSFET MN1 is connected to the gate of MOSFET MP3, and the drain of MOSFET MP3 is connected to the drain of MOSFET MN1 and capacitor C. X The switch CLKR is connected, the source of MOSFET MN1 is connected to the drain of MOSFET MN3, the source of MOSFET MN3 is connected to the source of MOSFET MN4 and the switch CLK1, and the gate of MOSFET MP4 is connected to the common-mode point V. CM The gate of MOSFET MN2 is connected to the gate of MOSFET MP4, and the drain of MOSFET MP4 is connected to the drain of MOSFET MN2 and capacitor C, respectively. X The switch CLKR is connected, and the capacitor C is connected. X The other end is connected to ground, the source of MOSFET MN2 is connected to the drain of MOSFET MN4, and capacitor C... RES The upper-level board is connected to switches CLKR and CLK1 respectively, and capacitor C RES The lower-level boards are connected to switches CLKR and CLK1 respectively.

[0014] A method for operating a circuit structure for a micro gas sensor array, comprising:

[0015] The multiplexer MUX selects and transmits electrical signals from multiple sensors to the programmable gain amplifier PGA; the programmable gain amplifier PGA amplifies the signal with programmable gain by using a rail-to-rail input / output method; the output of the programmable gain amplifier PGA is connected to a low-pass filter LPF, which filters the output signal of the programmable gain amplifier PGA.

[0016] The filtered signal is transmitted to the driver Drive to provide driving force for the successive approximation analog-to-digital converter (SAR ADC), and the signal is input to the input terminal VIP of the successive approximation analog-to-digital converter (SAR ADC).

[0017] The successive approximation analog-to-digital converter (SAR ADC) circuit uses a pseudo-differential input method. Input terminal VIP is connected to the input gas sensor signal, and the other input terminal VIN is connected to the reference voltage VREF. The input signal is fed into the NS-SAR internal circuit via the CLKS clock signal, which controls the sample-and-hold circuit S / H. When CLKS is high, the input signal is sampled; when CLKS is low, the input signal is sampled and held. The gas sensor signal and the reference voltage signal are input to two of the input terminals of the time-domain comparator COMP via input terminals VIP and VIN, respectively. The time-domain comparator COMP outputs the result of the first comparison to the asynchronous SAR logic. The asynchronous SAR logic resets the time-domain comparator COMP by outputting a CLKC reset signal through the nanosecond-level ultra-long delay module DELAY. Simultaneously, the asynchronous SAR logic outputs a signal to control the capacitor array switch (DAC). SWITCH switches between capacitor array DAC+ and capacitor array DAC-. The voltages VDAC+ and VDAC- of capacitor array DAC+ and capacitor array DAC- begin to approach each other sequentially. Capacitor array DAC+ and capacitor array DAC- use a bridging capacitor method, with the upper plate of the bridging capacitor Ca connected to the high-level capacitor and the lower plate of the bridging capacitor Ca connected to the low-level capacitor.

[0018] After the signal CLKC flips 8 times, the time-domain comparator COMP completes the successive comparison of the input signal, and the asynchronous SAR logic outputs an 8-bit digital code value BOUT<7:0>; the residual voltage generated after the successive approximation of DAC+ and DAC- is used as the input signal and input to the noise shaping module; the 8-bit digital code value BOUT<7:0> is also sent to the dynamic weighted average DWA logic controlled by the clock signal CLK0.

[0019] When CLK0 flips to a high level, the dynamic weighted average DWA logic controls the capacitor array switch DAC switch in the noise shaping module according to the value of BOUT<7:0>, thereby realizing capacitor switching; the upper plate of the bridge capacitor Cb is connected to the high-order capacitor, while the lower plate is connected to the low-order capacitor.

[0020] When the clock signal CLK1 flips to a high level, the control switch connects the lower plates of the two integrating capacitors CF to the non-inverting and inverting input terminals of the dynamic amplifier, respectively, and the upper plates of the two integrating capacitors CF to the non-inverting and inverting output terminals of the dynamic amplifier, respectively, thereby starting noise shaping of the residual voltage generated after successive approximation.

[0021] The noise-shaped voltages VA1 and VA2 are output to the other two inputs of the time-domain comparator COMP, respectively. When the next clock signal CLKS flips to a low level, VA1 and VA2 will be superimposed on the original input signal and enter the next round of successive comparison process together.

[0022] When the clock signal CLK1N is high, the control switch connects the upper and lower plates of the two integrating capacitors CF to the common-mode voltage VCM, clearing the charge on the two integrating capacitors CF and resetting the integrating capacitors CF.

[0023] The signal processed by the successive approximation analog-to-digital converter (SAR ADC) is then passed through the DigitalControl module and communicated in real time with an external microcontroller via the IIC interface to display the output data of multiple sensors.

[0024] Furthermore, the operation of the cascode floating inverted dynamic amplifier is divided into two stages: reset and amplification. During the reset stage, switch CLKR is at a high level and switch CLK1 is at a low level. At this time, the energy storage capacitor C... RES It is pre-charged to the supply voltage; simultaneously, the amplifier is locked, with both its input and output reset to V. CM During the amplification stage, switch CLKR is low and switch CLK1 is high. The cascode floating inverted dynamic amplifier is controlled by C... RES Power supply. The multiplexer (MUX) plays a crucial role in the off-chip microsensor array, accurately selecting and transmitting electrical signals from multiple sensors to subsequent signal processing units. This design not only enables the multiplexing of signal processing units but also allows the system to process multiple signals simultaneously, ensuring real-time transmission of multiple sensor signals, greatly improving the efficiency of data acquisition and processing, and helping to reduce chip area.

[0025] The programmable gain amplifier (PGA) employs resistive feedback to achieve programmable gain amplification of the signal. The PGA design utilizes a rail-to-rail input / output configuration, ensuring virtually distortion-free transmission of the gas sensor array's output signal. The PGA accurately amplifies the weak analog signal output by the voltage divider method, bringing it within the quantization voltage range of the subsequent successive approximation analog-to-digital converter (SAR ADC). Simultaneously, the PGA supports an adjustable gain mode to minimize input offset voltage and further improve signal processing accuracy. A low-pass filter (LPF) is applied after the PGA to filter the output signal, enhancing the signal quality of the PGA output.

[0026] The driver is used to isolate the PGA and the SAR ADC, which can effectively reduce the impact of the SAR ADC sampling switch switching state on the PGA load, and has a sufficiently strong driving capability for the SAR ADC to ensure the stability and reliability of signal transmission.

[0027] The IIC interface is used for real-time serial communication with an external microcontroller, thereby enabling real-time display of the output data from multiple sensors.

[0028] The SAR ADC converts the analog signal output from the gas sensor into a digital signal. The successive approximation analog-to-digital converter (SAR ADC) employs an optimized NS-SAR architecture. This SAR ADC module uses a pseudo-differential circuit structure, which has higher linearity than single-ended input and lower power consumption than fully differential input. It uses a common-source cascode floating inverted dynamic amplifier, significantly improving the circuit's insensitivity to process, voltage, and temperature (PVT) variations. By increasing the number of voltage-controlled delays in the time-domain comparator (COMP), input reference noise is reduced. A nanosecond-level ultra-long delay module (DELAY) is integrated after the asynchronous SAR logic, effectively reducing SAR ADC sampling errors and improving the overall system measurement accuracy. The beneficial effects of this invention are: the circuit structure includes a multiplexer (MUX), a programmable gain amplifier (PGA), a low-pass filter (LPF), a driver, a successive approximation analog-to-digital converter (SAR ADC), a digital control module, and an IIC interface for communication. Specifically, it has the following advantages:

[0029] (1) The use of a common-source cascode floating inverting dynamic amplifier significantly improves the circuit's insensitivity to process, voltage, and temperature (PVT) variations. Compared to traditional dynamic amplifiers, this common-source cascode floating inverting dynamic amplifier reduces power consumption through automatic shutdown. Simultaneously, during amplification, the operating region of the MOSFET also extends towards higher energy efficiency. Therefore, this common-source cascode floating inverting dynamic amplifier, while maintaining its insensitivity to PVT variations, reduces the design of common-mode feedback circuits, simplifies the system structure, and improves amplifier efficiency, achieving superior performance across the entire dynamic range.

[0030] (2) The optimized NS-SAR reduces input reference noise by increasing the number of voltage-controlled delays in the time-domain comparator (COMP). The output of the VCDL in the time-domain comparator can achieve rail-to-rail output swing without static power consumption, allowing the power supply voltage to be reduced to the minimum threshold required for digital logic operation, thus reducing system power consumption. The phase detector (PD) circuit in the time-domain comparator consists of D flip-flops and NAND gates. Based on the edge detection method of D flip-flops, there is no specific requirement for the waveform frequency of the input signal, and the sign of the phase detector gain remains unchanged, ensuring the stable operation of the system. Even if the phase difference exceeds 180°, the system can still detect the phase normally.

[0031] (3) By integrating a nanosecond-level ultra-long delay module (DELAY) after the asynchronous SAR logic, the SAR ADC sampling error is effectively reduced, thereby improving the measurement accuracy of the entire system. The effective number of bits (ENOB) of the SAR ADC of the overall system is 13.39 bits, and the SNDR is 82.3 dB.

[0032] (4) The PGA design adopts a rail-to-rail input / output method to ensure that the output signal of the gas sensor array is almost undistorted during transmission. The PGA can accurately amplify the weak analog signal output by the voltage divider method, bringing it into the quantization voltage range of the subsequent SARADC; at the same time, the PGA also supports an adjustable gain mode to minimize the input offset voltage and further improve the accuracy of signal processing. An LPF is used after the PGA to filter the output signal, improving the signal quality of the PGA output.

[0033] (5) The driver isolates the PGA and SAR ADC, which can effectively reduce the impact of the ADC sampling switch switching state on the PGA load, and can have a strong enough driving capability for the SAR ADC to ensure the stability and reliability of signal transmission. Attached Figure Description

[0034] Figure 1 This is a circuit diagram of a gas sensor.

[0035] Figure 2 This is an optimized NS-SAR block diagram.

[0036] Figure 3 This is an optimized NS-SAR ADC timing diagram.

[0037] Figure 4 This is a diagram of a time-domain comparator.

[0038] Figure 5 This is a voltage-controlled delay circuit diagram.

[0039] Figure 6 This is the timing diagram for the phase detector.

[0040] Figure 7 This is the schematic diagram of a common-source cascode floating inverted dynamic amplifier.

[0041] Figure 8 It is a power spectral density diagram. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail with reference to the accompanying drawings.

[0043] Figure 1The circuit structure of a micro gas sensor array is shown, which includes a multiplexer (MUX), a programmable gain amplifier (PGA), a low-pass filter (LPF), a driver, a successive approximation analog-to-digital converter (SAR ADC), a digital control module, and an IIC interface for communication.

[0044] Figure 2 The optimized NS-SAR block diagram includes a sample-and-hold circuit (S / H), capacitor arrays DAC+ and DAC-, a capacitor array switch DAC SWITCH, a time-domain comparator (COMP), SAR logic, a nanosecond-level ultra-long delay module (DELAY), and a noise shaping module. The noise shaping module includes a capacitor array DAC, a capacitor array switch DAC, dynamic weighted average (DWA) logic, a cascode floating inverting dynamic amplifier, switch CLK1, switch CLK1N, and integrating capacitor CF. The sample-and-hold circuit S / H is connected to the input terminals VIP and VIN, the clock control signal CLKS, the capacitor arrays DAC+ and DAC-, and the capacitor array DAC, respectively. The capacitor arrays DAC+ and DAC- are connected to the capacitor array switch DAC SWITCH. The capacitor arrays DAC+ and DAC-, A1, and A2 are connected to the input terminals of COMP. The output terminal of COMP is connected to the SAR logic. The output of the SAR logic is connected to the capacitor array switch DAC SWITCH, the nanosecond-level ultra-long delay module DELAY, and the DWA logic, respectively. The output of the nanosecond-level ultra-long delay module DELAY is connected to the time-domain comparator COMP. The output of the DWA logic is connected to the capacitor array switch DACSwitch. The capacitor array DAC is connected to the switch CLK1 and the capacitor array switch DAC, respectively. The switch is connected to the non-inverting input, inverting input, non-inverting output, and inverting output terminals of the common-source cascode floating inverting amplifier, as well as the switches CLK1N, A1, A2, and the upper and lower plates of the integrating capacitor CF. The switch CLK1N is connected to the common-mode voltage VCM.

[0045] like Figure 3The figure shows the timing diagram of the optimized NS-SAR ADC. The optimized NS-SAR uses a pseudo-differential input method. The input terminal VIP is connected to the input gas sensor signal, and the other input terminal VIN is connected to the reference voltage VREF. The input signal enters the NS-SAR through a sample-and-hold circuit (S / H) controlled by the CLKS clock signal. When CLKS is high, the input signal is sampled; when CLKS is low, the input signal is sampled and held. VIP and VIN are input to two of the input terminals of COMP. COMP outputs the result of the first comparison to the asynchronous SAR logic. The asynchronous SAR logic resets COMP by outputting the CLKC reset signal via DELAY. At the same time, the SAR logic output signal controls the DAC SWITCH to switch between DAC+ and DAC-. The voltages of DAC+ and DAC- (VDAC+ and VDAC-) begin to approximate each other sequentially. DAC+ and DAC- use a bridging capacitor method, with the upper plate of the bridging capacitor Ca connected to the high-order capacitor and the lower plate of the bridging capacitor Ca connected to the low-order capacitor. After the CLKC signal flips eight times, COMP completes the successive comparison of the input signal, and the SAR logic outputs an 8-bit digital code value BOUT<7:0>. The residual voltage generated after the successive approximation of DAC+ and DAC- is used as the input signal and input to the noise shaping module. This 8-bit digital code value BOUT<7:0> is simultaneously fed into the Dynamic Weighted Average (DWA) logic controlled by the clock signal CLK0. When CLK0 is high, the DWA logic controls the DAC Switch in the noise shaping module according to the value of BOUT<7:0>, thereby realizing capacitor switching. During this process, the upper plate of the bridging capacitor Cb is connected to the high-order capacitor, while the lower plate is connected to the low-order capacitor. At the same time, when the clock signal CLK1 flips to high, the control switch connects the lower plates of the two integrating capacitors CF to the non-inverting and inverting input terminals of the dynamic amplifier, respectively, and the upper plates of the two integrating capacitors CF to the non-inverting and inverting output terminals of the dynamic amplifier, respectively, thus starting the noise shaping process on the residual voltage generated after the successive approximation. The noise-shaped voltages (VA1 and VA2) are output to the other two input terminals of COMP. When the next clock signal CLKS flips to a low level, VA1 and VA2 are superimposed on the original input signals and enter the next round of successive comparison. Furthermore, when the clock signal CLK1N is high, the control switch connects the upper and lower plates of the two integrating capacitors CF to the common-mode voltage (VCM), clearing the charge on the two integrating capacitors CF, thereby resetting the integrating capacitors CF.

[0046] like Figure 4 The diagram shown illustrates the structure of a time-domain comparator. This comparator consists of two differential voltage-controlled delay units (VCDLs) and a binary phase detector (PD). Figure 5As shown, the voltage-controlled delay circuit (VCDL) consists of PMOS and NMOS transistors and an inverter. In the time-domain comparator, the VCDL acts as a preamplifier, while the PD acts as a latch stage. The output of the VCDL can achieve rail-to-rail oscillation without static power consumption, allowing the supply voltage to be reduced to the minimum threshold required for digital logic operations, thus reducing system power consumption. Figure 6 The diagram shown is the timing diagram of the phase detector. The phase detector (PD) circuit consists of D flip-flops and NAND gates. When the output signals of both D flip-flops are high, the output signal of the NAND gate is low, thus enabling the D flip-flops to reset, pulling VOUTP and VOUTN low simultaneously. Based on the edge detection method of D flip-flops, there are no specific requirements for the waveform frequency of the input signal, and the sign of the phase detector gain remains unchanged, ensuring stable operation of the system. Even if the phase difference exceeds 180°, the system can still detect the phase normally.

[0047] like Figure 7 The diagram shown is a schematic of a common-source cascode floating inverting dynamic amplifier, including switches CLKR and CLK1, MOSFETs MP1~MP4 and MN1~MN4, and capacitor C. X and C RES The sources of MOSFETs MP1 and MP2 are connected to switch CLK1. The drain of MOSFET MP1 is connected to the source of MOSFET MP3. The gate of MOSFET MP1 is connected to the gate of MN3 and voltage V. + And connected to switch CLKR, the drain of MOSFET MP2 is connected to the source of MOSFET MP4, and the gate of MOSFET MP2 is connected to the gate of MOSFET MN4 and voltage V. - And connected to switch CLKR, the gate of MOSFET MP3 is connected to the common-mode point V. CM The gate of MOSFET MN1 is connected to the gate of MOSFET MP3, and the drain of MOSFET MP3 is connected to the drain of MOSFET MN1 and capacitor C. X The switch CLKR is connected, the source of MN1 is connected to the drain of MOSFET MN3, the source of MOSFET MN3 is connected to the source of MOSFET MN4 and switch CLK1, and the gate of MOSFET MP4 is connected to the common-mode point V. CM The gate of MOSFET MN2 is connected to the gate of MOSFET MP4, and the drain of MOSFET MP4 is connected to the drain of MOSFET MN2 and capacitor C, respectively. X The switch CLKR is connected, the source of MOSFET MN2 is connected to the drain of MOSFET MN4, and capacitor C... RES The upper-level board is connected to switches CLKR and CLK1 respectively, and capacitor C RES The lower-level board is connected to switches CLKR and CLK1 respectively, and capacitor C XThe other end is connected to ground. Using a common-source, cascode floating inverting dynamic amplifier not only effectively reduces the impact of PVT variations on performance, but also allows the output voltage to be naturally stabilized at the common-mode point (V) through a floating power supply mode. CM The operation is divided into two stages: reset and amplification. During the reset stage, CLKR is high and CLK1 is low. At this time, the energy storage capacitor C... RES It is pre-charged to the supply voltage; simultaneously, the amplifier is locked, with both its input and output reset to V. CM This ensures that the cascode floating inverting dynamic amplifier has a stable initial state before starting operation. During the amplification phase, CLKR is low and CLK1 is high. The cascode floating inverting dynamic amplifier is controlled by C... RES Power Supply. Compared to traditional dynamic amplifiers, this cascode floating inverting dynamic amplifier reduces power consumption through automatic shutdown. Simultaneously, during amplification, the operating region of the MOSFETs is pushed towards higher energy efficiency. Therefore, this cascode floating inverting dynamic amplifier, while maintaining its insensitivity to PVT changes, reduces the design of common-mode feedback circuitry, simplifies the system structure, and improves amplifier efficiency, achieving superior full-dynamic performance.

[0048] like Figure 8 The image shows the power spectral density. This SAR ADC module employs a cascode floating inverted dynamic amplifier, significantly improving the circuit's insensitivity to variations in process technology, voltage, and temperature (PVT). By increasing the number of voltage-controlled delays in the time-domain comparator (COMP), input reference noise is reduced. A 100-nanosecond-level ultra-long delay module (DELAY) is integrated after the asynchronous SAR logic, effectively reducing SAR ADC sampling errors and thus improving the overall system's measurement accuracy. The overall system's SAR ADC has an effective ENOB of 13.39 bits and an SNDR of 82.3 dB.

Claims

1. A circuit structure of a micro gas sensor array, characterized by: The circuit structure comprises a multiplexer MUX, a programmable gain amplifier PGA, a low-pass filter LPF, a driver Driver, a successive approximation analog-to-digital converter SAR ADC, a digital control module Digital Control and an IIC interface; The multiplexer MUX is used for selecting an electrical signal from electrical signals output by a plurality of sensors and transmitting the electrical signal to a subsequent signal processing unit; The programmable gain amplifier PGA adopts a resistance feedback mode to realize programmable gain amplification of the signal; An output end of the programmable gain amplifier PGA is connected to the low-pass filter LPF, and the low-pass filter LPF is used for filtering the signal output by the programmable gain amplifier PGA; An output end of the low-pass filter LPF is connected to the driver Driver, and the driver Driver is used for driving the successive approximation analog-to-digital converter SAR ADC; an output end of the driver Driver and an output end of a reference voltage are connected to the successive approximation analog-to-digital converter SAR ADC, and the successive approximation analog-to-digital converter SAR ADC is used for converting an analog signal output by the gas sensor into a digital signal; The circuit of the successive approximation type analog-to-digital converter SAR ADC comprises a sample-and-hold circuit S / H, a capacitor array DAC+, a capacitor array DAC-, a capacitor array switch DAC SWITCH, a time-domain comparator COMP, asynchronous SAR logic, a nanosecond-level super-long delay module DELAY, and a noise shaping module; the noise shaping module comprises a capacitor array DAC, a capacitor array switch DAC Switch, dynamic weighted average DWA logic, a common-source common-gate floating reverse dynamic amplifier, a switch CLK1, a switch CLK1N, and an integration capacitor CF; the sample-and-hold circuit S / H is connected with an input end VIP, an input VIN, a clock control signal CLKS, the capacitor array DAC+, the capacitor array DAC-, and the capacitor array DAC; the capacitor array DAC+ is connected with the first capacitor array switch DAC SWITCH; the capacitor array DAC- is connected with the second capacitor array switch DAC SWITCH; the capacitor array DAC+, the capacitor array DAC-, A1, and A2 are connected with the input end of the time-domain comparator COMP; the output end of the time-domain comparator COMP is connected with the asynchronous SAR logic; the output end of the asynchronous SAR logic has four branches; the first branch is connected with the first capacitor array switch DAC SWITCH; the second branch is connected with the second capacitor array switch DAC SWITCH; the third branch is connected with the input end of the nanosecond-level super-long delay module DELAY; the output end of the nanosecond-level super-long delay module DELAY is connected with the time-domain comparator COMP; the fourth branch is connected with the input end of the first DWA logic and the input end of the second DWA logic; the output end of the first DWA logic is connected with the third capacitor array switch DAC Switch; the output end of the second DWA logic is connected with the fourth capacitor array switch DAC Switch; the capacitor array DAC is connected with the third capacitor array switch DAC Switch and the fourth capacitor array switch DAC Switch; A1 is connected to one end of the first switch CLK1, the other end of the first switch CLK1 is connected to a first common connection point, the first common connection point is divided into two branches, one branch is connected to the first end of the common-source common-gate floating reverse dynamic amplifier, and the other branch is connected to a second common connection point; the second common connection point is divided into two branches, one branch is connected to the first common-mode point V CM after passing through the first switch CLK1N, and the other branch is connected to one end of the first capacitor CF, the other end of the first capacitor CF is connected to a third common connection point; the third common connection point is divided into two branches, one branch is connected to the second common-mode point V CM after passing through the second switch CLK1N, and the other branch is connected to the fourth common connection point through the third switch CLK1; the fourth common connection point is divided into two branches, one branch is connected to the second end of the common-source common-gate floating reverse dynamic amplifier, and the other branch is connected to the capacitor array DAC through the fourth switch CLK1; A2 connects one end of the fifth switch CLK1, the other end of the fifth switch CLK1 is connected to the fifth common connection point, the fifth common connection point is divided into two branches, one branch is connected to the third end of the common-source common-gate floating reverse dynamic amplifier, the other branch is connected to the sixth common connection point; the sixth common connection point is divided into two branches, one branch is connected to the third common mode point V CM after passing through the third switch CLK1N, the other branch is connected to one end of the second capacitor CF, the other end of the second capacitor CF is connected to the seventh common connection point; the seventh common connection point is divided into two branches, one branch is connected to the fourth common mode point V CM after passing through the fourth switch CLK1N, the other branch is connected to the eighth common connection point through the seventh switch CLK1; the eighth common connection point is divided into two branches, one branch is connected to the fourth end of the common-source common-gate floating reverse dynamic amplifier, the other branch is connected to the capacitor array DAC through the eighth switch CLK1.

2. A circuit structure for a micro-gas sensor array according to claim 1, characterized in that: The circuit of the common-source common-gate floating reverse dynamic amplifier comprises a switch CLKR, a switch CLK1, a capacitor C X , a capacitor C RES、 , MOS tubes MP1~MP4 and MN1~MN4; The source of the MOS transistor MP1 and the source of the MOS transistor MP2 are connected, the drain of the MOS transistor MP1 and the source of the MOS transistor MP3 are connected, the gate of the MOS transistor MP1 and the gate of the MOS transistor MN3 are connected, a certain point of the connecting line and the first common node are connected, one branch of the first common node and the voltage V + are connected, and the other branch of the first common node is connected to the fifth common mode point V CM after passing through the first reverse switch CLKR. The drain of the MOS transistor MP2 is connected to the source of the MOS transistor MP4, the gate of the MOS transistor MP2 is connected to the gate of the MOS transistor MN4, a connection line is connected to the second common node, one branch of the second common node is connected to the voltage V - ; and the other branch of the second common node is connected to the sixth common mode point V CM after passing through the second reverse switch CLKR. The gate of the MOS transistor MP3 is connected to the gate of the MOS transistor MN1, and a point on the connecting line is connected to the seventh common mode point V CM ; the drain of the MOS transistor MP3 is connected to the drain of the MOS transistor MN1, and a point on the connecting line is connected to the third common node, one branch of the third common node is connected to one end of the first capacitor C X , and the other end of the first capacitor C X is grounded; the second branch of the third common node is connected to the fourth common node through the third reverse switch CLKR, and the fourth common node is connected to the eighth common mode point; The source of the MOS transistor MN1 is connected with the drain of the MOS transistor MN3, and the source of the MOS transistor MN3 is connected with the source of the MOS transistor MN4; The gate of the MOS transistor MP4 is connected with the gate of the MOS transistor MN2, and a point on the connecting line is connected to the ninth common mode point V CM ; the drain of the MOS transistor MP4 is connected with the drain of the MOS transistor MN2, and a point on the connecting line is connected to the fifth common node, one branch of the fifth common node is connected to one end of the second capacitor C X , and the other end of the second capacitor C X is connected to the ground; the second branch of the fifth common node is also connected to the fourth common node after passing through the fourth reverse switch CLKR. The voltage VDD is connected to one end of the capacitor C through the fifth reverse switch CLKR and the seventh common node in sequence RES , and the other end of the capacitor C RES is grounded through the sixth common node and the sixth reverse switch CLKR in sequence; the seventh common node is connected to one end of the ninth switch CLK1, and the other end is connected to the ninth common node, which is arranged on the connection line of the source of the MOS transistor MP1 and the source of the MOS transistor MP2; the sixth common node is connected to one end of the tenth switch CLK1, and the other end is connected to the eighth common node, which is arranged on the connection line of the source of the MOS transistor MN3 and the source of the MOS transistor MN4.

3. The working method of the circuit structure of the micro gas sensor array according to claim 1, characterized in that: The multiplexer MUX selects and transmits the electrical signals output by the plurality of sensors to the programmable gain amplifier PGA; The programmable gain amplifier PGA with the rail-to-rail input and output amplifies the signals in a programmable gain manner; The output end of the programmable gain amplifier PGA is connected with the low-pass filter LPF, and the low-pass filter LPF filters the output signal of the programmable gain amplifier PGA; The filtered signal is transmitted to the driver Driver to provide driving force for the successive approximation type analog-to-digital converter SAR ADC, and the signal is input to the input end VIP of the successive approximation type analog-to-digital converter SAR ADC; The successive approximation type analog-digital converter (SAR ADC) circuit uses a pseudo-differential input mode, an input end VIP is connected to an input gas sensor signal, and another input end VIN is connected to a reference voltage VREF; an input signal is controlled by a CLKS clock signal to enter a NS-SAR inside a sample and hold circuit S / H, when the CLKS is high, the input signal is sampled, and when the CLKS is low, the input signal is sampled and held; the gas sensor signal and the reference voltage signal are input to two input ends of a time domain comparator COMP through the input end VIP and the input end VIN respectively, and the time domain comparator COMP outputs a first comparison result to an asynchronous SAR logic; the asynchronous SAR logic outputs a CLKC reset signal through a hundred nanosecond level super long delay module DELAY to reset the time domain comparator COMP, and at the same time, the asynchronous SAR logic output signal controls a capacitor array switch DAC SWITCH to switch the capacitor array DAC+ and the capacitor array DAC-, and the voltages VDAC+ and VDAC- of the capacitor array DAC+ and the capacitor array DAC- start to be sequentially approximated, the capacitor array DAC+ and the capacitor array DAC- adopt a bridge capacitor mode, and an upper plate of a bridge capacitor Ca is connected to a high-order capacitor, and a lower plate of the bridge capacitor Ca is connected to a low-order capacitor; When the signal CLKC flips 8 times, the time domain comparator COMP completes the successive comparison of the input signal, and the asynchronous SAR logic outputs an 8-bit digital code value BOUT<7:0>; the residual voltage generated after the DAC+ and the DAC- are sequentially approximated is taken as an input signal and input to a noise shaping module; and the 8-bit digital code value BOUT<7:0> is sent into a dynamic weighted average (DWA) logic controlled by a clock signal CLK0; When the CLK0 flips to high, the dynamic weighted average (DWA) logic controls the capacitor array switch DAC SWITCH in the noise shaping module according to the value of BOUT<7:0> to realize capacitor switching; an upper plate of a bridge capacitor Cb is connected to a high-order capacitor, and a lower plate of the bridge capacitor Cb is connected to a low-order capacitor; When the clock signal CLK1 flips to high, the control switch connects the lower plates of the two integration capacitors CF to the non-inverting input end and the inverting input end of the dynamic amplifier respectively, and the upper plates of the two integration capacitors CF are connected to the non-inverting output end and the inverting output end of the dynamic amplifier respectively, so as to start the noise shaping processing of the residual voltage generated after the successive approximation is completed; The voltages VA1 and VA2 after noise shaping are output to the other two input ends of the time domain comparator COMP; when the next clock signal CLKS flips to low, VA1 and VA2 will be superimposed with the original input signal and enter the next round of successive comparison process together; When the clock signal CLK1N is high, the control switch connects the upper and lower plates of the two integration capacitors CF to the common mode voltage VCM, and the charges on the two integration capacitors CF are cleared, so as to reset the integration capacitors CF. The signal processed by the successive approximation analog-digital converter (SAR ADC) is communicated with an external single-chip microcomputer in real time through IIC interface and digital control module (Digital Control) after the signal is processed by the successive approximation analog-digital converter (SAR ADC), and the output data of the multiple sensors are displayed in real time.

4. A method of operating a circuit structure of a micro-gas sensor array according to claim 3, characterized in that: The working process of the common-source common-gate floating reverse dynamic amplifier is divided into two stages of reset and amplification: in the reset stage, the switch CLKR is high level and the switch CLK1 is low level, at this time the energy storage capacitor C RES is pre-charged to the power supply voltage; at the same time, the amplifier is in a locked state, and the input and output are reset to V CM ; in the amplification stage, the switch CLKR is low level and the switch CLK1 is high level, and the common-source common-gate floating reverse dynamic amplifier is powered by C RES .

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