Image sensing device

Abstract

An image sensing apparatus includes: a counter configured to generate first count data by counting pulses generated by detection of photocharges; a shift register configured to store second count data corresponding to a high digit of the first count data; and an adder configured to sum the second count data and an overflow value indicating whether the first count data overflows.

Description

Technical Field

[0001] Techniques and embodiments disclosed in this patent application generally relate to an image sensing device capable of obtaining an image of a scene by detecting light. Background Art

[0002] Image sensing devices are devices that capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the development of the automotive, medical, computer and communication industries, the demand for high-performance image sensing devices is increasing in various devices such as smartphones, digital cameras, game consoles, IOT (Internet of Things), robots, security cameras and medical micro cameras.

[0003] As a unit circuit for detecting light in an image sensing device, a pixel may be implemented in various ways depending on the purpose or use of the image sensing device, and miniaturization of pixels has also emerged as an important issue for image sensing devices and the quality of images generated by the image sensing devices. In order to improve image quality, it is important to increase the performance of pixels, but additional space may be required to increase such pixel performance. Since the performance of a pixel and the size of the pixel are generally in a trade-off relationship, the importance of system design that can increase the performance of a pixel while minimizing the size of the pixel is increasing. Summary of the invention

[0004] Various embodiments of the present disclosure are directed to an image sensing device that can maximize pixel performance while minimizing pixel size.

[0005] According to an embodiment of the present disclosure, an image sensing device may include: a counter configured to generate first counting data by counting pulses generated by detection of photocharges; a shift register configured to store second counting data corresponding to high digits of the first counting data; and an adder configured to sum the second counting data with an overflow value indicating whether the first counting data overflows.

[0006] According to another embodiment of the present disclosure, an image sensing device may include: a counter configured to generate first counting data by counting pulses corresponding to photocharges; and an adder configured to generate an overflow value indicating whether the first counting data overflows, and configured to add the overflow value to second counting data corresponding to a high digit of the first counting data.

[0007] According to another embodiment of the present disclosure, an image sensing device may include: a counter configured to generate first counting data by counting pulses corresponding to photocharges; and a shift register configured to store second counting data corresponding to high digits of the first counting data, configured to receive the first counting data after outputting the second counting data, and configured to output the received first counting data, wherein the second counting data refers to data added to an overflow value indicating whether the first counting data overflowed.

[0008] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and descriptive and are intended to provide further description of embodiments of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features and advantageous aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0010] Figure 1 is a block diagram illustrating an imaging device according to some embodiments of the present disclosure.

[0011] Figure 2 Some embodiments of the present disclosure are shown Figure 1 Circuit diagram of the pixel shown.

[0012] Figure 3 is a conceptual diagram illustrating the operation of a pixel at various time periods according to some embodiments of the present disclosure.

[0013] Figure 4 It is a diagram showing some embodiments of the present disclosure. Figure 3 A timing diagram of the operation of a pixel during a reset period and an exposure period is shown.

[0014] Figure 5 It is a diagram showing some embodiments of the present disclosure. Figure 3 A timing diagram showing the operation of a pixel during the readout period is shown.

[0015] Figure 6 Some embodiments of the present disclosure are shown Figure 2 The circuit diagram of the shift register is shown in FIG.

[0016] Figure 7 is a circuit diagram showing a counter flip-flop according to some embodiments of the present disclosure.

[0017] Figure 8 is a circuit diagram showing a register flip-flop according to some embodiments of the present disclosure.

[0018] Fig. 9is a circuit diagram showing another register flip-flop according to some embodiments of the present disclosure.

[0019] Fig.10 It is a diagram showing some embodiments of the present disclosure including Figure 2 A conceptual diagram of a downsampling method for an image sensing device with pixels.

[0020] Fig.11 is a circuit diagram illustrating pixel clustering that may perform a contrast-based downsampling method according to some embodiments of the present disclosure.

[0021] Fig.12 Some embodiments of the present disclosure are shown Fig.11 A flowchart of the operation of pixel clustering is shown. DETAILED DESCRIPTION

[0022] The present disclosure provides embodiments and examples of image sensing devices capable of obtaining an image of a scene by detecting light, which can be used in a configuration that substantially solves one or more technical or engineering problems and mitigates limitations or disadvantages encountered in some other image sensing devices. Some embodiments of the present disclosure relate to an image sensing device that can maximize pixel performance while minimizing pixel size. The present disclosure provides various embodiments of image sensing devices that can significantly reduce the pixel size of generated pixel data by counting the number of pulses corresponding to photocharges. The present disclosure provides various embodiments of image sensing devices that can reduce the amount of power to be consumed in a pixel array by performing contrast-based downsampling on pixel clusters that include pixels.

[0023] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the accompanying drawings to represent the same or similar parts. Although the embodiments are susceptible to various modifications and alternative forms, specific embodiments thereof are illustrated as examples in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0024] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or substitutions of the embodiments. The embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0025] Figure 1 is a block diagram showing an imaging device 10 according to some embodiments of the present disclosure.

[0026] Reference Figure 1, the imaging device 10 may refer to a device such as a digital still camera for capturing still images or a digital video camera for capturing moving images. For example, the imaging device 10 may be implemented as a digital single-lens reflex (DSLR) camera, a mirrorless camera, or a smart phone, among other similar devices. The imaging device 10 may include a device having both a lens and an image pickup element, so that the device can capture (or photograph) a target object, and thus can create an image of the target object.

[0027] In some embodiments, the imaging device may include not only the image sensing device 10 but also an image signal processor that performs image processing (eg, demosaicing, noise reduction, etc.) on image data generated by the image sensing device 10 .

[0028] The image sensing device 10 may be or may include a complementary metal oxide semiconductor image sensor (CIS) for converting an optical signal into an electrical signal. The image sensing device 10 may include a pixel array 110 , a pixel controller 120 , a readout block 130 , and a timing generator 140 .

[0029] The pixel array 110 may include a plurality of pixels (PX) continuously arranged in a two-dimensional (2D) matrix structure (e.g., continuously arranged in a column direction and / or a row direction). Each of the plurality of pixels (PX) may detect incident light and may generate pixel data under the control of the pixel controller 120. The pixel data may refer to data indicating the amount of photocharges generated in response to the intensity of the incident light. The structure of each pixel (PX) and the operation of generating pixel data will be described later. Figure 2 to describe.

[0030] Pixels (PX) belonging to one row may receive the same pixel control signal from the pixel controller 120. Pixels (PX) belonging to one column may be connected to one column line, and may output pixel data to the readout block 130. In some other implementations, pixels (PX) belonging to one column may be independently connected to different column lines, and may output pixel data to the readout block 130.

[0031] The pixel controller 120 may drive the pixels (PX) of the pixel array 110 in response to the timing signal output from the timing generator 140. For example, the pixel controller 120 may generate a control signal capable of selecting and controlling the pixels (PX) included in at least one row line among a plurality of row lines of the pixel array 110.

[0032] The readout block 130 may detect pixel data output from the pixel array 110 under the control of the timing generator 140, and may output the detected pixel data as image data. Specifically, the readout block 130 may include a sense amplifier configured to amplify and output a voltage level of each bit of the pixel data, a memory configured to temporarily store the pixel data output from the sense amplifier, and / or an output interface configured to output the resulting pixel data to an external device (e.g., an image signal processor) under the control of the timing generator 140.

[0033] The timing generator 140 may generate a timing signal to control the operation of the pixel controller 120 and the readout block 130. In some embodiments, the timing generator 140 may generate a timing signal in response to a request from an image signal processor. In some embodiments, the timing generator 140 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, etc.

[0034] Figure 2 Some embodiments of the present disclosure are shown Figure 1 Circuit diagram of a pixel (PX) shown.

[0035] Reference Figure 2 , the pixel (PX) can correspond to Figure 1 An example of individual pixels included in the pixel array 110 is shown.

[0036] The pixel (PX) may include a light sensor 210 , a counter 220 , an adder 230 , a shift register 240 , and a buffer 250 .

[0037] The light sensor 210 may be enabled or disabled in response to an enable control signal (EN). The enabled light sensor 210 may detect incident light to generate photo charges, and may generate a charge pulse signal (CP) serving as a pulse signal corresponding to the number of generated photo charges.

[0038] In some embodiments, the light sensor 210 may be implemented as a photomultiplier tube. For example, the light sensor 210 may include a photoelectric conversion element 212 , a capacitor 214 , a comparator 216 , a delay circuit 218 , a reset transistor (RX), and an enable switch 219 .

[0039] The photoelectric conversion element 212 may generate photocharges corresponding to the intensity of incident light. The photoelectric conversion element 212 may be implemented as a photodiode or a single photon avalanche diode (SPAD), but other implementations are also possible. The photoelectric conversion element 212 may be connected between a ground terminal and a floating diffusion node (FD).

[0040] The capacitor 214 may provide a predetermined capacitance to the floating diffusion node (FD) so that photocharges generated by the photoelectric conversion element 212 may be accumulated in the floating diffusion node FD. The capacitor 214 may be connected between the floating diffusion node (FD) and a ground terminal.

[0041] The comparator 216 may include an inverting input terminal connected to the floating diffusion node (FD) and a non-inverting input terminal connected to the enable switch 219, and may output a voltage according to a comparison result of a voltage input to the inverting input terminal and a voltage input to the non-inverting input terminal. When the voltage input to the inverting input terminal is higher than the voltage input to the non-inverting input terminal, the voltage output from the comparator 216 may have a logic low level. On the contrary, when the voltage input to the inverting input terminal is lower than the voltage input to the non-inverting input terminal, the voltage output from the comparator 216 may have a logic high level.

[0042] The delay circuit 218 may delay the voltage output from the comparator 216 and may output the delayed voltage as the charge pulse signal CP. The delay circuit 218 may be implemented as an inverter chain including a plurality of inverters. The pulse width of the charge pulse signal CP may be determined according to the number of inverters.

[0043] The reset transistor (RX) may be connected between the reset voltage (Vrst) and the floating diffusion node (FD), and may receive the charge pulse signal (CP) through its gate terminal. The reset transistor (RX) may be turned on according to the voltage level of the charge pulse signal (CP) to reset the floating diffusion node (FD) to the reset voltage (Vrst).

[0044] One terminal of the enable switch 219 may be connected to the non-inverting input terminal of the comparator 216, and the other terminal of the enable switch 219 may be connected to the threshold voltage (Vth) terminal or the disable voltage (Vd) terminal. The other terminal of the enable switch 219 may be selectively connected to the threshold voltage (Vth) terminal or the disable voltage (Vd) terminal in response to the enable control signal (EN). When the enable control signal (EN) is at a logic high level, the enable switch 219 may connect its other terminal to the threshold voltage (Vth) terminal. When the enable control signal (EN) is at a logic low level, the enable switch 219 may connect its other terminal to the disable voltage (Vd) terminal.

[0045] Here, the threshold voltage (Vth) may be determined to be lower than the voltage of the floating diffusion node (FD) where no photocharge is accumulated, and may be determined to be higher than the voltage of the floating diffusion node (FD) where photocharge is accumulated. That is, when the other terminal of the enable switch 219 is connected to the threshold voltage (Vth) terminal, the light sensor 210 is enabled so that a charge pulse signal (CP) having a pulse shape may be generated according to whether photocharge is accumulated in the floating diffusion node (FD).

[0046] The deactivation voltage (Vd) may be determined to be lower than the voltage of the floating diffusion node (FD) where the photo charges are accumulated. That is, when the other terminal of the enable switch 219 is connected to the deactivation voltage (Vd) terminal, the light sensor 210 is deactivated so that a charge pulse signal (CP) having a logic low level may be generated regardless of whether photo charges are accumulated in the floating diffusion node (FD).

[0047] To describe the operation when the light sensor 210 is enabled, when the photoelectric conversion element 212 does not generate photocharges, photocharges may not be accumulated in the floating diffusion node (FD). At this time, since the voltage of the floating diffusion node (FD) is higher than the threshold voltage (Vth), the voltage and the charge pulse signal (CP) output from the comparator 216 may be maintained at a logic low level. When the photoelectric conversion element 212 generates photocharges, the voltage of the floating diffusion node (FD) that accumulates the photocharges becomes lower than the threshold voltage (Vth) so that the voltage output from the comparator 216 may be converted to a logic high level. A logic high level voltage may be output as the charge pulse signal (CP) after a predetermined time has passed through the delay circuit 218. In addition, as the charge pulse signal (CP) is converted to a logic high level, the reset transistor RX is turned on, and the floating diffusion node (FD) may be reset to a reset voltage (Vrst). Since the voltage of the reset floating diffusion node FD is higher than the threshold voltage (Vth), the voltage output from the comparator 216 may be converted from a logic high level to a logic low level. A logic low level voltage may be output as a charge pulse signal (CP) after a predetermined time has elapsed through the delay circuit 218. As described above, the light sensor 210 may generate a charge pulse signal (CP) having a pulse corresponding to a photo charge generated by sensing incident light. Here, the number of photo charges generating the pulse may be one "1", but other implementations are also possible.

[0048] The counter 220 may generate and store first count data (LB) by counting pulses of the charge pulse signal (CP).

[0049] The counter 220 may include a plurality of triggers whose number is equal to the number of bits included in the first count data (LB). Figure 2As shown, the first counting data (LB) may include M bits (LB[M-1]~LB[0]), where M is an integer of 2 or greater, and the counter 220 may include first to Mth counter triggers (225-1~225-M) corresponding to the M bits (LB[M-1]~LB[0]), respectively.

[0050] The first counter trigger 225-1 may include a clock terminal (CK) receiving a charge pulse signal (CP), an input terminal (D) and an inverting output terminal (Q') connected to each other, an output terminal (Q) outputting a first bit (LB[0]) of the first count data (LB), and a reset terminal (R') receiving a counter reset signal (RST). The reset terminal (R') may send a signal obtained by inverting the counter reset signal (RST) to the inside of the first counter trigger 225-1. The first counter trigger 225-1 may store the first bit (LB[0]) of the first count data (LB), may detect an edge (e.g., a falling edge) of the charge pulse signal (CP), may change the value of the currently stored first bit (LB[0]) to another value, and may store and output the changed value.

[0051] The second counter trigger 225-2 may include a clock terminal (CK) receiving a first bit (LB[0]) of the first count data (LB), an input terminal (D) and an inverting output terminal (Q') connected to each other, an output terminal (Q) outputting a second bit (LB[1]) of the first count data (LB), and a reset terminal (R') receiving a counter reset signal (RST). The second counter trigger 225-2 may store the second bit (LB[1]) of the first count data (LB), detect an edge (e.g., a falling edge) of the first bit (LB[0]) of the first count data (LB), change the value of the currently stored second bit (LB[1]) to another value, and store and output the changed value. That is, when the value of the first bit (LB[0]) changes from "1" to "0", the second bit (LB[1]) stored in the second counter trigger 225-2 may change.

[0052] Each of the third to Mth counter flip-flops (225-3~225-M) may operate in substantially the same manner as the second counter flip-flop 225-2 and may be sequentially connected to the second counter flip-flop 225-2.

[0053] The counter 220 may increase the first count data (LB) by "1" by counting the number of pulses of the charge pulse signal (CP). The first bit (LB[0]) may be the least significant bit (LSB) of the first count data (LB), and the Mth bit (LB[M-1]) may be the most significant bit (MSB) of the first count data (LB). Among the multiple bits from the first bit (LB[0]) to the Mth bit (LB[M-1]), as the order of the target bit becomes closer to the Mth order, the target bit may be used as a high bit with a higher order.

[0054] Each of the first to Mth counter flip-flops (225-1225-M) may be reset in response to a counter reset signal (RST). Here, the expression "reset" may mean that a signal is initialized to a logic low level.

[0055] The adder 230 stores an overflow value (OF) indicating whether the first count data (LB) overflows, and then outputs a summation result (SUM) of the second count data (UB) stored in the shift register 240 and the overflow value (OF). Here, the overflow of the first count data (LB) may mean that the Mth bit (LB[M-1]) of the first count data (LB) changes from a logic high level to a logic low level. The second count data (UB) may constitute count data corresponding to the pixel data together with the first count data (LB). The first count data (LB) may correspond to a low digit of the count data, and the second count data (UB) may correspond to a high digit of the count data. The number of bits included in the first count data (LB) may be determined according to the number of counter flip-flops included in the counter 220. The number of bits included in the second count data (UB) may be determined according to the number of register flip-flops included in the shift register 240.

[0056] The adder 230 may include a first selector 232 , a second selector 234 , a latch 235 , a third selector 236 , and a half adder 238 .

[0057] The adder 230 may operate in an addition mode or an overflow mode according to a mode selection signal (SEL).

[0058] When the mode selection signal (SEL) is at a logic high level, the adder 230 may operate in an addition mode. Here, the addition mode may refer to an operation mode in which the sum (SUM) of the second count data (UB) stored in the shift register 240 and the overflow value (OF) is calculated, and the resulting sum (SUM) is stored again in the shift register 240. At this time, the adder 230 may sequentially add the overflow value (OF) to the bits (UB[0]) to the MSB (UB[N-1]) output as the second count data (UB).

[0059] When the mode selection signal (SEL) is at a logic low level, the adder 230 may operate in an overflow mode. Here, the overflow mode may refer to a mode in which an operation of creating and storing an overflow value (OF) indicating whether the first count data (LB) overflows may be performed.

[0060] The first selector 232 may output one of a carry value (CARRY) output from the half adder 238 and a logic high level (e.g., 1) according to a mode selection signal (SEL). When the mode selection signal (SEL) is at a logic high level, the first selector 232 may output the carry value (CARRY). When the mode selection signal (SEL) is at a logic low level, the first selector 232 may output a logic high level.

[0061] The second selector 234 may select one of the Mth bit (LB[M-1]) of the first count data (LB) output from the counter 220 and the shift control signal (SC) according to the mode selection signal SEL. When the mode selection signal (SEL) is at a logic high level, the second selector 234 may output the shift control signal (SC). When the mode selection signal (SEL) is at a logic low level, the second selector 234 may output the Mth bit (LB[M-1]) of the first count data (LB). Here, the shift control signal (SC) may be a signal for controlling an operation of shifting bits stored in the shift register 240, and may also control the addition operation of the adder 230.

[0062] The latch 235 may store and output the output signal of the first selector 232 as an overflow value (OF) in response to an edge (e.g., a falling edge) of the output signal of the second selector 234. When the mode selection signal (SEL) is at a logic high level, the latch 235 may store a carry value (CARRY) as an overflow value (OF) in response to an edge of the shift control signal (SC). When the mode selection signal (SEL) is at a logic low level, the latch 235 may store a value "1" as an overflow value (OF) in response to an edge of the Mth bit (LB[M-1]).

[0063] In some embodiments, when the M-th bit (LB[M-1]) is at a logic high level during a period in which the mode selection signal (SEL) is at a logic low level, the latch 235 may receive the output value "1" of the first selector 232. Thereafter, at the logic high level of the mode selection signal (SEL), the output signal of the second selector 234 may transition from the logic high level of the M-th bit (LB[M-1]) to the logic low level of the shift control signal (SC). In response to this transition, the output value "1" of the first selector 232 may be stored as an overflow value (OF).

[0064] The third selector 236 may output one of the overflow value (OF) output from the latch 235 and a logic low level (e.g., 0) according to the mode selection signal (SEL). When the mode selection signal (SEL) is at a logic high level, the third selector 236 may output the overflow value (OF). When the mode selection signal (SEL) is at a logic low level, the third selector 236 may output a logic low level.

[0065] The half adder 238 may sum the output signal of the third selector 236 and the output signal (SR_OUT) of the shift register 240 , and may output a carry value (CARRY) and a sum value (SUM) based on the sum value.

[0066] For example, when the bit corresponding to the output of the third selector 236 is zero "0" and the output signal (SR_OUT) of the shift register 240 is "1", the carry value (CARRY) may be zero "0" and the sum value (SUM) may be "1". In addition, when the bit corresponding to the output of the third selector 236 is "1" and the output signal (SR_OUT) of the shift register 240 is "1", the carry value (CARRY) may be "1" and the sum value (SUM) may be zero "0".

[0067] The shift register 240 may store the second count data (UB) as a result of summing the M bits (LB[M-1:0]) of the first count data (LB) generated sequentially. In addition, the shift register 240 may output the second count data (UB) through the buffer 250, may receive the first count data (LB) from the counter 220, may temporarily store the received first count data (LB), and may output the stored first count data (LB) through the buffer 250. That is, the shift register 240 operates not only as a memory for generating and storing the second count data (UB), but also as a serializer for transmitting the first count data (LB) to the outside.

[0068] The shift register 240 may include a plurality of flip-flops whose number is equal to the number of bits included in the second count data (UB). Figure 2 As shown, the second count data (UB) may include N bits (UB[N-1] to UB[0]), where N is an integer of 2 or greater. The shift register 240 may include first to N-th register flip-flops (245-1 to 245-N) corresponding to the N bits (UB[N-1] to UB[0]), respectively, and first to N-th register switches (247-1 to 247-N) corresponding to output signals of the first to N-th register flip-flops (245-1 to 245-N), respectively.

[0069] The first register flip-flop 245-1 may include an input terminal (D) receiving the sum value (SUM) of the half adder 238, a clock terminal (CK) receiving the shift control signal (SC), and an output terminal (Q) outputting the (N-1)th bit (UB[N-1]) of the second count data (UB). The first register flip-flop 245-1 may store the (N-1)th bit (UB[N-1]) of the second count data (UB), may detect an edge (e.g., a falling edge) of the shift control signal (SC), may send the currently stored bit to the second register flip-flop 245-2, and may store and output the newly input sum value (SUM).

[0070] The second register flip-flop 245-2 may include an input terminal (D) receiving an output signal of the first register flip-flop 245-1, a clock terminal (CK) receiving a shift control signal (SC), and an output terminal (Q) outputting the (N-2)th bit (UB[N-2]) of the second count data (UB). The second register flip-flop 245-2 may store the (N-2)th bit (UB[N-2]) of the second count data (UB), may detect an edge (e.g., a falling edge) of the shift control signal (SC), may send a currently stored bit to the third register flip-flop 245-3, and may store and output the output signal of the first register flip-flop 245-1.

[0071] Each of the third to N-th register flip-flops (245-3 to 245-N) may operate in substantially the same manner as the second register flip-flop 245-2 and may be sequentially connected to the second register flip-flop 245-2. In particular, the output signal of the N-th register flip-flop 245-N may correspond to the output signal (SR_OUT) of the shift register 240.

[0072] Each of the first to N-th register switches (247-1 to 247-N) may be connected between the counter 220 and the output node of each of the first to N-th register flip-flops (245-1 to 245-N). For example, the first register switch 247-1 may be connected between the counter 220 and the output node of the first register flip-flop 245-1, the second register switch 247-2 may be connected between the counter 220 and the output node of the second register flip-flop 245-2, and the N-th register switch 247-N may be connected between the counter 220 and the output node of the N-th register flip-flop 245-N. For example, the first register switch 247-1 may be connected between the output node of the first register flip-flop 245-1 and the output node of the M-th counter flip-flop 225-M of the counter 220, and may selectively connect the two nodes to each other.

[0073] Each of the first to Nth register switches (247-1 to 247-N) may be opened or closed in response to a write control signal (WR). When the write control signal (WR) is at a logic low level, each of the first to Nth register switches (247-1 to 247-N) may be opened to separate the output node of the corresponding register trigger and the output node of the corresponding counter trigger from each other. When the write control signal (WR) is at a logic high level, each of the first to Nth register switches (247-1 to 247-N) may be short-circuited to connect the output node of the corresponding register trigger and the output node of the corresponding counter trigger to each other. At this time, the first to Mth bits (LB[0] to LB[M-1]) of the first count data (LB) may be transmitted to the output nodes of the first to Nth register triggers (245-1 to 245-N), respectively.

[0074] Although for the sake of convenience, Figure 2 The embodiment disclosed an example case where M and N are equal to each other, but other implementations are also possible. It should be noted that, according to another embodiment, M and N may also be different from each other. For example, N may be greater than M.

[0075] Unlike the first to Mth counter triggers (225-1 to 225-M), each of the first to Nth register triggers (245-1 to 245-N) may not include a reset terminal. The operation for resetting the first to Nth register triggers (245-1 to 245-N) can be achieved by resetting the first to Mth counter triggers (225-1 to 225-M) and sending the first to Mth bits (LB[0] to LB[M-1]) of the first counting data (LB) to the output nodes of the first to Nth register triggers (245-1 to 245-N) through the first to Nth register switches (247-1 to 247-N). That is, the hardware for performing the reset operation on the first to Nth register triggers (245-1 to 245-N) can be omitted, so that the size of each pixel (PX) can be further reduced.

[0076] In response to the readout signal (RO), the buffer 250 may transmit the output signal (SR_OUT) from the shift register 240 to the output line (PX_OUT) of the pixel (PX) through the column line connected to the pixel (PX). When the readout signal (RO) is at a logic low level, the buffer 250 may not transmit the output signal (SR_OUT) from the shift register 240 to the column line. When the readout signal (RO) is at a logic high level, the buffer 250 may transmit the output signal (SR_OUT) from the shift register 240 to the output line (PX_OUT) of the pixel PX through the column line.

[0077] Figure 3is a conceptual diagram illustrating the operation of a pixel at various time periods according to some embodiments of the present disclosure.

[0078] Reference Figure 3 , Figure 2 The pixel (PX) can be operated on a frame basis. For example, Figure 3 A first frame (FRAME1) and a second frame (FRAME2) are shown scheduled to be executed in sequence. In each of the first frame (FRAME1) and the second frame (FRAME2), a pixel (PX) may generate pixel data of a scene to be captured.

[0079] The first frame (FRAME1) may include a reset period (Reset), an exposure period (Exposure), and a readout period (Readout).

[0080] In the reset period, an operation of resetting (or initializing) photo charges and data stored in the pixel (PX) may be performed.

[0081] In the exposure period, an operation of counting the number of pulses corresponding to photocharges generated by light incident on the pixel (PX) and generating count data (or pixel data) indicating the amount of photocharges (or the intensity of incident light) may be performed.

[0082] In the readout period, count data (or pixel data) stored in the pixel (PX) may be output through a column line connected to the pixel (PX). At this time, when the pixel (PX) belonging to one column is connected to one column line, the pixels (PX) included in a plurality of rows (ROW1 to ROWk) (where "k" is an integer of 2 or more) may sequentially output count data on a row basis. Here, the count data may be the same data as the pixel data.

[0083] Figure 4 It is a diagram showing some embodiments of the present disclosure. Figure 3 A timing diagram of the operation of a pixel during a reset period and an exposure period is shown.

[0084] Reference Figure 4 , the reset period (Reset) and exposure period (Exposure) can refer to Figure 3 The reset period and exposure interval are shown. Figure 4 In the example of , each of M and N is set to 3, and the count data may include first count data (LB) consisting of 3 bits and second count data (UB) consisting of 3 bits. That is, the count data including 6 bits may represent the result of counting up to 64 pulses. However, the first count data (LB) consisting of 3 bits may count up to 8 pulses. Due to the configuration of the pixel (PX), the count result of more than 8 pulses cannot be immediately reflected in the second count data (UB).

[0085] On the other hand, according to the present embodiment, if necessary, a logic high level and a value of 1 may be used interchangeably, and a logic low level and a value of zero "0" may also be used interchangeably.

[0086] In some embodiments, the exposure period may include a plurality of sub-exposure intervals and a plurality of pause intervals after the sub-exposure intervals. Figure 4 In the example of , the exposure period may include eight sub-exposure intervals (SE1 to SE8) and eight pause intervals (SP1 to SP8), so that at most 64 pulses can be counted.

[0087] First, in the reset period, each of the counter reset signal (RST) and the write control signal (WR) may have a logic high level, and each of the enable control signal (EN), the mode selection signal (SEL), and the shift control signal (SC) may have a logic low level. Therefore, the first and second count data (LB, UB), the overflow value (OF), the carry value (CARRY), and the sum value (SUM) stored in the pixel (PX) may be initialized to a logic low level.

[0088] In each sub-exposure interval (SE1~SE8), the counter 220 can count the pulses of the charge pulse signal (CP) output from the light sensor 210 to generate and store the first counting data LB, and the adder 230 can generate and store the overflow value (OF) indicating whether the first counting data (LB) overflows (that is, whether the third bit (LB[2]) of the first counting data (LB) changes from "1" to "0").

[0089] In each pause interval (SP1~SP8), the operation of the counter 220 can be stopped (or paused), and the adder 230 can calculate the sum of the second count data (UB) and the overflow value (OF) stored in the shift register 240, and the second count data corresponding to the sum result can be stored in the shift register 240.

[0090] exist Figure 4 In the figure, the pulse of the charge pulse signal (CP) appears a total of 25 times in the corresponding frame, six times in the first sub-exposure interval (SE1), four times in the second sub-exposure interval (SE2), eight times in the third sub-exposure interval (SE3), and seven times in the fourth sub-exposure interval (SE4).

[0091] In the first sub-exposure interval (SE1), each of the counter reset signal (RST), the write control signal (WR), the mode selection signal (SEL), and the shift control signal (SC) may have a logic low level, and the enable control signal (EN) may have a logic high level.

[0092] When the enable control signal (EN) has a logic high level, the light sensor 210 may be enabled to detect incident light, and may generate a charge pulse signal (CP) having 6 pulses corresponding to the generated photocharges. The counter 220 may count the 6 pulses of the charge pulse signal (CP) and increase the first count data (LB) by "1" for each pulse. That is, when the first sub-exposure interval (SE1) is completed, the first count data (LB) may have a value from the initialization value "0" to a value of 6.

[0093] When the mode selection signal (SEL) has a logic low level, the adder 230 may operate in an overflow mode and may store an overflow value (OF) indicating whether the first count data (LB) overflows. Since the third bit (LB[2]) of the first count data (LB) does not change from "1" to "0", the overflow value (OF) may be maintained at zero "0".

[0094] In the first pause interval (SP1), each of the counter reset signal (RST), the write control signal (WR), and the enable control signal (EN) may have a logic low level, and the mode selection signal (SEL) may have a logic high level. The shift control signal (SC) may include three pulses. Here, the number of pulses may be equal to the number of bits of the second count data stored in the shift register 240, or may be equal to the number of register flip-flops included in the shift register 240.

[0095] When the enable control signal EN has a logic high level, the light sensor 210 may be enabled, and the counter 220 may maintain the stored first count data (LB).

[0096] When the mode selection signal (SEL) has a logic high level, the adder 230 may operate in the addition mode, and the half adder 238 of the adder 230 may sum the output signal (SR_OUT) and the overflow value (OF) of the shift register 240, and may output a carry value (CARRY) and a sum value (SUM). Since each of the output signal (SR_OUT) and the overflow value (OF) of the shift register 240 is zero "0", each of the carry value (CARRY) and the sum value (SUM) may be zero "0".

[0097] As the shift control signal (SC) changes from "0" to "1" at the falling edge of the first pulse of the shift control signal (SC), the carry value (CARRY) may be input to the latch 235 and may be output as an overflow value (OF). The first bit (UB[0]) of the second count data (UB) may be reflected in the sum value (SUM) and stored in the first register flip-flop 245-1 of the shift register 240 so that the stored bit may be output as the third bit (UB[2]). In addition, the third bit (UB[2]) and the second bit (UB[1]) stored in the first register flip-flop 245-1 and the second register flip-flop 245-2 of the shift register 240, respectively, may be shifted and stored in the second register flip-flop 245-2 and the third register flip-flop 245-3, respectively.

[0098] Not only at the falling edge of the second pulse of the shift control signal (SC), but also at the falling edge of the third pulse of the shift control signal (SC), the operation at the falling edge of the first pulse of the shift control signal (SC) may be performed in substantially the same manner as in the second and third pulses of the shift control signal (SC). That is, the adder 230 may sequentially perform the summation between the overflow value (OF) and the second count data (UB) in a direction from the LSB (e.g., the first bit UB[0]) to the MSB (e.g., the third bit UB[2]) of the second count data (UB). The shift register 240 may sequentially store a sum value (SUM) as a summation result of the overflow value (OF) and the second count data (UB), and may store a summation result between the second count data (UB) and the overflow value (OF) as a new second count data (UB).

[0099] In the first pause interval ( SP1 ), a sum value “0” of the second count data (UB) zero “0” and the overflow value (OF) zero “0” may be stored in the shift register 240 as the second count data (UB).

[0100] In the following description, the control signals (RST, WR, EN, SEL, SC) generated in each sub-exposure interval (SE2-SE8) may have the same waveform as the control signals (RST, WR, EN, SEL, SC) generated in the first sub-exposure interval (SE1), and the control signals (RST, WR, EN, SEL, SC) generated in each pause interval (SP2-SP8) may have the same waveform as the control signals (RST, WR, EN, SEL, SC) generated in the first pause interval (SP1). In each sub-exposure interval (SE2-SE8), the pixel (PX) may perform substantially the same operation as in the first sub-exposure interval (SE1), and in each pause interval (SP2-SP8), the pixel (PX) may perform substantially the same operation as in the first pause interval SP1, so the redundant description thereof will be omitted in the following description of each interval below.

[0101] In the second sub-exposure interval (SE2), the counter 220 may count four pulses of the charge pulse signal (CP) and increase the first count data (LB) by 1 for each pulse. The counter 220 may be initialized after counting two pulses and may count the remaining two pulses and store the first count data LB 2.

[0102] When the counter 220 is initialized, the third bit (LB[2]) of the first count data (LB) is changed from "1" to "0" so that the overflow value (OF) may be changed to "1".

[0103] In the second pause interval (SP2), as the mode selection signal (SEL) changes to a logic high level, the output signal (SR_OUT) zero "0" of the shift register 240 and the overflow value (OF) "1" are summed so that the carry value (CARRY) can be zero "0" and the sum value (SUM) can be "1".

[0104] In the second pause interval (SP2), according to the shift control signal (SC) including three pulses, the operation of summing the overflow value (OF) “1” and the second count data (UB) zero “0” by the adder 230 may be sequentially performed in bit units (bit-based), so that the sum value “1” of the second count data (UB) “0” and the overflow value (OF) “1” may be stored as the second count data (UB) in the shift register 240. Therefore, after such summing is completed, the output signal (SR_OUT) (the first bit (UB[0])) of the shift register 240 may be “1”, and the sum value (SUM) may be “1”.

[0105] In the third sub-exposure interval (SE3), the counter 220 may count eight pulses of the charge pulse signal (CP) and increase the first count data (LB) by "1" for each pulse. The counter 220 may be initialized after counting six pulses and may count the remaining two pulses and store the first count data (LB)2.

[0106] When the counter 220 is initialized, the third bit (LB[2]) of the first count data (LB) is changed from "1" to "0" so that the overflow value (OF) may be changed to "1".

[0107] In the third pause interval (SP3), as the mode selection signal (SEL) changes to a logic high level, the output signal (SR_OUT) "1" of the shift register 240 and the overflow value (OF) "1" are summed so that the carry value (CARRY) can be "1" and the sum value (SUM) can be "0".

[0108] In the third pause interval (SP3), according to the shift control signal (SC) including three pulses, the operation of the adder 230 to sum the overflow value (OF) "1" and the second count data (UB) "1" may be sequentially performed on a bit basis, so that the sum value "2" of the second count data (UB) "1" and the overflow value (OF) "1" may be stored as the second count data (UB) in the shift register 240. Therefore, after such summation is completed, the output signal (SR_OUT) (first bit (UB[0])) of the shift register 240 may be "0", and the sum value (SUM) may be "0".

[0109] exist Figure 4 In the example of FIG. 1 , in the fourth to seventh sub-exposure intervals (SE4-SE7), the charge pulse signal (CP) does not include a pulse. Therefore, the data stored in each of the counter 220, the adder 230, and the shift register 240 may remain unchanged.

[0110] In the eighth sub-exposure interval (SE8), the counter 220 may count seven pulses of the charge pulse signal (CP) and increase the first count data LB by "1" for each pulse. The counter 220 may be initialized after counting six pulses and may count the remaining one pulse to store the first count data (LB)1.

[0111] When the counter 220 is initialized, the third bit (LB[2]) of the first count data (LB) is changed from "1" to "0" so that the overflow value (OF) may be changed to "1".

[0112] In the eighth pause interval (SP8), as the mode selection signal (SEL) changes to a logic high level, the output signal (SR_OUT) zero "0" and the overflow value (OF) "1" of the shift register 240 are summed so that the carry value (CARRY) can be zero "0" and the sum value (SUM) can be "1".

[0113] In the eighth pause interval (SP8), according to the shift control signal (SC) including three pulses, the operation of the adder 230 to sum the overflow value (OF) "1" and the second count data (UB) "2" may be sequentially performed on a bit basis, so that the sum value "3" of the second count data (UB) "2" and the overflow value (OF) "1" may be stored as the second count data (UB) in the shift register 240. Therefore, after such summation is completed, the output signal (SR_OUT) (first bit (UB[0])) of the shift register 240 may be "1", and the sum value (SUM) may be "1".

[0114] Figure 5 It is a diagram showing some embodiments of the present disclosure. Figure 3 A timing diagram showing the operation of a pixel during the readout period is shown.

[0115] Reference Figure 5 , the readout interval (Readout) can refer to Figure 3 In addition, in the readout interval Figure 4 Under the same conditions as (PX) Figure 4 The readout interval after the exposure interval will be referred to below. Figure 4 to describe.

[0116] In the readout period, each of the enable control signal (EN) and the mode selection signal (SEL) may have a logic low level, and the readout signal (RO) may have a logic high level within a predetermined time required to output the count data. That is, while the readout signal (RO) has a logic high level, the second count data (UB) and the first count data (LB) may be sequentially output from the pixel (PX).

[0117] After the exposure period is completed, under the condition that the output signal (SR_OUT) of the shift register 240 (i.e., the first bit (UB[0])) is set to "1", when the read-out signal (RO) is converted to a logic high level, the output signal (PX_OUT) of the pixel (PX) may be "1", indicating the output signal (SR_OUT) of the shift register 240.

[0118] At the first falling edge of the shift control signal (SC), the second count data (UB) stored in the shift register 240 may be shifted on a bit basis so that the output signal (SR_OUT) of the shift register 240 may be the second bit (UB[1]). Therefore, the output signal (PX_OUT) of the pixel (PX) may be "1", indicating the output signal (SR_OUT) of the shift register 240.

[0119] At the second falling edge of the shift control signal (SC), the second count data (UB) stored in the shift register 240 may be shifted on a bit basis so that the output signal (SR_OUT) of the shift register 240 may be the third bit (UB[2]). Therefore, the output signal (PX_OUT) of the pixel (PX) may be "0", indicating the output signal (SR_OUT) of the shift register 240.

[0120] Therefore, the output of the second count data UB can be completed by two pulses included in the shift control signal (SC).

[0121] Thereafter, as the write control signal (WR) changes to a logic high level, the third bit (LB[2]) of the first counting data (LB) may be sent to the output data (UB[2]) of the first register trigger 245-1 of the shift register 240, the second bit (LB[1]) of the first counting data (LB) may be sent to the output data (UB[1]) of the second register trigger 245-2, and the first bit (LB[0]) of the first counting data (LB) may be sent to the output data (UB[0]) of the third register trigger 245-3.

[0122] Therefore, the output signal (PX_OUT) of the pixel (PX) may be zero '0', corresponding to the output signal (SR_OUT) of the shift register 240 corresponding to the first bit (LB[0]) of the first count data (LB).

[0123] At the third falling edge of the shift control signal (SC), the first count data (LB) stored in the shift register 240 may be shifted bit by bit so that the output signal (SR_OUT) of the shift register 240 may be the second bit (LB[1]) of the first count data (LB). Therefore, the output signal (PX_OUT) of the pixel (PX) may be zero "0", corresponding to the output signal (SR_OUT) of the shift register 240.

[0124] At the fourth falling edge of the shift control signal (SC), the first count data (LB) stored in the shift register 240 may be shifted bit by bit so that the output signal (SR_OUT) of the shift register 240 may be the third bit (LB[2]) of the first count data (LB). Therefore, the output signal (PX_OUT) of the pixel (PX) may be zero "0", corresponding to the output signal (SR_OUT) of the shift register 240.

[0125] like Figure 5 As shown, as the operation of outputting count data (UB, LB) is performed in the read-out period, the first count data (LB) stored in the counter 220 may be maintained at a value of "1", and the second count data (UB) stored in the shift register 240 may be changed sequentially in the order of 3→5→6→1→4→2.

[0126] The output signal (PX_OUT) of the pixel (PX) can change to "1", "1" and "0" in sequence, indicating the second counting data (UB) corresponding to the high bit of the counting data, and can change to "1", "0" and "0" in sequence, indicating the first counting data (LB) corresponding to the low bit of the counting data.

[0127] The output signal (PX_OUT) of the pixel (PX) may be reorganized into 011001 (=25) by an external device (eg, an image signal processor).

[0128] The shift register 240 may perform a refresh operation on the stored second count data (UB).

[0129] In some embodiments, the shift register 240 may receive a refresh control signal including three pulses instead of the shift control signal (SC) in the sub-exposure interval, and may control the half adder 238 to sum the value "0" (output from the third selector 236) and each bit of the second count data (UB) and output the sum value. Therefore, the shift register 240 may prevent the second count data (UB) from being lost due to the leakage current generated in each register flip-flop (245-1 to 245-N) during the sub-exposure interval.

[0130] In some other embodiments, the shift register 240 of the pixels belonging to another row different from the row in which the operation of the readout interval is performed may receive a refresh control signal including three pulses in the readout interval of the another row, and may control the half adder 238 to sum the output value "0" of the third selector 236 and each bit of the second count data (UB) and output the sum. Therefore, the shift register 240 may prevent the second count data (UB) from being lost due to leakage current occurring in each register flip-flop (245-1 to 245-N) during the readout period of the another row.

[0131] Figure 6 Some embodiments of the present disclosure are shown Figure 2 The circuit diagram of the shift register is shown in FIG.

[0132] Although for the sake of convenience, Figure 2 The embodiment shows the case where the number of bits (M) of the first count data (LB) and the number of bits (N) of the second count data (UB) are the same as each other, but other implementations are also possible. Figure 6 The following embodiments will hereinafter disclose a case where the number of bits (M) of the first count data (LB) is higher than the number of bits (N) of the second count data (UB) with reference to the accompanying drawings.

[0133] like Figure 6 As shown, when the number of bits (N) of the second count data (UB) is higher than the number of bits (M) of the first count data (LB) by a value "1", the number of register triggers (245-1 to 245-N) included in the shift register 240' may be higher than the number of counter triggers (225-1 to 225-M) included in the counter 220 by a value "1".

[0134] In this case, a fixed input signal (e.g., “0”) may be applied to one terminal of the first register switch 247-1 connected to an output terminal (UB[N-1]) of the first register trigger 245-1 among the register triggers (245-1 to 245-N) that does not correspond to the counter trigger (225-1 to 225-M).

[0135] As described above, a fixed input signal may be applied to one terminal of the first register switch 247-1. As a result, an operation of initializing the second register flip-flop 245-2 in the reset period and another operation of inputting and outputting the first count data (LB) to the shift register 240' in the readout period may be performed normally.

[0136] In some other embodiments, the fixed input signal may not be applied to one terminal of the first register switch 247-1, but the output signal (LB[M-1]) of the Mth counter flip-flop 225-M may be applied to one terminal of the first register switch 247-1.

[0137] Figure 7 is a circuit diagram showing a counter flip-flop according to some embodiments of the present disclosure.

[0138] Reference Figure 7 , the counter trigger 700 can be Figure 2 Examples of the various counter flip-flops (225-1 to 225-M) shown. Figures 7 to 9The power supply voltage (VDD) and ground voltage shown may correspond to a logic high level and a logic low level, respectively.

[0139] The counter trigger 700 may include first to eighteenth transistors (M1 to M18). Here, the first to eighteenth transistors (M1 to M18) may be classified into PMOS transistors (M1, M3, M5, M7, M9, M11, M13, M15, M17) and NMOS transistors (M2, M4, M6, M8, M10, M12, M14, M16, M18).

[0140] The first transistor and the second transistor (M1, M2) may constitute a first transmission gate. When a logic low level input signal is received through the clock terminal (CK), each of the first transistor and the second transistor (M1, M2) may be short-circuited to send data input to the input terminal (D) to the other terminal thereof. In addition, when a logic high level input signal is received through the clock terminal (CK), each of the first transistor and the second transistor (M1, M2) may be disconnected to not send data input to the input terminal (D) to the other terminal thereof.

[0141] The third to sixth transistors (M3-M6) may constitute a NAND gate that performs a NAND operation between the first data input to the reset terminal (R) and the second data input to the other terminal of the first transmission gate and sends the result of such NAND operation to the storage node (SN). In more detail, in a time period when the counter reset signal (RST) is at a logic low level, the NAND gate may invert the data input to the input terminal (D) and store the inverted data in the storage node (SN). In a time period when the counter reset signal (RST) is at a logic high level, the NAND gate may store data "1" in the storage node (SN) regardless of the data input to the input terminal (D).

[0142] The seventh to tenth transistors (M7-M10) may constitute a first feedback circuit. The first feedback circuit may float the other terminal of the first transmission gate in response to a low-level input signal of the clock terminal (CK). Alternatively, the first feedback circuit may invert the data of the storage node (SN) in response to a high-level input signal of the clock terminal (CK), so that the inverted data may be fed back to the other terminal of the first transmission gate.

[0143] The eleventh transistor and the twelfth transistor (M11, M12) may constitute a second transmission gate. In response to a high-level input signal of the clock terminal (CK), each of the eleventh transistor and the twelfth transistor (M11, M12) may be short-circuited to send data of the storage node (SN) to the other terminal thereof. Alternatively, in response to a low-level input signal of the clock terminal (CK), each of the eleventh transistor and the twelfth transistor (M11, M12) may be disconnected to not send data of the storage node (SN) to the other terminal thereof.

[0144] The thirteenth and fourteenth transistors (M13, M14) may constitute an inverter, and may invert data of the other terminal of the second transmission gate and transmit the inverted data to the output terminal (Q).

[0145] The fifteenth to eighteenth transistors (M15-M18) may constitute a second feedback circuit. The second feedback circuit may float the other terminal of the second transmission gate in response to a high-level input signal of the clock terminal (CK). Alternatively, the second feedback circuit may invert the data of the output terminal (Q) in response to a low-level input signal of the clock terminal (CK), so that the inverted data may be fed back to the other terminal of the second transmission gate. The other terminal of the second transmission gate may be connected to the inverting output terminal (Q').

[0146] The counter trigger 700 includes not only a NAND gate for initializing the data stored in the storage node (SN), but also a first feedback circuit and a second feedback circuit capable of maintaining the data stored in the storage node (SN) and the data stored in the output terminal (Q) without any loss. After the counter trigger 700 stores specific data in the exposure period, the counter trigger 700 must maintain the stored data until the next pulse of the charge pulse signal (CP) appears (particularly, the counter trigger 700 must maintain the stored data for a long time under low illumination conditions), so that the first feedback circuit and the second feedback circuit can help improve the data retention performance of the counter trigger 700.

[0147] Reference Figure 7 , a counter flip-flop 700 suitable for the counter 220 may include a relatively large number (eg, 18) of transistors.

[0148] Figure 8 is a circuit diagram showing a register flip-flop according to some embodiments of the present disclosure.

[0149] Reference Figure 8 , the register flip-flop 800 may be Figure 2 Examples of various register flip-flops (245-1 to 245-N) are shown.

[0150] The register flip-flop 800 may include first to eleventh transistors (M1 to M11). Here, the first to eleventh transistors (M1 to M11) may be classified as PMOS transistors (M1, M3, M5, M7, M9) and NMOS transistors (M2, M4, M6, M8, M10, M11). In addition, it should be noted that Figure 8 The first to eleventh transistors (M1 to M11) of the register flip-flop 800 are connected to Figure 7 The first to eleventh transistors (M1-M11) of the counter flip-flop 700 are shown as being irrelevant.

[0151] The register flip-flop 800 may correspond to a true single phase clock (TSPC) flip-flop.

[0152] The register trigger 800 may include: a first transistor and a second transistor (M1, M2), each having a gate terminal connected to an input terminal (D) to operate as an inverter; a third transistor and a fourth transistor (M3, M4), each having a gate terminal connected to a node (D'); a fifth transistor, a seventh transistor, an eighth transistor and an eleventh transistor (M5, M7, M8, M11), each having a gate terminal connected to a clock terminal (CK); a sixth transistor M6, having a gate terminal connected to a node (A); and a ninth transistor and a tenth transistor (M9, M10), each having a gate terminal connected to a node (B).

[0153] When the signal input to the clock terminal (CK) is at a logic low level and the signal input to the input terminal (D) is at a logic high level, the third transistor M3 and the fifth transistor M5 may be turned on and the fourth transistor M4 may be turned off so that the signal of the node (A) connected to the fifth transistor M5 may be at a logic high level. Therefore, the sixth transistor M6 may be turned on and the seventh transistor M7 may also be turned on by the signal input to the clock terminal (CK). In addition, the node (B) connected to the seventh transistor M7 may be precharged to a logic high level.

[0154] On the other hand, when the signal input to the clock terminal CK is at a logic low level and the signal input to the input terminal (D) is at a logic low level, the signal at the node A may have a logic low level. In addition, the sixth transistor M6 may be turned off, the seventh transistor M7 may be turned on by the signal input to the clock terminal (CK), and the node (B) may be precharged to a logic high level.

[0155] When the node (B) is precharged as described above, the output terminal (Q) is in a state of latching a previous output value so that the previous output value can be maintained at the output terminal (Q).

[0156] Then, when the signal input to the clock terminal (CK) changes from a logic low level to a logic high level, it can be determined whether the node (B) will remain at a precharged logic high level or will be discharged to a logic low level according to whether the output value of the node (A) is at a logic low level or a logic high level. As a result, the output terminal (Q) can be determined to be a logic low level or a logic high level according to whether the node (B) is at a logic high level or a logic low level.

[0157] The register flip-flop 800 may perform the above-described operation, and may output the same data as data input to the input terminal (D) in response to a signal input to the clock terminal (CK).

[0158] Figure 8 The register flip-flop 800 may include only 11 transistors, which is significantly less than Figure 7 The number of transistors included in the counter trigger 700.

[0159] Since the register flip-flop 800 receives the initialized data from the counter 220 as described above, the register flip-flop 800 does not need to perform self-initialization, and thus a NAND gate connected to the reset terminal (R) may not be required.

[0160] In addition, since the register flip-flop 800 causes the circulation of the data stored in each pause interval, the register flip-flop 800 only needs to maintain the data for a relatively short time compared to the counter flip-flop 700, so that the first feedback circuit and the second feedback circuit are not required. In addition, as described above, due to the refresh operation of the shift register 240, the data retention performance required by the register flip-flop 800 can be further reduced.

[0161] Fig. 9 is a circuit diagram showing another register flip-flop according to some embodiments of the present disclosure.

[0162] Reference Fig. 9 , the register flip-flop 900 can be implemented as Figure 2 Another implementation of each register flip-flop (245-1 to 245-N) is shown.

[0163] The register flip-flop 900 may include first to ninth transistors (M1 to M9). Here, the first to ninth transistors (M1 to M9) may be classified into PMOS transistors (M1, M3, M5, M7) and NMOS transistors (M2, M4, M6, M8, M9). In addition, Fig. 9 The first to ninth transistors (M1 to M9) of the register flip-flop 900 shown in FIG. 9 can be similar in structure and function to those of FIG. Figure 8 The third to eleventh transistors (M3-M11) of the register flip-flop 800 are shown to be substantially identical.

[0164] The register flip-flop 900 may have a structure in which the first and second transistors (M1, M2) corresponding to the inverter are omitted from the register flip-flop 800. The register flip-flop 900 may correspond to a inverting true single phase clock (TSPC) flip-flop.

[0165] Since the structure and function of the register flip-flop 900 are substantially the same as those of the register flip-flop 800 except that the inverter is omitted, redundant descriptions thereof will be omitted herein for the sake of brevity.

[0166] However, since the register flip-flop 900 does not include an inverter, data input to the input terminal (D) of the register flip-flop 900 may be inverted and output to the output terminal (Q).

[0167] Therefore, the shift register 240 may include an even number of register flip-flops 900 so that data input to the shift register 240 is not inverted and output as an output signal (SR_OUT) of the shift register 240 .

[0168] Alternatively, when the shift register 240 includes an odd number of register flip-flops 900 , an inverter for inverting data may be additionally placed before or after the odd number of register flip-flops 900 .

[0169] When the shift register 240 includes a register flip-flop 900 composed of nine transistors, the size of the pixel (PX) can be further reduced.

[0170] Fig.10 It is a diagram showing some embodiments of the present disclosure including Figure 2 A conceptual diagram of a downsampling method for an image sensing device with pixels.

[0171] Reference Fig.10 , Fig.10 (a) shows an example of pixels arranged in a matrix including 12 rows and 12 columns, and pixels indicated by hatching may be pixels included in a texture indicated by diamonds. Fig.10 In (a), pixels included in the texture have a relatively higher average value of pixel data than other pixels not included in the texture.

[0172] The image sensing device 10 may perform downsampling to reduce the amount of power consumed by the pixel array 110. Downsampling may be performed in units of pixel clusters including a plurality of pixels (#1 to #4) arranged in a (2×2) matrix structure. Such downsampling may mean acquiring pixel data by enabling only some pixels determined according to a predetermined rule, rather than acquiring pixel data by enabling all pixels included in the pixel clusters.

[0173] Although for the sake of convenience, Fig.10 The embodiment discloses an example case where the pixel cluster includes four pixels arranged in a (2×2) matrix, but other implementations are also possible, and it should be noted that the pixel cluster may include two or more pixels and the two or more pixels may not be adjacent to each other. In addition, the number of pixels downsampled and enabled in the pixel cluster may be selected within a range where the number of pixels is less than the total number of pixels included in the pixel cluster.

[0174] Fig.10 (b) and Fig.10 The method shown in (c) may correspond to a comparative example of the disclosed technology (indicated by “4 to 1 downsampling”), Fig.10 (d) and Fig.10 The method shown in (e) may correspond to one embodiment of the present disclosure (indicated by “contrast-based downsampling”).

[0175] First, you can Fig.10 As can be seen from (b), only pixels located at fixed positions (e.g., pixels located at the upper left side of the figure) among the pixels included in each pixel cluster may be enabled, and the remaining pixels other than the enabled pixels may be disabled so that only the pixels at the fixed positions can generate pixel data. Enabled pixels may be represented by solid lines, and disabled pixels may be represented by dotted lines.

[0176] Reference Fig.10 (c), according to the 4-to-1 downsampling method, the disabled pixels included in the same pixel cluster as the enabled pixels can be reconstructed to have the same pixel data as the pixel data obtained from the enabled pixels. The straight line depicted as interconnecting the pixels can be a straight line through which the pixels providing pixel data (i.e., the enabled pixels) are connected to other pixels receiving pixel data (i.e., the disabled pixels) during the reconstruction process. The 4-to-1 downsampling method has the advantage of reducing power consumption without requiring additional hardware implementation due to its own relatively simple operation method, but as Fig.10 As shown in (c), there is a problem that the shape of the texture may change, such as Fig.10 The original data in (a) and Fig.10 The comparison results between the restored data are shown in (c).

[0177] Reference Fig.10 (d) of FIG. 1 , it can be determined whether to enable only the pixels located on the upper left side of the pixel cluster or to enable all pixels belonging to the pixel cluster based on the difference (contrast) between the pixel data (i.e., count data) of the pixels included in each pixel cluster. The enabled pixels can be represented by a solid line, and the disabled pixels can be represented by a dotted line.

[0178] When the difference (contrast) between pixel data within a pixel cluster exceeds a predetermined level, all pixels in the pixel cluster may be enabled. On the other hand, when the difference (contrast) between pixel data within a pixel cluster is a predetermined level or less, only some pixels of the pixel cluster (e.g., pixels located on the upper left side of the pixel cluster) may be enabled. That is, downsampling may be performed on a pixel cluster in which the difference in pixel data between pixels is relatively small, and downsampling may not be performed on a pixel cluster in which the difference in pixel data between pixels is relatively large.

[0179] Available from Fig.10 As can be seen from (d), when the pixel cluster includes not only pixels included in the texture (e.g., shadow pixels) but also other pixels not included in the texture (e.g., white pixels), the pixel data difference between the pixels within the pixel cluster exceeds a predetermined level so that all pixels belonging to the pixel cluster can be enabled. When the pixel cluster includes only pixels included in the texture (e.g., shadow pixels) or only pixels not included in the texture (e.g., white pixels), the pixel data difference between the pixels within the pixel cluster may be a predetermined level or less so that only pixels located on the upper left side of the pixel cluster can generate pixel data.

[0180] Reference Fig.10 (e) According to the contrast-based downsampling method, no separate reconstruction operation is performed on the pixel clusters that have not been downsampled, and the reconstruction operation may be performed on the pixel clusters that have been downsampled. Fig.10 The same reconstruction operations as those in (c) are performed. Fig.10 As shown in (e), the contrast-based downsampling method can be achieved by Fig.10 The original data of (a) and Fig.10 The reconstructed data (ie, restored data) of (e) is compared to maintain the same texture shape, thereby increasing the quality of the image. In addition, downsampling may be selectively applied to pixel clusters with smaller differences between pixel data, thereby reducing power consumption as much as possible.

[0181] Fig.11 is a circuit diagram illustrating pixel clustering that may perform a contrast-based downsampling method according to some embodiments of the present disclosure.

[0182] Reference Fig.11 , the pixel cluster 1100 may include four pixels (eg, first to fourth pixels) and a contrast matching unit 1110 that determines whether to apply downsampling to the pixel cluster 1100 . Fig.11 Some elements directly related to the contrast-based down-sampling method among the constituent elements of the pixel cluster 1100 are shown.

[0183] The pixel cluster 1100 may include first to fourth light sensors ( 210 - 1 ˜ 210 - 4 ), first to fourth shift registers ( 240 - 1 ˜ 240 - 4 ), and a contrast matching unit 1110 .

[0184] The first to fourth light sensors (210-1 to 210-4) may be included in the first to fourth pixels, respectively. The first to fourth shift registers (240-1 to 240-4) may be included in the first to fourth pixels, respectively.

[0185] The contrast matching unit 1110 may determine whether to perform down-sampling on the pixel cluster 1100 based on output signals (SR_OUT1 ˜ SR_OUT4 ) of the first to fourth shift registers ( 240 - 1 ˜ 240 - 4 ).

[0186] The contrast matching unit 1110 may include a first AND gate 1112 , an exclusive OR (XOR) gate 1114 , a sampling controller 1116 , and a second AND gate 1118 .

[0187] The first AND gate 1112 may send a result (hereinafter referred to as a multiplication result) of multiplying the output signal (SR_OUT1) of the first shift register 240-1 by the threshold value (TH) to the sampling controller 1116. The threshold value (TH) may be a reference value for determining whether the output signal (SR_OUT1) of the first shift register 240-1 is a valid value, and may be a bit string other than the M lower bits among the bit strings corresponding to a number equal to the "P" power of 2, where P is a natural number greater than M and less than or equal to N. That is, the output signal (SR_OUT1) of the first shift register 240-1 may change sequentially from the first bit (UB[0]) to the Nth bit (UB[N-1]). In response to this sequential change, the threshold value (TH) may also change sequentially in the direction from the bit corresponding to the first bit (UB[0]) to the bit corresponding to the Nth bit (UB[N-1]).

[0188] The XOR gate 1114 may receive the output signals (SR_OUT1 to SR_OUT4) of the first to fourth shift registers (240-1 to 240-4), may perform an XOR operation on the received signals, and may send the result of the XOR operation (hereinafter referred to as "XOR result") to the sampling controller 1116. Here, the XOR operation on the output signals (SR_OUT1 to SR_OUT4) of the first to fourth shift registers (240-1 to 240-4) may be performed sequentially in units of bits. For example, after performing an XOR operation on the first bit (UB[0]) of the second count data (UB), an XOR operation may be performed on the second bit (UB[1]) of the second count data (UB).

[0189] If the output signals (SR_OUT1 to SR_OUT4) of the first to fourth shift registers (240-1 to 240-4) all have the same value, the XOR result may be zero "0". Conversely, when at least one of the output signals (SR_OUT1 to SR_OUT4) of the first to fourth shift registers (240-1 to 240-4) has a different value, the XOR result may be "1".

[0190] The sampling controller 1116 may be initialized by the counter reset signal (RST) and generates a sampling control signal (SAM) for determining whether to perform a downsampling operation based not only on the multiplication result received from the first AND gate 1112 but also on the XOR result received from the XOR gate 1114.

[0191] The sampling controller 1116 may determine whether the output signal (SR_OUT1) of the first shift register 240-1 is a valid value according to the multiplication result received from the first AND gate 1112. The valid condition for determining the validity of the output signal (SR_OUT1) of the first shift register 240-1 may be a condition that the output signal (SR_OUT1) of the first shift register 240-1 is greater than a threshold value (TH).

[0192] When it is determined that the output signal (SR_OUT1) of the first shift register 240-1 is not a valid value, the sampling controller 1116 may generate a sampling control signal (SAM) corresponding to a value of "1" regardless of the XOR result, and may send the sampling control signal (SAM) to the second AND gate 1118.

[0193] When it is determined that the output signal (SR_OUT1) of the first shift register 240-1 is a valid value, the sampling controller 1116 may generate a sampling control signal (SAM) according to the XOR result and transmit the sampling control signal (SAM) to the second AND gate 1118. That is, when the XOR result of the entire second count data (UB) is zero "0" (for example, the cumulative sum of the XOR results is 0), the sampling controller 1116 may generate a sampling control signal (SAM) corresponding to zero "0". On the contrary, when the XOR result of at least one bit of the second count data (UB) is "1" (for example, the cumulative sum of the XOR results is a value of 1 or greater), the sampling controller 1116 may generate a sampling control signal (SAM) corresponding to a value of 1.

[0194] The second AND gate 1118 may transmit an enable control signal (EN′) indicating an execution result of a multiplication operation between the enable control signal (EN) and the sampling control signal (SAM) to the second to fourth light sensors ( 210 - 2 ˜ 210 - 4 ).

[0195] Each of the second to fourth light sensors (210-2 to 210-4) may stop generating the charge pulse signal (CP) in response to the enable control signal (EN') 0. In addition, each of the second to fourth light sensors (210-2 to 210-4) may generate the charge pulse signal (CP) in response to the enable control signal (EN') 1 in the same manner as in the first light sensor 210-1.

[0196] When the output signal (SR_OUT1) of the first shift register (240-1) is equal to or greater than a predetermined value and the second count data (UB) values ​​output from the first to fourth shift registers (240-1 to 240-4) are completely equal to each other, the contrast matching unit 1110 may perform down-sampling to deactivate the second to fourth light sensors (210-2 to 210-4).

[0197] If the above conditions are not satisfied, the contrast matching unit 1110 may enable the second to fourth light sensors ( 210 - 2 ˜ 210 - 4 ) to perform sampling on all pixels belonging to the pixel cluster 1100 .

[0198] In the disclosed technology, the reason why the second count data (UB) is used to determine whether to perform downsampling is because the first count data (LB) includes a large amount of noise components such as shot noise and is considered unsuitable for determining whether there is data similarity between pixels.

[0199] Fig.12 Some embodiments of the present disclosure are shown Fig.11 A flowchart of the operation of pixel clustering is shown.

[0200] exist Fig.12 In the embodiment, the first to fourth pixels included in the pixel cluster 1100 may simultaneously perform an operation during a reset period, an operation during an exposure period, and an operation during a readout period within the same frame.

[0201] First, in the reset period, the first and second count data (LB, UB), the overflow value (OF), the carry value (CARRY), and the sum value (SUM) stored in each of the first to fourth pixels may be initialized to a logic low level, and not only the sub-exposure counter value indicating how many times the operation of the sub-exposure interval is performed, but also the data stored in the sampling controller 1116 may be initialized (S10). Here, the sub-exposure counter value may be a value stored in the timing generator 140.

[0202] In the sub-exposure interval, the counter may generate and store first count data (LB) by counting pulses of the charge pulse signal (CP) output from the photosensor, and the adder may generate and store an overflow value (OF) indicating whether the first count data (LB) overflows (S20).

[0203] The timing generator 140 may control whether to enable the sampling controller 1116 according to a request from an external device (eg, an image signal processor) ( S30 ).

[0204] If the sampling controller 1116 is disabled (No in S30 ), operations S40 to S70 may not be performed, and operation S80 may be performed.

[0205] If the sampling controller 1116 is enabled (Yes in S30 ), the sampling controller 1116 may determine whether the output signal ( SR_OUT1 ) of the first shift register 240 - 1 is a valid value according to the multiplication result received from the first AND gate 1112 ( S40 ).

[0206] When it is determined that the output signal (SR_OUT1) of the first shift register 240-1 is not a valid value (S40 is "No"), regardless of the XOR result, the sampling controller 1116 may generate a sampling control signal (SAM) corresponding to the value 1, and may send the sampling control signal (SAM) to the second AND gate 1118 to enable the second to fourth light sensors (210-2 to 210-4), so that operation S80 may be performed.

[0207] When it is determined that the output signal (SR_OUT1) of the first shift register 240-1 is a valid value (S40 is "Yes"), the sampling controller 1116 can determine whether the output signals (SR_OUT1~SR_OUT4) of the shift registers (240-1~240-4) are the same as each other according to the result of the XOR operation (S50).

[0208] If the XOR result of at least one bit of the second count data (UB) is "1" (for example, the cumulative sum value of the XOR result is 1 or greater), the sampling controller 1116 can determine that the values ​​of the second count data (UB) of the shift registers (240-1 to 240-4) are different from each other (S50 is No), a sampling control signal (SAM) corresponding to the value 1 can be generated, and the sampling control signal (SAM) can be sent to the second AND gate 1118 to enable the second to fourth light sensors (210-2 to 210-4), so that operation S80 can be performed.

[0209] When the XOR result of the entire second count data (UB) is zero “0” (for example, the cumulative sum value of the XOR result is zero “0”), the sampling controller 1116 can determine whether the values ​​of the second count data (UB) of the shift registers (240-1 to 240-4) are the same as each other (S50 is “Yes”), and a sampling control signal (SAM) corresponding to zero “0” can be generated, and the sampling control signal (SAM) can be sent to the second AND gate 1118, so that down sampling can be performed to deactivate the second to fourth light sensors (210-2 to 210-4) (S60, S70).

[0210] When the operation of the sub-exposure interval is completed (S80), in the pause interval, the operation of the light sensor and the operation of the counter may be stopped (S80), and the adder may sum the second count data (UB) and the overflow value (OF) stored in the shift register, and the second count data corresponding to the summation result may be stored in the shift register (S90, S100).

[0211] The timing generator 140 may determine whether the sub-exposure interval has been performed N times by referring to a sub-exposure counter value indicating the number of times the sub-exposure interval has been performed ( S110 ).

[0212] If the operation of the sub-exposure interval has been performed less than N times (“No” in S110 ), operation S20 may be performed again.

[0213] If the operation of the sub-exposure interval has been performed N times (“Yes” in S110 ), the pixel clustering 1100 may proceed to the readout interval.

[0214] As apparent from the above description, an image sensing device according to some embodiments of the present disclosure can significantly reduce the size of a pixel that generates pixel data by counting the number of pulses corresponding to photo charges.

[0215] In addition, an image sensing device according to some embodiments of the present disclosure may reduce the amount of power to be consumed in a pixel array by performing contrast-based downsampling on a pixel cluster including pixels.

[0216] The embodiments of the present disclosure can provide various effects that can be recognized directly or indirectly.

[0217] Although a number of exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments may be conceived based on what is described and / or shown in this disclosure. In addition, these embodiments may be combined to form additional embodiments.

[0218] CROSS-REFERENCE TO RELATED APPLICATIONS

[0219] This patent application claims priority to and the benefit of Korean Patent Application No. 10-2023-0112956, filed on August 28, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensing device, comprising: a counter that generates first count data by counting pulses generated by detection of the photocharges; a shift register storing second counting data corresponding to high digits of the first counting data; as well as An adder that sums the second count data and an overflow value indicating whether the first count data overflows. 2 . The image sensing device according to claim 1 , further comprising a photosensor that generates a charge pulse signal including the pulse.

3. The image sensing device according to claim 1, wherein: The counter, the shift register, and the adder correspond to one pixel.

4. The image sensing device according to claim 3, in, The pixel operates in different ways according to a reset period, an exposure period, and a readout period, and The reset period is used to initialize the data stored in the pixel. The exposure period is used to generate pixel data including the first count data and the second count data by counting the pulses, and The readout period is used to output the pixel data to the column lines.

5. The image sensing device according to claim 4, wherein: In the reset period, the counter initializes the first count data in response to a counter reset signal of a logic high level.

6. The image sensing device according to claim 5, wherein: The counter includes at least one counter flip-flop having a reset terminal for receiving the counter reset signal.

7. The image sensing device according to claim 6, wherein: The shift register includes at least one register flip-flop, and the at least one register flip-flop does not include the reset terminal.

8. The image sensing device according to claim 7, wherein: The shift register also includes a register switch that selectively connects an output node of the counter flip-flop and an output node of the register flip-flop to each other.

9. The image sensing device according to claim 8, wherein: The register switch transmits an output signal of the counter flip-flop initialized according to the counter reset signal to the register flip-flop.

10. The image sensing device according to claim 4, wherein: The exposure period includes: a sub-exposure interval, the sub-exposure interval being used to generate the first counting data; and A pause interval, where the pause interval is used to generate the second counting data.

11. The image sensing device according to claim 10, wherein: The counter generates the first count data by counting the pulses in the sub-exposure interval; and The adder generates the overflow value according to whether the most significant bit MSB of the first count data is changed from a logic high level to a logic low level in the sub-exposure interval.

12. The image sensing device according to claim 10, wherein: The shift register performs a refresh operation by shifting the second count data via the adder in the sub-exposure interval.

13. The image sensing device according to claim 10, wherein: The counter stops generating the first count data in the pause interval, and The adder sequentially adds the overflow value to bits ranging from a least significant bit LSB to a most significant bit MSB of the second count data in the pause interval.

14. The image sensing device according to claim 4, wherein: In the readout period, the shift register sequentially outputs the second count data, receives the first count data from the counter, and sequentially outputs the first count data.

15. The image sensing device according to claim 1, further comprising a pixel cluster, the pixel cluster comprising a plurality of pixels adjacent to each other, in, Each of the plurality of pixels includes the counter, the shift register, and the adder.

16. The image sensing device according to claim 15, wherein: The pixel clustering further includes a contrast matching unit that performs a down-sampling operation of the pixel clustering according to whether values ​​of the second count data of the plurality of pixels are identical to each other.

17. The image sensing device according to claim 16, wherein: When the values ​​of the second count data of the plurality of pixels are identical to each other, the contrast matching unit deactivates some pixels among the plurality of pixels.

18. An image sensing device, comprising: a counter that generates first count data by counting pulses corresponding to the photocharges; as well as An adder generates an overflow value indicating whether the first count data overflows, and adds the overflow value to second count data corresponding to high bits of the first count data.

19. An image sensing device, comprising: a counter that generates first count data by counting pulses corresponding to the photocharges; as well as a shift register storing second count data corresponding to high digits of the first count data, receiving the first count data after outputting the second count data, and outputting the received first count data, The second count data refers to data added to an overflow value indicating whether the first count data overflows.

20. The image sensing device according to claim 19, wherein: The shift register performs a refresh operation of the second count data when the first count data is generated.

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