Semiconductor structure and method of manufacturing the same, storage system

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof and a storage system, and relates to the technical field of semiconductor chips, and aims to solve the problem of poor performance of capacitors. The semiconductor structure comprises a stack structure, a second conductive layer and a storage functional layer. The stack structure comprises a plurality of first conductive layers and a plurality of isolation layers which are alternately stacked; the second conductive layer penetrates the stack structure; the storage functional layer is located between the first conductive layer and the second conductive layer and surrounds the second conductive layer. The first conductive layer comprises a plate line layer and a conductive pattern, the conductive pattern is located between the plate line layer and the storage functional layer and surrounds the storage functional layer. Through the above arrangement, the storage functional layer is avoided to be directly formed on the side wall of the plate line layer, thereby avoiding the plate line layer to be oxidized into a silicon oxide layer, which is beneficial to improve the problem that the polarization reversal of the storage functional layer is hindered, thereby improving the performance of the capacitor. The above semiconductor structure is applied to a three-dimensional memory to realize the read and write operations of data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a storage system. Background Technology

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling planar memory cells faces challenges due to limitations in process technology and reliability issues.

[0003] To overcome the limitations of 2D or planar memory cells, the industry has developed three-dimensional (3D) memories, which increase storage density by arranging memory cells three-dimensionally on a substrate. Currently, there is still room for optimization of capacitors in 3D memories. Summary of the Invention

[0004] The embodiments of this disclosure provide a semiconductor structure and its fabrication method, as well as a storage system, aimed at solving the problem of poor capacitor performance in three-dimensional memory.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, a semiconductor structure is provided, comprising: a stacked structure, a second conductive layer, and a storage functional layer. The stacked structure includes a plurality of alternating first conductive layers and a plurality of isolation layers; the second conductive layer extends through the stacked structure; the storage functional layer is located between the first conductive layers and the second conductive layer, and surrounds the second conductive layer. The first conductive layer includes a board line layer and a conductive pattern, the conductive pattern being located between the board line layer and the storage functional layer, and surrounding the storage functional layer.

[0007] In this embodiment, the first conductive layer and the isolation layer are alternately stacked, and the conductive patterns in the first conductive layer and the isolation layer are also alternately stacked to electrically isolate adjacent conductive patterns and prevent short circuits between the formed capacitors. Furthermore, since the conductive patterns are located between the board line layer and the storage functional layer, direct contact between the storage functional layer and the board line layer is avoided, thus preventing the storage functional layer from forming directly on the sidewalls of the board line layer. This prevents the portion of the board line layer near the storage functional layer from oxidizing into a silicon oxide layer, which helps to improve the problem of hindered polarization switching of the storage functional layer, thereby improving the performance of the capacitor.

[0008] In some implementations, multiple conductive patterns stacked around the same storage function layer and in a direction perpendicular to the board line layer are disposed on the same layer.

[0009] In some implementations, the isolation layer has a first gap.

[0010] In some implementations, the first gap is located between two adjacent board line layers along a first direction, and the first gap is also located between two adjacent storage function layers; the first direction is perpendicular to the board line layers.

[0011] In some implementations, in adjacent conductive patterns and board lines: a first surface of the conductive pattern is recessed relative to the board line layer, and a portion of the isolation layer is located within a first recessed region enclosed by the first surface, the board line layer, and the storage function layer; and / or, a second surface of the conductive pattern is recessed relative to the board line layer, and a portion of the isolation layer is located within a second recessed region enclosed by the second surface, the board line layer, and the storage function layer; the first surface and the second surface are disposed opposite each other in a direction perpendicular to the board line layer.

[0012] In some implementations, the semiconductor structure further includes an isolation portion that extends through the stacked structure and is connected to the isolation layer.

[0013] In some implementations, the isolation layer and the isolation part are integrally formed.

[0014] In some implementations, the isolation section has a second gap that communicates with at least one of the first gaps.

[0015] In some implementations, the second gap is located between two adjacent storage function layers and extends in a direction perpendicular to the board line layer.

[0016] In some implementations, the semiconductor structure includes a substrate and a dielectric layer, the substrate being located on one side of the stacked structure and the dielectric layer being located on the other side of the stacked structure, the isolation portion also penetrating the dielectric layer and extending into a portion of the substrate.

[0017] In some implementations, the material of the storage functional layer includes ferroelectric materials.

[0018] On the other hand, a method for fabricating a semiconductor structure is provided, comprising:

[0019] A stacked structure is provided, the stacked structure comprising a plurality of alternating line layers and a plurality of sacrificial layers;

[0020] A capacitor hole is formed, which penetrates the stacked structure;

[0021] Multiple conductive patterns, a storage functional layer, and a second conductive layer are formed within the capacitor via. Each conductive pattern and a board line layer constitute a first conductive layer. The storage functional layer is located between the multiple first conductive layers and the second conductive layer, and surrounds the second conductive layer. The multiple conductive patterns are located between the board line layer and the storage functional layer, and surround the storage functional layer.

[0022] The sacrificial layer is replaced with the isolation layer to form a stacked structure.

[0023] In some implementations, forming multiple conductive patterns, a storage functional layer, and a second conductive layer includes:

[0024] A third conductive layer, a storage function layer, and a second conductive layer are sequentially formed inside the capacitor hole.

[0025] Remove the sacrificial layer to form a first filling space;

[0026] The portion of the third conductive layer exposed in the first filling space is removed to form a plurality of the conductive patterns.

[0027] In some implementations, after the third conductive layer, the storage functional layer, and the second conductive layer are sequentially formed within the capacitor hole, and before the sacrificial layer is removed, the fabrication method further includes:

[0028] A second filling space is formed, which extends through the stacked structure;

[0029] The removal of the sacrificial layer includes: removing the sacrificial layer through the second fill space.

[0030] In some implementations, a substrate is provided prior to providing the stacked structure, the substrate being located on one side of the stacked structure;

[0031] After providing the stacked structure and before forming the capacitor via, the fabrication method further includes: providing a dielectric layer located on the side of the stacked structure opposite to the substrate;

[0032] The formation of the second filling space includes: the second filling space also penetrates the dielectric layer and extends into a portion of the substrate.

[0033] In some implementations, replacing the sacrificial layer with the isolation layer includes:

[0034] An insulating material is deposited within the first filling space and between two adjacent conductive patterns to form an insulating layer having a first gap.

[0035] In some implementations, the preparation method further includes forming a second space.

[0036] During the deposition of the isolation material in the first filling space, the isolation material is also deposited in the second filling space to form an isolation section having a second gap communicating with at least one of the first gaps.

[0037] In another aspect, a storage system is provided, comprising: a semiconductor structure, wherein the semiconductor structure is the semiconductor structure described in any of the above embodiments; and a controller coupled to the semiconductor structure.

[0038] It is understood that the beneficial effects of the semiconductor structure, the method for preparing the semiconductor structure, and the storage system provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0040] Figure 1 This is a block diagram of a storage system according to some embodiments;

[0041] Figure 2 A block diagram of a storage system according to some other embodiments;

[0042] Figure 3 This is a structural diagram of a semiconductor structure according to some embodiments;

[0043] Figure 4 These are structural diagrams of semiconductor structures from some embodiments;

[0044] Figure 5 This is a structural diagram of a semiconductor structure according to some embodiments;

[0045] Figure 6 This is a structural diagram of a semiconductor structure according to some embodiments;

[0046] Figure 7 This is a structural diagram of a semiconductor structure according to some embodiments;

[0047] Figure 8 This is a structural diagram of a semiconductor structure according to some embodiments;

[0048] Figure 9 for Figure 8 A cross-sectional view of a semiconductor structure along section line AA;

[0049] Figure 10 for Figure 8 A cross-sectional view of another semiconductor structure along section line AA;

[0050] Figure 11 for Figure 8 A cross-sectional view of another semiconductor structure along the BB section line;

[0051] Figure 12 for Figure 8 A cross-sectional view of another semiconductor structure along the BB section line;

[0052] Figure 13 This is a flowchart of the steps in a method for fabricating a semiconductor structure according to some embodiments;

[0053] Figure 14 This is a structural diagram of a capacitor hole formed in a method for fabricating a semiconductor structure according to some embodiments;

[0054] Figure 15 This is a structural diagram of a semiconductor structure after filling the capacitor hole with material in a method for fabricating a semiconductor structure according to some embodiments;

[0055] Figure 16 This is a structural diagram of the second filling space formed in a method for fabricating a semiconductor structure according to some embodiments;

[0056] Figure 17 This is a structural diagram of the first filling space formed in a method for fabricating a semiconductor structure according to some embodiments;

[0057] Figure 18 This is a structural diagram of a semiconductor structure fabrication method according to some embodiments, after removing a portion of the third conductive layer exposed in the first filling space;

[0058] Figure 19 This is a structural diagram showing the formation of an isolation layer and an isolation portion in a semiconductor structure fabrication method according to some embodiments. Detailed Implementation

[0059] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0060] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0061] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0062] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0063] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0064] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0065] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0066] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation for that particular value, said acceptable range of deviation being determined by one of ordinary skill in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). “Equal” includes absolute equality and approximate equality, wherein an acceptable range of deviation for approximate equality may, for example, be a difference between the two equal values ​​that is less than or equal to 5% of either one.

[0067] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0068] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0069] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0070] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0071] The term "three-dimensional memory" refers to a semiconductor device formed by arrays of memory cell transistors arranged on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0072] Some embodiments of this disclosure provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0073] The electronic device may include a storage system 1000, and may also include at least one of a processor and a cache. The processor is the control center of the electronic device, connecting various parts of the device via various interfaces and lines. It performs various functions and processes data by running or executing software programs and / or modules stored in the storage system 1000, and by accessing data stored in the storage system 1000, thereby providing overall monitoring of the electronic device. Optionally, the processor may include one or more processing units. For example, the processor may include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. Different processing units may be independent devices or integrated into one or more processors. For example, the processor may integrate an application processor and a modem processor, where the application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may also not be integrated into the processor. The application processor may, for example, be a central processing unit (CPU).

[0074] Those skilled in the art will understand that the structure of the above-described electronic device does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than the above-described components, or may combine some of the above-described components, or may be arranged differently from the above-described components.

[0075] The storage system 1000 may be the storage system 1000 provided in any of the following embodiments of this disclosure.

[0076] Figure 1 This is a block diagram of a storage system according to some embodiments. Figure 2 This is a block diagram of a storage system according to some other embodiments.

[0077] Please see Figure 1 and Figure 2 Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller 200 and a semiconductor structure 100, with the controller 200 coupled to the semiconductor structure 100. The semiconductor structure 100 can be a three-dimensional memory, and the controller 200 is used to control the semiconductor structure 100 to store data.

[0078] The following explanation uses semiconductor structure 100 as an example of a three-dimensional memory.

[0079] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0080] In some embodiments, see Figure 1 The storage system 1000 includes a controller 200 and a semiconductor structure 100, and the storage system 1000 can be integrated into a memory card.

[0081] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0082] In other embodiments, see Figure 2 The storage system 1000 includes a controller 200 and multiple semiconductor structures 100, and the storage system 1000 is integrated into a solid state drive (SSD).

[0083] In some embodiments of the storage system 1000, the controller 200 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0084] In other embodiments, the controller 200 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0085] In some embodiments, the controller 200 may be configured to manage data stored in the semiconductor structure 100 and to communicate with external devices (e.g., a host). In some embodiments, the controller 200 may also be configured to control operations of the semiconductor structure 100, such as read, erase, and program operations. In some embodiments, the controller 200 may also be configured to manage various functions relating to data stored or to be stored in the semiconductor structure 100, including at least one of bad block management, garbage collection, logic-to-physical address translation, and wear leveling. In some embodiments, the controller 200 is also configured to process error correction codes relating to data read from or written to the semiconductor structure 100.

[0086] Of course, the controller 200 can also perform any other suitable functions, such as formatting the semiconductor structure 100; for example, the controller 200 can communicate with external devices (e.g., a host) through at least one of various interface protocols.

[0087] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0088] Semiconductor structure 100 can be, for example, ferroelectric random access memory (FeRAM). Ferroelectric random access memory is a high-performance, low-power non-volatile memory that combines the advantages of conventional non-volatile memory (flash memory and EEPROM) and high-speed RAM (SRAM and DRAM). FeRAM outperforms existing memories such as EEPROM and flash memory due to its lower power consumption, faster response speed, and greater endurance to multiple read and write operations.

[0089] The semiconductor structure 100 may include a core region and a connection region, which are adjacent to each other. The connection region includes multiple contact structures, and the core region includes multiple memory cells. The memory cells are electrically connected to the contact structures to achieve functions such as reading. The semiconductor structure 100 provided in this embodiment may, for example, be a semiconductor structure 100 located in the core region.

[0090] Figure 3 This is a structural diagram of a semiconductor structure 100 according to some embodiments. For example... Figure 3 As shown, the semiconductor structure 100 includes a stacked structure 20. The semiconductor structure 100 may also include a substrate 10 and a dielectric layer 30, wherein the substrate 10 may be located on one side of the stacked structure 20 and the dielectric layer 30 may be located on the other side of the stacked structure 20.

[0091] The dielectric layer 30 may be made of insulating materials such as silicon dioxide, silicon nitride, or silicon oxynitride. The dielectric layer 30 and the stacked structure 20 are made of different materials, and under the same process conditions, the etching rate of the dielectric layer 30 differs from that of the stacked structure 20. This allows the dielectric layer 30 to prevent the etching solution from entering the stacked structure 20, protecting the stacked structure 20 from etching during subsequent removal of structures located on the side of the stacked structure 201 facing away from the substrate 10.

[0092] The stacked structure 20 includes an alternately stacked first conductive layer 22 and an insulating layer 21. The insulating layer 21 may be made of an insulating material, which may include one or more combinations of insulating materials such as SiO2 (silicon dioxide), Al2O3 (alumina), HfO2 (hafnium dioxide), ZrO2 (zirconia), TiO2 (titanium dioxide), Y2O3 (yttrium oxide), and Si3N4 (silicon nitride).

[0093] The semiconductor structure 100 further includes a second conductive layer 42 and a storage functional layer 41 penetrating the stacked structure 20. The storage functional layer 41 is located between and surrounds the first conductive layer 22 and the second conductive layer 42. Exemplarily, the storage functional layer 41 may be generally cylindrical. In some embodiments, the second conductive layer 42 may be generally cylindrical, and correspondingly, the semiconductor structure 100 may further include a support pillar 43 penetrating the stacked structure 20 and located within the cylindrical structure enclosed by the second conductive layer 42. The material of the support pillar 43 may include an insulating material or a conductive material.

[0094] Of course, in some other embodiments, the second conductive layer 42 may also be in the form of a columnar structure, and the second conductive layer 42 can serve as a support. Accordingly, the support column 43 may be omitted from the semiconductor structure 100.

[0095] With the above configuration, at least a portion of the first conductive layer 22 surrounding the outer surface of the storage functional layer 41 constitutes the first capacitor electrode, the second conductive layer 42 is the second capacitor electrode, and the storage functional layer 41 is the capacitor dielectric layer, so that the first conductive layer 22, the second conductive layer 42, and the storage functional layer 41 constitute multiple stacked capacitors C1. The multiple stacked capacitors C1 share the same second capacitor electrode and the same storage functional layer 41. (Continuing to refer to...) Figure 3 Multiple capacitors C1 stacked along a direction perpendicular to the substrate 10 can be referred to as capacitor banks C2. The semiconductor structure 100 may include multiple capacitor banks C2 extending through the stacked structure 20. In some embodiments, the multiple capacitor banks C2 are arranged in a multi-row, multi-column configuration.

[0096] The material of the storage functional layer 41 may include ferroelectric materials. For example, the storage functional layer 41 may be a ferroelectric material such as ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, Y-doped HfO2, or other materials doped with other elements based on such materials, or any combination thereof. When the material of the storage functional layer 41 includes a ferroelectric material, the capacitor C1 is a ferroelectric capacitor C1, and correspondingly, the three-dimensional memory is a ferroelectric memory.

[0097] It is worth noting that the semiconductor structure 100 may also include a transistor, which is electrically connected to the capacitor C1. The transistor may be located on the side of the stacked structure 20 away from the substrate 10, or it may be located on the side of the stacked structure 20 closer to the transistor. This application embodiment does not limit the number of transistors electrically connected to the capacitor bank C2.

[0098] For example, a transistor can be electrically connected to a capacitor bank C2, such that multiple capacitors C1 in the capacitor bank C2 and the transistor constitute a memory cell. This memory cell has a 1TnC (1-transistor-n-capacitor) structure, meaning that one memory cell includes one transistor and n capacitors C1. Accordingly, in some embodiments, multiple memory cells can also be arranged in a multi-row, multi-column configuration.

[0099] Based on the above structure, when the ferroelectric memory is working, the first conductive layer 22 can receive line control signals. The line control signals are connected to the corresponding capacitor C1 through the first conductive layer 22, causing the storage function layer 41 of the selected capacitor C1 to be positively or negatively polarized, so that different logic information can be written into the selected capacitor C1. For example, when the storage function layer 41 is positively polarized, the logic signal "0" is written; and when the storage function layer 41 is negatively polarized, the logic signal "1" is written.

[0100] Figure 4 This is a structural diagram of a semiconductor structure 100' according to some embodiments. For example... Figure 4 As shown, in some embodiments, the first conductive layer 22' is a board-line layer 221', and the board-line layer 221' surrounds the storage functional layer 41'. With the above arrangement, at least a portion of the board-line layer 221' surrounding the storage functional layer 41' constitutes the first capacitor plate.

[0101] In some embodiments, the process of fabricating the semiconductor structure 100' includes: forming a capacitor hole 40' through the plate line layer 221'; and then sequentially depositing a ferroelectric material and a conductive material within the capacitor hole 40' to form a storage functional layer 41' and a second conductive layer 42'.

[0102] However, the material of the plate line layer 221' typically includes heavily doped polycrystalline silicon. During the deposition of ferroelectric material within the capacitor via 40' to form the storage functional layer 41' (the storage functional layer 41' may include, for example, a hafnium-based ferroelectric thin film), the oxidant used in the fabrication process typically oxidizes the heavily doped polycrystalline silicon, causing a portion of the plate line layer 221' near the storage functional layer 41' to oxidize into a silicon oxide layer. This silicon oxide layer is located between the plate line layer 221' and the storage functional layer 41', and its dielectric constant is much lower than that of the storage functional layer 41', resulting in the actual voltage division of the storage functional layer 41' being much lower than the applied voltage. Simultaneously, the defect states in this silicon oxide layer trap electrons, exerting a depolarizing effect and hindering the polarization reversal of the ferroelectric domains, i.e., preventing the storage functional layer 41' from becoming positively or negatively polarized, thus leading to poor capacitor performance.

[0103] In view of this, refer to Figure 3In this embodiment of the application, the first conductive layer 22 includes a board line layer 221 and a conductive pattern 222. The conductive pattern 222 is located between the board line layer 221 and the storage function layer 41, and surrounds the storage function layer 41.

[0104] For example, the conductive pattern 222 can be generally tubular in shape, with its outer peripheral surface in contact with the board line layer 221 and its inner peripheral surface in contact with the storage function layer 41. The material of the conductive pattern 222 can include metals. For example, the material of the conductive pattern 222 can include one or more combinations of conductive materials such as Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver). Of course, in some other embodiments, the material of the conductive pattern 222 can also be other conductive materials, and this application embodiment does not limit this.

[0105] In some embodiments, the conductive pattern 222 is made of the same material as the second conductive layer 42. For example, the materials of the conductive pattern 222 and the second conductive layer 42 may include TiN (titanium nitride). This configuration helps to ensure the conductivity of the conductive pattern 222 and the second conductive layer 42, thereby ensuring the performance of the capacitor bank C2.

[0106] For ease of description, the direction perpendicular to the board line layer 221 will be referred to as the first direction X, and the direction parallel to the board line layer 221 will be referred to as the second direction Y and the third direction Z, with the third direction Z being perpendicular to the second direction Y.

[0107] Furthermore, since the first conductive layer 22 and the insulating layer 21 are alternately stacked, and the first conductive layer 22 includes a conductive pattern 222, the conductive pattern 222 and the insulating layer 21 are alternately stacked. Through the above arrangement, two adjacent conductive patterns 222 in the first direction X are electrically isolated, thereby preventing a short circuit between the first capacitor plates of two adjacent capacitors C1.

[0108] With the above configuration, during the fabrication of the semiconductor structure 100, a capacitor hole 40 penetrating the plate line layer 221 can be formed. A conductive pattern 222 is then formed within the capacitor hole 40, followed by the formation of a storage functional layer 41 within the capacitor hole 40 with the conductive pattern 222. A second conductive layer 42 is then formed within the capacitor hole 40 with the conductive pattern 222 and the storage functional layer 41. Because the conductive pattern 222 is located between the plate line layer 221 and the storage functional layer 41, direct contact between the storage functional layer 41 and the plate line layer 221 is avoided. This prevents the storage functional layer 41 from being directly formed on the sidewall of the plate line layer 221, thus preventing the portion of the plate line layer 221 near the storage functional layer 41 from oxidizing into a silicon oxide layer. This helps to improve the problem of hindered polarization reversal of the storage functional layer 41, thereby improving the performance of the capacitor C1.

[0109] As described in the above embodiments, during the fabrication of the semiconductor structure 100, multiple capacitor holes 40 can be fabricated, and capacitor banks C2 can be formed within the corresponding capacitor holes 40. Furthermore, multiple conductive patterns 222 stacked around the same storage functional layer 41 and along a direction perpendicular to the board line layer 221 can be disposed in the same layer. Here, "distributed in the same layer" can be understood as a layer structure formed using the same film deposition process, and the layer structure being made of the same material. Specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0110] For example, in the same capacitor bank C2, since multiple capacitors C1 are stacked along the first direction X, multiple conductive patterns 222 are also stacked along the first direction X; and since multiple capacitors C1 share the same storage function layer 41, multiple conductive patterns 222 surround the same storage function layer 41. With the above arrangement, multiple capacitors C1 in the same capacitor bank C2 are fabricated together, which helps to simplify the fabrication process of capacitors C1 and improve the fabrication efficiency of capacitors C1.

[0111] like Figure 3 As shown, in some embodiments, the isolation layer 21 can be a solid structure. Of course, in some other embodiments, the isolation layer 21 may also include a hollow structure.

[0112] Figure 5 This is a structural diagram of a semiconductor structure 100 according to some embodiments. For example... Figure 5As shown, the isolation layer 21 may have a first gap 211. For example, the isolation layer 21 may enclose the first gap 211. In the stacked structure 20, at least one of the multiple isolation layers 21 may have a first gap 211. Further, an isolation layer 21 may include one first gap 211. Alternatively, an isolation layer 21 may also include multiple spaced-apart first gaps 211, which are not connected to each other.

[0113] During the preparation of the isolation layer 21, a deposition process can be used to deposit material within the corresponding filling space, with the deposited material initially covering the sidewalls of the filling space. However, since the deposition process cannot achieve uniform coverage, the thickness of the material deposited on the sidewalls of the filling space varies. As more material is deposited into the filling space, the thicker deposited material closes first, resulting in the formation of a first gap 211 containing air.

[0114] It is understood that the first gap 211 contains air, and the dielectric constant of air is approximately 1. Compared to the solid structure of the isolation layer 21, the dielectric constant of the isolation layer 21 with the first gap 211 is reduced, which is beneficial to further improve the electrical isolation effect between two adjacent board line layers 221, thereby reducing the parasitic capacitance between two adjacent board line layers 221.

[0115] Continue to refer to Figure 5 The first gap 211 can be located between two adjacent board line layers 221 along the first direction X, and can also be located between two adjacent storage function layers 41. For example, the first gap 211 is located inside the isolation layer 21, and is spaced apart from both the board line layer 221 and the storage function layer 41. Here, "spaced apart" means that the first gap 211 does not contact the board line layer 221, and does not contact the storage function layer 41. This arrangement also helps to improve the electrical isolation effect between two adjacent capacitor banks C2, thereby reducing the parasitic capacitance between the two adjacent capacitor banks C2.

[0116] Continue to refer to Figure 5The conductive pattern 222 may include a first surface 222a and a second surface 222b disposed opposite to each other along the first direction X. Here, "disposed opposite to each other along the first direction X" should be interpreted in the broadest sense, meaning that the orthographic projection of the first surface 222a onto the conductive pattern 222 caused by light rays parallel to this direction overlaps with the orthographic projection of the second surface 222b onto the conductive pattern 222 caused by light rays in this direction. This overlap can be, for example, complete or partial. The first surface 222a may be farther from the substrate 10 than the second surface 222b; for example, the first surface 222a may be... Figure 5 The upper surface of the conductive pattern 222, and the second surface 222b can be Figure 5 The lower surface of the conductive pattern 222 in the middle.

[0117] In some embodiments, in adjacent conductive patterns 222 and line layers 221: the first surface 222a of the conductive pattern 222 may be recessed relative to the line layer 221, and a portion of the isolation layer 21 may be located within the first recessed region enclosed by the first surface 222a, the line layer 221, and the storage functional layer 41. For example, in the first recessed region M1 enclosed by the first surface 222a, the line layer 221, and the storage functional layer 41, a portion of the isolation layer 21 is located within the first recessed region M1, that is, a portion of the isolation layer 21 extends between the storage functional layer 41 and the line layer 221. This configuration helps to further improve the electrical isolation effect between two adjacent capacitor banks C2, thereby reducing the parasitic capacitance between the two adjacent capacitor banks C2.

[0118] Similarly, in some embodiments, the second surface 222b of the conductive pattern 222 may be recessed relative to the board line layer 221, and a portion of the isolation layer 21 may be located within the second recessed region enclosed by the second surface 222b, the board line layer 221, and the storage function layer 41. For example, in the second recessed region M2 enclosed by the second surface 222b, the board line layer 221, and the storage function layer 41, a portion of the isolation layer 21 is located within the second recessed region M2, that is, a portion of the isolation layer 21 extends between the storage function layer 41 and the board line layer 221. This arrangement helps to further improve the electrical isolation effect between two adjacent capacitor banks C2, thereby reducing the parasitic capacitance between the two adjacent capacitor banks C2.

[0119] Figure 6 This is a structural diagram of a semiconductor structure 100 according to some embodiments. (Refer to...) Figure 6The semiconductor structure 100 may further include an isolation portion 50, which may penetrate the stacked structure 20 and be connected to the isolation layer 21. For example, the isolation portion 50 may be located between two adjacent capacitor banks C2. This arrangement helps to further improve the electrical isolation effect between two adjacent capacitor banks C2, thereby reducing the parasitic capacitance between them. Simultaneously, the isolation portion 50 can also provide mechanical support and / or load balancing.

[0120] In some examples, the isolation portion 50 can be a columnar structure. Alternatively, in other examples, the isolation portion 50 can also be an isolation sidewall. Of course, the shape of the isolation portion 50 is not limited to the above-described structure, and the embodiments of this application do not limit the shape of the isolation portion 50. The number of isolation portions 50 can be one or more, and the present application does not limit the number of isolation portions 50.

[0121] In embodiments where the semiconductor structure 100 also includes a substrate 10 and a dielectric layer 30, the isolation portion 50 may also penetrate the dielectric layer 30 and extend into a portion of the substrate 10.

[0122] In some embodiments, the isolation layer 21 and the isolation portion 50 can be integrally formed. Here, "integratedly formed" means that during the fabrication of the semiconductor structure 100, the same material can be used to simultaneously fabricate the isolation layer 21 and the isolation portion 50, and the isolation portion 50 and the isolation layer 21 can be integrated into a single unit. For example, a filling space can be formed first, and then the same material can be deposited within the filling space using a thin film deposition process such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), or ALD (Atomic Layer Deposition), thereby simultaneously forming the isolation layer 21 and the isolation portion 50.

[0123] The above-described configuration helps to further reduce the process difficulty of fabricating the isolation layer 21 and the isolation portion 50, and improves the fabrication efficiency of the semiconductor structure 100. At the same time, since the isolation layer 21 and the isolation portion 50 are made of the same material, it helps to reduce the fabrication cost of the semiconductor structure 100.

[0124] like Figure 6 As shown, in some embodiments, the isolation portion 50 can be a solid structure. Of course, in some other embodiments, the isolation portion 50 may also include a hollow structure.

[0125] Figure 7 This is a structural diagram of a semiconductor structure 100 according to some embodiments; Figure 8 This is a structural diagram of a semiconductor structure 100 according to some embodiments. For example... Figure 7 and Figure 8 As shown, the isolation portion 50 may have a second gap 51, which may communicate with at least one first gap 211. Exemplarily, the isolation portion 50 may enclose the second gap 51. In embodiments where each isolation layer 21 has a first gap 211, each first gap 211 may communicate with the second gap 51.

[0126] During the preparation of the isolation section 50, a deposition process can be used to deposit material within the corresponding filling space, with the deposited material initially covering the sidewalls of the filling space. However, since the deposition process cannot achieve uniform coverage, the thickness of the material deposited on the sidewalls of the filling space varies. During further material deposition into the filling space, the thicker deposited material closes first, resulting in the formation of a second gap 51 containing air.

[0127] It is understood that the first gap 211 includes air, and the dielectric constant of air is approximately 1. Compared to the solid structure of the isolation portion 50, the dielectric constant of the isolation portion 50 with the second gap 51 is reduced, which is beneficial to further improve the electrical isolation effect between two adjacent capacitor banks C2, thereby reducing the parasitic capacitance between the two adjacent capacitor banks C2.

[0128] Reference Figure 7 The second gap 51 can be located between two adjacent storage function layers 41 and extends along the first direction X. For example, since the isolation layer 21 penetrates the board line layer 221 and the isolation layer 21, the second gap 51 is also located within the board line layer 221, so that the board line layer 221 is arranged around the second gap 51; the second gap 51 is also connected to the first gap 211, so that the isolation layer 21 is also arranged around the second gap 51. Simultaneously, the second gap 51 is also spaced apart from the board line layer 221. Here, "spaced apart" means that the second gap 51 does not contact the board line layer 221. Through the above arrangement, it is also beneficial to further improve the electrical isolation effect between two adjacent capacitor banks C2, thereby further reducing the parasitic capacitance between the two adjacent capacitor banks C2.

[0129] The above Figure 6 , Figure 7 as well as Figure 8 This illustrates embodiments of different structures formed by the combination of the isolation section 50 and the isolation layer 21 provided in this application. For example, Figure 6 The isolation layer 21 is a solid structure, and the isolation part 50 is also a solid structure; Figure 7 The isolation layer 21 is a solid structure, and the isolation part 50 is a hollow structure; Figure 8 The isolation layer 21 is a hollow structure, and the isolation part 50 is also a hollow structure.

[0130] When both the isolation layer 21 and the isolation pillar are solid structures, it is beneficial to improve the stability of the semiconductor structure 100; when both the isolation layer 21 and the isolation pillar are hollow structures, it is beneficial to reduce parasitic capacitance and improve the performance of the semiconductor structure 100. In the application of the semiconductor structure 100, the appropriate combination structure of the isolation layer 21 and the isolation portion 50 can be selected according to actual needs.

[0131] The following is based on only... Figure 8 The semiconductor structure 100 shown is used as an example for illustration. Among them, Figure 9 for Figure 8 A cross-sectional view of a semiconductor structure 100 along section line AA; Figure 10 for Figure 8 A cross-sectional view along section line AA of another semiconductor structure 100. It is worth noting that... Figure 9 and Figure 10 The blank areas in the diagram indicate that the interior of the isolation section 50 is not filled.

[0132] Reference Figure 9 In some embodiments, the isolation portion 50 may be generally columnar. For example, the isolation portion 50 may be generally cylindrical, and the second gap 51 within the isolation portion 50 may also be generally columnar.

[0133] Reference Figure 10 In some embodiments, the isolation portion 50 may be generally a sidewall structure, and the second gap 51 within the isolation portion 50 may also be generally in the shape of a sidewall. Of course, the shape of the second gap 51 in the embodiments of this application is not limited to the above two types, and this application does not impose specific limitations on the shape of the second gap 51 in the isolation portion 50.

[0134] Figure 11 for Figure 8 A cross-sectional view of another semiconductor structure 100 along the BB section line; Figure 12 for Figure 8 Another semiconductor structure 100 is shown in a cross-sectional view along the BB section line. It is worth noting that when the isolation portion is approximately cylindrical, Figure 11 and Figure 12 The area within the dashed-dot frame can be the second filling space 62 (the second filling space 62 is a hole) where the isolation part is located. An isolation part with a second gap 51 needs to be formed within the second filling space 62. Figure 11 and Figure 12 The area within the dashed box can be considered the second gap 51. It is worth noting that... Figure 11 and Figure 12 The blank areas indicate that the interior of the isolation layer 21 and the isolation section 50 is not filled.

[0135] In some embodiments, such as Figure 11 As shown, the first gap 211 is located between two adjacent storage functional layers 41 arranged along the second direction Y; the distance between two adjacent storage functional layers 41 arranged along the third direction Z is smaller, so that there may be no first gap 211 between two adjacent storage functional layers 41 arranged along the third direction Z. With the above arrangement, a portion of the isolation layer 21 surrounds the storage functional layer 41, and the isolation layers 21 surrounding different storage functional layers 41 can contact each other.

[0136] In some other embodiments, such as Figure 12 As shown, the first gap 211 can be located between two adjacent storage functional layers 41 arranged along the second direction Y, and the first gap 211 can also be located between two adjacent storage functional layers 41 arranged along the third direction Z. With the above arrangement, a portion of the isolation layer 21 surrounds the storage functional layer 41, and is spaced apart around the isolation layers 21 outside different storage functional layers 41.

[0137] As described in the above embodiments, the isolation portion 50 and the isolation layer 21 can be integrally formed. During the preparation of the isolation portion 50 and the isolation layer 21, material can be deposited in the filling space, and the deposited material first covers the sidewalls of the filling space. At the same time, since the deposition process may not achieve uniform coverage, the thickness of the material deposited on the sidewalls of the filling space is different (for example, during the deposition process, the material on the side away from the substrate 10 may be thicker, that is, the material at the top in the figure is thicker). During the further deposition of material into the filling space, the thicker material will close first (for example, the material at the top in the figure closes first), resulting in the formation of a connected first gap 211 and a second gap 51.

[0138] When the filling space forming the isolation portion 50 is narrower than the filling space forming the isolation layer 21: during the process of depositing material into the filling space, the narrower filling space may be filled first, resulting in the isolation portion 50 forming a solid structure and the isolation layer 21 forming a hollow structure, that is, the isolation portion 50 has no gaps, while the isolation layer 21 has a first gap 211.

[0139] Conversely, when the filling space forming the isolation layer 21 is narrower than the filling space forming the isolation portion 50, the narrower filling space may be filled first during the deposition of material into the filling space, resulting in the isolation layer 21 forming a solid structure and the isolation portion 50 forming a hollow structure. That is, the isolation layer 21 has no gaps, while the isolation portion 50 has a second gap 51.

[0140] This application also provides a method for preparing a semiconductor structure 100, which is used to prepare the semiconductor structure 100 in any of the above embodiments. Figure 13This is a flowchart illustrating the steps of a method for fabricating a semiconductor structure 100 according to some embodiments. The following is a description of the steps described in conjunction with the accompanying drawings. Figure 13 The preparation method includes steps S1-S4.

[0141] S1. Provide a stacked structure, which includes multiple line layers and multiple sacrificial layers arranged in alternating layers.

[0142] Figure 14 This is a structural diagram of the capacitor hole 40 formed in the fabrication method of the semiconductor structure 100 according to some embodiments. Referring below... Figure 14 The steps for providing the stacked structure 201 are explained.

[0143] It is worth noting that, prior to forming the stacked structure 201, the method may further include providing a substrate 10, which is located on one side of the stacked structure 201. (Refer to...) Figure 14 The substrate 10 may, for example, comprise a composite substrate 10, the material of which may include a combination of silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), and any other suitable materials. Of course, in some embodiments, the substrate 10 may also comprise a single-layer structure, which is not limited to this embodiment.

[0144] Reference Figure 14 The step of forming the stacked structure 201 includes: alternately forming a plurality of line-fed layers 221 and a plurality of sacrificial layers 223. The sacrificial layers 223 and the line-fed layers 221 are made of two different materials, and under the same process conditions, the etching rate of the sacrificial layers 223 is different from that of the line-fed layers 221. In some examples, the sacrificial layer 223 comprises a nitride (e.g., silicon nitride), and the line-fed layers 221 comprise heavily doped polysilicon.

[0145] The number of sacrificial layers 223 and the number of board line layers 221 can be equal. It is understood that the number of sacrificial layers 223 and board line layers 221 can be adjusted according to the number of capacitors in a capacitor bank. For example, for a capacitor bank containing three capacitors, three sacrificial layers 223 and three board line layers 221 can be stacked.

[0146] After providing the stacked structure 201 and before forming the capacitor via 40, the fabrication method further includes providing a dielectric layer 30, which is located on the side of the stacked structure 201 facing away from the substrate 10. The dielectric layer 30 may be, for example, an etch stop layer, which is used to protect the stacked structure 201 from being etched during subsequent removal of the structure on the stacked structure 201.

[0147] In this embodiment of the application, after the formation of the stacked structure 201, the fabrication process of the semiconductor structure 100 further includes step S2.

[0148] S2. A capacitor hole is formed, which penetrates the stacked structure.

[0149] Continue to refer to Figure 14 In embodiments where the semiconductor structure also includes a dielectric layer 30 and a substrate 10, the capacitor hole 40 also penetrates the dielectric layer 30 and extends into the interior of the substrate 10.

[0150] The number of capacitor holes 40 can be multiple. In some embodiments, the multiple capacitor holes 40 can be arranged in an array.

[0151] In this embodiment of the application, after the capacitor hole 40 is formed, the fabrication process of the semiconductor structure 100 further includes step S3.

[0152] S3. Multiple conductive patterns, a storage function layer, and a second conductive layer are formed within the capacitor via. A conductive pattern and a board line layer constitute a first conductive layer. The storage function layer is located between the multiple first conductive layers and the second conductive layer and surrounds the second conductive layer. Multiple conductive patterns are located between the board line layer and the storage function layer and surround the storage function layer.

[0153] Figure 15 This is a structural diagram showing the filling of material within the capacitor hole 40 in a method for fabricating a semiconductor structure 100 according to some embodiments. (Refer to...) Figure 15 In this embodiment of the application, the step of forming multiple conductive patterns 222, storage function layer 41 and second conductive layer 42 may include: forming a third conductive layer 44, storage function layer 41 and second conductive layer 42 sequentially in capacitor hole 40.

[0154] For example, the third conductive layer 44 can cover the sidewalls and bottom wall of the capacitor hole 40 to form a groove, the storage function layer 41 can cover the sidewalls and bottom wall of the groove formed by the third conductive layer 44, and the second conductive layer 42 can cover the sidewalls and bottom wall of the groove formed by the storage function layer 41. In the above steps, thin film deposition processes such as CVD, PVD, or ALD can also be used to form the third conductive layer 44, the storage function layer 41, and the second conductive layer 42.

[0155] As described in the above embodiments, the third conductive layer 44 and the second conductive layer 42 can be made of the same material, such as a conductive material like a metal. In some preferred embodiments, the materials of the third conductive layer 44 and the second conductive layer 42 include TiN (titanium nitride).

[0156] Furthermore, a support pillar 43 may be formed within the groove enclosed by the second conductive layer 42, wherein the material of the support pillar 43 may include an insulating material or a conductive material. In some other examples, the second conductive layer 42 may also fill the groove enclosed by the storage functional layer 41. Based on the above structure, the support pillar 43 may be omitted in the semiconductor structure 100.

[0157] Figure 16 This is a structural diagram of the second filling space 62 formed in the fabrication method of the semiconductor structure 100 according to some embodiments. Figure 17 This is a structural diagram of the first filling space 61 formed in a method for fabricating a semiconductor structure 100 according to some embodiments.

[0158] Combination Figure 16 and Figure 17 As shown in the embodiment of this application, the steps of forming multiple conductive patterns 222, storage function layer 41 and second conductive layer 42 may further include: removing sacrificial layer 223 to form first filling space 61.

[0159] For example, after removing the sacrificial layer 223, the original location of the sacrificial layer 223 becomes the first filling space 61. Since the sacrificial layer 223 and the board line layer 221 are alternately stacked, to facilitate the removal of the sacrificial layer 223 and achieve side cutouts in the stacked structure 201, a second filling space 62 penetrating the stacked structure 201 can be formed before removing the sacrificial layer 223, so that the sacrificial layer 223 can be exposed.

[0160] Reference Figure 16 After the third conductive layer 44, the storage function layer 41 and the first conductive layer 22 are sequentially formed in the capacitor hole 40, and before the sacrificial layer 223 is removed, the method for fabricating the semiconductor structure 100 further includes: forming a second filling space 62, the second filling space 62 penetrating the stacked structure 201.

[0161] In some embodiments, the second filling space 62 can be a via. It is understood that the semiconductor structure 100 may also include a plurality of virtual capacitor banks penetrating the stacked structure 201, and the virtual capacitor banks may have the same structure as capacitor bank C2. It should be noted that the virtual capacitor banks may not actually be used as storage cells, but rather serve to provide mechanical support and / or load balancing for the three-dimensional memory. During the fabrication of the virtual capacitor banks, vias penetrating the stacked structure 201 can be formed, thereby forming virtual capacitor banks within the vias. These vias may include the second filling space 62.

[0162] For example, a portion of the stacked structure 201 can be removed to form a through-hole penetrating the stacked structure 201. The step of forming the second filling space 62 further includes: the second filling space 62 also penetrates the dielectric layer 30 and extends into a portion of the substrate 10. Exemplarily, the through-hole can also penetrate the dielectric layer 30 and a portion of the substrate 10. This application does not specifically limit the number or location of the through-holes.

[0163] In some other embodiments, the second filling space 62 may also be a groove. It is understood that the semiconductor structure 100 may also include a slit penetrating the stacked structure 201. During the fabrication of the slit, a groove penetrating the stacked structure 201 may be formed, thereby forming a slit within the via. This groove may include the second filling space 62.

[0164] For example, a portion of the stacked structure 201 can be removed to form a groove penetrating the stacked structure 201. The step of forming the second filling space 62 further includes: the second filling space 62 also penetrates the dielectric layer 30 and extends into a portion of the substrate 10. Exemplarily, the orthographic projection of the groove onto the substrate 10 can be approximately rectangular, and the groove can also penetrate the dielectric layer 30 and a portion of the substrate 10. This application does not specifically limit the number or location of the grooves.

[0165] Reference Figure 16 and 17 Removing the sacrificial layer 223 may include removing it through the second fill space 62. For example, since the sacrificial layer 223 is exposed in the second fill space 62, an etchant may be added to the second fill space 62, and a wet etching process may be used to remove the sacrificial layer 223. In some examples, by selecting an etchant corresponding to the material of the sacrificial layer 223, the etching rate of the sacrificial layer 223 is greater than the etching rate of the board line layer 221 under the etching conditions created by the etchant.

[0166] For example, the sacrificial layer 223 can be removed using an isotropic etching process. Isotropic etching, which is etching that is equal in all directions, means that the orientation of the substrate does not affect the removal of material by the etchant. Removing the sacrificial layer 223 using an isotropic etching process can improve the fabrication efficiency of the semiconductor structure 100.

[0167] Figure 18 This is a structural diagram showing the semiconductor structure 100 after removing a portion of the third conductive layer 44 exposed in the first filling space 61, according to a method for fabricating the semiconductor structure 100 according to some embodiments. Figure 18 As shown in the embodiment of this application, the steps of forming multiple conductive patterns 222, storage functional layer 41 and second conductive layer 42 may further include: removing a portion of the third conductive layer 44 exposed to the first filling space 61 to form multiple conductive patterns 222.

[0168] For example, after removing the sacrificial layer 223, the space where the original sacrificial layer 223 was located becomes the first filling space 61. Since the sacrificial layer 223 is removed through the second filling space 62, the second filling space 62 is connected to the first filling space 61, and part of the third conductive layer 44 is exposed in the first filling space 61, so that the third conductive layer 44 can be removed through the first filling space 61 and the second filling space 62.

[0169] Continue to refer to Figure 18 When removing the portion of the third conductive layer 44 exposed to the first filling space 61, a portion of the third conductive layer 44 located between the board line layer 221 and the storage function layer 41 is also removed. For example, when removing the portion of the third conductive layer 44 exposed to the first filling space 61, etching can continue towards the side away from the substrate 10. With the above arrangement, in the adjacent conductive pattern 222 and board line layer 221, the first surface 222a of the conductive pattern 222 can be recessed relative to the board line layer 221, and the first surface 222a, the board line layer 221, and the storage function layer 41 can enclose a first recessed region M1. For example, when removing the portion of the third conductive layer 44 exposed to the first filling space 61, etching can continue towards the side closer to the substrate 10. With the above configuration, the second surface 222b of the conductive pattern 222 can be recessed relative to the board line layer 221 in the adjacent conductive pattern 222 and board line layer 221, and the second surface 222b, board line layer 221 and storage function layer 41 can form a second recessed area M2.

[0170] In this embodiment of the application, after the conductive pattern 222 is formed, the fabrication process of the semiconductor structure 100 further includes step S4.

[0171] S4. Replace the sacrificial layer with an isolation layer to form a stacked structure.

[0172] Figure 19 This is a structural diagram showing the formation of the isolation layer 21 and the isolation portion 50 in a method for fabricating a semiconductor structure 100 according to some embodiments. (Refer to...) Figure 19 and combined Figure 16 The step of replacing the sacrificial layer 223 with the isolation layer 21 may include: depositing an isolation material in the first filling space 61 and between two adjacent conductive patterns 222 to form the isolation layer 21, wherein the isolation layer 21 has a first gap 211.

[0173] For example, a deposition process can be used to deposit an insulating material within the first filling space 61 and between two adjacent conductive patterns 222, so that the insulating material covers the surface of the board line layer 221, the surface of the conductive patterns 222, and the surface of the storage functional layer 41. Furthermore, a portion of the insulating material covering the surface of the conductive patterns 222 is also located between the board line layer 221 and the storage functional layer 41. The deposited insulating layer 21 encloses a first gap 211, wherein the specific shape and position of the first gap 211 can be as described in the above embodiments, and will not be repeated here.

[0174] Furthermore, an isolation layer 21 is formed within the first filling space 61, which means that the original sacrificial layer 223 is replaced by the isolation layer 21. The isolation layer 21 and the board line layer 221 are alternately stacked so that multiple isolation layers 21 and multiple board line layers 221 together constitute a stacked structure 20.

[0175] In the case where the preparation method further includes forming a second filling space 62: during the process of depositing isolation material in the first filling space 61, isolation material is also deposited in the second filling space 62 to form an isolation portion 50, the isolation portion 50 having a second gap 51, the second gap 51 communicating with at least one first gap 211.

[0176] like Figure 19 As shown, the first filling space 61 and the second filling space 62 are connected. While the isolation material is deposited in the first filling space 61, the second filling space 62 is also deposited with isolation material. The isolation material in the first filling space 61 forms the isolation layer 21, and the isolation material in the second filling space 62 forms the isolation section 50.

[0177] Through the above steps, the isolation layer 21 and the isolation portion 50 can be brought into contact and integrated, which is beneficial to improving the fabrication efficiency of the semiconductor structure 100.

[0178] Furthermore, during the deposition of the isolation material within the second filling space 62, the isolation material is also deposited on the surface of the plate line layer 221, the surface of the dielectric layer 30, and the surface of the substrate 10, so that the isolation material can surround the second gap 51. As shown in the above embodiment, the second gap 51 communicates with at least one first gap 211.

[0179] When the second filling space 62 is narrower than the first filling space 61: during the process of depositing material into the filling space, the second filling space 62 may be filled first, which will result in the isolation part 50 being formed as a solid structure and the isolation layer 21 being formed as a hollow structure. That is, the isolation part 50 does not have gaps, while the isolation layer 21 has a first gap 211.

[0180] Conversely, when the first filling space 61 is narrower than the second filling space 62, during the process of depositing material into the filling space, the first filling space 61 may be filled first, resulting in the isolation layer 21 forming a solid structure and the isolation part 50 forming a hollow structure. That is, the isolation layer 21 has no gaps, while the isolation part 50 has a second gap 51.

[0181] As described in the above embodiments, the semiconductor structure 100 can be a semiconductor structure 100 located in the core region. The semiconductor structure 100 located in the connection region also includes a stacked structure with alternating plate line layers and sacrificial layers. In the process of replacing the sacrificial layer 223 in the stacked structure 201 in the core region with the isolation layer 21, it is not necessary to replace the sacrificial layer in the stacked structure in the connection region. Since the connection region includes a contact structure, the contact structure can contact the plate line layer in the connection region, so that the contact structure is electrically connected to the corresponding capacitor through the plate line layer. Because the sacrificial layer in the stacked structure in the connection region does not need to be replaced, it is beneficial to reduce the fabrication process of the semiconductor structure located in the connection region.

[0182] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: The stacked structure includes multiple first conductive layers and multiple insulating layers arranged in alternating layers; A second conductive layer extends through the stacked structure; A storage function layer is located between the first conductive layer and the second conductive layer, and surrounds the second conductive layer; The first conductive layer includes a board line layer and a conductive pattern, wherein the conductive pattern is located between the board line layer and the storage function layer, and surrounds the storage function layer.

2. The semiconductor structure according to claim 1, characterized in that, Multiple conductive patterns are stacked around the same storage function layer and arranged in a direction perpendicular to the board line layer.

3. The semiconductor structure according to claim 1 or 2, characterized in that, The isolation layer has a first gap.

4. The semiconductor structure according to claim 3, characterized in that, The first gap is located between two adjacent board line layers along a first direction, and the first gap is also located between two adjacent storage function layers; the first direction is perpendicular to the board line layers.

5. The semiconductor structure according to claim 3, characterized in that, In the adjacent conductive pattern and the board line layer: the first surface of the conductive pattern is recessed relative to the board line layer, and a portion of the isolation layer is located in the first recessed area enclosed by the first surface, the board line layer, and the storage function layer; and / or, the second surface of the conductive pattern is recessed relative to the board line layer, and a portion of the isolation layer is located in the second recessed area enclosed by the second surface, the board line layer, and the storage function layer; the first surface and the second surface are arranged opposite each other in a direction perpendicular to the board line layer.

6. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure further includes an isolation portion that extends through the stacked structure and is connected to the isolation layer.

7. The semiconductor structure according to claim 6, characterized in that, The isolation layer and the isolation part are integrally formed.

8. The semiconductor structure according to claim 6, characterized in that, The isolation section has a second gap, which communicates with at least one of the first gaps.

9. The semiconductor structure according to claim 8, characterized in that, The second gap is located between two adjacent storage function layers and extends in a direction perpendicular to the board line layer.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure includes a substrate and a dielectric layer. The substrate is located on one side of the stacked structure, and the dielectric layer is located on the other side of the stacked structure. The isolation portion also penetrates the dielectric layer and extends into a portion of the substrate.

11. The semiconductor structure according to claim 1 or 2, characterized in that, The material of the storage functional layer includes ferroelectric materials.

12. A method for fabricating a semiconductor structure, characterized in that, include: A stacked structure is provided, the stacked structure comprising a plurality of alternating line layers and a plurality of sacrificial layers; A capacitor hole is formed, which penetrates the stacked structure; Multiple conductive patterns, a storage functional layer, and a second conductive layer are formed within the capacitor via. Each conductive pattern and a board line layer constitute a first conductive layer. The storage functional layer is located between the multiple first conductive layers and the second conductive layer, and surrounds the second conductive layer. The multiple conductive patterns are located between the board line layer and the storage functional layer, and surround the storage functional layer. The sacrificial layer is replaced with an isolation layer to form a stacked structure.

13. The preparation method according to claim 12, characterized in that, The formation of multiple conductive patterns, a storage functional layer, and a second conductive layer includes: A third conductive layer, a storage function layer, and a second conductive layer are sequentially formed inside the capacitor hole. Remove the sacrificial layer to form a first filling space; The portion of the third conductive layer exposed in the first filling space is removed to form a plurality of the conductive patterns.

14. The preparation method according to claim 13, characterized in that, After the third conductive layer, the storage functional layer, and the second conductive layer are sequentially formed within the capacitor hole, and before the sacrificial layer is removed, the fabrication method further includes: A second filling space is formed, which extends through the stacked structure; The removal of the sacrificial layer includes: removing the sacrificial layer through the second fill space.

15. The preparation method according to claim 14, characterized in that, Prior to providing the stacked structure, a substrate is also provided, the substrate being located on one side of the stacked structure; After providing the stacked structure and before forming the capacitor via, the fabrication method further includes: providing a dielectric layer located on the side of the stacked structure opposite to the substrate; The formation of the second filling space includes: the second filling space also penetrates the dielectric layer and extends into a portion of the substrate.

16. The preparation method according to any one of claims 13 to 15, characterized in that, The step of replacing the sacrificial layer with the isolation layer includes: An insulating material is deposited within the first filling space and between two adjacent conductive patterns to form an insulating layer having a first gap.

17. The preparation method according to claim 16, characterized in that, In the case where the preparation method further includes forming a second space, During the deposition of the isolation material in the first filling space, the isolation material is also deposited in the second filling space to form an isolation section having a second gap communicating with at least one of the first gaps.

18. A storage system, characterized in that, include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure as described in any one of claims 1 to 17; The controller is coupled to the semiconductor structure.

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