Display device

Abstract

A display device is disclosed. A display device includes a display panel including a plurality of pixels and including a substrate divided into a first region disposed at a center and a second region surrounding the first region; and a gate driver including a plurality of stages configured to supply gate signals to the pixels through the gate lines. Each of a plurality of stages included in the gate driver is disposed in a gate region, the gate region at least partially overlapping the first region and the second region, the plurality of pixels including a plurality of first pixels disposed on the first region and a plurality of second pixels disposed on the second region, the first pixels may be disposed in the first region at a first density, and the second pixels may be disposed in the second region at a second pixel density lower than the first pixel density.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] With the advent of the information age, the display field that visually expresses electrical information signals has been rapidly developed, and in response to this, various display devices having excellent properties such as thin thickness, light weight, and low power consumption have been developed. Examples of such display devices include liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), and the like.

[0003] The applicable range of the display device is diverse to personal digital assistants as well as monitors of computers and televisions, and display devices having a large display area and reduced volume and weight are being studied.

[0004] Recently, a display device manufactured by forming a display unit, wiring, etc. on a flexible substrate such as plastic, which is a flexible material so as to be stretchable in a specific direction and changeable in various forms, has attracted attention as a next-generation display device. Summary of the invention

[0005] An object to be achieved by the present disclosure is to provide a display device that reduces or minimizes the frame area.

[0006] Another object to be achieved by the present disclosure is to provide a display device in which a peripheral area can be modified to have a curved shape.

[0007] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0008] In order to achieve the above-mentioned purpose, according to one aspect of the present disclosure, a display device includes a display panel, the display panel includes a plurality of pixels and includes a substrate, the substrate is divided into a first area set at the center of the display device and a second area surrounding (surrounding) the first area; a data driver, which is configured to provide a data signal to the pixel through a data line; and a gate driver, including a plurality of stages configured to provide a gate signal to the pixel through a gate line. Each of the plurality of stages included in the gate driver is set in a gate region, the gate region at least partially overlaps the first region and the second region, the plurality of pixels include a plurality of first pixels set on the first region and a plurality of second pixels set on the second region, the first pixels can be set in the first region at a first pixel density, and the second pixels can be set in the second region at a second pixel density lower than the first pixel density.

[0009] Additional details of example embodiments are included in the detailed description and the accompanying drawings.

[0010] In the display device according to the exemplary embodiment of the present disclosure, the gate region where various components constituting the gate driver are disposed is disposed to overlap at least a portion of the display area (the first region and the second region) where various components constituting the pixel are disposed. That is, the gate driver is disposed in an array gate (GIA) manner and formed on the gate region, so that the border area of ​​the display device can be reduced or minimized.

[0011] In addition, the display device according to the exemplary embodiment of the present disclosure includes a first area as a central area and a second area as a peripheral area surrounding (surrounding) the first area. The second pixel arranged in the second area can be arranged to have a lower pixel density than the first pixel arranged in the first area. Therefore, in the second area as the peripheral area, the display device can be modified so that the second area as the peripheral area can be configured to have a curved shape.

[0012] The effects according to the present disclosure are not limited to the contents of the above examples, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present disclosure;

[0015] Figure 2A is shown along Figure 1 A cross-sectional view of the example taken along line II';

[0016] Figure 2B is shown along Figure 1 A cross-sectional view of an example taken along line II-II';

[0017] Figure 3 It is used to describe the settings Figure 1 A diagram showing an example of a disposition relationship of a first pixel on a first area of ​​a display device;

[0018] Figure 4 It is used to describe the settings Figure 1 A diagram showing an example of a disposition relationship of second pixels on a second area of ​​a display device;

[0019] Figure 5 is a plan view showing a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 6 It shows that the setting Figure 5FIG. 1 is a diagram showing an example of a gate driver on a gate region of a display device;

[0021] Figure 7 is a schematic diagram showing the Figure 5 A cross-sectional view of an example of a display panel in a display device;

[0022] Figure 8 Is magnification Figure 5 an enlarged view of an example of a portion of a first sub-region, a second sub-region, a fifth sub-region, a sixth sub-region, a seventh sub-region, and an eighth sub-region;

[0023] Fig. 9A Is magnification Figure 5 an enlarged view of an example of a portion of the third sub-region and the fourth sub-region;

[0024] Fig. 9B Is magnification Figure 5 an enlarged view of another example of a portion of the third sub-region and the fourth sub-region; and

[0025] Fig.10 is shown along Figure 5 A cross-sectional view of the example taken along line III-III'. DETAILED DESCRIPTION

[0026] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0027] The shapes, sizes, ratios, angles, quantities, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "consisting of..." used herein are generally intended to allow the addition of other components unless the term is used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0028] Parts are interpreted as including ordinary tolerances even if not expressly stated.

[0029] When terms such as “on,” “above,” “below,” and “beside” are used to describe a positional relationship between two components, one or more components may be located between the two components unless the terms are used together with the terms “immediately” or “directly.”

[0030] When an element or layer is referred to as being “on” another element or layer, the other layer or other elements may be directly interposed on the other element or layer.

[0031] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component mentioned below may be the second component.

[0032] Throughout the specification, like reference numerals generally refer to like elements.

[0033] The size and thickness of each component shown in the drawings are shown for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0034] The features of the various embodiments of the present disclosure may be partially or entirely adhered to or combined with each other, and may be interlocked and operated in technically various ways, and the embodiments may be performed independently or in association with each other.

[0035] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a plan view showing a display device according to an exemplary embodiment of the present disclosure.

[0037] Figure 2A It is a description along Figure 1 A cross-sectional view of the example taken along line II'.

[0038] Figure 2B is shown along Figure 1 A cross-sectional view of the example taken along line II-II'.

[0039] Figure 1 is a diagram illustrating a front surface of a display device 1000 according to an exemplary embodiment of the present disclosure.

[0040] Despite Figure 1 , the display device 1000 is shown to be implemented in the form of a smart phone, but it is not limited thereto, and the display device 1000 may be implemented as various electronic devices (eg, a smart watch, a tablet PC, etc.).

[0041] Even in Figure 1 , Figure 2A and Figure 2B , for convenience of description, among the components included in the display device 1000, only the window WD is shown.

[0042] Reference Figure 1 The display device 1000 according to an exemplary embodiment of the present disclosure may include a display panel DP (see Figure 7 ) and the covering display panel DP (see Figure 7 ) window WD (see Figure 2A and Figure 2B ).

[0043] The display device 1000 may display an image through a display surface. Here, the display surface may be defined as a region in which an image is displayed. The display device 1000 may include a display panel DP (see Figure 5 ), and the display panel DP (see Figure 5 ) may include multiple pixels for displaying an image.

[0044] The display surface where the image is displayed may be parallel to a surface defined by a first direction axis (e.g., an axis extending in the first direction DR1) and a second direction axis (e.g., an axis extending in the second direction DR2). Typically, these directions are referred to as the x-direction and the y-direction, respectively. The normal direction of the display surface, i.e., the thickness direction of the display device 1000, may be defined as a third direction DR3. Typically, this is referred to as the z-direction.

[0045] The front surface (or top surface) and the rear surface (or bottom surface) of the components or units of the display device 1000 to be described below can be distinguished by the third direction DR3. However, the first to third directions DR1 (e.g., x direction), DR2 (e.g., y direction), and DR3 (e.g., z direction) shown in the specification are merely illustrative, and the first to third directions DR1, DR2, and DR3 are relative concepts to be converted into other directions. In the following, for the convenience of description, the same reference numerals represent the first to third directions DR1, DR2, and DR3, respectively.

[0046] When expressed as “overlapping”, this means that two components overlap in the thickness direction of the display device 1000 (ie, the third direction DR3 ), unless otherwise defined.

[0047] The display surface of the display device 1000 can be used not only as an area for displaying an image, but also as an area for recognizing a user's touch input (e.g., a sensing area or a touch area). In this case, the display device 1000 may further include a touch sensor. According to an exemplary embodiment, the area for recognizing a user's touch input may correspond to the above-mentioned display surface and overlap with at least a portion of the display surface.

[0048] exist Figure 1In the embodiment, even if the display device 1000 has a rounded corner where one long side and one short side meet, this is merely illustrative, and the shape of the display device 1000 is not limited thereto. For example, the display device 1000 may have an angled shape at a corner where one long side and one short side meet, etc.

[0049] In one exemplary embodiment, the display device 1000 may include a display surface having a flat central area and a display surface having a curved peripheral area (eg, edge area). For example, the front surface of the display device 1000 may be provided as the display surface.

[0050] More specifically, the display device 1000 may include a first area A1 and a second area A2 other than the first area A1. For example, the second area A2 may be defined as an area surrounding (or may be considered to surround) the first area A1. The first area A1 may occupy most of the area of ​​the display surface.

[0051] In one exemplary embodiment, the second area A2 may include a left area, a right area, a lower area, an upper area, and a corner area of ​​the first area A1. For example, the second area A2 may include a first sub-area A2a (e.g., a left area) adjacent to one side of the first area A1 along the first direction DR1, a second sub-area A2b (e.g., a right area) adjacent to the other side of the first area A1 along the first direction DR1, a third sub-area A2c (e.g., a lower area) adjacent to one side of the first area A1 along the second direction DR2, a fourth sub-area A2d (an upper area) adjacent to one side of the first area A1 along the second direction DR2, a fifth sub-area A2e (e.g., a first corner area) between the first sub-area A2a and the third sub-area A2c, a sixth sub-area A2f (e.g., a second corner area) between the first sub-area A2a and the fourth sub-area A2d, a seventh sub-area A2g (e.g., a third corner area) between the second sub-area A2b and the third sub-area A2c, and an eighth sub-area A2h (e.g., a fourth corner area) between the second sub-area A2b and the fourth sub-area A2d.

[0052] According to an exemplary embodiment, the first area A1 is an area corresponding to the central area of ​​the display device 1000, the second area A2 (for example, the first sub-area A2a to the eighth sub-area A2h) may be a curved shape, and the second area A2 is an area corresponding to the peripheral area (edge ​​area) of the display device 1000.

[0053] For example, further reference Figure 2A and Figure 2B ,like Figure 2A As shown (along Figure 1The first sub-region A2a and the second sub-region A2b may have a curved shape that is curved in a direction substantially parallel to the first direction DR1 (eg, the first strain direction). Figure 2B As shown (along Figure 1 The third sub-region A2c and the fourth sub-region A2d may have a curved shape that is curved in a direction substantially parallel to the second direction DR2 (eg, the second strain direction). Figure 2A and Figure 2B Although not shown, each of the fifth to eighth sub-regions (A2e to A2h) may have a curved shape curved along the first direction DR1 and the second direction DR2 (e.g., the first strain direction and the second strain direction). The first direction DR1 may be substantially parallel to one short side of the display device 1000, and the second direction may be substantially parallel to one long side of the display device 1000, but the first direction DR1 and the second direction DR2 are not limited thereto.

[0054] In an exemplary embodiment, the display device 1000, for example, and the display panel DP (see FIG. 1 ) included in the display device 1000 Figure 5 ) may have a bendable or stretchable characteristic. For example, the display device 1000, for example, a display panel DP (see FIG. 1 ) included in the display device 1000 Figure 5 ) may have not only flexibility but also stretchability. Therefore, the shape of the display device 1000 corresponding to the first to eighth sub-areas A2a to A2h may be freely modified so that it may be designed to have a curved shape in the corresponding area.

[0055] This will be referenced below Figures 1 to 5 Describe in more detail.

[0056] Figure 3 is used to explain the settings in Figure 1 A diagram of an example of a setting relationship of a first pixel on a first area of ​​a display device.

[0057] Figure 4 is used to explain the settings in Figure 1 A diagram of an example of a setting relationship of second pixels on a second area of ​​a display device.

[0058] Reference Figure 1 , Figure 2A , Figure 2B , Figure 3 and Figure 4 , the display device 1000 may include a first area A1 and a second area A2. Figure 1 , Figure 2A and Figure 2B As described above, the first area A1 is an area corresponding to the central area of ​​the display device 1000 and may have a flat shape, and the second area A2 is an area corresponding to the peripheral area (edge ​​area) of the display device 1000 and may have a curved shape.

[0059] The display device 1000 may include a plurality of first pixels PX1 disposed in a first area A1 and a plurality of second pixels PX2 disposed in a second area A2. Each of the first pixels PX1 and each of the second pixels PX2 includes at least one of a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. In some cases, at least some of the first pixels PX1 and the second pixels PX2 may further include a white sub-pixel (not shown).

[0060] According to an exemplary embodiment, the light emitting efficiency of the light emitting diode may be determined according to the colors of the sub-pixels R, G, and B. In view of this, the sizes of the sub-pixels R, G, and B may be determined according to the colors.

[0061] For example, among the sub-pixels R, G, and B, the blue sub-pixel B may have the largest size and the green sub-pixel G may have the smallest size, but this is merely illustrative and exemplary embodiments of the present disclosure are not limited thereto.

[0062] In one exemplary embodiment, the display device 1000 may have a different pixel density for each region.

[0063] For example, the display device 1000 may include a plurality of first pixels PX1 disposed on a first area A1 and a plurality of second pixels PX2 disposed on a second area A2. Here, the first pixels PX1 may be disposed on the first area A1 at a first pixel density, and the second pixels PX2 may be disposed on the second area A2 at a second pixel density less than the first pixel density.

[0064] Here, the pixel density may be defined as the total area of ​​the portion where the actual pixels are provided relative to the entire size of the corresponding area, or as the total area of ​​the pixels included in a predetermined unit area. Here, the area where each pixel is provided may be the area of ​​the light emitting surface of the light emitting diode included in each pixel. For example, when the pixel includes an organic light emitting diode, the area of ​​the pixel may be the area of ​​the anode exposed between the pixel defining films, or the area of ​​the light emitting layer.

[0065] More specifically, if Figure 3 and Figure 4 As shown, in the first area A1 and the second area A2, unit areas UA having substantially the same size may be defined.

[0066] Here, referring to the unit area UA, the first pixel PX1 disposed on the first area A1 may be disposed at a relatively large first pixel density. For example, in the first area A1, the first pixel PX1 may be disposed at a high PPI. Therefore, an image with high resolution may be displayed in the first area A1, which occupies most of the display surface area and corresponds to the central area.

[0067] Here, referring to the unit area UA, the second pixel PX2 disposed on the second area A2 may be disposed at a relatively small second pixel density. Here, the second pixel density is less than the first pixel density, and for example, the first pixel density may be eight times the second pixel density, but this is merely illustrative, and the exemplary embodiments of the present disclosure are not limited thereto. For example, the PPI of the second area A2 may be set to be lower than the PPI of the first pixel PX1 of the first area A1.

[0068] Here, as described above, the second area A2 is a peripheral area (edge ​​area) and may have a curved shape that is bent in the strain direction. For example, the substrate of the display device 1000 is composed of a flexible substrate. A plurality of rigid board patterns are arranged on the substrate in a manner spaced apart from each other. The second pixel PX2 of the unit area UA of the second area A2 is arranged on the rigid board pattern. In an area where the second pixel PX2 is not arranged, a wavy connecting line is arranged so that the display device 1000 can be stretched in the second area A2. Therefore, the display device 1000 may have a curved shape that is bent in the strain direction on the second area A2.

[0069] Figure 5 is a plan view showing a display device according to an exemplary embodiment of the present disclosure.

[0070] Figure 6 It shows that the setting Figure 5 FIG. 1 is a diagram of an example of a gate driver on a gate region of a display device.

[0071] In order to avoid duplication of description, the main description is separated from the reference Figures 1 to 4 The parts not described in detail follow the above-described exemplary embodiments, and the same reference numerals denote the same components.

[0072] Reference Figure 5 The display device 1000 according to an exemplary embodiment of the present disclosure may include a display panel DP, a plurality of pixels PX, a gate driver GD, and a data driver DD. In an exemplary embodiment, the display device 1000 may further include a printed circuit board PCB.

[0073] As described above, the display device 1000 may include a first area A1 and a second area A2. For example, the display panel DP of the display device 1000 may include a substrate as the first area A1 and the second area A2. Here, the first area A1 and the second area A2 may be defined as a display area.

[0074] Each pixel PX (e.g., the first pixel PX1 of the first area A1 and / or the second pixel PX2 of the second area A2) may include a display element and various driving elements for driving the display element. For example, the various driving elements may include at least one thin film transistor (TFT) and a capacitor. In addition, the pixels PX may be connected to various wirings, respectively. For example, each pixel PX may be connected to various wirings, such as a gate line (e.g., a scan signal line or a light emitting signal line), a data line, and a power supply voltage line.

[0075] In addition, the display panel DP may include a gate area GIA. The gate area GIA may overlap at least a portion of the first area A1 and at least a portion of the second area A2. For example, a plurality of gate areas GIA extending along the second direction DR2 and spaced apart from each other along the first direction DR1 may be disposed to overlap a portion of the first area A1 and the second area A2 (e.g., the third sub-area A2c and the fourth sub-area A2d).

[0076] exist Figure 5 , although it is shown that the display panel DP includes five gate areas GIA, this is only illustrative, but exemplary embodiments of the present disclosure are not limited thereto.

[0077] The gate driver GD may be disposed on the gate area GIA. For example, the gate driver GD may be formed in an array on the gate area GIA, which overlaps at least a portion of the first area A1 and the second area A2 in the gate. For example, according to an exemplary embodiment, the gate driver GD may be disposed on the same layer as the pixel PX on the display panel DP, or may be disposed on a different layer. Therefore, the frame of the display device 1000 may be reduced or minimized.

[0078] Further references Figure 6, a scan driver 200 configured to provide a scan signal to the pixel PX and a light emitting driver 300 configured to provide a light emitting control signal to the pixel PX may be disposed on the gate area GIA. The scan driver 200 may include a first scan driver 210 (SC1) configured to provide a first scan signal to the pixel PX, a second scan driver 220 (SC2) configured to provide a second scan signal to the pixel PX, a third scan driver 230 (SC3) configured to provide a third scan signal to the pixel PX, and a fourth scan driver 240 (SC4) configured to provide a fourth scan signal to the pixel PX.

[0079] For example, components included in the first scan driver 210 (e.g., transistors, capacitors, various connection signal lines, etc.), components included in the second scan driver 220 (e.g., transistors, capacitors, various connection signal lines, etc.), components included in the third scan driver 230 (e.g., transistors, capacitors, various connection signal lines, etc.), components included in the fourth scan driver 240 (e.g., transistors, capacitors, various connection signal lines, etc.), and components included in the light emitting driver 300 (e.g., transistors, capacitors, various connection signal lines, etc.) can be set on the gate area GIA.

[0080] In addition, the power line PL configured to provide the low potential voltage VSS to the pixel PX can be disposed together on the gate area GIA. As described above, the power line PL configured to provide the low potential voltage VSS is disposed to overlap the first area A1 and the second area A2 as the display area to reduce or minimize the frame of the display device 1000.

[0081] Refer again Figure 5 , the printed circuit board PCB can send signals and voltages for driving the display elements from the controller to the display elements. Therefore, the printed circuit board PCB can also be called a driving substrate. A controller such as an IC chip or a circuit unit can be mounted on the printed circuit board PCB. In addition, a memory, a processor, etc. can also be mounted on the printed circuit board PCB.

[0082] The data driver DD may provide data signals to the pixels PX disposed in the first area A1 and / or the second area A2. For example, the data driver DD may provide data signals to the pixels PX through data lines.

[0083] In one exemplary embodiment, the data driver DD is configured as an integrated circuit chip (IC chip) called a data integrated circuit. The data driver DD can be mounted in a chip on chip (COF) method, a chip on board (COB) method, a chip on glass (COG) method, a tape carrier package (TCP) method, etc.

[0084] In the following, reference will be made to Figure 7 A specific cross-sectional structure of the display panel DP is described.

[0085] Figure 7 is a schematic diagram showing the Figure 5 A cross-sectional view of an example of a display panel in a display device.

[0086] Reference Figures 5 to 7 , at least one transistor TR1 and TR2 and a light emitting diode LD may be disposed on a substrate SUB.

[0087] The first transistor TR1 among the transistors disposed on the substrate SUB may be a polysilicon semiconductor transistor. For example, the first transistor TR1 may be a p-type MOSFET transistor (PMOS transistor) including a polysilicon semiconductor layer formed by a low temperature polysilicon (LTPS) process as an active layer (channel).

[0088] In addition, the second transistor TR2 among the transistors provided on the substrate SUB may be an oxide semiconductor transistor. For example, the second transistor TR2 may be an n-type MOSFET transistor (NMOS transistor) including an oxide semiconductor layer as an active layer (channel).

[0089] The substrate SUB is a basic component of the display panel DP and may be substantially a transparent and transmissive substrate. The substrate SUB may be a flexible substrate formed of a plastic material. Here, the flexible property may be interpreted as the same meaning as bendable, unbreakable, rollable, and foldable properties.

[0090] For example, the substrate SUB may include plastic, and in this case, the substrate SUB may be referred to as a plastic film or a plastic substrate. For example, the substrate SUB may include at least one selected from the group consisting of a polyester-based polymer, a silicon-based polymer, an acrylic polymer, a polyolefin-based polymer, and polymers thereof. For example, the substrate SUB may include polyimide (PI).

[0091] When the substrate SUB includes polyimide (PI), moisture passes through the substrate SUB formed of polyimide (PI) and infiltrates into the thin film transistor included in the pixel PX, thereby reducing reliability of the pixel PX and thus reducing performance of the display device 1000 .

[0092] Therefore, in an exemplary embodiment, the substrate SUB may include a double polyimide (PI). In addition, the substrate SUB also includes an inorganic film formed between the two polyimides (PI) to prevent moisture components from penetrating into the lower polyimide (PI), thereby further improving the reliability of product performance. In addition, an inorganic film is formed between the two polyimides (PI) to block the electric charge charged in the lower polyimide (PI), thereby improving the reliability of the product.

[0093] For example, Figure 7 As shown, the substrate SUB may include: a first sub-substrate SUBa including polyimide (PI), a second sub-substrate SUBb disposed on the first sub-substrate SUBa and including an inorganic insulating material, and a third sub-substrate SUBc disposed on the second sub-substrate SUBb and including polyimide PI.

[0094] The inorganic insulating material included in the second sub-substrate SUBb may be formed by a single layer or a multilayer of silicon nitride SiNx or silicon oxide SiOx. However, this is merely illustrative, so that the exemplary embodiments of the present disclosure are not limited thereto. For example, the inorganic insulating material included in the second sub-substrate SUBb may include a silicon oxide SiOx material. For example, the inorganic insulating material included in the second sub-substrate SUBb may include silicon dioxide (silica, SiO2). As another example, the inorganic insulating material included in the second sub-substrate SUBb may be formed by a double layer of silicon dioxide SiO2 and silicon nitride SiNx.

[0095] Even in Figure 7 Not shown separately, a back plate and a metal plate may also be further arranged under the substrate SUB.

[0096] The pattern layer 120 may be disposed on the substrate SUB. The pattern layer 120 supports the pixels PX, the gate driver GD, and the connection lines, and may include a plurality of plate patterns and a plurality of line patterns disposed on the second area A2. Figures 8 to 10 The pattern layer 120 is described in more detail.

[0097] A shielding metal layer including at least one shielding metal pattern BSM may be disposed on the substrate SUB (or the pattern layer 120 ).

[0098] The shielding metal pattern BSM included in the shielding metal layer may be formed by a single layer or a multilayer formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0099] According to example embodiments, the shielding metal pattern BSM may be defined as a component included in the first transistor TR1. For example, the shielding metal pattern BSM may configure a lower gate of the first transistor TR1.

[0100] The first buffer layer BUF1 may be disposed on the substrate SUB (or the pattern layer 120). For example, the first buffer layer BUF1 may be disposed on the substrate SUB (or the pattern layer 120) to cover the shielding metal pattern BSM.

[0101] In one exemplary embodiment, the first buffer layer BUF1 may include a multi-buffer layer BUF1 a disposed on the substrate SUB (or the pattern layer 120 ) and an active buffer layer BUF1 b disposed on the multi-buffer layer BUF1 a .

[0102] The first transistor TR1 may be disposed on the first buffer layer BUF1. The first transistor TR1 may include a first semiconductor pattern ACT1, a first gate G1, a source SE1, and a drain DE1. According to exemplary embodiments, as described above, the first transistor TR1 may further include a shield metal pattern BSM disposed between the first buffer layer BUF1 and the substrate SUB.

[0103] A first semiconductor layer including at least one first semiconductor pattern ACT1 may be disposed on the first buffer layer BUF1.

[0104] For example, the first semiconductor pattern ACT1 included in the first transistor TR1 of the first semiconductor layer may be disposed on the first buffer layer BUF1. The first semiconductor pattern ACT1 may include a first region S1 (or source or source region), a second region D1 (or drain or drain region), and a channel region A1 therebetween. In addition, as described above, the first semiconductor pattern ACT1 may include a polycrystalline silicon semiconductor layer formed by a low temperature polycrystalline silicon (LTPS) process.

[0105] The first gate insulating layer GI1 may be disposed on the first semiconductor layer (eg, the first semiconductor pattern ACT1). For example, the first gate insulating layer GI1 is disposed to cover the first semiconductor layer (eg, the first semiconductor pattern ACT1) to insulate the first semiconductor pattern ACT1 of the first transistor TR1 from the first gate G1.

[0106] For example, the first gate insulating layer G11 may be configured of a single layer of silicon nitride SiNx or silicon oxide SiOx or a multi-layer thereof, but is not limited thereto.

[0107] The first conductive layer GAT1 may be disposed on the first gate insulating layer GI1. The first conductive layer GAT1 may be configured as at least a portion of a light emitting control line for providing a light emitting control signal to the pixel PX, a scan line for providing a scan signal, and a power line for providing various power supply voltages. Here, when the first conductive layer GAT1 is configured as at least a portion of a power supply line configured to provide a power supply voltage, the first conductive layer GAT1 may include a material having high conductivity, such as a metal or a conductive oxide. For example, the first conductive layer GAT1 may be formed of a single layer or multiple layers including aluminum (Al), copper (Cu), titanium (Ti), and the like. In some exemplary embodiments, the first conductive layer GAT1 may be configured as three layers of titanium, aluminum, and titanium (Ti / Al / Ti) disposed sequentially. However, the first conductive layer GTA1 is not limited thereto, and may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0108] The first gate G1 of the first transistor TR1 configuring at least a portion of the light emitting control line or the scan line of the first conductive layer GAT1 may be disposed on the first gate insulating layer GI1 .

[0109] The first gate G1 of the first transistor TR1 may be disposed to overlap at least a portion of the first semiconductor pattern ACT1 .

[0110] The first insulating layer ILD1 may be disposed on the first conductive layer GAT1 (eg, the first gate G1 of the first transistor TR1). For example, the first insulating layer ILD1 may be disposed to cover the first conductive layer GAT1 (eg, the first gate G1 of the first transistor TR1).

[0111] The first insulating layer ILD1 may be configured of a single layer of silicon nitride SiNx or silicon oxide SiOx or a multi-layer thereof, but is not limited thereto.

[0112] The second conductive layer TM1 may be disposed on the first insulating layer ILD1. The second conductive layer TM1 includes molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be formed of a single layer or a multilayer.

[0113] The second insulating layer ILD2 may be disposed on the second conductive layer TM1. For example, the second insulating layer ILD2 may be disposed to cover the second conductive layer TM1.

[0114] The first insulating layer ILD1 may be configured of a single layer of silicon nitride or silicon oxide or a multi-layer thereof, but is not limited thereto.

[0115] The third conductive layer TM2 may be disposed on the second insulating layer ILD2. The third conductive layer TM2 includes molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be formed of a single layer or a plurality of layers.

[0116] For example, the first source electrode SE1 and the first drain electrode DE1 of the first transistor TR1 of the third conductive layer TM2 may be disposed on the second insulating layer ILD2. The first source electrode SE1 of the first transistor TR1 of the third conductive layer TM2 may contact the first region S1 of the first semiconductor pattern ACT1 through a contact hole passing through the second insulating layer ILD2, the first insulating layer ILD1, and the first gate insulating layer GI1. The first drain electrode DE1 of the first transistor TR1 of the third conductive layer TM2 may contact the second region D1 of the first semiconductor pattern ACT1 through a contact hole passing through the second insulating layer ILD2, the first insulating layer ILD1, and the first gate insulating layer GI1.

[0117] The third insulating layer ILD3 may be disposed on the third conductive layer TM2 (eg, on the first source SE1 and the first drain DE1 of the first transistor TR1 ). For example, the third insulating layer ILD3 may be disposed to cover the third conductive layer TM2 .

[0118] The third insulating layer ILD3 may be configured of a single layer of silicon nitride SiNx or silicon oxide SiOx or a multi-layer thereof, but is not limited thereto.

[0119] The second buffer layer BUF2 may be disposed on the third insulating layer ILD3 .

[0120] The second buffer layer BUF2 may be configured of a single layer of silicon nitride SiNx or silicon oxide SiOx or a multi-layer thereof, but is not limited thereto.

[0121] A second semiconductor layer including at least one second semiconductor pattern ACT2 may be disposed on the second buffer layer BUF2 .

[0122] For example, the second semiconductor pattern ACT2 included in the second transistor TR2 of the second semiconductor layer may be disposed on the second buffer layer BUF2. The second semiconductor pattern ACT2 may include a first region S2 (or source or source region), a second region D2 (or drain or drain region) and a channel region A2 therebetween. In addition, as described above, the second semiconductor pattern ACT2 may include an oxide semiconductor layer.

[0123] The second gate insulating layer GI2 may be disposed on the second semiconductor layer (eg, the second semiconductor pattern ACT2). The second gate insulating layer G12 may be configured of a single layer of silicon nitride SiNx or silicon oxide SiOx or a multi-layer thereof, but is not limited thereto.

[0124] The fourth conductive layer GAT2 may be disposed on the second gate insulating layer GI2. The fourth conductive layer GAT2 includes molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may be formed of a single layer or a plurality of layers.

[0125] For example, the second gate G2 of the second transistor TR2 configuring at least a portion of the scan line of the fourth conductive layer GAT2 may be disposed on the second gate insulating layer GI2.

[0126] The second gate G2 of the second transistor TR2 may be disposed to overlap at least a portion of the second semiconductor pattern ACT2 .

[0127] The fourth insulating layer ILD4 may be disposed on the fourth conductive layer GAT2 (eg, the second gate G2 of the second transistor TR2). For example, the fourth insulating layer ILD4 may be disposed to cover the fourth conductive layer GAT2 (eg, the second gate G2 of the second transistor TR2).

[0128] The fifth conductive layer SD1 may be disposed on the fourth insulating layer ILD4. The fifth conductive layer SD1 may be configured to be at least a portion of a power line configured to provide a power supply voltage. Here, since the fifth conductive layer SD1 is configured to be at least a portion of a power line configured to provide a power supply voltage, the fifth conductive layer SD1 may include a material having high conductivity, such as a metal or a conductive oxide. For example, the fifth conductive layer SD1 may be formed of a single layer or multiple layers including aluminum (Al), copper (Cu), titanium (Ti), and the like. In some exemplary embodiments, the fifth conductive layer SD1 may be provided as three layers of titanium, aluminum, and titanium (Ti / Al / Ti) disposed sequentially. However, the fifth conductive layer SD1 is not limited thereto, and may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0129] In addition, at least a portion of the fifth conductive layer SD1 may be used as a connection electrode. For example, at least a portion of the fifth conductive layer SD1 may be connected to the source SE1 and / or drain DE1 of the first transistor TR1 of the third conductive layer TM2 through a contact hole that passes through the fourth insulating layer ILD4, the second gate insulating layer GI2, the second buffer layer BUF2, and the third insulating layer ILD3. Alternatively, at least a portion of the fifth conductive layer SD1 may be in contact with a portion of the fourth conductive layer GAT2 through a contact hole that passes through the fourth insulating layer ILD4.

[0130] In addition, at least a portion of the fifth conductive layer SD1 may configure a second source electrode SE2 and a second drain electrode DE2 of the second transistor TR2. For example, the second source electrode SE2 of the second transistor TR2 of the fifth conductive layer SD1 may contact the first region S2 of the second semiconductor pattern ACT2 through a contact hole passing through the fourth insulating layer ILD4 and the second gate insulating layer GI2. The second drain electrode DE2 of the second transistor TR2 of the fifth conductive layer SD1 may contact the second region D2 of the second semiconductor pattern ACT2 through a contact hole passing through the fourth insulating layer ILD4 and the second gate insulating layer GI2.

[0131] In an exemplary embodiment, at least a portion of the fifth conductive layer SD1 may configure a clock line CLK configured to provide a clock signal to a gate driver GD disposed on the gate area GIA of the display panel DP, which has been described with reference to FIG. Figure 5 and Figure 6 For example, at least a portion of the fifth conductive layer SD1 may configure a clock line CLK that transmits a clock signal, which is an input signal of each stage included in a gate driver GD (e.g., a scan driver 200 and / or a light emitting driver 300) disposed on the gate area GIA. For example, the clock line CLK of the fifth conductive layer SD1 that transmits a clock signal may be electrically connected to each stage of the gate driver GD (e.g., configuring at least a portion of the transistors of each stage) through a jumper structure.

[0132] The first planarization layer PNL1 may be disposed on the fifth conductive layer SD1. The first planarization layer PNL1 may be an organic layer that planarizes an upper portion thereunder and protects components disposed thereunder. For example, the first planarization layer PNL1 may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0133] The sixth conductive layer SD2 may be disposed on the first planarization layer PNL1 .

[0134] The sixth conductive layer SD2 may be configured as at least a portion of a data line for providing a data signal to the pixel PX or a power line for providing a high potential power supply voltage VDD. Here, since the sixth conductive layer SD2 is configured as at least a portion of a power line configured to provide a power supply voltage, the sixth conductive layer SD2 may include a material having high conductivity, such as a metal or a conductive oxide. For example, the sixth conductive layer SD2 may be formed of a single layer or multiple layers including aluminum (Al), copper (Cu), titanium (Ti), etc. In some exemplary embodiments, the sixth conductive layer SD2 may be provided as three layers of titanium, aluminum, and titanium (Ti / Al / Ti) arranged sequentially. However, the sixth conductive layer SD2 is not limited thereto, and may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0135] In addition, at least a portion of the sixth conductive layer SD2 may be used as a connection electrode. For example, at least a portion of the sixth conductive layer SD2 may be connected to at least a portion of the fifth conductive layer SD1 through a contact hole passing through the first planarization layer PNL1.

[0136] The second planarization layer PNL2 may be disposed on the sixth conductive layer SD2. The second planarization layer PNL2 may be an organic layer that planarizes an upper portion thereunder and protects components disposed thereunder. For example, the second planarization layer PNL2 may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0137] The seventh conductive layer SD3 may be disposed on the second planarization layer PNL2 and may be formed of a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd).

[0138] In an exemplary embodiment, at least a portion of the seventh conductive layer SD3 may be used as a shielding pattern SM. For example, as described above, at least a portion of the fifth conductive layer SD1 configures at least a portion of the clock line CLK that sends a clock signal to the gate driver GD. Therefore, there may be signal interference between the clock line CLK of the fifth conductive layer SD1 and the anode AND of the light emitting diode LD disposed thereon. In this case, the voltage of the anode AND of the light emitting diode LD is unstable, so that the display quality of the pixel PX may deteriorate. Therefore, in the case of the display device 1000 according to the exemplary embodiment of the present disclosure, the seventh conductive layer SD3 disposed above the second planarization layer PNL2 is used as a shielding pattern SM, which shields the signal between at least a portion of the fifth conductive layer SD1 (e.g., the clock line CLK) and the anode AND of the light emitting diode LD. Therefore, the display quality can be improved.

[0139] According to an exemplary embodiment, for the shielding function, the width of the shielding pattern SM of the seventh conductive layer SD3 may be greater than the width of the anode AND of the light emitting diode LD. Fig.10 As shown, the conductive layer SD3 and the conductive layer SD2 may be positioned on a layer between TR1 and / or TR2 and a layer where the light emitting diode LD is positioned.

[0140] In addition, at least a portion of the seventh conductive layer SD3 may be connected to at least a portion of the sixth conductive layer SD2 through a contact hole passing through the second planarization layer PNL2 .

[0141] The third planarization layer PNL3 may be disposed on the seventh conductive layer SD3. The third planarization layer PNL3 may be an organic layer that planarizes an upper portion thereunder and protects components disposed thereunder. For example, the third planarization layer PNL3 may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0142] The light emitting diode LD may be disposed on the third planarization layer PNL3. The light emitting diode LD may include an anode AND (or a first electrode), a cathode CAD (or a second electrode), and a light emitting layer EML formed therebetween.

[0143] The anode AND may be disposed on the third planarization layer PNL3.

[0144] When the display device 1000 is a top emission type, in which light emitted from the light emitting diode LD is emitted above the substrate SUB on which the light emitting diode LD is disposed, the anode AND may further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer may be formed of a transparent conductive oxide such as ITO or IZO, and the reflective layer may include, for example, silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), alloys thereof, and the like.

[0145] The bank layer BNK is provided so as to cover at least a portion of the anode AND and may open the remaining portion of the anode AND. For example, the bank layer BNK may be provided to open a portion of the light emitting region of the pixel PX. Therefore, a portion of the anode AND may be exposed through the opening portion of the bank layer BNK.

[0146] The bank layer BNK may include an inorganic insulating material such as silicon nitride SiNx or silicon oxide SiOx, or an organic insulating material such as benzocyclobutene resin, acrylic resin, or imide resin, but is not limited thereto.

[0147] The light emitting layer EML may be disposed on the front surface of the pixel PX on the top surfaces of the bank layer BNK and the anode AND. A portion of the light emitting layer EML may contact the exposed portion of the anode AND through the opening portion of the bank layer BNK.

[0148] According to example embodiments, the emission layer EML may include a plurality of organic films.

[0149] The cathode CAD may be disposed on the light emitting layer EML. For example, the cathode CAD may be disposed on the front surface of the pixel PX.

[0150] The light emitting diode LD may be formed of an anode AND, a light emitting layer EML, and a cathode CAD.

[0151] The spacer SPC may be provided so as not to contact a screen mask and a substrate with each other during a process of depositing the light emitting layer EML. The spacer SPC is disposed on the bank layer BNK, and the light emitting layer EML and the cathode CAD may be applied to cross the spacer SPC disposed in the display area AA.

[0152] According to an exemplary embodiment, the light emitting layer EML and / or the cathode CAD may not cross the spacer SPC. The spacer SPC is disposed only in a portion of the bank layer BNK in the display area AA, so that even if the cathode CAD does not cross the spacer SPC, the cathode CAD may be connected while covering the entire display area AA.

[0153] The encapsulation layer may be disposed above the light emitting diode LD. For example, the encapsulation layer may include a first inorganic encapsulation layer PAS1, a first organic encapsulation layer PCL1 on the first inorganic encapsulation layer PAS1, a second inorganic encapsulation layer PAS2 on the first organic encapsulation layer PCL1, a second organic encapsulation layer PCL2 on the second inorganic encapsulation layer PAS2, and a third inorganic encapsulation layer PAS3 on the second organic encapsulation layer PCL2. The first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 may be used to block the penetration of moisture or oxygen. For example, the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 may be formed of an inorganic material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium nitride. The first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

[0154] The first organic encapsulation layer PCL1 may be disposed between the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2, and the second organic encapsulation layer PCL2 may be disposed between the second inorganic encapsulation layer PAS2 and the third inorganic encapsulation layer PAS3. The first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2 may be formed to have a thickness greater than that of the first inorganic encapsulation layer PAS1, the second inorganic encapsulation layer PAS2, and the third inorganic encapsulation layer PAS3 to adsorb and / or block particles. Particles may be generated during the manufacturing process. The first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2 may be formed of an organic material, such as silicon oxide carbon silicon propylene or epoxy resin. The first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2 may be formed by a coating process, such as an inkjet coating process or a slit coating process.

[0155] Figure 8 Is magnification Figure 5 An enlarged view of an example of a portion of the first sub-region, the second sub-region, the fifth sub-region, the sixth sub-region, the seventh sub-region, and the eighth sub-region.

[0156] Fig. 9A Is magnification Figure 5 An enlarged view of an example of a portion of the third sub-region and the fourth sub-region.

[0157] Fig. 9B Is magnification Figure 5 An enlarged view of another example of a portion of the third sub-region and the fourth sub-region.

[0158] Figure 8This is an enlarged view showing an example of a plan view showing a part of any one of the first sub-region A2a, the second sub-region A2b, the fifth sub-region A2e, the sixth sub-region A2f, the seventh sub-region A2g, and the eighth sub-region A2h in an enlarged manner. Fig. 9A This is an enlarged view showing an example of a plan view in which a part of one of the third sub-region A2c and the fourth sub-region A2d is enlarged. Fig. 9B This is another example of an enlarged view of a top view showing a portion of either the third sub-region A2c or the fourth sub-region A2d. Figure 5 GIA in areas A2c and A2d.

[0159] Reference Figure 1 , Figure 3 , Figure 4 , Figures 5 to 9A , the display device 1000 according to an exemplary embodiment of the present disclosure may include a substrate SUB, a pattern layer 120 , a plurality of pixels PX, a gate driver GD, and a data driver DD.

[0160] As described above, the substrate SUB is a base component of the display panel DP, and is a substrate for supporting and protecting various components of the display device 1000 .

[0161] The substrate SUB is a flexible substrate that expands and contracts reversibly. Therefore, the substrate SUB can be called a stretchable substrate, an elastic substrate, a stretchable substrate, or a flexible substrate. In addition, the elastic modulus of the substrate SUB can be several MPa to several hundred MPa. In addition, the ductile fracture rate of the substrate SUB can be 100%. Here, the ductile fracture rate refers to the stretching rate when the object to be stretched breaks or ruptures.

[0162] The pattern layer 120 may be disposed on the substrate SUB. In one exemplary embodiment, the pattern layer 120 may support the pixels PX, the gate driver GD, and the connection lines 181, 182, 183, and 184 disposed on the second area A2.

[0163] In one exemplary embodiment, the pattern layer 120 may include a plurality of first plate patterns 121 , a plurality of second plate patterns 122 , a plurality of line patterns 123 , and a plurality of second line patterns 124 disposed in the second area A2 .

[0164] The first plate pattern 121 may be disposed on the second area A2 of the substrate SUB. For example, the first plate pattern 121 may be disposed above the first to eighth sub-areas A2a to A2h of the substrate SUB, respectively. Figure 5 , Figure 8 and Fig. 9A As shown, it includes a plurality of sub-pixels SPX (for example, referring to Figure 4A plurality of second pixels PX2 of the sub-pixels R, G, and B described above may be disposed on the first plate pattern 121 .

[0165] The first plate patterns 121 may be spaced apart from each other to be disposed on the second area A2 of the substrate SUB. Figure 8 and Fig. 9A As shown, the first plate patterns 121 may be disposed in a matrix form on the second area A2 of the substrate SUB, but this is merely illustrative, and exemplary embodiments of the present disclosure are not limited thereto.

[0166] The second plate pattern 122 may be disposed on the second area A2 of the substrate SUB. For example, the second plate pattern 122 may be disposed above the third sub-area A2c and the fourth sub-area A2d of the substrate SUB, respectively. Figure 5 and Fig. 9A As shown, the gate driver GD may be disposed on the second plate pattern 122. For example, various transistors, capacitors, and signal lines configuring the gate driver GD may be disposed on the second plate pattern 122.

[0167] The second plate patterns 122 may be spaced apart from each other to be disposed on a portion of the second area A2 (eg, the third sub-area A2c and the fourth sub-area A2d) of the substrate SUB. Fig. 9A As shown, the second plate patterns 122 may be disposed in a matrix form on the third and fourth sub-regions A2c and A2d of the substrate SUB, but this is merely illustrative, and exemplary embodiments of the present disclosure are not limited thereto.

[0168] For example, the first plate pattern 121 and the second plate pattern 122 may be integrally formed on the third sub-region A2c and the fourth sub-region A2d of the second region A2.

[0169] Specifically, refer to Fig. 9B , the pattern layer 120_1 may include a plurality of plate patterns 121_1 disposed on the third sub-region A2c and the fourth sub-region A2d. The plurality of plate patterns 121_1 may be spaced apart from each other to be disposed on the third sub-region A2c and the fourth sub-region A2d of the second region A2 of the substrate SUB. For example, Fig. 9B As shown, each of the plurality of plate patterns 121_1 extends on the third and fourth sub-regions A2c and A2d of the substrate SUB along the first direction DR1, and the plurality of plate patterns 121_1 may be disposed to be spaced apart from each other along the second direction DR2.

[0170] In addition, a plurality of sub-pixels SPX (for example, as already mentioned in reference Figure 4A plurality of second pixels PX2 of the sub-pixels R, G, and B described above and the gate driver GD (e.g., various transistors, capacitors, and signal lines configuring the gate driver GD) may be disposed on a plurality of plate patterns 121_1. For example, the gate driver GD (e.g., various transistors, capacitors, signal lines, etc. configuring the gate driver GD) may be disposed on the plate pattern 121_1 disposed on the third sub-region A2c and the fourth sub-region A2d, and may overlap with the gate region GIA. In addition, the second pixel PX2 may be disposed on the plate pattern 121_1 disposed on the third sub-region A2c and the fourth sub-region A2d, and may not overlap with the gate region GIA. The plate pattern 121_1 may be considered to include the plate patterns 121 and 122 formed as a whole.

[0171] Reference Fig. 9A , the first line pattern 123 may be disposed on the second area A2 of the substrate SUB. For example, the first line pattern 123 may be disposed on each of the first to eighth sub-areas A2a to A2h of the substrate SUB.

[0172] The first line pattern 123 is a pattern disposed on the second area A2 and connecting the first plate patterns 121 adjacent to each other, and may be referred to as a first connection pattern. That is, at least one first line pattern 123 may be disposed between the first plate patterns 121.

[0173] In one exemplary embodiment, referring to Figure 8 and Fig. 9A , each of the first line patterns 123 has a wavy shape. For example, the first line pattern 123 may have a sinusoidal shape. However, this is merely illustrative, and thus the shape of the first line pattern 123 is not limited thereto. For example, each of the first line patterns 123 may have a zigzag shape. As another example, each of the first line patterns 123 may have various shapes, such as a plurality of rhombus-shaped substrates connected and extending at a vertex. As described above, Figure 8 and Fig. 9A The number and shape of the first line patterns 123 shown are illustrative, and the number and shape of the first line patterns 123 may vary according to design.

[0174] In addition, connection lines 181, 182, and 183 may be disposed above each first line pattern 123. The first line pattern 123 (eg Fig.10 LP) can be used as a supporting connection line (e.g. Fig.10 SD3(CL)) substrate.

[0175] The second line pattern 124 may be disposed on the second area A2 of the substrate SUB. For example, the second line pattern 124 may be disposed over the third sub-area A2c and the fourth sub-area A2d of the substrate SUB, respectively.

[0176] The second line pattern 124 is a pattern disposed on the second area A2 and connecting the second plate patterns 122 adjacent to each other, and may be referred to as a second connection pattern. That is, at least one second line pattern 124 may be disposed between the second plate patterns 122.

[0177] In one exemplary embodiment, referring to Fig. 9A , each second line pattern 124 may have a wavy shape. For example, the second line pattern 124 may have a sine curve shape. However, this is merely illustrative, and thus the shape of the second line pattern 124 is not limited thereto. For example, each second line pattern 124 may have a zigzag shape. As another example, each of the second line patterns 124 may have various shapes, such as a plurality of rhombus-shaped substrates connected and extending at the vertices. As described above, Fig. 9A The number and shape of the second line patterns 124 shown are illustrative, and the number and shape of the second line patterns 124 may vary according to design.

[0178] In addition, a fourth connection line 184 may be disposed on each second line pattern 124. The second line pattern 124 may serve as a substrate supporting the connection line.

[0179] In an exemplary embodiment, the first plate pattern 121, the second plate pattern 122, the first line pattern 123, and the second line pattern 124 are respectively rigid patterns. For example, each of the first plate pattern 121, the second plate pattern 122, the first line pattern 123, and the second line pattern 124 may be harder than the substrate SUB. Therefore, the elastic modulus of the first plate pattern 121, the second plate pattern 122, the first line pattern 123, and the second line pattern 124 may be higher than the elastic modulus of the substrate SUB. The elastic modulus is a parameter indicating the deformation rate against the stress applied to the substrate, and the higher the elastic modulus, the higher the hardness. Therefore, the first plate pattern 121, the second plate pattern 122, the first line pattern 123, and the second line pattern 124 may be referred to as the first to fourth rigid patterns, respectively. For example, each elastic modulus of the first plate pattern 121, the second plate pattern 122, the first line pattern 123, and the second line pattern 124 may be 1000 times higher than the elastic modulus of the substrate SUB, but this is illustrative, and the exemplary embodiments of the present disclosure are not limited thereto.

[0180] In an exemplary embodiment, each of the first plate pattern 121, the second plate pattern 122, the first line pattern 123, and the second line pattern 124 may include a plastic material having lower flexibility than the substrate SUB. For example, each of the first plate pattern 121, the second plate pattern 122, the first line pattern 123, and the second line pattern 124 may include at least one material of polyimide (PI), polyacrylate, and polyacetate.

[0181] According to an exemplary embodiment, the first plate pattern 121, the second plate pattern 122, the first line pattern 123, and the second line pattern 124 may be formed of the same material, but are not limited thereto, and may be formed of different materials. When the first plate pattern 121, the second plate pattern 122, the first line pattern 123, and the second line pattern 124 are formed of the same material, the first plate pattern 121, the second plate pattern 122, the first line pattern 123, and the second line pattern 124 may be formed integrally.

[0182] In an exemplary embodiment, Figure 8 As shown, in the first subregion A2a, the second subregion A2b, the fifth subregion A2e, the sixth subregion A2f, the seventh subregion A2g and the eighth subregion A2h, the first connection line 181 extending along the first direction DR1 and the second connection line 182 extending along the second direction DR2 can be set on the first line pattern 123.

[0183] Here, the first connection line 181 and the second connection line 182 can be connection lines connecting the second pixels PX2 set above the first plate pattern 121, and the first plate pattern 121 is spaced apart from each other on the first sub-area A2a, the second sub-area A2b, the fifth sub-area A2e, the sixth sub-area A2f, the seventh sub-area A2g and the eighth sub-area A2h.

[0184] Furthermore, in one exemplary embodiment, Fig. 9A As shown, in the third and fourth sub-regions A2c and A2d, the third connection lines 183 extending in the second direction DR2 and the fourth connection lines 184 extending in the second direction DR2 may be disposed on the first line pattern 123 .

[0185] Here, the third connection line 183 may be a connection line connecting the second pixel PX2 disposed above the first plate pattern 121 which is spaced apart from each other on the third and fourth sub-areas A2c and A2d.

[0186] In addition, the fourth connection line 184 may be a connection line connecting the gate driver GD disposed over the second plate pattern 122 spaced apart from each other on the third and fourth sub-areas A2c and A2d.

[0187] The sub-pixel SPX may be connected to a plurality of connection lines 181 , 182 , and 183 .

[0188] For example, the sub-pixels SPX included in the second pixels PX2 disposed on the first sub-region A2a, the second sub-region A2b, the fifth sub-region A2e, the sixth sub-region A2f, the seventh sub-region A2g and the eighth sub-region A2h of the second area A2 can be electrically connected to the first connection line 181 extending along the second direction DR2 and the second connection line 182 extending along the first direction DR1.

[0189] As another example, the sub-pixels SPX included in the second pixels PX2 disposed on the third and fourth sub-regions A2c and A2d of the second region A2 may be electrically connected to the third connection line 183 extending in the second direction DR2.

[0190] In an exemplary embodiment, the connection lines 181, 182 and 183 connected to the subpixel SPX may include various wirings such as a gate line (e.g., a scan signal line or a light emission control line), a data line, a high potential voltage line, a low potential voltage line and an initialization voltage line.

[0191] As described above, the gate driver GD is disposed above the second plate pattern 122 on the gate area GIA to provide a gate signal to the pixels PX (eg, the first pixel PX1 and the second pixel PX2). Figure 5 and Fig. 9A As shown, the gate region GIA may be disposed to overlap the first region A1 and a portion of the second region A2 (eg, the third sub-region A2c and the fourth sub-region A2d).

[0192] The gate driver GD includes a plurality of stages respectively formed above the plurality of second plate patterns 122, and each stage included in the gate driver GD may be electrically connected to each other through a plurality of gate connection lines. Therefore, a gate signal output from any one stage may be transmitted to another stage. Each stage may sequentially provide a gate signal to a plurality of pixels PX (e.g., a first pixel PX1 or a second pixel PX2) connected to each stage.

[0193] In addition, the gate driver GD may be connected to the fourth connection line 184 .

[0194] For example, the gate driver GD (eg, the stages included in the gate driver GD) disposed on the third and fourth sub-regions A2c and A2d of the second region A2 may be electrically connected to the fourth connection line 184 extending in the second direction DR2.

[0195] Fig.10 is shown along Figure 5 A cross-sectional view of the example taken along line III-III'.

[0196] To avoid duplication of description, separate the main description with the reference Figures 1 to 9BThe parts not described in detail follow the above exemplary embodiments, and the same reference numerals represent the same parts.

[0197] exist Fig.10 , a cross-sectional structure of the display device 1000 in the second area A2 (e.g., the third sub-area A2c), the connection area CA, and the driving area DA is shown. Here, the driving area DA may correspond to an area where a data driver DD, etc. is disposed, and the connection area CA may refer to an area between the display panel DP and the data driver DD.

[0198] Reference Figures 5 to 10 The pattern layer 120 and various insulating layers (for example, first and second buffer layers BUF1 and BUF2, first and second gate insulating layers GI1 and GI2, first to fourth insulating layers ILD1 to ILD4, and first to third planarizing layers PNL1 to PNL3) may be disposed on the substrate SUB.

[0199] In addition, the transistors TR1 and TR2, the light emitting diode LD, and the encapsulation layers above the light emitting diode LD (for example, the first to third inorganic encapsulation layers PAS1, PAS2, and PAS3 and the first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2) may be disposed on the second area A2 of the substrate SUB or the pattern layer 120. For example, the transistors TR1 and TR2, the light emitting diode LD, and the encapsulation layers above the light emitting diode LD (for example, the first to third inorganic encapsulation layers PAS1, PAS2, and PAS3 and the first organic encapsulation layer PCL1 and the second organic encapsulation layer PCL2) may be disposed on the plate pattern PP of the pattern layer 120. Fig.10 The plate pattern PP shown may be Figure 8 , Fig. 9A and Fig. 9B Described board patterns 121, 121_1 and 122.

[0200] In addition, the data driver DD is disposed on the driving area DA of the driving or pattern layer 120 of the substrate SUB, and the connection signal line CL connecting the display panel DP and the data driver DD may be disposed on the connection area CA of the substrate SUB or the pattern layer 120. For example, the data driver DD may be disposed on the plate pattern PP disposed in the driving area DA of the pattern layer 120, and the connection signal line CL connecting the display panel DP and the data driver DD may be disposed on the line pattern LP disposed on the connection area CA of the pattern layer 120. Fig.10 The line pattern LP shown may be Figure 8 , Fig. 9A and Fig. 9B Line patterns 123 and 124 are described.

[0201] In an exemplary embodiment, at least a portion of the seventh conductive layer SD3 disposed over the second planarization layer PNL2 may extend from the second area A2 (e.g., the third sub-area A2c) to the connection area CA and the driving area DA. At least a portion of the seventh conductive layer SD3 (e.g., the connection signal line CL) may be disposed on the pattern layer 120 (e.g., the line pattern LP) to directly contact the pattern layer 120 (e.g., the line pattern LP) on the connection area CA.

[0202] As described above, in the display device according to the exemplary embodiment of the present disclosure, the gate region configured with various components constituting the gate driver can be configured to overlap at least a portion of the display area (first region or second region) configured with various components constituting the pixel. That is, the gate driver is provided in an array gate (GIA) manner and formed on the gate region, so that the border area of ​​the display device can be reduced or minimized.

[0203] In addition, the display device according to the exemplary embodiment of the present disclosure includes a first area as a central area and a second area as a peripheral area surrounding the first area. The second pixel arranged in the second area can be arranged to have a lower pixel density than the first pixel arranged in the first area. Therefore, in the second area as the peripheral area, the display device can be modified so that the second area as the peripheral area can be configured to have a curved shape.

[0204] Exemplary embodiments of the present disclosure may also be described as follows:

[0205] According to one aspect of the present disclosure, a display device includes a display panel including a plurality of pixels and a substrate divided into a first area disposed in the center and a second area surrounding the first area; a data driver configured to provide a data signal to the pixel through a data line; and a gate driver including a plurality of stages configured to provide a gate signal to the pixel through a gate line. Each of the plurality of stages included in the gate driver is disposed in a gate region, the gate region at least partially overlaps the first region and the second region, the plurality of pixels include a plurality of first pixels disposed on the first region and a plurality of second pixels disposed on the second region, the first pixels may be disposed in the first region at a first density, and the second pixels may be disposed in the second region at a second pixel density lower than the first pixel density.

[0206] The second region may include a first sub-region adjacent to one side of the first region along a first direction, a second sub-region adjacent to another side of the first region along the first direction, a third sub-region adjacent to one side of the first region along a second direction different from the first direction, a fourth sub-region adjacent to another side of the first region along the second direction, a fifth sub-region between the first sub-region and the third sub-region, a sixth sub-region between the first sub-region and the fourth sub-region, a seventh sub-region between the second sub-region and the third sub-region, and an eighth sub-region between the second sub-region and the fourth sub-region.

[0207] The display device may further include a pattern layer disposed on the second region of the substrate, the pattern layer including a plurality of first plate patterns, a plurality of second plate patterns, a plurality of first line patterns, and a plurality of second line patterns.

[0208] In the first, second, fifth, sixth, seventh, and eighth sub-regions, a plurality of first plate patterns may be disposed to be spaced apart from each other, and a plurality of first line patterns connect the first plate patterns adjacent to each other.

[0209] The display device may further include a plurality of connecting lines arranged on the plurality of first line patterns, wherein each of the plurality of second pixels may be arranged above each of the plurality of first plate patterns, and each of the plurality of connecting lines may be arranged above each of the plurality of first line patterns to connect the second pixels in the first, second, fifth, sixth, seventh and eighth sub-regions.

[0210] In the third and fourth sub-regions, a plurality of first plate patterns may be disposed to be spaced apart from each other, and a plurality of first line patterns connect the first plate patterns adjacent to each other in the second direction.

[0211] The display device may further include a plurality of connecting lines disposed on the plurality of first line patterns, and each of the plurality of second pixels may be disposed above each of the plurality of first line patterns, and each of the plurality of connecting lines is disposed above each of the plurality of first line patterns to connect the second pixels in the third and fourth sub-regions.

[0212] In the third and fourth sub-regions, a plurality of second plate patterns may be disposed to be spaced apart from each other, and a plurality of second line patterns connect the second plate patterns adjacent to each other in the second direction.

[0213] The display device may further include a plurality of connection lines disposed on the plurality of second line patterns, and each of the plurality of stages included in the gate driver may be disposed above each of the plurality of second line patterns, and each of the plurality of connection lines may be disposed above each of the plurality of second line patterns to connect the stages in the third and fourth sub-regions.

[0214] The gate region may overlap the first region, the third sub-region, and the fourth sub-region.

[0215] Each of the plurality of second plate patterns and the plurality of second line patterns may be disposed to overlap the gate region.

[0216] The display device may further include a power supply line which is disposed on the gate region and supplies a low potential power supply voltage to the pixel.

[0217] The display panel may include a first buffer layer disposed on a substrate, a first semiconductor layer disposed on the first buffer layer and including a first semiconductor pattern of a first transistor, a first gate insulating layer disposed on the first semiconductor layer, a first conductive layer disposed on the first gate insulating layer and including a first gate of the first transistor, a first insulating layer disposed on the first conductive layer, a second conductive layer disposed on the first insulating layer, a second insulating layer disposed on the second conductive layer, a third conductive layer disposed on the second insulating layer and including a first source and a first drain of the first transistor, and a third insulating layer disposed on the third conductive layer.

[0218] The display panel may further include a second buffer layer disposed on the third insulating layer, a second semiconductor layer disposed on the second buffer layer and including a second semiconductor pattern of a second transistor, a second gate insulating layer disposed on the second semiconductor layer, a fourth conductive layer disposed on the second gate insulating layer and including a second gate of the second transistor, a fourth insulating layer disposed on the fourth conductive layer, and a fifth conductive layer disposed on the fourth insulating layer and including a second source and a second drain of the second transistor.

[0219] The fifth conductive layer may further include a clock line.

[0220] The display panel further includes a first planarization layer disposed on the fifth conductive layer; a sixth conductive layer disposed on the first planarization layer, a second planarization layer disposed on the sixth conductive layer, and a seventh conductive layer disposed on the second planarization layer.

[0221] The substrate may further include a driving region in which the data driver is disposed and a connection region between the second region and the driving region, and the seventh conductive layer extends from the second region to the connection region and the driving region.

[0222] The seventh conductive layer may be in direct contact with the substrate on the connection region.

[0223] The display panel may further include a light emitting diode disposed on the seventh conductive layer and an encapsulation layer disposed on the light emitting diode, and the encapsulation layer may include a first inorganic encapsulation layer disposed on the light emitting diode, a first organic encapsulation layer disposed on the first inorganic encapsulation layer, a second inorganic encapsulation layer disposed on the first organic encapsulation layer, a second organic encapsulation layer disposed on the second inorganic encapsulation layer, and a third inorganic encapsulation layer disposed on the second organic encapsulation layer.

[0224] The display panel may include a light emitting diode, a clock line configured to provide a clock signal to the gate driver, and a shielding pattern disposed between the light emitting diode and the clock line.

[0225] According to one aspect of the present disclosure, a display device includes a display panel including a plurality of pixels and includes a substrate divided into a first area set at the center of the display device and a second area surrounding the first area; a data driver configured to provide data signals to the pixels through data lines; and a gate driver including a plurality of stages configured to provide gate signals to the pixels through gate lines, wherein each of the plurality of stages included in the gate driver is set in each of a plurality of gate areas overlapping the first area and the second area, and the plurality of pixels include a plurality of first pixels set on the first area and a plurality of second pixels set on the second area, wherein the first pixels are set in the first area at a first pixel density, and the second pixels are set in the second area at a second pixel density lower than the first pixel density.

[0226] The display device may further include a plurality of first plate patterns disposed in the second area; and the second pixels are disposed on at least some of the first plate patterns.

[0227] Each of the plurality of gate regions extends along a first direction of the display device, and the plurality of gate regions are spaced apart from each other along a second direction of the display device perpendicular to the first direction; and optionally, wherein the first direction is from top to bottom of the display device.

[0228] The second region may include a plurality of sub-regions, wherein each of the plurality of sub-regions is disposed adjacent to each side of the first region.

[0229] The first plate pattern may be provided in each of the plurality of sub-regions.

[0230] The display device further includes a second plate pattern disposed in some of the plurality of sub-regions opposite to the upper side and the lower side of the first region.

[0231] The gate driver may be disposed on the second plate pattern; and wherein the second plate pattern is disposed between the first plate patterns.

[0232] The first plate pattern and the second plate pattern are integrally arranged in some sub-areas opposite to the upper side and the lower side of the first area among the plurality of sub-areas, and extend in a second direction parallel to the upper side and the lower side of the first area, and are spaced apart from each other in a first direction perpendicular to the second direction.

[0233] The display device further includes at least one first line pattern disposed in the second region to connect each adjacent first plate pattern.

[0234] The display device further includes at least one second line pattern disposed in the second area to connect each adjacent second plate pattern.

[0235] The display device may further include at least one first line pattern and at least one second line pattern, which serve as substrates supporting the connection lines.

[0236] The display device further includes a first conductive layer and a second conductive layer located on a layer between the first and second pixels; and wherein at least a portion of the first conductive layer forms a connection line including a wavy shape.

[0237] At least a portion of the first conductive layer forming the connection line may be directly disposed on the line pattern serving as the substrate.

[0238] At least a portion of the first conductive layer is disposed to form a shielding pattern.

[0239] The shielding pattern is disposed between at least a portion of the third conductive layer serving as the clock line and the anode of the pixel; and a width of the shielding pattern is greater than a width of the anode of the pixel and the pixel.

[0240] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be interpreted as falling within the scope of the present disclosure.

[0241] CROSS-REFERENCE TO RELATED APPLICATIONS

[0242] This application claims the priority of Korean Patent Application No. 10-2023-0115321 filed on August 31, 2023, and Korean Patent Application No. 10-2024-0083837 filed on June 26, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference.

Claims

1. A display device, comprising: a display panel including a plurality of pixels and including a substrate divided into a first area disposed at a center of the display device and a second area surrounding the first area; a data driver configured to provide a data signal to the pixel through a data line; as well as a gate driver including a plurality of stages configured to supply a gate signal to the pixel through a gate line, wherein each of the plurality of stages included in the gate driver is arranged in each of a plurality of gate regions overlapping the first region and the second region, the plurality of pixels include a plurality of first pixels arranged on the first region and a plurality of second pixels arranged on the second region, wherein the first pixels are arranged in the first region at a first pixel density, and the second pixels are arranged in the second region at a second pixel density lower than the first pixel density.

2. The display device according to claim 1, The display device further includes a plurality of first plate patterns disposed in the second area, in, The second pixels are disposed on at least some of the first plate patterns.

3. The display device according to claim 1, in, Each of the plurality of gate regions extends along a first direction of the display device, and the plurality of gate regions are spaced apart from each other along a second direction of the display device that is perpendicular to the first direction; And wherein the first direction is from the top to the bottom of the display device.

4. The display device according to claim 2, in, The second area includes a plurality of sub-areas, Each of the plurality of sub-areas is arranged adjacent to each side of the first area.

5. The display device according to claim 4, in, The first plate pattern is provided in each of the plurality of sub-regions.

6. The display device according to claim 4, The display device further includes a second plate pattern disposed in some of the plurality of sub-regions opposite to upper and lower sides of the first region.

7. The display device according to claim 6, in, The gate driver is disposed on the second plate pattern; and wherein the second plate pattern is disposed between the first plate patterns.

8. The display device according to claim 6, in, The first plate pattern and the second plate pattern are integrally arranged in some sub-areas of the multiple sub-areas opposite to the upper side and the lower side of the first area, and the first plate pattern and the second plate pattern extend in a second direction parallel to the upper side and the lower side of the first area, and are spaced apart from each other in a first direction perpendicular to the second direction.

9. The display device according to claim 2, The display device further includes at least one first line pattern disposed in the second region to connect each adjacent first plate pattern.

10. The display device according to claim 9, The display device further includes at least one second line pattern disposed in the second region to connect each adjacent second plate pattern.

11. The display device according to claim 1, The display device further includes at least one first line pattern and at least one second line pattern, the at least one first line pattern and the at least one second line pattern serving as a substrate supporting the connection line.

12. The display device according to claim 1, The display device further includes a first conductive layer and a second conductive layer located on a layer between the first pixel and the second pixel, in, At least a portion of the first conductive layer forms a connection line including a wavy shape.

13. The display device according to claim 12, in, At least a portion of the first conductive layer forming the connection line is directly disposed on a line pattern serving as a substrate.

14. The display device according to claim 12, in, The at least a portion of the first conductive layer is disposed to form a shielding pattern.

15. The display device according to claim 14, in, The shield pattern is disposed between at least a portion of the third conductive layer as a clock line and the anode of the pixel; and Wherein, the width of the shielding pattern is greater than the width of the anode of the pixel.

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