Pixel circuit, display panel and display device thereof

Abstract

The embodiment of the utility model provides a pixel circuit, a display panel and a display device thereof, relates to the technical field of display, and is used for improving the pixel density and resolution of the display panel. The pixel circuit comprises a driving sub-circuit and a gating sub-circuit. The driving sub-circuit is connected with the first node, the second node and the third node. And the driving sub-circuit is configured to generate a driving current signal according to the voltage of the first node and the third node in a light emitting stage, and transmit the driving current signal to the third node. The gating sub-circuit is connected with the third node. The gating sub-circuit is configured to connect a plurality of light-emitting devices and transmit the driving current signal from the third node to different light-emitting devices in different light-emitting stages. Wherein the driving sub-circuit comprises a first transistor, the gating sub-circuit comprises a second transistor, and a channel of at least one second transistor and a channel of the first transistor are located in different layers and are at least partially opposite to each other. The pixel circuit is used for the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a display panel, and a display device thereof. Background Art

[0002] With the rapid development of display technologies, display devices have gradually become ubiquitous in people's lives. Among them, Organic Light Emitting Diode (OLED for short) has been widely used in intelligent products such as mobile phones, televisions, and laptop computers due to its advantages of self-luminescence, low power consumption, wide viewing angle, fast response speed, high contrast, and flexible display.

[0003] In related technologies, the display panel cannot achieve a higher Pixel Per Inch (PPI), and thus cannot meet the growing demand for resolution from users. Summary of the Utility Model

[0004] The purpose of the embodiments of the present disclosure is to provide a pixel circuit, a display panel, and a display device thereof, which are used to increase the pixel density and resolution of the display panel and meet the growing demand for resolution from users.

[0005] To achieve the above purpose, the embodiments of the present disclosure provide the following technical solutions:

[0006] On the one hand, a pixel circuit is provided. A frame period includes a plurality of sub-segments that are sequentially performed, and each of the sub-segments includes a light-emitting stage. The pixel circuit includes a driving sub-circuit and a gating sub-circuit. The driving sub-circuit is connected to a first node, a second node, and a third node. The first node is coupled to a data signal terminal, and the second node is coupled to a first power signal terminal. The driving sub-circuit is configured to generate a driving current signal according to the voltages of the first node and the third node during the light-emitting stage, and transmit the driving current signal to the third node. The gating sub-circuit is connected to the third node. The gating sub-circuit is configured to connect a plurality of light-emitting devices, and transmit the driving current signal from the third node to different light-emitting devices during different light-emitting stages. Wherein, the driving sub-circuit includes a first transistor, the gating sub-circuit includes a second transistor, the channels of at least one of the second transistors are located in different layers and at least partially opposite to the channel of the first transistor.

[0007] The pixel circuit provided by the embodiments of the present disclosure enables multiple light-emitting devices to be coupled to the same pixel circuit to form multiple sub-pixels. Among them, the light-emitting devices of the multiple sub-pixels can at least share one driving sub-circuit to generate a driving current signal. That is, the multiple sub-pixels share one driving sub-circuit, which can save the number of driving sub-circuits and compress the area occupied by the pixel circuits of the multiple sub-pixels, so that more sub-pixels can be arranged per unit area of the display panel, thereby improving the pixel density and resolution of the display panel and meeting the user's demand for increased resolution.

[0008] In some embodiments, the gating sub-circuit includes multiple gating branches, the gating branches are coupled to the third node, the fourth node, and the first light-emitting control signal terminal, and the fourth nodes and the first light-emitting control signal terminals coupled by different gating branches are different. The fourth node is configured to be coupled to the light-emitting device, and the light-emitting devices coupled to different fourth nodes are different. The gating branch is configured to transmit the driving current signal of the third node to the fourth node in response to the light-emitting control signal received at the first light-emitting control signal terminal during one light-emitting stage of one frame period.

[0009] In some embodiments, the gating branch includes the second transistor, the control electrode of the second transistor is coupled to the first light-emitting control signal terminal, the first electrode is coupled to the third node, and the second electrode is coupled to the fourth node.

[0010] In some embodiments, the sub-segment includes a reset stage, the reset stage is located before the light-emitting stage, the pixel circuit further includes a reset sub-circuit, the reset sub-circuit is coupled to the reset signal terminal and the initialization signal terminal, and is also coupled to the third node and / or the fourth node. The reset sub-circuit is configured to transmit the initialization signal received at the initialization signal terminal to the third node and / or the fourth node in response to the reset signal received at the reset signal terminal during the reset stage.

[0011] In some embodiments, the reset sub-circuit includes a third transistor, the control electrode of the third transistor is coupled to the reset signal terminal, the first electrode is coupled to the initialization signal terminal, and the second electrode is coupled to the third node. The channel of the third transistor and the channel of the first transistor are located in the same layer, and the channels of at least one of the second transistors and the third transistor are at least partially opposite.

[0012] In some embodiments, the gating sub - circuit includes two gating branches, and each gating branch includes a second transistor. Among the two second transistors included in the two gating branches, the channel of one second transistor is at least partially opposite to the channel of the first transistor, and the channel of the other second transistor is at least partially opposite to the channel of the third transistor.

[0013] In some embodiments, the sub - segment further includes a data writing stage, the data writing stage is located before the light - emitting stage, and the pixel circuit further includes a data writing sub - circuit, and the data writing sub - circuit is coupled to the first scan signal terminal, the data signal terminal, and the first node. The data writing sub - circuit is configured to, in the data writing stage, in response to the first scan signal received at the first scan signal terminal, transmit the data signal received at the data signal terminal to the first node.

[0014] In some embodiments, the sub - segment further includes a compensation stage, and the compensation stage is located before the data writing stage. The driving sub - circuit is further configured to, in the compensation stage, under the control of the voltages of the first node and the third node, transmit the voltage of the second node to the third node until the voltage difference between the first node and the third node is equal to the threshold voltage of the first transistor included in the driving sub - circuit.

[0015] The pixel circuit further includes a first energy - storage sub - circuit, and the first energy - storage sub - circuit is coupled to the first node and the third node. The first energy - storage sub - circuit is configured to, in the light - emitting stage, according to the change in the voltage of the third node, raise or lower the voltage of the first node to maintain the voltage difference between the first node and the third node unchanged.

[0016] In some embodiments, the data writing sub - circuit is further configured to, in the compensation stage, in response to the first scan signal received at the first scan signal terminal, transmit the data signal received at the data signal terminal to the first node.

[0017] In some embodiments, the pixel circuit further includes a first voltage sub - circuit, and the first voltage sub - circuit is coupled to the second scan signal terminal, the first voltage signal terminal, and the first node. The first voltage sub - circuit is configured to, in the compensation stage, in response to the second scan signal received at the second scan signal terminal, transmit the first voltage signal received at the first voltage signal terminal to the first node.

[0018] In some embodiments, the data writing sub-circuit includes a fourth transistor. The control electrode of the fourth transistor is coupled to the first scan signal terminal, the first electrode is coupled to the data signal terminal, and the second electrode is coupled to the first node. The channel of the fourth transistor and the channel of the first transistor are located in the same layer.

[0019] In some embodiments, the pixel circuit includes a reset sub-circuit, and the reset sub-circuit includes a third transistor. Along a first direction, the channel of the third transistor and the channel of the fourth transistor are located on opposite sides of the channel of the first transistor.

[0020] In some embodiments, the pixel circuit includes a first voltage sub-circuit, and the first voltage sub-circuit includes a fifth transistor. The control electrode of the fifth transistor is coupled to the second scan signal terminal, the first electrode is coupled to the first voltage signal terminal, and the second electrode is coupled to the first node. The channel of the fifth transistor and the channel of the fourth transistor are located in different layers and at least partially opposite to each other.

[0021] On the other hand, a display panel is provided. A frame period includes a plurality of sub-segments that are sequentially performed, and each of the sub-segments includes a light-emitting stage. The display panel includes a driving circuit layer and a light-emitting device layer.

[0022] The driving circuit layer includes a plurality of pixel circuits. The pixel circuit includes a driving sub-circuit and a gating sub-circuit. The driving sub-circuit is coupled to a first node, a second node, and a third node. The first node is coupled to the data signal terminal, the second node is coupled to the first power supply signal terminal; the gating sub-circuit is coupled to the third node. The driving sub-circuit includes a first transistor, the gating sub-circuit includes a second transistor, and the channels of at least one of the second transistors and the channel of the first transistor are located in different layers and at least partially opposite to each other.

[0023] The light-emitting device layer is disposed on one side of the driving circuit layer. The light-emitting device layer includes a plurality of light-emitting devices. The light-emitting devices are coupled to the gating sub-circuit, and at least two of the light-emitting devices are coupled to the same gating sub-circuit. The gating sub-circuit is configured to transmit the driving current signal from the third node to different light-emitting devices during different light-emitting stages.

[0024] In some embodiments, the pixel circuit includes a reset sub-circuit. The reset sub-circuit is connected to a reset signal terminal and an initialization signal terminal, and is also coupled to the third node.

[0025] The display panel further includes an initialization signal line, which is coupled to the initialization signal terminal. The initialization signal line includes a plurality of first sub-lines and a plurality of second sub-lines. The first sub-lines extend in a first direction, and the second sub-lines extend in a second direction. Wherein, one of the first sub-lines is connected to the plurality of second sub-lines, and one of the second sub-lines is connected to the plurality of first sub-lines. The first direction and the second direction intersect.

[0026] The display panel further includes a first power supply line, which is coupled to the first power supply signal terminal. The first power supply line includes a plurality of third sub-lines and a plurality of fourth sub-lines. The third sub-lines extend in the first direction, and the fourth sub-lines extend in the second direction. Wherein, one of the third sub-lines is connected to the plurality of fourth sub-lines, and one of the fourth sub-lines is connected to the plurality of third sub-lines. Moreover, the third sub-lines are arranged staggeredly with respect to the first sub-lines, and the fourth sub-lines are arranged staggeredly with respect to the second sub-lines.

[0027] In some embodiments, the pixel circuit includes a reset sub-circuit, which is connected to the reset signal terminal and the initialization signal terminal, and is also coupled to a fourth node.

[0028] The display panel further includes an initialization signal line, which is coupled to the initialization signal terminal. The initialization signal line includes a plurality of first sub-lines and a plurality of second sub-lines. The first sub-lines extend in a first direction, and the second sub-lines extend in a second direction. Wherein, one of the first sub-lines is connected to the plurality of second sub-lines, and one of the second sub-lines is connected to the plurality of first sub-lines. The first direction and the second direction intersect.

[0029] The display panel further includes a first power supply line, which is coupled to the first power supply signal terminal. The first power supply line includes a plurality of third sub-lines and a plurality of fourth sub-lines. The third sub-lines extend in the first direction, and the fourth sub-lines extend in the second direction. Wherein, one of the third sub-lines is connected to the plurality of fourth sub-lines, and one of the fourth sub-lines is connected to the plurality of third sub-lines. Moreover, the third sub-lines are arranged staggeredly with respect to the first sub-lines, and the fourth sub-lines are arranged staggeredly with respect to the second sub-lines.

[0030] In some embodiments, the display panel includes 10 conductive layers, and the driving circuit layer includes 8 conductive layers. Or, the display panel includes 9 conductive layers, and the driving circuit layer includes 7 conductive layers. Or, the display panel includes 8 conductive layers, and the driving circuit layer includes 6 conductive layers.

[0031] In some embodiments, the pixel circuit includes a data writing sub-circuit, and the data writing sub-circuit is coupled to a first scan signal terminal, a data signal terminal, and a first node. The display panel includes a first source-drain conductive layer, and the first source-drain conductive layer includes data lines, and the data lines are coupled to the data signal terminals.

[0032] The driving circuit layer includes a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, and a third gate conductive layer. The first semiconductor layer includes a first channel portion and a first conductive portion. The first gate conductive layer is disposed on a side of the first semiconductor layer close to the light-emitting device layer. The first gate conductive layer includes a reset signal line and a first scan signal line, the reset signal line and the first scan signal line extend along the second direction, and the reset signal line and the first scan signal line respectively overlap with the first channel portion of the first semiconductor layer. The second gate conductive layer is disposed on a side of the first gate conductive layer close to the light-emitting device layer. The second gate conductive layer includes a second conductive block. The third gate conductive layer is disposed on a side of the second gate conductive layer close to the light-emitting device layer.

[0033] In some embodiments, the first gate conductive layer further includes a first conductive block, the first conductive block overlaps with the first channel portion of the first semiconductor layer, and the second conductive block is at least partially opposite to the first conductive block.

[0034] In some embodiments, the third gate conductive layer further includes a third conductive block, and the third conductive block is at least partially opposite to the second conductive block.

[0035] In some embodiments, the display panel further includes an initialization signal line and a first power supply line. The initialization signal line includes a first sub-line and a second sub-line, and the first power supply line includes a third sub-line and a fourth sub-line. The first sub-line is located in the first source-drain conductive layer. The second sub-line is located in the second gate conductive layer, and the third sub-line and the fourth sub-line are located in the third gate conductive layer.

[0036] In some embodiments, the display panel further includes an initialization signal line and a first power supply line. The initialization signal line includes a first sub-line and a second sub-line, and the first power supply line includes a third sub-line and a fourth sub-line. The first sub-line and the third sub-line are located in the first source-drain conductive layer, and the second sub-line and the fourth sub-line are located in the second gate conductive layer.

[0037] In some embodiments, the reset signal line and the first scan signal line extend along the second direction, and two reset signal lines are located between two first scan signal lines.

[0038] In some embodiments, the second sub-line is located between two adjacent reset signal lines.

[0039] In some embodiments, the fourth sub - line is located between the reset signal line and the first scan signal line.

[0040] In some embodiments, the driving circuit layer includes a first sub - driving layer, and the first sub - driving layer includes a first transistor. The second sub - driving layer is disposed between the first sub - driving layer and the light - emitting device layer. The second sub - driving layer includes a second transistor, and the channels of at least one second transistor are at least partially opposite to the channels of the first transistor.

[0041] In some embodiments, the pixel circuit includes a data - writing sub - circuit, and the data - writing sub - circuit is coupled to a first scan signal terminal, a data signal terminal, and a first node. The display panel further includes a first source - drain conductive layer, and the first source - drain conductive layer is disposed between the first sub - driving layer and the second sub - driving layer. The first source - drain conductive layer includes a data line, and the data line is coupled to the data signal terminal.

[0042] In some embodiments, the first sub - driving layer includes a second gate conductive layer, and the second gate conductive layer includes a second conductive block. The second sub - driving layer includes a fourth gate conductive layer and a second semiconductor layer. The fourth gate conductive layer includes a first transfer block, and the first transfer block is connected to the second conductive block. The second semiconductor layer is disposed on a side of the fourth gate conductive layer away from the first sub - driving layer. The second semiconductor layer includes a second channel portion, a second conductive portion, and a first connection column. The first connection column is located between the second conductive portion and the first transfer block and is in electrical contact with the second conductive portion and the first transfer block.

[0043] In some embodiments, the first sub - driving layer includes a second gate conductive layer, and the second gate conductive layer includes a second conductive block. The second sub - driving layer includes a fourth gate conductive layer, a second semiconductor layer, and a second source - drain conductive layer. The fourth gate conductive layer includes a first transfer block, and the first transfer block is connected to the second conductive block. The second semiconductor layer is disposed on a side of the fourth gate conductive layer away from the first sub - driving layer. The second semiconductor layer includes a second channel portion and a second conductive portion.

[0044] The second source - drain conductive layer is disposed on a side of the second semiconductor layer away from the first sub - driving layer. The second source - drain conductive layer includes a third transfer block and a second connection column. A part of the second connection column is offset from the second channel portion and the second conductive portion and is located between the third transfer block and the first transfer block and is in electrical contact with the third transfer block and the first transfer block. Another part is located between the third transfer block and the second conductive portion and is in electrical contact with the third transfer block and the second conductive portion.

[0045] In some embodiments, the first sub-driving layer includes a second gate conductive layer, and the second gate conductive layer includes a second conductive block. The second sub-driving layer includes a fourth gate conductive layer, a second semiconductor layer, and a second source-drain conductive layer. The fourth gate conductive layer includes a first transfer block, and the first transfer block is connected to the second conductive block. The second semiconductor layer is disposed on a side of the fourth gate conductive layer away from the first sub-driving layer. The second semiconductor layer includes a second channel portion and a second conductive portion.

[0046] The second source-drain conductive layer is disposed on a side of the second semiconductor layer away from the first sub-driving layer. The second source-drain conductive layer includes a fourth transfer block, a third connection column, and a fourth connection column, and the third connection column and the fourth connection column are spaced apart. Wherein, the third connection column is staggered from the second channel portion and the second conductive portion, and is located between the fourth transfer block and the first transfer block, and is in electrical contact with the fourth transfer block and the first transfer block. The fourth connection column is located between the fourth transfer block and the second conductive portion, and is in electrical contact with the fourth transfer block and the second conductive portion.

[0047] In some embodiments, the second sub-driving layer further includes a fifth gate conductive layer, the fifth gate conductive layer is disposed on a side of the fourth gate conductive layer away from the first sub-driving layer, and the second semiconductor layer is disposed on a side of the fifth gate conductive layer away from the first sub-driving layer. The fifth gate conductive layer includes a second scan signal line and a first light-emitting control signal line, the second scan signal line and the first light-emitting control signal line extend along the second direction, and respectively overlap with the second channel portion of the second semiconductor layer.

[0048] In some embodiments, the second sub-driving layer further includes a sixth gate conductive layer, the sixth gate conductive layer is disposed on a side of the second semiconductor layer away from the first sub-driving layer. The sixth gate conductive layer includes a second scan signal line and a first light-emitting control signal line, the second scan signal line and the first light-emitting control signal line extend along the second direction, and respectively overlap with the second channel portion of the second semiconductor layer.

[0049] In some embodiments, at least 4 of the first light-emitting control signal lines are located between two of the second scan signal lines.

[0050] In some embodiments, the display panel includes a reset signal line and a first scan signal line, and the reset signal line and the first scan signal line extend along the second direction. The second scan signal line at least partially overlaps with the first scan signal line. The reset signal line is located between two adjacent first light-emitting control signal lines that are connected to the first light-emitting control signal terminals of different pixel circuits.

[0051] In some embodiments, the display panel further includes a first power line, the first power line includes a third sub-line and a fourth sub-line, and the fourth sub-line is located between the adjacent first light-emitting control signal line and the second scanning signal line.

[0052] In some embodiments, the first sub-driving layer includes a first semiconductor layer, and the material of the first semiconductor layer includes an oxide or low-temperature polycrystalline silicon. The second sub-driving layer includes a second semiconductor layer, and the material of the second semiconductor layer includes an oxide or low-temperature polycrystalline silicon.

[0053] In some embodiments, the materials of the first semiconductor layer and the second semiconductor layer include oxides.

[0054] In some embodiments, the difference between the number of transistors included in the first sub-driving layer and the number of transistors included in the second sub-driving layer is 0 or 1.

[0055] In some embodiments, the driving circuit layer includes a plurality of the pixel circuits, the plurality of pixel circuits are arranged in multiple rows and multiple columns, each column includes at least two of the pixel circuits arranged in a first direction, each row includes at least two of the pixel circuits arranged in a second direction, and the first direction intersects the second direction. Moreover, in the first direction and / or the second direction, any two adjacent pixel circuits are symmetrically arranged.

[0056] In some embodiments, a plurality of the light-emitting devices are arranged in multiple rows and multiple columns, each column includes at least two of the light-emitting devices arranged in a first direction, each row includes at least two light-emitting devices arranged in a second direction, and the first direction intersects the second direction. Moreover, a plurality of the light-emitting devices connected to the same gating sub-circuit are located in the same column.

[0057] In some embodiments, the gating sub-circuit includes a plurality of gating branches, the gating branches are connected to the third node, the fourth node, and the first light-emitting control signal terminal, the fourth node is connected to the light-emitting device, and the fourth nodes connected by different gating branches are connected to different light-emitting devices.

[0058] The display panel further includes a first gate driving circuit and a first light emission control signal line. The first light emission control signal line is connected to the first gate driving circuit. Along the first direction, a plurality of the first light emission control signal lines are divided into a plurality of first light emission control signal line groups, and each first light emission control signal line group includes at least two adjacent first light emission control signal lines. Moreover, the first light emission control signal ends of a plurality of selection branches in one row of the pixel circuits are respectively connected to a plurality of first light emission control signal lines in one first light emission control signal line group.

[0059] A plurality of the first light emission control signal lines in the first light emission control signal line group are respectively connected to a plurality of the first gate driving circuits. Moreover, along the first direction, in any two adjacent first light emission control signal line groups, the number of first light emission control signal lines between two first light emission control signal lines connected to the same first gate driving circuit is the same.

[0060] In some embodiments, multiple columns of the light emitting devices include a first type of light emitting device column and a second type of light emitting device column. The light emitting colors of at least two light emitting devices in the first type of light emitting device column are different. The light emitting devices in the second type of light emitting device column have the same light emitting color.

[0061] In some embodiments, the first type of light emitting device column includes a plurality of red light emitting devices and a plurality of blue light emitting devices, and the plurality of red light emitting devices and the plurality of blue light emitting devices are arranged alternately. The second type of light emitting device column includes a plurality of green light emitting devices.

[0062] Alternatively, the first type of light emitting device column includes a plurality of red light emitting devices and a plurality of green light emitting devices, and the plurality of red light emitting devices and the plurality of green light emitting devices are arranged alternately. The second type of light emitting device column includes a plurality of blue light emitting devices.

[0063] In some embodiments, the display panel further includes a pixel defining layer, and the pixel defining layer is provided with a plurality of pixel openings, and one light emitting device is located in one pixel opening. The shape of the pixel opening is generally quadrilateral or elliptical.

[0064] In some embodiments, the light emitting device includes a first electrode, a light emitting portion, and a second electrode. The first electrode and the second electrode are located on opposite sides of the light emitting portion, and the first electrode is located on the side of the light emitting portion close to the driving circuit layer. The first electrode includes a main body portion and a lapping portion. At least part of the main body portion is exposed by the pixel opening, and the lapping portion is connected to the second pole of the second transistor through a connection hole.

[0065] In some embodiments, two adjacent columns of light-emitting devices are a first column of light-emitting devices and a second column of light-emitting devices. In the first column of light-emitting devices, along the first direction, the overlapping portion is located on a first side of the main body portion. In the second column of light-emitting devices, along the first direction, the overlapping portion is located on a second side of the main body portion. The first side and the second side are opposite sides of the main body portion.

[0066] In some embodiments, the ratio of the area of the main body portion to the area of the pixel opening is 0.7 to 0.9.

[0067] In some embodiments, in any direction parallel to the pixel defining layer, the ratio of the size of the connection hole to the size of the pixel opening is 0.5 to 0.9.

[0068] In some embodiments, the display panel includes a plurality of gate lines, and the plurality of gate lines include at least one of a first light-emitting control signal line, a first scan signal line, a second scan signal line, and a reset signal line. Along a direction perpendicular to the extension direction of the gate line, the ratio of the size of the gate line to the size of the pixel opening is 0.5 to 1.2.

[0069] In another aspect, a display panel is provided. The display panel includes a driving circuit layer, a light-emitting device layer, and a pixel defining layer.

[0070] The driving circuit layer includes a plurality of pixel circuits, and the pixel circuits include a common sub-circuit. The common sub-circuit is coupled to a data signal terminal, a first power signal terminal, and a third node. The common sub-circuit is configured to generate a driving current signal during the light-emitting stage and transmit the driving current signal to the third node.

[0071] The light-emitting device layer is disposed on one side of the driving circuit layer. The light-emitting device layer includes a plurality of light-emitting devices. The light-emitting devices are coupled to the common sub-circuit, and at least two of the light-emitting devices are coupled to the same common sub-circuit. The light-emitting device includes a first electrode, and the first electrode includes a main body portion and an overlapping portion. The overlapping portion is connected to the pixel circuit through a connection hole.

[0072] The pixel defining layer is disposed on one side of the driving circuit layer. The pixel defining layer is provided with a plurality of pixel openings. One light-emitting device is located in one pixel opening, and the pixel opening exposes at least a part of the main body portion. Along a first direction, the connection hole is at least partially opposite to the pixel opening.

[0073] In some embodiments, the common sub - circuit includes a driving sub - circuit, the driving sub - circuit is coupled to a first node, a second node, and the third node; the first node is coupled to the data signal terminal, the second node is coupled to the first power signal terminal; the driving sub - circuit is configured to, in the light - emitting stage, generate a driving current signal according to the voltages of the first node and the third node, and transmit the driving current signal to the third node.

[0074] In some embodiments, the common sub - circuit further includes a reset sub - circuit, the reset sub - circuit is coupled to the third node, a reset signal terminal, and an initialization signal terminal. The reset sub - circuit is configured to, in the reset stage, in response to the reset signal received at the reset signal terminal, transmit the initialization signal received at the initialization signal terminal to the third node.

[0075] In some embodiments, the common sub - circuit further includes a data writing sub - circuit, the data writing sub - circuit is coupled to a first scan signal terminal, the data signal terminal, and the first node. The data writing sub - circuit is configured to, in the data writing stage, in response to the first scan signal received at the first scan signal terminal, transmit the data signal received at the data signal terminal to the first node.

[0076] In some embodiments, the common sub - circuit further includes a first energy storage sub - circuit, the first energy storage sub - circuit is coupled to the first node and the third node. The first energy storage sub - circuit is configured to, in the light - emitting stage, according to the change in the voltage of the third node, raise or lower the voltage of the first node to maintain the voltage difference between the first node and the third node unchanged.

[0077] In some embodiments, the common sub - circuit further includes a first voltage sub - circuit, the first voltage sub - circuit is coupled to a second scan signal terminal, a first voltage signal terminal, and the first node; the first voltage sub - circuit is configured to, in the compensation stage, in response to the second scan signal received at the second scan signal terminal, transmit the first voltage signal received at the first voltage signal terminal to the first node.

[0078] In another aspect, a display device is provided. The display device is any one of a wearable device, a virtual reality device, and an augmented reality device. The display device includes a display panel and a circuit board as described in any of the above embodiments, and the circuit board is connected to the display panel.

[0079] The above - mentioned display panel and its display device have the same structure and beneficial technical effects as the pixel circuit provided in the above - mentioned some embodiments, and will not be elaborated here. Description of the Drawings

[0080] To more clearly illustrate the technical solutions in the present disclosure, the accompanying drawings required for some embodiments of the present disclosure will be briefly introduced below. Obviously, the accompanying drawings in the following description are only the accompanying drawings of some embodiments of the present disclosure. For those of ordinary skill in the art, other accompanying drawings can also be obtained based on these drawings. In addition, the accompanying drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual dimensions of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0081] Figure 1 Structural diagram of a display device according to some embodiments;

[0082] Figure 2 Structural diagram of another display device according to some embodiments;

[0083] Figure 3 is Figure 1 A cross-sectional view taken along the section line A-A in;

[0084] Figure 4 Structural diagram of a display panel according to some embodiments;

[0085] Figure 5 Cross-sectional view of a display panel according to some embodiments;

[0086] Figure 6 Structural block diagram of a pixel circuit according to some embodiments;

[0087] Figure 7 Circuit diagram of a pixel circuit according to some embodiments;

[0088] Figure 8 is Figure 7 Timing diagram of the pixel circuit shown;

[0089] Fig. 9 Circuit diagram of another pixel circuit according to some embodiments;

[0090] Fig.10 is Fig. 9 Timing diagram of the pixel circuit shown;

[0091] Fig.11 Circuit diagram of yet another pixel circuit according to some embodiments;

[0092] Fig.12 Circuit diagram of yet another pixel circuit according to some embodiments;

[0093] Fig.13A is Fig.11 Timing diagram of a pixel circuit shown;

[0094] Fig. 13B Another timing diagram of the pixel circuit shown in Fig.11 Figure

[0095] Fig.14 Another timing diagram of the pixel circuit shown in Fig.12 Figure

[0096] Fig.15A A circuit diagram of another pixel circuit according to some embodiments;

[0097] Fig. 15B Another current flow diagram of the pixel circuit shown in Fig.15A Figure

[0098] Fig.16 Another timing diagram of the pixel circuit shown in Fig. 15B Figure

[0099] Fig.17 A circuit diagram of another pixel circuit according to some embodiments;

[0100] Fig.18 A circuit diagram of another pixel circuit according to some embodiments;

[0101] Fig.19 Another timing diagram of the pixel circuit shown in Fig.18 Figure

[0102] Fig. 20 A top view of the driving circuit layer of a display panel according to some embodiments;

[0103] Fig.21 A structural diagram of the first semiconductor layer of a display panel according to some embodiments;

[0104] Fig. 22 A structural diagram of the first gate conductive layer of a display panel according to some embodiments;

[0105] Fig.23 A structural diagram of the second gate conductive layer of a display panel according to some embodiments;

[0106] Fig.24 A structural diagram of the stack of the first semiconductor layer, the first gate conductive layer and the second gate conductive layer of a display panel according to some embodiments;

[0107] Fig.25 A structural diagram of the third gate conductive layer of a display panel according to some embodiments;

[0108] Fig.26 A structural diagram of the first source-drain conductive layer of a display panel according to some embodiments;

[0109] Fig. 27 Structural diagram of the stacked second gate conductive layer, third gate conductive layer and first source-drain conductive layer of a display panel according to some embodiments;

[0110] Fig.28 Structural diagram of the first gate conductive layer of another display panel according to some embodiments;

[0111] Fig.29 Structural diagram of the second gate conductive layer of another display panel according to some embodiments;

[0112] Fig.30 Structural diagram of the third gate conductive layer of another display panel according to some embodiments;

[0113] Fig.31 Structural diagram of the first source-drain conductive layer of another display panel according to some embodiments;

[0114] Fig.32 Structural diagram of the stacked first semiconductor layer, first gate conductive layer and second gate conductive layer of another display panel according to some embodiments;

[0115] Fig.33 Structural diagram of the stacked second gate conductive layer, third gate conductive layer and first source-drain conductive layer of another display panel according to some embodiments;

[0116] Fig.34 Structural diagram of the fourth gate conductive layer of a display panel according to some embodiments;

[0117] Fig.35 Structural diagram of the stacked first semiconductor layer, first gate conductive layer, second gate conductive layer and fourth gate conductive layer of a display panel according to some embodiments;

[0118] Fig.36 Cross-sectional view of the stacked first sub-driving layer, first source-drain conductive layer and fourth gate conductive layer of a display panel according to some embodiments;

[0119] Fig.37 Cross-sectional view of the stacked first sub-driving layer, first source-drain conductive layer and fourth gate conductive layer of another display panel according to some embodiments;

[0120] Fig.38A Structural diagram of the fifth gate conductive layer of a display panel according to some embodiments;

[0121] Fig.38B Structural diagram of multiple gate lines of a display panel according to some embodiments;

[0122] Fig.39Structural diagram of the second semiconductor layer of a display panel according to some embodiments;

[0123] Fig.40 Structural diagram of the sixth gate conductive layer of a display panel according to some embodiments;

[0124] Fig.41 Structural diagram of the second source-drain conductive layer of a display panel according to some embodiments;

[0125] Fig.42A Structural diagram of the stack of the first electrode layer and the light-emitting functional layer of a display panel according to some embodiments;

[0126] Fig.42B Structural diagram of a first electrode of a display panel according to some embodiments;

[0127] Fig.42C Structural diagram of another first electrode of a display panel according to some embodiments;

[0128] Fig.43 Structural diagram of the second sub-driving layer of a display panel according to some embodiments;

[0129] Fig.44 Cross-sectional view of the second sub-driving layer of a display panel according to some embodiments;

[0130] Fig.45 Cross-sectional view of the second sub-driving layer of another display panel according to some embodiments;

[0131] Fig.46 Cross-sectional view of the second sub-driving layer of yet another display panel according to some embodiments;

[0132] Fig.47 Structural diagram of another display panel according to some embodiments;

[0133] Fig.48 Structural diagram of yet another display panel according to some embodiments. Detailed implementation manners

[0134] Next, in conjunction with the drawings, the technical solutions in some embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope protected by the present disclosure.

[0135] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms such as the third-person singular form "comprises" and the present participle form "comprising" are construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples", etc. are intended to indicate that the specific features, structures, materials, or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described above may be included in any one or more embodiments or examples in any suitable manner.

[0136] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0137] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "coupling" may also refer to the situation where two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0138] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0139] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0140] As used herein, depending on context, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting". Similarly, depending on context, the phrase "if determined" or "if [stated condition or event] is detected" is optionally interpreted to mean "when determining" or "in response to determining" or "when [stated condition or event] is detected" or "in response to detecting [stated condition or event]".

[0141] The use of "configured to" or "adapted to" in this document means open and inclusive language that does not exclude devices that are configured to or adapted to perform additional tasks or steps.

[0142] Additionally, the use of "based on" means open and inclusive because a process, step, calculation, or other action "based on" one or more of the stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0143] Taking into account the measurements being discussed and the errors associated with a particular quantity of measurements (i.e., the limitations of the measurement system), as used herein, "about", "approximate", or "substantially" includes the stated value and means within an acceptable deviation for a particular value as determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0144] As used herein, "parallel", "perpendicular", "equal" include the stated cases as well as cases similar to the stated cases, where the similar cases are within an acceptable deviation range, and the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurements being discussed and the errors associated with a particular quantity of measurements (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, the difference between the two equal values is less than or equal to 5% of either one.

[0145] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0146] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations resulting from, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0147] In this specification, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. It will be further understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0148] In this disclosure, terms such as "lower", "below", "upper", and "above" are used to explain the relational associations of components shown in the drawings. The terms can be relative concepts and are described based on the directions shown in the drawings, or can also be described based on the order of formation of process steps, but are not limited thereto.

[0149] The term "opposite" means that a first element can be directly or indirectly opposite a second element. In the case where a third element is between the first element and the second element, although still opposite to each other, the first element and the second element can be understood as being indirectly opposite to each other.

[0150] In the embodiments of this disclosure, the transistors employed can be thin film transistors (Thin Film Transistor, abbreviated as TFT), metal oxide semiconductor field effect transistors (abbreviated as MOS), or other switching devices with the same characteristics. In the embodiments of this disclosure, thin film transistors are taken as examples for illustration.

[0151] In an embodiment of the present disclosure, the control electrode of each thin-film transistor employed is the gate of the transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. Since the source and drain of the thin-film transistor can be symmetric in structure, there may be no difference between the source and drain in structure, that is to say, there may be no difference between the first electrode and the second electrode of the thin-film transistor in the embodiment of the present disclosure in structure. Exemplarily, when the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; Exemplarily, when the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0152] In an embodiment of the present disclosure, the capacitor may be a capacitor device fabricated separately through a process, for example, by fabricating dedicated capacitive electrodes to implement the capacitor device, and each capacitive electrode of the capacitor may be implemented through a metal layer, a semiconductor layer (such as doped polysilicon), etc. The capacitor may also be a parasitic capacitance between transistors, or be implemented through the transistor itself and other devices or circuits, or utilize the parasitic capacitance between the circuits of the circuit itself.

[0153] In the embodiment of the present disclosure, nodes such as the first node, the second node, and the third node do not represent actual existing components, but represent the convergence points of relevant electrical connections in the circuit diagram, that is to say, these nodes are nodes equivalent to the convergence points of relevant electrical connections in the circuit diagram.

[0154] In addition, in the circuit provided in the embodiment of the present disclosure, N-type transistors are taken as examples for illustration. It should be noted that the embodiments of the present disclosure include but are not limited to this. For example, one or more transistors in the circuit provided in the embodiment of the present disclosure may also be P-type transistors, and only need to connect the electrodes of the selected type of transistor corresponding to the electrodes of the corresponding transistor in the embodiment of the present disclosure, and make the corresponding voltage terminals provide corresponding high voltages or low voltages.

[0155] In the pixel circuit provided in the embodiment of the present disclosure, the "operating voltage" refers to the voltage that can turn on the operating transistor included therein. Correspondingly, the "non-operating voltage" (or "non-turn-on voltage") refers to the voltage that cannot turn on the operating transistor included therein (that is, the transistor is cut off). Depending on factors such as the type (N-type or P-type) of the transistor in the circuit structure of the pixel circuit, the operating voltage may be higher or lower than the non-operating voltage.

[0156] Such as Figure 1 and Figure 2As shown, some embodiments of the present disclosure provide a display device 1000, and the display device 1000 can be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still images), and whether text or not.

[0157] Exemplarily, the display device 1000 can be a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a mixed reality (MR) device, an extended reality (XR) device, a sight, a rangefinder, or any other product or component with a display function.

[0158] For example, as Figure 1 shown, the display device 1000 can be a portable display product; for example, the display device 1000 can be Figure 1 the mobile phone shown. Again, for example, referring to Figure 2 , the display device 1000 can be Figure 2 the VR device shown in

[0159] It should be noted that according to different application scenarios, the display device 1000 can be a flat display device, a curved display device, a foldable display device, etc., and the shape of the display surface of the display device 1000 can be any one of a circle, an ellipse, a polygon, or an irregular shape. The embodiments of the present disclosure do not make specific limitations here.

[0160] Below, taking the above-mentioned display device 1000 as Figure 1 the mobile phone shown as an example, some embodiments of the present disclosure will be schematically described. However, the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical idea is applied.

[0161] In some embodiments, referring to Figure 3 , the display device 1000 includes a display panel 100. The display panel 100 can, for example, include a display side and a non-display side that are oppositely arranged. The display side is the side of the display panel 100 for display, that is, Figure 3 the upper side in

[0162] The types of the above-mentioned display panel 100 include various types, and can be selected and set according to actual needs. Exemplarily, the above-mentioned display panel 100 may be: an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diodes (Micro LED) display panel, etc. The embodiments of the present disclosure do not make specific limitations here.

[0163] Taking the above-mentioned display panel 100 as an OLED display panel as an example below, some embodiments of the present disclosure will be schematically described. However, the implementation manners of the present disclosure are not limited thereto, and any other display panel can also be considered as long as the same technical idea is applied.

[0164] In some embodiments, referring to Figure 3 , the above-mentioned display device 1000 may further include a housing 200, a cover plate 300, a circuit board 400, and other electronic accessories. Among them, the display panel 100 and the circuit board 400 may be disposed in the housing 200.

[0165] Exemplarily, as Figure 3 shown, the housing 200 may be a box-shaped structure with an opening, and the cover plate 300 is disposed on one side of the display panel 100 for displaying a picture and is located at the opening of the housing 200. The display panel 100 and the circuit board 400 may be disposed in the housing 200, and the circuit board 400 may be bonded to the display panel 100 at the end of the display panel 100 and bent to the back side of the display panel 100 to reduce the border of the display panel 100 and improve the screen-to-body ratio.

[0166] In some embodiments, referring to Figure 4 , the display panel 100 includes a display area A and a peripheral area B located on at least one side of the display area A. For example, the peripheral area B surrounds the display area A, Figure 4 and the example in

[0167] schematically shows the peripheral area B surrounding the display area A. Figure 5 Among them, referring to

[0168] As Figure 4 and Figure 5As shown, the substrate 10 can be a rigid substrate or a flexible substrate. Among them, the material of the rigid substrate can include glass and / or polymethyl methacrylate (PMMA for short). The material of the flexible substrate can include at least one of polyethylene terephthalate (PET for short), polyethylene naphthalate two formic acid glycol ester (PEN for short), and polyimide (PI for short).

[0169] As Figure 4 and Figure 5 shown, the driving circuit layer 110 includes a pixel circuit 20 disposed in the display area A. The pixel circuit 20 includes a plurality of transistors T. The transistor T includes a channel 201, a first pole 211, a second pole 212, and a control pole 213. Both the first pole 211 and the second pole 212 are in contact with the channel 201. One of the first pole 211 and the second pole 212 is the source electrode, and the other is the drain electrode. The embodiments of the present disclosure do not make specific limitations here.

[0170] As Figure 4 and Figure 5 shown, the light-emitting device layer 120 includes a light-emitting device 30 disposed in the display area A. The light-emitting device 30 includes a first electrode 31, a light-emitting portion 32, and a second electrode 33. The first electrode 31 is coupled to the first pole 211 or the second pole 212 of a transistor T. The second electrode 33 is coupled to the second power supply signal terminal VSS (see Figure 6 ). Figure 5 In Figure 6 , an example is given with the first electrode 31 coupled to the second pole 212 of the transistor T. It should be noted that the second power supply signal received by the second power supply signal terminal VSS (see

[0171] Figure 6

[0172] In the related art, a pixel circuit is connected to a light-emitting device to form a sub-pixel. In this case, since the area occupied by the pixel circuit on the display panel is much larger than the area occupied by the light-emitting device on the display panel, therefore, limited by the size of the pixel circuit, the number of sub-pixels set per unit area of the display panel cannot be further increased, resulting in the display panel being unable to achieve a higher pixels per inch (PPI), and unable to meet the growing demand for resolution of users. Figure 6 and Figure 7Some embodiments of the present disclosure provide a pixel circuit 20, including a common sub-circuit 270, which is coupled to a data signal terminal DATA, a first power signal terminal VDD and a third node N3. The common sub-circuit 270 is configured to generate a driving current signal in a light emitting phase P10, and transmit the driving current signal to the third node N3.

[0173] Wherein, at least two light emitting devices 30 are coupled to the same common sub-circuit 270, and the plurality of light emitting devices 30 are connected to the same common sub-circuit 270 in one frame period F (see Figure 8 ) Time-sharing light.

[0174] like Figure 7 and Figure 8 As shown, a frame period F refers to the time period in which the display panel 100 displays an image. A frame period F may include multiple sub-segments P. The sub-segment P includes a light-emitting stage P10. Multiple light-emitting devices 30 coupled to the pixel circuit 20 emit light in the light-emitting stages P10 of the multiple sub-segments P respectively.

[0175] In some examples, the shared subcircuit 270 includes a driving subcircuit 210, the driving subcircuit 210 is used to provide a driving current signal, and the pixel circuit 20 further includes a gating subcircuit 220, the gating subcircuit 220 is coupled to the plurality of light emitting devices 30 to Figure 8 ) Time-sharingly drives multiple light-emitting devices 30 to emit light.

[0176] like Figure 6 and Figure 7 As shown, the driving subcircuit 210 can be coupled to a first node N1, a second node N2, and a third node N3. The first node N1 is coupled to the data signal terminal DATA, and the second node N2 is coupled to the first power signal terminal VDD. Figure 7 and Figure 8 As shown, the driving subcircuit 210 is configured to generate a driving current signal according to the voltages of the first node N1 and the third node N3 in the light emitting stage P10, and transmit the driving current signal to the third node N3. It should be noted that the first power signal received by the first power signal terminal VDD can be a signal of the positive electrode of the DC power supply.

[0177] For example, Figure 7 As shown, the driving sub-circuit 210 includes a first transistor T1, a control electrode of the first transistor T1 is coupled to the first node N1, a first electrode is coupled to the second node N2, and a second electrode is coupled to the third node N3. Figure 7 and Figure 8 As shown, in the light emitting stage P10, the first transistor T1 is turned on, and generates a driving current signal according to the voltages of the first node N1 and the third node N3, and transmits the driving current signal to the third node N3.

[0178] As Figure 6 and Figure 7 shown, the gating sub - circuit 220 can be coupled to the third node N3. Among them, the gating sub - circuit 220 is configured to couple multiple light - emitting devices 30. That is, the gating sub - circuit 220 is coupled to multiple light - emitting devices 30. As Figure 7 and Figure 8 shown, and the gating sub - circuit 220 is configured to transmit the drive current signal from the third node N3 to different light - emitting devices 30 at different light - emitting stages P10, so that multiple light - emitting devices 30 emit light respectively at the light - emitting stages P10 of multiple sub - segments P of a frame period F.

[0179] In this case, multiple light - emitting devices 30 are coupled to the same pixel circuit 20 to form multiple sub - pixels. Among them, the light - emitting devices 30 of multiple sub - pixels can at least share one drive sub - circuit 210 to generate a drive current signal. That is, multiple sub - pixels share one drive sub - circuit 210, which can save the number of drive sub - circuits 210 and compress the area occupied by the pixel circuits 20 of multiple sub - pixels, so that more sub - pixels can be set per unit area of the display panel 100, thereby improving the pixel density and resolution of the display panel 100 to meet the user's demand for increased resolution.

[0180] On this basis, referring to Figure 5 , Figure 7 and Fig. 20 , the gating sub - circuit 220 includes a second transistor T2, and the channel 201 (see Fig.39 ) of at least one second transistor T2 in the gating sub - circuit 220 and the channel 201 (see Fig.21 ) of the first transistor T1 are located in different layers and at least partially opposite. That is, the orthographic projection of the channel 201 of at least one second transistor T2 on the substrate 10 coincides at least partially with the orthographic projection of the channel 201 of the first transistor T1 on the substrate 10.

[0181] In this article, the term "opposite" means that the first element can be directly or indirectly opposite to the second element. In the case where a third element is between the first element and the second element, although still opposite to each other, the first element and the second element can be understood as being indirectly opposite to each other.

[0182] In this case, at least one second transistor T2 in the gating sub-circuit 220 is disposed on one side of the first transistor T1 close to or away from the substrate 10, and the second transistor T2 and the first transistor T1 may overlap, so that the total area occupied by the first transistor T1 and the second transistor T2 can be reduced, which is beneficial to further reducing the area occupied by the pixel circuit 20, so that more sub-pixels can be arranged per unit area of the display panel 100, thereby further increasing the pixel density and resolution of the display panel 100 to meet the user's demand for increased resolution.

[0183] Exemplarily, as Figure 7 shown, the gating sub-circuit 220 includes a plurality of gating branches 221, the gating branches 221 are coupled to the third node N3, the fourth node N4, and the first light emission control signal terminal EM1, and the fourth nodes N4 and the first light emission control signal terminals EM1 coupled by different gating branches 221 are different. The fourth node N4 is configured to be coupled to the light emitting device 30, and the light emitting devices 30 coupled by different fourth nodes N4 are different. That is, the light emitting devices 30 coupled by the plurality of gating branches 221 are different.

[0184] Among them, as Figure 7 and Figure 8 shown, the gating branch 221 is configured to transmit the drive current signal of the third node N3 to the fourth node N4 in response to the light emission control signal received at the first light emission control signal terminal EM1 during a light emission stage P10 of a frame period F. That is to say, each gating branch 221 is controlled by a first light emission control signal terminal EM1 to be turned on respectively during the light emission stages P10 of a plurality of sub-segments P of a frame period F, so that the plurality of light emitting devices 30 coupled to the gating sub-circuit 220 emit light respectively during the light emission stages P10 of a plurality of sub-segments P of a frame period F.

[0185] For example, as Figure 7 shown, the gating branch 221 may include a second transistor T2, the control electrode of the second transistor T2 is coupled to the first light emission control signal terminal EM1, the first electrode is coupled to the third node N3, and the second electrode is coupled to the fourth node N4, and the circuit structure is simple and easy to fabricate.

[0186] In some examples, as Figure 7 and Figure 8 shown, the gating sub-circuit 220 includes two gating branches 221, the two gating branches 221 are respectively coupled to two first light emission control signal terminals EM1, and the two first light emission control signal terminals EM1 are respectively a first sub-light emission control signal terminal EM1-1 and a second sub-light emission control signal terminal EM1-2.

[0187] At this time, the two gating branches 221 are respectively controlled by the first sub-light-emitting control signal terminal EM1-1 and the second sub-light-emitting control signal terminal EM1-2 to be turned on respectively during the light-emitting stage P10 of multiple sub-segments P in one frame period F, so that the two light-emitting devices 30 emit light respectively during the light-emitting stage P10 of multiple sub-segments P in one frame period F.

[0188] In some other examples, such as Fig. 9 and Fig.10 shown, the gating sub-circuit 220 includes three gating branches 221, the three gating branches 221 are respectively coupled to three first light-emitting control signal terminals EM1, and the three first light-emitting control signal terminals EM1 are respectively the first sub-light-emitting control signal terminal EM1-1, the second sub-light-emitting control signal terminal EM1-2, and the third sub-light-emitting control signal terminal EM1-3.

[0189] At this time, the three gating branches 221 are respectively controlled by the first sub-light-emitting control signal terminal EM1-1, the second sub-light-emitting control signal terminal EM1-2, and the third sub-light-emitting control signal terminal EM1-3 to be turned on respectively during the light-emitting stage P10 of multiple sub-segments P in one frame period F, so that the three light-emitting devices 30 emit light respectively during the light-emitting stage P10 of multiple sub-segments P in one frame period F.

[0190] Hereinafter, taking the gating sub-circuit 220 including two gating branches 221 as an example, some embodiments of the present disclosure will be schematically described. However, the implementation manners of the present disclosure are not limited thereto, and it is also possible to consider that the gating sub-circuit 220 includes more gating branches 221, as long as the same technical idea is applied.

[0191] In some embodiments, referring to Figure 8 , the sub-segment P further includes a reset stage P20, and the reset stage P20 is located before the light-emitting stage P10.

[0192] At this time, as Figure 6 and Fig.11 shown, the common sub-circuit 270 may further include a reset sub-circuit 230. The reset sub-circuit 230 is coupled to the reset signal terminal RESET and the initialization signal terminal VINIT, and is also coupled to the third node N3.

[0193] Among them, referring to Fig.11 and Fig.13A , the reset sub-circuit 230 is configured to, during the reset stage P20, in response to the reset signal received at the reset signal terminal RESET, transmit the initialization signal received at the initialization signal terminal VINIT to the third node N3 to reset the voltage of the third node N3, eliminate the influence of the voltage of the previous frame period F, and improve the display effect.

[0194] Exemplarily, such as Fig.11 and Fig.13A As shown in Fig.13A , the reset sub - circuit 230 is coupled to the reset signal terminal RESET, the initialization signal terminal VINIT, and the third node N3. For example, the reset sub - circuit 230 includes a third transistor T3. The control electrode of the third transistor T3 is coupled to the reset signal terminal RESET, the first electrode is coupled to the initialization signal terminal VINIT, and the second electrode is coupled to the third node N3. The circuit structure is simple and convenient for fabrication.

[0195] In this case, the light - emitting devices 30 of multiple sub - pixels can at least share one reset sub - circuit 230 to reset the third node N3. That is, multiple sub - pixels share one reset sub - circuit 230, which can save the number of reset sub - circuits 230 and compress the area occupied by the pixel circuits 20 of multiple sub - pixels. Thus, more sub - pixels can be set per unit area of the display panel 100, so as to increase the pixel density and resolution of the display panel 100 and meet the user's demand for increased resolution.

[0196] On this basis, referring to Figure 5 、 Fig.11 and Fig.13A , the gating sub - circuit 220 can also be configured to transmit the initialization signal from the third node N3 to the fourth node N4 during the reset stage P20 to reset the first electrode 31 of the light - emitting device 30.

[0197] Exemplarily, as shown in Figure 5 、 Fig.11 and Fig.13A , the gating sub - circuit 220 includes two gating branches 221. The two gating branches 221 can be respectively turned on during the reset stage P20 of multiple sub - segments P of a frame period F, so that the first electrodes 31 of two light - emitting devices 30 are respectively reset during the reset stage P20 of multiple sub - segments P of a frame period F. In this way, the interval between the reset stage P20 and the light - emitting stage P10 of each light - emitting device 30 is short, which is beneficial to improving the uniformity of the brightness of the light - emitting device 30.

[0198] Exemplarily, as shown in Figure 5 、 Fig.11 and Fig. 13B , the gating sub - circuit 220 includes two gating branches 221. The two gating branches 221 can be simultaneously turned on during the same reset stage P20 of a frame period F, so that the first electrodes 31 of two light - emitting devices 30 are simultaneously reset during the same reset stage P20 of a frame period F. In this way, each light - emitting device 30 is reset during the same reset stage P20, which is beneficial to simplifying the circuit design.

[0199] In some other embodiments, as shown in Fig.12As shown, the pixel circuit 20 may further include a reset sub-circuit 230. The reset sub-circuit 230 is coupled to a reset signal terminal RESET and an initialization signal terminal VINIT, and is also coupled to a fourth node N4.

[0200] Among them, referring to Fig.12 and Fig.14 , the reset sub-circuit 230 is configured to, in the reset phase P20, in response to the reset signal received at the reset signal terminal RESET, transmit the initialization signal received at the initialization signal terminal VINIT to the fourth node N4 to reset the voltage of the fourth node N4, eliminate the influence of the voltage of the previous frame period F, and improve the display effect.

[0201] Exemplarily, as Fig.12 and Fig.14 shown, the reset sub-circuit 230 is coupled to the reset signal terminal RESET, the initialization signal terminal VINIT, and the fourth node N4. For example, two reset sub-circuits 230 are respectively coupled to the fourth nodes N4 of two gating branches 221, and each reset sub-circuit 230 includes a third transistor T3. The control electrode of the third transistor T3 is coupled to the reset signal terminal RESET, the first electrode is coupled to the initialization signal terminal VINIT, and the second electrode is coupled to the fourth node N4. The circuit structure is simple and convenient for preparation.

[0202] Among them, as Fig.12 and Fig.14 shown, two reset sub-circuits 230 are respectively coupled to two reset signal terminals RESET and two initialization signal terminals VINIT, and the two reset signal terminals RESET are respectively a first sub-reset signal terminal RESET1-1 and a second sub-reset signal terminal RESET1-2, and the two initialization signal terminals VINIT are respectively a first sub-initialization signal terminal VINIT1-1 and a second sub-initialization signal terminal VINIT1-2.

[0203] At this time, the two reset sub-circuits 230 are respectively controlled by the first sub-reset signal terminal RESET1-1 and the second sub-reset signal terminal RESET1-2 to be turned on respectively in the reset phase P20 of multiple sub-segments P of a frame period F, so that the first electrodes 31 of the two light-emitting devices 30 are respectively reset in the reset phase P20 of multiple sub-segments P of a frame period F.

[0204] The signals transmitted by the above first sub-reset signal terminal RESET1-1 and second sub-reset signal terminal RESET1-2 may be the same or different. For example, the first sub-reset signal terminal RESET1-1 and the second sub-reset signal terminal RESET1-2 are coupled to the same signal line.

[0205] The signals transmitted by the first sub-initialization signal terminal VINIT1-1 and the second sub-initialization signal terminal VINIT1-2 can be the same or different. For example, the first sub-initialization signal terminal VINIT1-1 and the second sub-initialization signal terminal VINIT1-2 are coupled to the same signal line.

[0206] Taking the reset sub-circuit 230 coupled to the reset signal terminal RESET, the initialization signal terminal VINIT, and the third node N3 as an example, some embodiments of the present disclosure will be schematically described, but the embodiments of the present disclosure are not limited thereto.

[0207] On this basis, referring to Fig.21 , the channel 201 of the third transistor T3 and the channel 201 of the first transistor T1 can be located on the same layer, that is, the channel 201 of the first transistor T1 and the channel 201 of the third transistor T3 can be fabricated in the same process step to simplify the process flow and reduce the fabrication cost.

[0208] In some embodiments, referring to Fig.11 , Fig. 20 , Fig.21 and Fig.39 , the channel 201 of at least one second transistor T2 in the gating sub-circuit 220 and the channel 201 of the third transistor T3 may not be opposite, or may be at least partially opposite.

[0209] Exemplarily, the orthographic projection of the channel 201 of at least one second transistor T2 on the substrate 10 and the orthographic projection of the channel 201 of the third transistor T3 on the substrate 10 at least partially overlap.

[0210] In this case, at least one second transistor T2 in the gating sub-circuit 220 is disposed on one side of the third transistor T3 close to or away from the substrate 10, and the second transistor T2 and the third transistor T3 can overlap, which can reduce the total area occupied by the second transistor T2 and the third transistor T3, thereby facilitating further reduction of the area occupied by the pixel circuit 20, so that more sub-pixels can be arranged per unit area of the display panel 100, to further improve the pixel density and resolution of the display panel 100 and meet the user's demand for increased resolution.

[0211] For example, as Fig.11 , Fig.21 and Fig.39As shown, the gating sub-circuit 220 includes two gating branches 221, and each gating branch 221 includes a second transistor T2. Among the two second transistors T2 included in the two gating branches 221, the channel 201 of one second transistor T2 is at least partially opposite to the channel 201 of the first transistor T1, and the channel 201 of the other second transistor T2 is at least partially opposite to the channel 201 of the third transistor T3.

[0212] In this case, one second transistor T2 and the first transistor T1 can overlap, and the other second transistor T2 and the third transistor T3 can overlap, which can further reduce the total area occupied by the first transistor T1, the second transistor T2, and the third transistor T3, thereby facilitating further reduction of the area occupied by the pixel circuit 20, so that more sub-pixels can be arranged per unit area of the display panel 100 to further improve the pixel density and resolution of the display panel 100.

[0213] It should be understood that referring to Figure 8 , the sub-segment P further includes a data writing stage P30, and the data writing stage P30 is located between the reset stage P20 and the light emitting stage P10 to write a data signal.

[0214] At this time, as Figure 6 , Figure 7 and Fig.11 shown, the common sub-circuit 270 may further include a data writing sub-circuit 240, and the data writing sub-circuit 240 is coupled to the first scan signal terminal G1, the data signal terminal DATA, and the first node N1.

[0215] Among them, referring to Figure 7 , Figure 8 and Fig.11 , the data writing sub-circuit 240 is configured to transmit the data signal received at the data signal terminal DATA to the first node N1 in response to the first scan signal received at the first scan signal terminal G1 during the data writing stage P30.

[0216] Exemplarily, as Figure 7 and Fig.11 shown, the data writing sub-circuit 240 includes a fourth transistor T4. The control electrode of the fourth transistor T4 is coupled to the first scan signal terminal G1, the first electrode is coupled to the data signal terminal DATA, and the second electrode is coupled to the first node N1. The circuit structure is simple and convenient for preparation.

[0217] In this case, the light-emitting devices 30 of multiple sub-pixels can at least share one data writing sub-circuit 240 to write a data signal to the first node N1. That is, multiple sub-pixels share one data writing sub-circuit 240, which can save the number of data writing sub-circuits 240 and compress the area occupied by the pixel circuits 20 of multiple sub-pixels, so that more sub-pixels can be arranged per unit area of the display panel 100, thereby improving the pixel density and resolution of the display panel 100.

[0218] On this basis, referring to Fig.21 , the channel 201 of the fourth transistor T4 and the channel 201 of the first transistor T1 can be located in the same layer, that is, the channel 201 of the fourth transistor T4 and the channel 201 of the first transistor T1 can be fabricated in the same process step to simplify the process flow and reduce the manufacturing cost.

[0219] In addition, as Fig.21 shown, along the first direction X, the channel 201 of the third transistor T3 and the channel 201 of the fourth transistor T4 can be located on opposite sides of the channel 201 of the first transistor T1. In this way, the circuit traces are more regular and it is beneficial to reduce the size of the pixel circuit 20 in the second direction Y. It should be noted that the first direction X intersects the second direction Y. For example, the first direction X is perpendicular to the second direction Y.

[0220] At the same time, the channel 201 of the third transistor T3 can extend along the first direction X, and the multiple light-emitting devices 30 coupled to the same pixel circuit 20 can be arranged along the first direction X. With this arrangement, in the pixel circuit 20 and the multiple light-emitting devices 30 coupled thereto, the maximum distance between the multiple light-emitting devices 30 and the maximum size of the pixel circuit 20 are both in the first direction X, which is beneficial to reducing the area occupied by multiple sub-pixels including the pixel circuit 20 and the multiple light-emitting devices 30 coupled thereto, so that more sub-pixels can be arranged per unit area of the display panel 100 to further improve the pixel density and resolution of the display panel 100.

[0221] In some embodiments, referring to Fig.13A , the sub-phase P further includes a compensation phase P40, and the compensation phase P40 is located between the data writing phase P30 and the reset phase P20.

[0222] At this time, as Figure 7 , Fig.11 and Fig.13AAs shown, the driving sub-circuit 210 is further configured to, during the compensation stage P40, under the control of the voltages of the first node N1 and the third node N3, transfer the voltage of the second node N2 to the third node N3 until the voltage difference between the first node N1 and the third node N3 is equal to the threshold voltage of the first transistor T1 included in the driving sub-circuit 210, thereby extracting the threshold voltage of the first transistor T1 included in the driving sub-circuit 210. In this case, during the data writing stage P30, the voltage difference between the first node N1 and the third node N3 compensates for this threshold voltage to eliminate the interference caused by this threshold voltage during the light emitting stage P10.

[0223] On this basis, as Figure 7 , Fig.11 and Fig.13A shown, the common sub-circuit 270 may further include a first energy storage sub-circuit 250, and the first energy storage sub-circuit 250 is coupled to the first node N1 and the third node N3. Moreover, the first energy storage sub-circuit 250 is configured to, during the light emitting stage P10, raise or lower the voltage of the first node N1 according to the change in the voltage of the third node N3 to maintain the voltage difference between the first node N1 and the third node N3 unchanged, playing a role in voltage stabilization.

[0224] Exemplarily, as Figure 7 and Fig.11 shown, the first energy storage sub-circuit 250 includes a first capacitor C1. The first plate of the first capacitor C1 is coupled to the first node N1, and the second plate of the first capacitor C1 is coupled to the third node N3, with a simple structure and being easy to fabricate.

[0225] In some embodiments, referring to Figure 7 , Fig.11 and Fig.13A , the data writing sub-circuit 240 is further configured to, during the compensation stage P40, in response to the first scan signal received at the first scan signal terminal G1, transfer the data signal received at the data signal terminal DATA to the first node N1. At this time, the magnitude of the driving current is calculated according to the data signals' voltages during the compensation stage P40 and the data writing stage P30.

[0226] It should be noted that the voltage of the data signal during the compensation stage P40 is different from the voltage of the data signal during the data writing stage P30; for example, the voltage of the data signal during the data writing stage P30 is greater than the voltage of the data signal during the compensation stage P40.

[0227] In addition, the data writing sub-circuit 240 may also be configured to, during the reset stage P20, in response to the first scan signal received at the first scan signal terminal G1, transfer the data signal received at the data signal terminal DATA to the first node N1 to reset the voltage of the first node N1.

[0228] In some other embodiments, referring to Fig.15A 、 Fig. 15B and Fig.16 , the common sub - circuit 270 may further include a first voltage sub - circuit 260, and the first voltage sub - circuit 260 is coupled to the second scan signal terminal G2, the first voltage signal terminal Vref, and the first node N1.

[0229] Among them, as Fig.15A 、 Fig. 15B and Fig.16 show, the first voltage sub - circuit 260 is configured to, in the compensation stage P40, in response to the second scan signal received at the second scan signal terminal G2, transmit the first voltage signal received at the first voltage signal terminal Vref to the first node N1. At this time, the magnitude of the drive current is calculated according to the first voltage signal in the compensation stage P40 and the voltage of the data signal in the data writing stage P30. It should be noted that the first voltage signal received at the first voltage signal terminal Vref may be a constant reference voltage, and this reference voltage is less than the voltage of the data signal in the data writing stage P30.

[0230] In addition, the first voltage sub - circuit 260 may further be configured to, in the reset stage P20, in response to the second scan signal received at the second scan signal terminal G2, transmit the first voltage signal received at the first voltage signal terminal Vref to the first node N1 to reset the voltage of the first node N1.

[0231] Exemplarily, as Fig.15A and Fig. 15B show, the first voltage sub - circuit 260 may, for example, include a fifth transistor T5. The control electrode of the fifth transistor T5 is coupled to the second scan signal terminal G2, the first electrode is coupled to the first voltage signal terminal Vref, and the second electrode is coupled to the first node N1. The circuit structure is simple and convenient for preparation.

[0232] On this basis, referring to Fig. 20 、 Fig.21 and Fig.39 , the channel 201 of the fifth transistor T5 and the channel 201 of the fourth transistor T4 may, for example, be located in different layers and at least partially opposite. That is, the positive projection of the channel 201 of the fifth transistor T5 on the substrate 10 coincides at least partially with the positive projection of the channel 201 of the fourth transistor T4 on the substrate 10.

[0233] In this case, the fifth transistor T5 is disposed on one side of the fourth transistor T4 close to or away from the substrate 10. The fourth transistor T4 and the fifth transistor T5 may overlap, so that the total area occupied by the fourth transistor T4 and the fifth transistor T5 can be reduced, which is beneficial to further reducing the area occupied by the pixel circuit 20, so that more sub-pixels can be arranged per unit area of the display panel 100, thereby further improving the pixel density and resolution of the display panel 100 to meet the user's demand for increased resolution.

[0234] In addition, as Fig.39 shown, the channel 201 of the fifth transistor T5 and the channel 201 of the second transistor T2 may be located in the same layer, that is, the channel 201 of the fifth transistor T5 and the channel 201 of the second transistor T2 can be fabricated in the same process step to simplify the process flow and reduce the manufacturing cost.

[0235] In some embodiments, referring to Fig.17 and Fig.18 , the common sub-circuit 270 further includes a light emission control sub-circuit 280. The light emission control sub-circuit 280 is coupled to the first power signal terminal VDD, the second light emission control signal terminal EM2, and the second node N2.

[0236] Wherein, referring to Fig.18 and Fig.19 , the light emission control sub-circuit 280 is configured to, in the compensation phase P40 and the light emission phase P10, in response to the second light emission control signal received at the second light emission control signal terminal EM2, transmit the first power signal received at the first power signal terminal VDD to the second node N2.

[0237] Moreover, the light emission control sub-circuit 280 can also be configured to be cut off in response to the second light emission control signal received at the second light emission control signal terminal EM2 in the reset phase P20, so as to avoid the first transistor T1 and the third transistor T3 being turned on in the reset phase P20, resulting in the first power signal terminal VDD being connected to the initialization signal terminal VINIT, causing power consumption loss.

[0238] Exemplarily, as Fig.17 and Fig.18 shown, the light emission control sub-circuit 280 includes a sixth transistor T6. The control electrode of the sixth transistor T6 is coupled to the second light emission control signal terminal EM2, the first electrode is coupled to the first power signal terminal VDD, and the second electrode is coupled to the second node N2. The circuit structure is simple and convenient for fabrication.

[0239] Next, taking the pixel circuit 20 shown in Fig. 15B as an example, in combination with the driving timing of Fig.16 , each stage within a sub-segment P will be exemplarily described. The embodiments of the present disclosure are not limited thereto.

[0240] During the reset phase P20, the first scan signal received at the first scan signal terminal G1 is a non-operating voltage (low voltage), and the fourth transistor T4 is turned off. The second scan signal received at the second scan signal terminal G2 is an operating voltage (high voltage), and the fifth transistor T5 is turned on, transmitting the first voltage signal received at the first voltage signal terminal Vref to the first node N1 to reset the voltage of the first node N1.

[0241] In addition, the reset signal received at the reset signal terminal RESET is an operating voltage (high voltage), and the third transistor T3 is turned on, transmitting the initialization signal received at the initialization signal terminal VINIT to the third node N3 to reset the voltage of the third node N3. Also, the first light emission control signal received at the first light emission control signal terminal EM1 is an operating voltage (high voltage), and the second transistor T2 is turned on to reset the fourth node N4, that is, the first electrode 31 of the light emitting device 30 (see Figure 5 ). At this time, under the action of the voltages of the first node N1 and the third node N3, the first transistor T1 is turned on.

[0242] During the compensation phase P40, the first scan signal received at the first scan signal terminal G1 is a non-operating voltage (low voltage), and the fourth transistor T4 is turned off. The second scan signal received at the second scan signal terminal G2 is an operating voltage (high voltage), and the fifth transistor T5 is turned on, transmitting the first voltage signal received at the first voltage signal terminal Vref to the first node N1 to maintain the voltage of the first node N1.

[0243] In addition, the reset signal received at the reset signal terminal RESET is a non-operating voltage (low voltage), and the third transistor T3 is turned off. Also, the first light emission control signal received at the first light emission control signal terminal EM1 is a non-operating voltage (low voltage), and the second transistor T2 is turned off. At this time, under the control of the voltages of the first node N1 and the third node N3, the voltage of the second node N2 is transmitted to the third node N3 until the voltage difference between the first node N1 and the third node N3 is equal to the threshold voltage of the first transistor T1, thereby extracting the threshold voltage of the first transistor T1.

[0244] During the data writing phase P30, the first scan signal received at the first scan signal terminal G1 is an operating voltage (high voltage), and the fourth transistor T4 is turned on, transmitting the data signal received at the data signal terminal DATA to the first node N1. The second scan signal received at the second scan signal terminal G2 is a non-operating voltage (low voltage), and the fifth transistor T5 is turned off. At this time, the data signal is written into the first node N1, and the first transistor T1 is turned on.

[0245] In addition, the reset signal received at the reset signal terminal RESET is a non-operating voltage (low voltage), and the third transistor T3 is turned off. Also, the first light emission control signal received at the first light emission control signal terminal EM1 is a non-operating voltage (low voltage), and the second transistor T2 is turned off.

[0246] In the light emission stage P10, the first scan signal received at the first scan signal terminal G1 is a non-operating voltage (low voltage), and the fourth transistor T4 is turned off. The second scan signal received at the second scan signal terminal G2 is a non-operating voltage (low voltage), and the fifth transistor T5 is turned off.

[0247] In addition, the reset signal received at the reset signal terminal RESET is a non-operating voltage (low voltage), and the third transistor T3 is turned off. Also, the first light emission control signal received at the first light emission control signal terminal EM1 is an operating voltage (high voltage), and the second transistor T2 is turned on. At this time, the first transistor T1 is turned on, and a drive current signal is generated according to the voltages of the first node N1 and the third node N3, and the drive current signal is transmitted to the third node N3; also, the second transistor T2 is turned on, and the drive current signal is transmitted to the light emitting device 30 to drive the corresponding light emitting device 30 to emit light.

[0248] In the display panel 100 provided by some embodiments of the present disclosure, refer to Figure 4 and Figure 5 , the driving circuit layer 110 includes a plurality of pixel circuits 20 of any of the above embodiments. The plurality of pixel circuits 20 can be arranged in multiple rows and multiple columns, for example. Each column includes at least two pixel circuits 20 arranged along the first direction X, and each row includes at least two pixel circuits 20 arranged along the second direction Y. On this basis, in the first direction X and / or the second direction Y, any two adjacent pixel circuits 20 can be symmetrically arranged, so that the circuit design is more regular, the structure is more compact, and the space utilization rate is high.

[0249] It should be noted that the first direction X is the column direction in which the plurality of pixel circuits 20 are arranged, and the second direction Y is the row direction in which the plurality of pixel circuits 20 are arranged.

[0250] In addition, refer to Figure 4 , the plurality of light emitting devices 30 are arranged in multiple rows and multiple columns. Each column includes at least two light emitting devices 30 arranged along the first direction X, and each row includes at least two light emitting devices 30 arranged along the second direction Y. Also, the plurality of light emitting devices 30 coupled to the same gating sub-circuit 220 are located in the same column.

[0251] Hereinafter, taking the arrangement of the plurality of pixel circuits 20 and the plurality of light emitting devices 30 in multiple rows and multiple columns as an example, some embodiments of the present disclosure will be exemplarily described, but the implementation manners of the present disclosure are not limited thereto.

[0252] Among them, refer to Fig.42A , the multi-column light-emitting device 30 includes a first type of light-emitting device column 311 and a second type of light-emitting device column 312. At least two light-emitting devices 30 in the first type of light-emitting device column 311 have different light-emitting colors. The light-emitting devices 30 in the second type of light-emitting device column 312 have the same light-emitting color.

[0253] Exemplarily, refer to Fig.42A , the first type of light-emitting device column 311 includes a plurality of red light-emitting devices R and a plurality of blue light-emitting devices B, and the plurality of red light-emitting devices R and the plurality of blue light-emitting devices B are arranged alternately. The second type of light-emitting device column 312 includes a plurality of green light-emitting devices G.

[0254] Exemplarily, refer to Fig.42A , the first type of light-emitting device column 311 includes a plurality of red light-emitting devices R and a plurality of green light-emitting devices G, and the plurality of red light-emitting devices R and the plurality of green light-emitting devices G are arranged alternately. The second type of light-emitting device column 312 includes a plurality of blue light-emitting devices B.

[0255] In some embodiments, refer to Figure 5 , the driving circuit layer 110 includes a first sub-driving layer 111 and a second sub-driving layer 112, and the second sub-driving layer 112 is disposed between the first sub-driving layer 111 and the light-emitting device layer 120.

[0256] Among them, the first sub-driving layer 111 includes a first transistor T1, and the second sub-driving layer 112 includes a second transistor T2. In this case, the second transistor T2 is closer to the light-emitting device 30, the distance between the second transistor T2 and the light-emitting device 30 is smaller, and in the process of connecting the second transistor T2 and the light-emitting device 30, the depth of the via hole to be etched is shallower, the process difficulty is low, and it is beneficial to improve the production yield.

[0257] At this time, refer to Figure 5 and Fig.15A , when the pixel circuit 20 further includes a third transistor T3, a fourth transistor T4, and a fifth transistor T5, the first sub-driving layer 111 further includes a third transistor T3 and a fourth transistor T4, and the second sub-driving layer 112 further includes a fifth transistor T5.

[0258] It should be noted that the difference between the number of transistors T included in the first sub-driving layer 111 and the number of transistors T included in the second sub-driving layer 112 can be 0 or 1, for example, so that the channel 201 of most transistors T can share a part of the area with the channel 201 of at least one transistor T, thereby improving the space utilization rate and reducing the occupied area of the pixel circuit 20.

[0259] On this basis, refer to Figure 5 and Fig.26, the display panel 100 may further include a first source-drain conductive layer SD1, which is disposed between the first sub-driving layer 111 and the second sub-driving layer 112. Moreover, the first source-drain conductive layer SD1 includes data lines DL, and the data lines DL extend along the first direction X and are configured to transmit data signals. One data line DL may be coupled to the data signal terminal DATA of a column of pixel circuits 20 (see Fig. 15B ).

[0260] In this case, the distance between the data line DL and the first electrode 31 of the light-emitting device 30 is relatively far, and the second sub-driving layer 112 is also disposed between the data line DL and the first electrode 31 of the light-emitting device 30, which is beneficial to reducing the influence of the voltage jump of the data line DL on the first electrode 31, thereby reducing the crosstalk between signals and improving the display effect.

[0261] In some embodiments, referring to Figure 4 , Fig. 27 and Fig.33 , the display panel 100 includes an initialization signal line VIL and a first power supply line VDL. The initialization signal line VIL is coupled to the initialization signal terminal VINIT, and the first power supply line VDL is coupled to the first power supply signal terminal VDD (see Fig.15A ).

[0262] In some examples, as shown in Figure 4 , Fig. 27 and Fig.33 , the initialization signal line VIL includes a plurality of first sub-lines VIL1 and a plurality of second sub-lines VIL2. The second sub-lines VIL2 extend along the second direction Y and are coupled to the initialization signal terminals VINIT of a row of pixel circuits 20 (see Fig.15A ) to transmit the initialization signal.

[0263] In addition, the first sub-lines VIL1 extend along the first direction X, and one first sub-line VIL1 is connected to a plurality of second sub-lines VIL2, and one second sub-line VIL2 is connected to a plurality of first sub-lines VIL1 to form a mesh structure. In this case, the initialization signal line VIL forms a mesh structure, which can reduce the voltage drop of the initialization signal and the difference in the initialization signals received by different pixel circuits 20, thereby improving the brightness uniformity of the display panel 100.

[0264] In some examples, as shown in Figure 4 , Fig. 27 and Fig.33 , the first power supply line VDL includes a plurality of third sub-lines VDL1 and a plurality of fourth sub-lines VDL2. The fourth sub-lines VDL2 extend along the second direction Y and are coupled to the first power supply signal terminals VDD of a row of pixel circuits 20 (see Fig.15A ) to transmit the first power supply signal.

[0265] In addition, the third sub-line VDL1 extends along the first direction X, and one third sub-line VDL1 is connected to multiple fourth sub-lines VDL2, and one fourth sub-line VDL2 is connected to multiple third sub-lines VDL1 to form a mesh structure. In this case, the first power supply line VDL forms a mesh structure, which can reduce the voltage drop of the first power signal and reduce the difference in the first power signal received by different pixel circuits 20, thereby improving the brightness uniformity of the display panel 100.

[0266] As Fig. 27 and Fig.33 shown, when the initialization signal line VIL includes the first sub-line VIL1 and the second sub-line VIL2, and the first power supply line VDL includes the third sub-line VDL1 and the fourth sub-line VDL2, the third sub-line VDL1 and the first sub-line VIL1 can be staggeredly arranged, and the fourth sub-line VDL2 and the second sub-line VIL2 can be staggeredly arranged. With this arrangement, the initialization signal line VIL and the first power supply line VDL are staggeredly arranged, which can reduce the risk of short circuit between the initialization signal line VIL and the first power supply line VDL caused by electrostatic breakdown and improve the product yield.

[0267] It should be noted that the staggered arrangement of the third sub-line VDL1 and the first sub-line VIL1 means that there is no overlapping part between the third sub-line VDL1 and the first sub-line VIL1. The staggered arrangement of the fourth sub-line VDL2 and the second sub-line VIL2 means that there is no overlapping part between the fourth sub-line VDL2 and the second sub-line VIL2.

[0268] In some embodiments, referring to Figure 5 , the display panel 100 includes 10 conductive layers, and the driving circuit layer 110 includes 8 conductive layers. For example, the driving circuit layer 110 includes a first gate conductive layer GT1, a second gate conductive layer GT2, a third gate conductive layer GT3, a first source-drain conductive layer SD1, a fourth gate conductive layer GT4, a fifth gate conductive layer GT5, a sixth gate conductive layer GT6, and a second source-drain conductive layer SD2. The light-emitting device layer 120 includes a first electrode layer 310 and a second electrode layer 330.

[0269] In other embodiments, the display panel 100 includes 9 conductive layers, and the driving circuit layer 110 includes 7 conductive layers. For example, the driving circuit layer 110 includes a first gate conductive layer GT1, a second gate conductive layer GT2, a third gate conductive layer GT3, a first source-drain conductive layer SD1, a fourth gate conductive layer GT4, and a second source-drain conductive layer SD2, and further includes any one of a fifth gate conductive layer GT5 and a sixth gate conductive layer GT6. The light-emitting device layer 120 includes a first electrode layer 310 and a second electrode layer 330.

[0270] In still other embodiments, the display panel 100 includes eight conductive layers, and the driving circuit layer 110 includes six conductive layers. For example, the driving circuit layer 110 includes a first gate conductive layer GT1, a second gate conductive layer GT2, a first source-drain conductive layer SD1, a fourth gate conductive layer GT4, and a second source-drain conductive layer SD2, and further includes any one of a fifth gate conductive layer GT5 and a sixth gate conductive layer GT6. The light-emitting device layer 120 includes a first electrode layer 310 and a second electrode layer 330.

[0271] In some embodiments, referring to Figure 5 、 Fig.36 and Fig.37 , the first sub-driving layer 111 includes a first semiconductor layer ACT1, a first gate conductive layer GT1, a second gate conductive layer GT2, and a third gate conductive layer GT3.

[0272] Moreover, the first gate conductive layer GT1 is disposed on a side of the first semiconductor layer ACT1 close to the light-emitting device layer 120, the second gate conductive layer GT2 is disposed on a side of the first gate conductive layer GT1 close to the light-emitting device layer 120, and the third gate conductive layer GT3 is disposed on a side of the second gate conductive layer GT2 close to the light-emitting device layer 120.

[0273] Wherein, the first sub-driving layer 111 may further include multiple insulating layers. The multiple insulating layers may, for example, include a first gate insulating layer GI1, a second gate insulating layer GI2, a third gate insulating layer GI3, and a first interlayer insulating layer ILD1. The first gate insulating layer GI1 is disposed between the first semiconductor layer ACT1 and the first gate conductive layer GT1, the second gate insulating layer GI2 is disposed between the first gate conductive layer GT1 and the second gate conductive layer GT2, the third gate insulating layer GI3 is disposed between the second gate conductive layer GT2 and the third gate conductive layer GT3, and the first interlayer insulating layer ILD1 is disposed between the third gate conductive layer GT3 and the first source-drain conductive layer SD1.

[0274] It should be noted that the thickness of the first interlayer insulating layer ILD1 is 150 nm to 300 nm; for example, the thickness of the first interlayer insulating layer ILD1 is any one of 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, and 300 nm.

[0275] In some examples, such as Fig.21As shown, the first semiconductor layer ACT1 includes a first channel portion 2011 and a first conductive portion 2012. Among them, the first channel portion 2011 may include the channel 201 of the transistor T of the first sub-driving layer 111. For example, the first channel portion 2011 includes the channels 201 of the first transistor T1, the third transistor T3, and the fourth transistor T4. In addition, two first conductive portions 2012 may be respectively disposed on opposite sides of a first channel portion 2011 as the first pole 211 and the second pole 212 of the transistor T to be coupled to other electronic components (such as capacitors, transistors, and light-emitting devices).

[0276] It should be noted that the material of the first semiconductor layer ACT1 includes oxides and / or low-temperature polysilicon. For example, the material of the first semiconductor layer ACT1 includes low-temperature polysilicon.

[0277] In some examples, as Fig. 22 、 Fig.24 、 Fig.28 and Fig.32 shown, the first gate conductive layer GT1 includes a reset signal line RL, a first scan signal line GL1, and a first conductive block 40. The reset signal line RL and the first scan signal line GL1 extend along the second direction Y, and the first conductive block 40 may be located between the reset signal line RL and the first scan signal line GL1.

[0278] Among them, in combination with Fig.36 and Fig.37 , the first conductive block 40 may serve as the first electrode plate of the first capacitor C1, and the reset signal line RL, the first scan signal line GL1, and the first conductive block 40 respectively overlap with the first channel portion 2011 of the first semiconductor layer ACT1 to respectively form the control electrodes of the third transistor T3, the fourth transistor T4, and the first transistor T1.

[0279] In addition, as Fig.38B shown, two reset signal lines RL may be located between two first scan signal lines GL1. On this basis, the second sub-line VIL2 may be located between two adjacent reset signal lines RL. Arranged in this way, the second sub-line VIL2 is also staggered from both the reset signal line RL and the first scan signal line GL1, which can reduce the risk of short circuit between the second sub-line VIL2 and the reset signal line RL and the first scan signal line GL1, reduce signal interference, and the circuit structure is compact, which is beneficial to improving the pixel density.

[0280] And, as Fig.38BAs shown, the fourth sub-line VDL2 is located between the reset signal line RL and the first scan signal line GL1. Set in this way, the fourth sub-line VDL2 is also staggeredly arranged with both the reset signal line RL and the first scan signal line GL1, which can reduce the risk of short circuit between the fourth sub-line VDL2 and the reset signal line RL and the first scan signal line GL1, reduce interference between signals, and the circuit structure is compact, which is beneficial to improving the pixel density.

[0281] In some examples, such as Fig.23 , Fig.24 , Fig.29 and Fig.32 shown, the second gate conductive layer GT2 includes a second conductive block 50, and the second conductive block 50 is at least partially opposite to the first conductive block 40 to form a first capacitor C1. Among them, in combination with Fig.36 and Fig.37 , the second conductive block 50 can be used as the second electrode plate of the first capacitor C1, and the geometric centers of the second conductive block 50 and the first conductive block 40 do not coincide, so that a part of the first conductive block 40 is exposed to facilitate the coupling of the first conductive block 40 with the corresponding circuit structure (such as the fourth transistor T4). For example, Fig.24 shows that the second conductive block 50 exposes the edge area of a corner of the first conductive block 40; or, Fig.32 shows that the second conductive block 50 exposes the edge area of a side of the first conductive block 40. In addition, the second sub-line VIL2 can be located in the second gate conductive layer GT2.

[0282] In this case, the distances between the second sub-line VIL2 and the first sub-line VIL1, and between the second sub-line VIL2 and the first pole 211 of the third transistor T3 are both small. During the process of connecting the second sub-line VIL2 and the first sub-line VIL1, and the second sub-line VIL2 and the first pole 211 of the third transistor T3, the depth of the vias to be etched is relatively shallow, the process difficulty is low, which is beneficial to improving the production yield.

[0283] On this basis, referring to Fig.25 and Fig.30 , the third gate conductive layer GT3 can be provided with a first power supply line VDL, or a third conductive block 60 can be provided to increase the capacitance of the first energy storage sub-circuit 250.

[0284] Exemplarily, such as Fig.23 , Fig.25 , Fig.26 and Fig. 27As shown, the first sub-line VIL1 can be located in the first source-drain conductive layer SD1, and the second sub-line VIL2 can be located in the second gate conductive layer GT2. The first power supply line VDL can be located in the third gate conductive layer GT3, that is, the third sub-line VDL1 and the fourth sub-line VDL2 are located in the third gate conductive layer GT3. In this case, the initialization signal line VIL and the first power supply line VDL are distributed in three conductive layers, namely the first source-drain conductive layer SD1, the second gate conductive layer GT, and the third gate conductive layer GT3, which can reduce the number of traces in each conductive layer, reduce the trace density, lower the process difficulty, and improve the production yield.

[0285] Exemplarily, as Fig.29 , Fig.30 , Fig.31 and Fig.33 shown, the first sub-line VIL1 and the third sub-line VDL1 are located in the first source-drain conductive layer SD1, and the second sub-line VIL2 and the fourth sub-line VDL2 are located in the second gate conductive layer GT2. On this basis, the third gate conductive layer GT3 can include a third conductive block 60, and the third conductive block 60 is at least partially opposite to the second conductive block 50 to form a first capacitor C1, so as to add a first capacitor C1. Among them, the third conductive block 60 can be connected to the first conductive block 40, so that the two first capacitors C1 are connected in parallel, thereby increasing the capacitance of the first energy storage sub-circuit 250.

[0286] In some embodiments, referring to Figure 5 , Fig.44 , Fig.45 and Fig.46 , the second sub-driving layer 112 includes a fourth gate conductive layer GT4, a fifth gate conductive layer GT5, a second semiconductor layer ACT2, a sixth gate conductive layer GT6, and a second source-drain conductive layer SD2 ( Fig.44 not shown in

[0287] ). Moreover, the fifth gate conductive layer GT5 is disposed on a side of the fourth gate conductive layer GT4 away from the first sub-driving layer 111, the second semiconductor layer ACT2 is disposed on a side of the fifth gate conductive layer GT5 away from the first sub-driving layer 111, the sixth gate conductive layer GT6 is disposed on a side of the second semiconductor layer ACT2 away from the first sub-driving layer 111, and the second source-drain conductive layer SD2 is disposed on a side of the sixth gate conductive layer GT6 away from the first sub-driving layer 111.

[0288] Among them, the second sub-driving layer 112 may further include multiple insulating layers. The multiple insulating layers may include, for example, a third interlayer insulating layer ILD3, a fourth gate insulating layer GI4, a fifth gate insulating layer GI5, a fourth interlayer insulating layer ILD4, and a first planarization layer PLN. The third interlayer insulating layer ILD3 is disposed between the fourth gate conductive layer GT4 and the fifth gate conductive layer GT5. The fourth gate insulating layer GI4 is disposed between the fifth gate conductive layer GT5 and the second semiconductor layer ACT2. The fifth gate insulating layer GI5 is disposed between the second semiconductor layer ACT2 and the sixth gate conductive layer GT6. The fourth interlayer insulating layer ILD4 is disposed between the sixth gate conductive layer GT6 and the second source / drain conductive layer SD2. The first planarization layer PLN is disposed between the second source / drain conductive layer SD2 and the light-emitting device layer 120.

[0289] In addition, the third interlayer insulating layer ILD3 may include a second planarization layer ILD31 and a buffer layer ILD32. The second planarization layer ILD31 has a planarizing effect. The buffer layer ILD32 is disposed on a side of the second planarization layer ILD31 away from the fourth gate conductive layer GT4, and functions to buffer and reduce the risk of damage to the upper transistor T.

[0290] On this basis, the material of the second planarization layer ILD31 includes a low dielectric constant material. For example, the material of the second planarization layer ILD31 includes a material with a dielectric constant less than or equal to 4. For example, the material of the second planarization layer ILD31 includes an organic resin, which is beneficial to reducing the interference between the first sub-driving layer 111 and the second sub-driving layer 112, and the interference between the data line DL and the first electrode 31. Moreover, the thickness of the second planarization layer ILD31 can be relatively large. For example, the thickness of the second planarization layer ILD31 is 1.5 μm to 2 μm. For example, the thickness of the second planarization layer ILD31 is any one of 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, and 2 μm, so as to further reduce the interference between the first sub-driving layer 111 and the second sub-driving layer 112, and the interference between the data line DL and the first electrode 31.

[0291] In some examples, as Fig.39 shown, the second semiconductor layer ACT2 includes a second channel portion 2021 and a second conductive portion 2022. Among them, the second channel portion 2021 may include the channel 201 of the transistor T in the second sub-driving layer 112. For example, the second channel portion 2021 includes the channel 201 of the second transistor T2 and the channel 201 of the fifth transistor T5. In addition, the two second conductive portions 2022 may be respectively disposed on opposite sides of a second channel portion 2021 as the first pole 211 and the second pole 212 of the transistor T to be coupled to other electronic components (such as capacitors, transistors, and light-emitting devices).

[0292] It should be noted that the material of the second semiconductor layer ACT2 may include an oxide. For example, the material of the second semiconductor layer ACT2 includes any one of indium gallium zinc oxide, indium tin zinc oxide, and indium zinc oxide, so as to avoid adverse effects on the transistor T of the lower first sub-driving layer 111 when forming low-temperature polysilicon by using a high-temperature process (for example, greater than or equal to 400 °C).

[0293] In addition, the materials of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may be the same. For example, the materials of both the first semiconductor layer ACT1 and the second semiconductor layer ACT2 are oxides. Of course, the materials of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may also be different. For example, the material of the first semiconductor layer ACT1 is low-temperature polysilicon, and the material of the second semiconductor layer ACT2 is an oxide.

[0294] In some examples, as Fig.34 shown, the fourth gate conductive layer GT4 includes a first adapter block 81 and a second adapter block 82.

[0295] Combined with Fig.34 、 Fig.35 、 Fig.36 、 Fig.39 and Fig.44 , the first adapter block 81 is respectively connected to the second conductive block 50 and the second conductive part 2022 to couple the first pole 211 of the second transistor T2 to the second electrode plate of the first capacitor C1. Combined with Fig.34 、 Fig.35 and Fig.36 , the second adapter block 82 is connected to the first conductive block 40 and the first conductive part 2012 to couple the second pole 212 of the fourth transistor T4 to the first electrode plate of the first capacitor C1.

[0296] Among them, referring to Fig.43 、 Fig.44 、 Fig.45 and Fig.46 , the connection method between the first adapter block 81 and the second conductive part 2022 is not unique, and it can be directly connected or transferred through the second source-drain conductive layer SD2.

[0297] Exemplarily, as Fig.44 shown, the second semiconductor layer ACT2 further includes a first connection post 91. The first connection post 91 is located between the second conductive part 2022 and the first adapter block 81 and is in electrical contact with the second conductive part 2022 and the first adapter block 81. With this arrangement, the distance between the second conductive part 2022 and the first adapter block 81 is relatively close, and the depth of the via hole that needs to be etched in the process of forming the first connection post 91 is relatively shallow, the process difficulty is low, and it is beneficial to improve the production yield.

[0298] Exemplarily, as Fig.45 As shown, the second source-drain conductive layer SD2 includes a third transfer block 83 and a second connection column 92. A part of the second connection column 92 is staggered from the second channel portion 2021 and the second conductive portion 2022, and is located between the third transfer block 83 and the first transfer block 81, and is in electrical contact with the third transfer block 83 and the first transfer block 81; another part is located between the third transfer block 83 and the second conductive portion 2022, and is in electrical contact with the third transfer block 83 and the second conductive portion 2022.

[0299] Set in this way, the first transfer block 81 and the second conductive portion 2022 are transferred through the second source-drain conductive layer SD2. The transfer process can be synchronized with the connection processes of other structures included in the second source-drain conductive layer SD2. For example, the connection between the fifth transfer block 85 and the second conductive portion 2022 mentioned below. This can simplify the process flow and reduce the manufacturing cost. Moreover, the second connection column 92 can be directly formed by one-step etching, simplifying the process flow and reducing the manufacturing cost.

[0300] Exemplarily, as Fig.46 shown, the second source-drain conductive layer SD2 further includes a fourth transfer block 84, a third connection column 93, and a fourth connection column 94. The third connection column 93 and the fourth connection column 94 are arranged at intervals. Among them, the third connection column 93 is staggered from the second channel portion 2021 and the second conductive portion 2022, and is located between the fourth transfer block 84 and the first transfer block 81, and is in electrical contact with the fourth transfer block 84 and the first transfer block 81. The fourth connection column 94 is located between the fourth transfer block 84 and the second conductive portion 2022, and is in electrical contact with the fourth transfer block 84 and the second conductive portion 2022.

[0301] Set in this way, the first transfer block 81 and the second conductive portion 2022 are transferred through the second source-drain conductive layer SD2. The transfer process can be synchronized with the connection processes of other structures included in the second source-drain conductive layer SD2. For example, the connection between the fifth transfer block 85 and the second conductive portion 2022 mentioned below. This can simplify the process flow and reduce the manufacturing cost. Moreover, the third connection column 93 and the fourth connection column 94 are formed separately, and the depths of the corresponding vias can be controlled respectively, avoiding the adverse effects caused by over-etching.

[0302] In some examples, as Fig.38A shown, the fifth gate conductive layer GT5 includes a second scan signal line GL2 and a first light emission control signal line EL1. The second scan signal line GL2 and the first light emission control signal line EL1 extend along the second direction Y, and respectively overlap with the second channel portion 2021 of the second semiconductor layer ACT2 to respectively form the first control electrode of the fifth transistor T5 and the first control electrode of the second transistor T2.

[0303] In some examples, as Fig.40 As shown, the sixth gate conductive layer GT6 includes a second scan signal line GL2 and a first light emission control signal line EL1. The second scan signal line GL2 and the first light emission control signal line EL1 extend along the second direction Y, and respectively overlap with the second channel portion 2021 of the second semiconductor layer ACT2 to respectively form the second control electrode of the fifth transistor T5 and the second control electrode of the second transistor T2.

[0304] That is to say, some of the second scan signal lines GL2 are located in the fifth gate conductive layer GT5 to form the first control electrode of the fifth transistor T5, and some of the second scan signal lines GL2 are located in the sixth gate conductive layer GT6 to form the second control electrode of the fifth transistor T5. In this way, the fifth transistor T5 can be controlled through the first control electrode and the second control electrode, and the leakage current can be reduced.

[0305] Moreover, some of the first light emission control signal lines EL1 are located in the fifth gate conductive layer GT5 to form the first control electrode of the second transistor T2, and some of the first light emission control signal lines EL1 are located in the sixth gate conductive layer GT6 to form the second control electrode of the second transistor T2. In this way, the second transistor T2 can be controlled through the first control electrode and the second control electrode, and the leakage current can be reduced.

[0306] It should be noted that the display panel 100 may also only include the fifth gate conductive layer GT5 and not include the sixth gate conductive layer GT6. Or, the display panel 100 may also only include the sixth gate conductive layer GT6 and not include the fifth gate conductive layer GT5.

[0307] Among them, as Fig.38B shown, at least 4 first light emission control signal lines EL1, for example, can be located between two second scan signal lines GL2. On this basis, the second scan signal line GL2 and the first scan signal line GL1 can at least partially overlap. The reset signal line RL is located between two adjacent first light emission control signal lines EL1 that are connected to and adjacent to the first light emission control signal terminals EM of different pixel circuits 20. With this setting, the reset signal line RL is also staggered from both the first light emission control signal line EL1 and the second scan signal line GL2, which can reduce the risk of short circuit between the reset signal line RL and the first light emission control signal line EL1 and the second scan signal line GL2, reduce the interference between signals, and the circuit structure is compact, which is beneficial to improving the pixel density.

[0308] Moreover, the fourth sub-line VDL2 can be located, for example, between the adjacent first light-emitting control signal line EL1 and the second scanning signal line GL2. In this way, the fourth sub-line VDL2 is staggered with the first light-emitting control signal line EL1 and the second scanning signal line GL2, which can reduce the risk of short-circuiting the fourth sub-line VDL2 with the first light-emitting control signal line EL1 and the second scanning signal line GL2, reduce interference between signals, and have a compact circuit structure, which is conducive to improving pixel density.

[0309] In some examples, such as Fig.41 As shown, the second source-drain conductive layer SD2 includes a reference voltage signal line VRL and a fifth adapter block 85 , which is connected to the second conductive portion 2022 and the first electrode 31 of the light-emitting device 30 to couple the second electrode 212 of the second transistor T2 to the first electrode 31 of the light-emitting device 30 .

[0310] It should be noted that, according to the arrangement of the light emitting devices 30 , the size and shape of the fifth adapter block 85 connected to different light emitting devices 30 can be adaptively adjusted, and the embodiment of the present disclosure does not specifically limit this.

[0311] In addition, the reference voltage signal line VRL includes a fifth sub-line VRL1 and a sixth sub-line VRL2, the fifth sub-line VRL1 extends along the first direction X, the sixth sub-line VRL2 extends along the second direction Y, and one fifth sub-line VRL1 is connected to a plurality of sixth sub-lines VRL2, and one sixth sub-line VRL2 is connected to a plurality of fifth sub-lines VRL1 to form a mesh structure. In this case, the reference voltage signal line VRL forms a mesh structure, which can reduce the voltage drop of the reference voltage signal and reduce the difference in the reference voltage signals received by different pixel circuits 20, thereby improving the brightness uniformity of the display panel 100.

[0312] In some embodiments, see Figure 5 The light emitting device layer 120 includes a first electrode layer 310 , a light emitting functional layer 320 and a second electrode layer 330 which are arranged in sequence, and the second electrode layer 330 is located on a side of the first electrode layer 310 away from the driving circuit layer 110 .

[0313] like Fig.41 and Fig.42A As shown, the first electrode layer 310 includes a plurality of first electrodes 31, and the first electrodes 31 are connected to the fifth adapter block 85 to be coupled to the second electrode 212 of the second transistor T2 through the fifth adapter block 85. Of course, the first electrode 31 may also be directly connected to the second electrode 212 of the second transistor T2, that is, the second source-drain conductive layer SD2 does not include the fifth adapter block 85, and the embodiments of the present disclosure are not limited thereto.

[0314] In addition, the light-emitting functional layer 320 includes a plurality of light-emitting portions 32. The second electrode layer 330 may be a continuous integral layer structure. The second electrode layer 330 includes a plurality of second electrodes 33. The second electrode 33 may be, for example, a portion of the second electrode layer 330 that overlaps with the light-emitting portion 32.

[0315] It should be noted that the light-emitting functional layer 320 may only include a light-emitting layer; or, in addition to the light-emitting layer, the light-emitting functional layer 320 further includes at least one of an electron transport layer (Election Transporting Layer, abbreviated as ETL), an electron injection layer (Election Injection Layer, abbreviated as EIL), a hole transport layer (Hole Transporting Layer, abbreviated as HTL), and a hole injection layer (Hole Injection Layer, abbreviated as HIL).

[0316] In some embodiments, as Figure 5 shown, the display panel 100 further includes a pixel definition layer PDL. The pixel definition layer PDL is provided with a plurality of pixel openings 101, and one light-emitting device 30 is located within one pixel opening 101. The shape of the pixel opening 101 is at least one of a substantially quadrilateral shape, an oval shape, and a circular shape.

[0317] In this article, "substantially circular or oval" means that the shape is generally circular or oval as a whole, but is not limited to a standard circular or oval shape. That is, the "circular or oval" here includes not only the basic circular or oval shape, but also a shape similar to a circular or oval shape.

[0318] In this article, "substantially quadrilateral" means that the shape is generally quadrilateral as a whole, but is not limited to a standard quadrilateral shape. That is, the "quadrilateral" here includes not only the basic quadrilateral shape, but also a shape similar to a quadrilateral shape. For example, the quadrilateral is curved at each intersecting position (i.e., the corner), that is, the corner is smooth, and the shape is a rounded quadrilateral.

[0319] In some embodiments, in combination with Fig.42A 、 Fig.42B and Fig.42C , the first electrode 31 includes a main body portion 301 and a lap portion 302. At least a part of the main body portion 301 is exposed by the pixel opening 101. The lap portion 302 is connected to the second pole 212 of the second transistor T2 through a connection hole 303 (see Fig.39 ). Along the first direction X, the connection hole 303 is at least partially opposite to the pixel opening 101. For example, the line connecting the geometric center of the connection hole 303 and the geometric center of the pixel opening 101 is substantially parallel to the first direction X.

[0320] In some embodiments, as Fig.42A , Fig.42B and Fig.42C As shown in Fig.42A , Fig.42B and Fig.42C , two adjacent columns of light-emitting devices 30 are the first light-emitting device column 313 and the second light-emitting device column 314. In the first light-emitting device column 313, along the first direction X, the overlapping portion 302 is located on the first side of the main body portion 301. In the second light-emitting device column 314, along the first direction X, the overlapping portion 302 is located on the second side of the main body portion 301. Among them, the first side and the second side are opposite sides of the main body portion 301.

[0321] In some embodiments, referring to Fig.42B and Fig.42C , the ratio of the area of the main body portion 301 to the area of the pixel opening 101 is 0.7 to 0.9. Exemplarily, the ratio of the area of the main body portion 301 to the area of the pixel opening 101 is any one of 0.7, 0.72, 0.75, 0.77,

[0322] 0.78, 0.8, 0.82, 0.85, 0.86, 0.88 and 0.9.

[0323] In some embodiments, referring to Fig.42B and Fig.42C , in any direction parallel to the pixel defining layer PDL (see Figure 5 ), the ratio of the size of the connection hole 303 to the size of the pixel opening 101 is 0.5 to 0.9. Exemplarily, the ratio of the size of the connection hole 303 to the size of the pixel opening 101 is any one of 0.5, 0.54, 0.55, 0.56, 0.58, 0.6, 0.65, 0.68, 0.7, 0.72, 0.75, 0.8, 0.82, 0.85, 0.88 and 0.9.

[0324] In some embodiments, referring to Figure 5 and Fig.38B , the display panel 100 includes multiple gate lines MGL. The multiple gate lines MGL may include, for example, at least one of a first light-emitting control signal line EL1, a first scan signal line GL1, a second scan signal line GL2, and a reset signal line RL. Along the direction perpendicular to the extension direction of the gate lines MGL, the ratio of the size of the gate lines MGL to the size of the pixel opening 101 is 0.5 to 1.2. Exemplarily, the ratio of the size of the gate lines MGL to the size of the pixel opening 101 is any one of 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, 1.05, 1.1, 1.15 and 1.2.

[0325] In some embodiments, as Figure 5As shown, the display panel 100 further includes an encapsulation layer 130 disposed on the side of the light-emitting device layer 120 away from the substrate 10 to reduce the risk of water and oxygen erosion. Among them, the encapsulation layer 130 can be an encapsulation film or an encapsulation substrate, and the embodiments of the present disclosure do not make specific limitations here.

[0326] In some embodiments, referring to Figure 4 , the display panel 100 includes a gate driving circuit 140 and a source driving circuit 150. Along the first direction X, the source driving circuit 150 is disposed on at least one side of the display area A; along the second direction Y, the gate driving circuit 140 is disposed on at least one side of the display area A.

[0327] Among them, the source driving circuit 150 is coupled to the data line DL, and one data line DL is coupled to at least one column of pixel circuits 20 to provide a data signal to at least one column of pixel circuits 20. Combining Figure 4 and Fig.47 , the gate driving circuit 140 includes a plurality of cascaded shift registers RS. One shift register RS is coupled to at least one control signal line KL, and one control signal line KL is coupled to one row of pixel circuits 20 to provide a control signal to at least one row of pixel circuits 20. The control signal includes any one of a first light emission control signal, a second light emission control signal, a first scan signal, a second scan signal, and a reset signal.

[0328] Exemplarily, referring to Fig.47 , the signal input terminal of the shift register RS of the first stage is coupled to the start signal line STV. Among every two adjacent shift registers RS, the signal input terminal of the lower-stage shift register RS is coupled to the output terminal of the upper-stage shift register RS.

[0329] In some examples, referring to Fig.47 , the gate driving circuit 140 is disposed on one side of the display area A, and drives each row of pixel circuits 20 sequentially row by row from one side of the display area A to form a single-sided drive. In some other examples, referring to Figure 4 , the gate driving circuit 140 is disposed on opposite sides of the display area A, and the two gate driving circuits 140 simultaneously drive each row of pixel circuits 20 sequentially row by row from opposite sides of the display area A to form a double-sided drive.

[0330] Taking the single-sided drive as an example below, some embodiments of the present disclosure are schematically described. However, the embodiments of the present disclosure are not limited thereto, and any other driving method can also be considered as long as the same technical idea is applied.

[0331] In some embodiments, referring to Fig.47, a plurality of gate driving circuits 140 includes a first gate driving circuit 141, and the first gate driving circuit 141 is coupled to a first light emission control signal line EL1 to provide a first light emission control signal.

[0332] Among them, as Fig.15A and Fig.47 shown, along the first direction X, a plurality of first light emission control signal lines EL1 are divided into a plurality of first light emission control signal line groups EL10, and each first light emission control signal line group EL10 includes at least two adjacent first light emission control signal lines EL1. Moreover, the first light emission control signal terminals EM1 of a plurality of strobe branches 221 in a row of pixel circuits 20 are respectively coupled to a plurality of first light emission control signal lines EL1 in a first light emission control signal line group EL10.

[0333] On this basis, referring to Fig.47 , a plurality of first light emission control signal lines EL1 in the first light emission control signal line group EL10 are respectively coupled to a plurality of first gate driving circuits 141, and the plurality of first gate driving circuits 141 are configured to be sequentially driven within a frame period F to respectively drive a plurality of light emitting devices 30 coupled to a row of pixel circuits 20 within a frame period F.

[0334] In addition, along the first direction Y, in any two adjacent first light emission control signal line groups EL10, the number of first light emission control signal lines EL1 between two first light emission control signal lines EL1 coupled to the same first gate driving circuit 141 is the same. In this case, the routing layout is regular, and the intervals between the rows where the sequentially lit light emitting devices 30 are located are fixed. Within a frame period F, the brightness of the light emitting devices 30 in adjacent two rows is fused, which can balance the overall brightness of the screen and improve the brightness uniformity.

[0335] Exemplarily, as Fig.47 shown, the first light emission control signal line group EL10 includes two first light emission control signal lines EL1, and the two first light emission control signal lines EL1 are respectively coupled to a first gate driving circuit 141.

[0336] At this time, one first gate driving circuit 141 is used to sequentially drive the light emitting devices 30 in odd rows, and another gate driving circuit 141 is used to sequentially drive the light emitting devices 30 in even rows. For example, one first gate driving circuit 141 sequentially drives the light emitting devices 30 in the 1st, 3rd, 5th, …, 2N + 1th rows, and another first gate driving circuit 141 sequentially drives the light emitting devices 30 in the 2nd, 4th, 6th …, 2(N + 1)th rows, where N is greater than or equal to 0 and is an integer.

[0337] Exemplarily, referring to Fig.48, the first light emission control signal line group EL10 includes three first light emission control signal lines EL1, and the three first light emission control signal lines EL1 are respectively coupled to a first gate driving circuit 141.

[0338] At this time, a first gate driving circuit 141 can, for example, sequentially drive the light emitting devices 30 in the 1st, 4th, 7th,..., (3M + 1)-th rows. A first gate driving circuit 141 can sequentially drive the light emitting devices 30 in the 2nd, 5th, 8th,..., (3M + 2)-th rows. The remaining first gate driving circuit 141 can sequentially drive the light emitting devices 30 in the 3rd, 6th, 9th,..., 3(M + 1)-th rows, where M is greater than or equal to 0 and is an integer.

[0339] In the description of this specification, specific features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0340] As described above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A pixel circuit, characterized in that: One frame period includes a plurality of sub-segments performed sequentially, each of the sub-segments includes a light-emitting phase, and the pixel circuit includes: A driving subcircuit is coupled to a first node, a second node and a third node; the first node is coupled to a data signal terminal, and the second node is coupled to a first power signal terminal; the driving subcircuit is configured to generate a driving current signal according to the voltages of the first node and the third node during the light emitting phase, and transmit the driving current signal to the third node; a gating subcircuit coupled to the third node; the gating subcircuit is configured to be coupled to a plurality of light-emitting devices, and transmit the driving current signal from the third node to different light-emitting devices in different light-emitting phases; The driving subcircuit includes a first transistor, the gating subcircuit includes a second transistor, and a channel of at least one of the second transistors is located at a different layer from a channel of the first transistor and is at least partially opposite to each other.

2. The pixel circuit according to claim 1, characterized in that: The gating subcircuit comprises: A plurality of gating branches, wherein the gating branches are coupled to the third node, the fourth node and the first light-emitting control signal terminal, and the fourth nodes and the first light-emitting control signal terminal are coupled to different gating branches; the fourth node is configured to be coupled to the light-emitting device, and the light-emitting devices coupled to different fourth nodes are different; The gating branch is configured to transmit the driving current signal of the third node to the fourth node in response to the light emitting control signal received at the first light emitting control signal terminal during one of the light emitting phases of a frame period.

3. The pixel circuit according to claim 2, characterized in that: The selection branch includes the second transistor, the control electrode of the second transistor is coupled to the first light-emitting control signal terminal, the first electrode is coupled to the third node, and the second electrode is coupled to the fourth node.

4. The pixel circuit according to claim 2, characterized in that: The sub-segment includes a reset phase, the reset phase is located before the light emitting phase, and the pixel circuit further includes: A reset subcircuit is coupled to the reset signal terminal and the initialization signal terminal, and is also coupled to the third node and / or the fourth node; the reset subcircuit is configured to, during the reset phase, transmit the initialization signal received at the initialization signal terminal to the third node and / or the fourth node in response to the reset signal received at the reset signal terminal.

5. The pixel circuit according to claim 4, characterized in that: The reset subcircuit comprises: A third transistor, wherein the control electrode of the third transistor is coupled to the reset signal terminal, the first electrode is coupled to the initialization signal terminal, and the second electrode is coupled to the third node; the channel of the third transistor is located in the same layer as the channel of the first transistor, and the channel of at least one of the second transistors is at least partially opposite to the channel of the third transistor.

6. The pixel circuit according to claim 5, characterized in that: The gating subcircuit includes two gating branches, each of which includes a second transistor; among the two second transistors included in the two gating branches, the channel of one of the second transistors is at least partially opposite to the channel of the first transistor, and the channel of the other second transistor is at least partially opposite to the channel of the third transistor.

7. The pixel circuit according to any one of claims 1 to 6, characterized in that: The sub-segment further includes a data writing phase, which is located before the light emitting phase, and the pixel circuit further includes: A data writing sub-circuit is coupled to the first scanning signal terminal, the data signal terminal and the first node; the data writing sub-circuit is configured to transmit the data signal received at the data signal terminal to the first node in response to the first scanning signal received at the first scanning signal terminal during the data writing phase.

8. The pixel circuit according to claim 7, characterized in that: The sub-segment further includes a compensation phase, the compensation phase being located before the data writing phase; The driving subcircuit is further configured to, during the compensation phase, under the control of the voltages of the first node and the third node, transmit the voltage of the second node to the third node until the voltage difference between the first node and the third node is equal to the threshold voltage of the first transistor included in the driving subcircuit; The pixel circuit further comprises: The first energy storage subcircuit is coupled to the first node and the third node; the first energy storage subcircuit is configured to, during the light-emitting stage, pull up or down the voltage of the first node according to the change of the voltage of the third node to maintain the voltage difference between the first node and the third node unchanged.

9. The pixel circuit according to claim 8, characterized in that: The data writing sub-circuit is further configured to transmit, during the compensation phase, a data signal received at the data signal terminal to the first node in response to a first scan signal received at the first scan signal terminal.

10. The pixel circuit according to claim 8, characterized in that: The pixel circuit further comprises: A first voltage sub-circuit is coupled to a second scan signal terminal, a first voltage signal terminal and the first node; the first voltage sub-circuit is configured to transmit a first voltage signal received at the first voltage signal terminal to the first node in response to a second scan signal received at the second scan signal terminal during the compensation phase.

11. The pixel circuit according to claim 7, characterized in that: The data writing sub-circuit comprises: A fourth transistor, wherein a control electrode of the fourth transistor is coupled to the first scan signal terminal, a first electrode is coupled to the data signal terminal, and a second electrode is coupled to the first node; a channel of the fourth transistor and a channel of the first transistor are located in the same layer.

12. The pixel circuit according to claim 11, characterized in that: A reset subcircuit is included, wherein the reset subcircuit includes a third transistor; along a first direction, a channel of the third transistor and a channel of the fourth transistor are located at opposite sides of a channel of the first transistor.

13. The pixel circuit according to claim 11, characterized in that: The invention comprises a first voltage subcircuit, wherein the first voltage subcircuit comprises: A fifth transistor, wherein the control electrode of the fifth transistor is coupled to the second scan signal terminal, the first electrode is coupled to the first voltage signal terminal, and the second electrode is coupled to the first node; the channel of the fifth transistor and the channel of the fourth transistor are located in different layers and are at least partially opposite to each other.

14. A display panel, characterized in that: One frame period includes a plurality of sub-segments performed sequentially, each of the sub-segments includes a light-emitting phase, and the display panel includes: A driving circuit layer, comprising a plurality of pixel circuits, wherein the pixel circuit comprises a driving subcircuit and a gating subcircuit, wherein the driving subcircuit is coupled to a first node, a second node and a third node; wherein the first node is coupled to a data signal terminal, and the second node is coupled to a first power signal terminal; wherein the gating subcircuit is coupled to the third node; wherein the driving subcircuit comprises a first transistor, and the gating subcircuit comprises a second transistor, wherein a channel of at least one of the second transistors is located in a different layer from a channel of the first transistor and is at least partially opposite to the channel of the first transistor; A light-emitting device layer is arranged on one side of the driving circuit layer; the light-emitting device layer includes a plurality of light-emitting devices, the light-emitting devices are coupled to a gating subcircuit, and at least two of the light-emitting devices are coupled to the same gating subcircuit; the gating subcircuit is configured to transmit the driving current signal from the third node to different light-emitting devices in different light-emitting stages.

15. The display panel according to claim 14, characterized in that: The pixel circuit includes a reset subcircuit, the reset subcircuit is coupled to the reset signal terminal and the initialization signal terminal, and is also coupled to the third node; the display panel also includes: An initialization signal line coupled to the initialization signal terminal; the initialization signal line comprises: A plurality of first sub-lines extending along a first direction; A plurality of second sub-lines extending along a second direction; one of the first sub-lines is connected to the plurality of second sub-lines, and one of the second sub-lines is connected to the plurality of first sub-lines; the first direction and the second direction intersect; A first power line is coupled to a first power signal terminal; the first power line comprises: a plurality of third sub-lines extending along the first direction; A plurality of fourth sub-lines extend along the second direction; one of the third sub-lines is connected to the plurality of fourth sub-lines, and one of the fourth sub-lines is connected to the plurality of third sub-lines; and the third sub-line is staggered with the first sub-line, and the fourth sub-line is staggered with the second sub-line.

16. The display panel according to claim 14, characterized in that: The pixel circuit includes a reset subcircuit, the reset subcircuit is coupled to the reset signal terminal and the initialization signal terminal, and is also coupled to the fourth node; The display panel further includes: An initialization signal line coupled to the initialization signal terminal; the initialization signal line comprises: A plurality of first sub-lines extending along a first direction; A plurality of second sub-lines extending along a second direction; one of the first sub-lines is connected to the plurality of second sub-lines, and one of the second sub-lines is connected to the plurality of first sub-lines; the first direction and the second direction intersect; A first power line is coupled to a first power signal terminal; the first power line comprises: a plurality of third sub-lines extending along the first direction; A plurality of fourth sub-lines extend along the second direction; one of the third sub-lines is connected to the plurality of fourth sub-lines, and one of the fourth sub-lines is connected to the plurality of third sub-lines; and the third sub-line is staggered with the first sub-line, and the fourth sub-line is staggered with the second sub-line.

17. The display panel according to claim 14, characterized in that: The display panel comprises 10 conductive layers, and the driving circuit layer comprises 8 conductive layers; or, the display panel comprises 9 conductive layers, and the driving circuit layer comprises 7 conductive layers; or, the display panel comprises 8 conductive layers, and the driving circuit layer comprises 6 conductive layers.

18. The display panel according to claim 17, characterized in that: The pixel circuit includes a data writing subcircuit, and the data writing subcircuit is coupled to a first scanning signal terminal, a data signal terminal and a first node; the display panel includes a first source-drain conductive layer, and the first source-drain conductive layer includes a data line, and the data line is coupled to the data signal terminal; The driving circuit layer comprises: A first semiconductor layer including a first channel portion and a first conductive portion; a first gate conductive layer, disposed on a side of the first semiconductor layer close to the light emitting device layer; the first gate conductive layer comprises a reset signal line and a first scan signal line, the reset signal line and the first scan signal line extend along a second direction, and the reset signal line and the first scan signal line overlap with a first channel portion of the first semiconductor layer respectively; A second gate conductive layer is disposed on a side of the first gate conductive layer close to the light emitting device layer; the second gate conductive layer includes a second conductive block; The third gate conductive layer is arranged on a side of the second gate conductive layer close to the light emitting device layer.

19. The display panel according to claim 18, characterized in that: The first gate conductive layer further includes a first conductive block, the first conductive block overlaps with the first channel portion of the first semiconductor layer, and the second conductive block is at least partially opposite to the first conductive block.

20. The display panel according to claim 18, characterized in that: The third gate conductive layer further includes a third conductive block, and the third conductive block is at least partially opposite to the second conductive block.

21. The display panel according to claim 18, characterized in that: The display panel further includes an initialization signal line and a first power line, the initialization signal line includes a first sub-line and a second sub-line, and the first power line includes a third sub-line and a fourth sub-line: The first sub-line is located in the first source-drain conductive layer; the second sub-line is located in the second gate conductive layer; the third sub-line and the fourth sub-line are located in the third gate conductive layer.

22. The display panel according to claim 18, characterized in that: The display panel further includes an initialization signal line and a first power line, the initialization signal line includes a first sub-line and a second sub-line, and the first power line includes a third sub-line and a fourth sub-line: The first sub-line and the third sub-line are located in the first source-drain conductive layer, and the second sub-line and the fourth sub-line are located in the second gate conductive layer.

23. The display panel according to claim 21, characterized in that: The reset signal line and the first scanning signal line extend along the second direction, and two of the reset signal lines are located between two of the first scanning signal lines.

24. The display panel according to claim 23, characterized in that: The second sub-line is located between two adjacent reset signal lines.

25. The display panel according to claim 23, characterized in that: The fourth sub-line is located between the reset signal line and the first scan signal line.

26. The display panel according to claim 14, characterized in that: The driving circuit layer comprises: A first sub-driving layer, comprising a first transistor; The second sub-driving layer is arranged between the first sub-driving layer and the light-emitting device layer; the second sub-driving layer includes second transistors, and a channel of at least one second transistor is at least partially opposite to a channel of the first transistor.

27. The display panel according to claim 26, characterized in that: The pixel circuit includes a data writing subcircuit, and the data writing subcircuit is coupled to the first scanning signal terminal, the data signal terminal and the first node; the display panel also includes: The first source-drain conductive layer is disposed between the first sub-driving layer and the second sub-driving layer; the first source-drain conductive layer includes a data line, and the data line is coupled to the data signal terminal.

28. The display panel according to claim 27, characterized in that: The first sub-driving layer includes a second gate conductive layer, the second gate conductive layer includes a second conductive block; the second sub-driving layer includes: A fourth gate conductive layer, comprising a first transfer block, wherein the first transfer block is connected to the second conductive block; A second semiconductor layer is arranged on a side of the fourth gate conductive layer away from the first sub-driving layer; the second semiconductor layer includes a second channel portion, a second conductive portion and a first connecting column; the first connecting column is located between the second conductive portion and the first adapter block, and is electrically contacted with the second conductive portion and the first adapter block.

29. The display panel according to claim 27, characterized in that: The first sub-driving layer includes a second gate conductive layer, the second gate conductive layer includes a second conductive block; the second sub-driving layer includes: A fourth gate conductive layer, comprising a first transfer block, wherein the first transfer block is connected to the second conductive block; A second semiconductor layer is disposed on a side of the fourth gate conductive layer away from the first sub-driving layer; the second semiconductor layer includes a second channel portion and a second conductive portion; A second source-drain conductive layer is arranged on a side of the second semiconductor layer away from the first sub-driving layer; the second source-drain conductive layer includes a third adapter block and a second connecting column, a portion of the second connecting column is staggered with the second channel portion and the second conductive portion, and is located between the third adapter block and the first adapter block, and is electrically contacted with the third adapter block and the first adapter block; the other portion is located between the third adapter block and the second conductive portion, and is electrically contacted with the third adapter block and the second conductive portion.

30. The display panel according to claim 27, characterized in that: The first sub-driving layer includes a second gate conductive layer, the second gate conductive layer includes a second conductive block; the second sub-driving layer includes: A fourth gate conductive layer, comprising a first transfer block, wherein the first transfer block is connected to the second conductive block; A second semiconductor layer is disposed on a side of the fourth gate conductive layer away from the first sub-driving layer; the second semiconductor layer includes a second channel portion and a second conductive portion; A second source-drain conductive layer is arranged on a side of the second semiconductor layer away from the first sub-driving layer; the second source-drain conductive layer includes a fourth adapter block, a third connecting column and a fourth connecting column, and the third connecting column and the fourth connecting column are arranged at intervals; wherein the third connecting column is staggered with the second channel portion and the second conductive portion, and is located between the fourth adapter block and the first adapter block, and is electrically contacted with the fourth adapter block and the first adapter block; the fourth connecting column is located between the fourth adapter block and the second conductive portion, and is electrically contacted with the fourth adapter block and the second conductive portion.

31. The display panel according to claim 28, characterized in that: The second sub-driving layer further includes a fifth gate conductive layer, the fifth gate conductive layer is arranged on a side of the fourth gate conductive layer away from the first sub-driving layer, and the second semiconductor layer is arranged on a side of the fifth gate conductive layer away from the first sub-driving layer; The fifth gate conductive layer includes a second scan signal line and a first light emission control signal line, wherein the second scan signal line and the first light emission control signal line extend along a second direction and overlap with a second channel portion of the second semiconductor layer, respectively.

32. The display panel according to claim 28, characterized in that: The second sub-driving layer further includes a sixth gate conductive layer, and the sixth gate conductive layer is arranged on a side of the second semiconductor layer away from the first sub-driving layer; The sixth gate conductive layer includes a second scan signal line and a first light emission control signal line, wherein the second scan signal line and the first light emission control signal line extend along a second direction and overlap with a second channel portion of the second semiconductor layer, respectively.

33. The display panel according to claim 31, characterized in that: At least four of the first light-emitting control signal lines are located between two of the second scanning signal lines.

34. The display panel according to claim 33, characterized in that: comprising a reset signal line and a first scan signal line, wherein the reset signal line and the first scan signal line extend along the second direction; The second scanning signal line at least partially overlaps with the first scanning signal line; the reset signal line is located between two adjacent first light emitting control signal lines connected to first light emitting control signal terminals belonging to different pixel circuits.

35. The display panel according to claim 34, characterized in that: The device further includes a first power line, wherein the first power line includes a third sub-line and a fourth sub-line, and the fourth sub-line is located between the first light emitting control signal line and the second scanning signal line that are adjacent to each other.

36. The display panel according to claim 26, characterized in that: The first sub-driving layer includes a first semiconductor layer, the material of which includes oxide or low-temperature polysilicon; the second sub-driving layer includes a second semiconductor layer, the material of which includes oxide or low-temperature polysilicon.

37. The display panel according to claim 36, characterized in that: The material of the first semiconductor layer and the second semiconductor layer includes oxide.

38. The display panel according to claim 26, characterized in that: A difference between the number of transistors included in the first sub-driving layer and the number of transistors included in the second sub-driving layer is 0 or 1.

39. The display panel according to any one of claims 14 to 38, characterized in that: The driving circuit layer includes a plurality of pixel circuits, and the plurality of pixel circuits are arranged in multiple rows and columns, each column includes at least two pixel circuits arranged along a first direction, and each row includes at least two pixel circuits arranged along a second direction, and the first direction and the second direction intersect; and, in the first direction and / or the second direction, any two adjacent pixel circuits are symmetrically arranged.

40. The display panel according to any one of claims 14 to 38, characterized in that: The plurality of light-emitting devices are arranged in a plurality of rows and columns, each column includes at least two light-emitting devices arranged along a first direction, each row includes at least two light-emitting devices arranged along a second direction, the first direction and the second direction intersect; and the plurality of light-emitting devices coupled to the same selection subcircuit are located in the same column.

41. The display panel according to claim 40, characterized in that: The gating subcircuit comprises a plurality of gating branches, wherein the gating branches are coupled to the third node, the fourth node and the first light-emitting control signal terminal, the fourth node is coupled to the light-emitting device, and the fourth nodes coupled to different gating branches are coupled to different light-emitting devices; The display panel further includes: a first gate driving circuit; a first light-emitting control signal line coupled to the first gate driving circuit; along the first direction, a plurality of the first light-emitting control signal lines are divided into a plurality of first light-emitting control signal line groups, each of the first light-emitting control signal line groups includes at least two first light-emitting control signal lines arranged adjacent to each other; and first light-emitting control signal terminals of a plurality of selection branches in a row of the pixel circuits are respectively coupled to a plurality of first light-emitting control signal lines in one of the first light-emitting control signal line groups; Multiple first light-emitting control signal lines in the first light-emitting control signal line group are respectively coupled to multiple first gate driving circuits; and, along the first direction, in any two adjacent first light-emitting control signal line groups, the number of first light-emitting control signal lines between two first light-emitting control signal lines coupled to the same first gate driving circuit is the same.

42. The display panel according to claim 40, characterized in that: The plurality of columns of light emitting devices include a first type of light emitting device column and a second type of light emitting device column; At least two of the light-emitting devices in the first-type light-emitting device column emit light of different colors; and the light-emitting devices in the second-type light-emitting device column emit light of the same color.

43. The display panel according to claim 42, characterized in that: The first type of light emitting device column includes a plurality of red light emitting devices and a plurality of blue light emitting devices, and the plurality of red light emitting devices and the plurality of blue light emitting devices are arranged alternately; the second type of light emitting device column includes a plurality of green light emitting devices; Alternatively, the first type of light emitting device column includes a plurality of red light emitting devices and a plurality of green light emitting devices, and the plurality of red light emitting devices and the plurality of green light emitting devices are arranged alternately; and the second type of light emitting device column includes a plurality of blue light emitting devices.

44. The display panel according to claim 40, characterized in that: It also includes a pixel defining layer, the pixel defining layer is provided with a plurality of pixel openings, one of the light emitting devices is located in one of the pixel openings; the shape of the pixel opening is substantially at least one of a quadrilateral, an ellipse and a circle.

45. The display panel according to claim 44, characterized in that: The light emitting device comprises a first electrode, a light emitting portion and a second electrode, wherein the first electrode and the second electrode are located at opposite sides of the light emitting portion, and the first electrode is located at a side of the light emitting portion close to the driving circuit layer; The first electrode includes a main body portion and a lap portion, the pixel opening exposes at least a portion of the main body portion, and the lap portion is connected to the second electrode of the second transistor through a connection hole.

46. ​​The display panel according to claim 45, characterized in that: Two adjacent columns of light-emitting devices are a first column of light-emitting devices and a second column of light-emitting devices. In the first column of light-emitting devices, along the first direction, the overlapping portion is located on the first side of the main body; in the second column of light-emitting devices, along the first direction, the overlapping portion is located on the second side of the main body; the first side and the second side are opposite sides of the main body.

47. The display panel according to claim 45, characterized in that: The area ratio of the main body portion to the pixel opening is 0.7 to 0.

9.

48. The display panel according to claim 45, characterized in that In any direction parallel to the pixel defining layer, the ratio of the size of the connection hole to the size of the pixel opening is 0.5 to 0.

9.

49. The display panel according to claim 45, characterized in that It comprises a plurality of gate lines, which include at least one of a first light-emitting control signal line, a first scanning signal line, a second scanning signal line and a reset signal line. Along an extension direction perpendicular to the gate lines, a ratio of a size of the gate lines to a size of the pixel opening is 0.5 to 1.

2.

50. A display panel, characterized in that: include: The driving circuit layer includes a plurality of pixel circuits, wherein the pixel circuits include a common subcircuit, wherein the common subcircuit is coupled to the data signal terminal, the first power signal terminal and the third node; the common subcircuit is configured to generate a driving current signal in a light emitting stage, and transmit the driving current signal to the third node; A light-emitting device layer is arranged on one side of the driving circuit layer; the light-emitting device layer includes a plurality of light-emitting devices, the light-emitting devices are coupled to the common sub-circuit, and at least two of the light-emitting devices are coupled to the same common sub-circuit; the light-emitting device includes a first electrode, the first electrode includes a main body and a lap part, and the lap part is connected to the pixel circuit through a connecting hole; A pixel defining layer is disposed on one side of the driving circuit layer; the pixel defining layer is provided with a plurality of pixel openings, one of the light emitting devices is located in one of the pixel openings, and the pixel opening exposes at least a portion of the main body; Along the first direction, the connection hole is at least partially opposite to the pixel opening.

51. The display panel according to claim 50, characterized in that: The shared sub-circuit comprises: A driving subcircuit is coupled to the first node, the second node and the third node; the first node is coupled to the data signal terminal, and the second node is coupled to the first power signal terminal; the driving subcircuit is configured to generate a driving current signal according to the voltages of the first node and the third node during the light-emitting phase, and transmit the driving current signal to the third node.

52. The display panel according to claim 50, characterized in that: The shared sub-circuit also includes: A reset subcircuit is coupled to the third node, the reset signal terminal and the initialization signal terminal; the reset subcircuit is configured to, in a reset phase, transmit the initialization signal received at the initialization signal terminal to the third node in response to the reset signal received at the reset signal terminal.

53. The display panel according to claim 50, characterized in that: The shared sub-circuit also includes: A data writing subcircuit is coupled to the first scanning signal terminal, the data signal terminal and the first node; the data writing subcircuit is configured to, in a data writing phase, transmit the data signal received at the data signal terminal to the first node in response to the first scanning signal received at the first scanning signal terminal.

54. The display panel according to claim 50, characterized in that: The shared sub-circuit also includes: The first energy storage subcircuit is coupled to the first node and the third node; the first energy storage subcircuit is configured to, during the light-emitting stage, pull up or down the voltage of the first node according to the change of the voltage of the third node to maintain the voltage difference between the first node and the third node unchanged.

55. The display panel according to any one of claims 50 to 54, characterized in that: The shared sub-circuit also includes: A first voltage sub-circuit is coupled to a second scan signal terminal, a first voltage signal terminal and a first node; the first voltage sub-circuit is configured to, in a compensation phase, transmit a first voltage signal received at the first voltage signal terminal to the first node in response to a second scan signal received at the second scan signal terminal.

56. A display device, characterized in that: The display device is any one of a wearable device, a virtual reality device and an augmented reality device, and the display device includes: The display panel according to any one of claims 14 to 55; A circuit board is connected to the display panel.

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