Clock signal generation method and device, electronic equipment and readable medium

Abstract

The invention belongs to the technical field of signal processing, and particularly discloses a clock signal generation method and device, equipment and a medium. The method comprises the following steps: determining a frequency parameter of a frequency adjustment unit according to a frequency association relationship between a first clock signal frequency of an original clock source and a second clock signal frequency of a to-be-generated target clock signal, the first clock signal frequency and a third clock signal frequency of a preset clock source, the frequency adjusting unit generates a target clock signal according to the frequency parameter; respectively counting the target clock signal and a source clock signal of an original clock source; determining whether the original clock source is in an abnormal state according to the first count value of the source clock signal and the second count value of the target clock signal; and when the original clock source is in a non-abnormal state, updating the frequency parameter, so that the frequency adjustment unit generates a subsequent target clock signal according to the updated frequency parameter. The method can improve the stability of the generated clock signal.

Description

Technical Field

[0001] The present disclosure relates to the field of signal processing technology, and in particular to a clock signal generating method, generating device, electronic device and readable medium. Background Art

[0002] In application scenarios such as video matrix, it is necessary to generate an output clock with a frequency correspondence relationship for the source clock. For example, the clock frequency of the output clock is in a multiple relationship with the clock frequency of the source clock.

[0003] However, in the traditional clock signal generation method, in order to generate an output clock having a frequency corresponding to the source clock, the source clock can only be used as a reference clock for frequency adjustment. Once the source clock is disordered, the output clock will be abnormal, affecting practical applications. Summary of the invention

[0004] To this end, the present disclosure provides a clock signal generating method, generating device, electronic device and readable medium to solve the problem of output clock abnormality caused by source clock disorder in the prior art.

[0005] In order to achieve the above object, the present disclosure provides a clock signal generating method according to a first aspect, the method comprising:

[0006] Determine a frequency correlation relationship between a first clock signal frequency of an original clock source and a second clock signal frequency of a target clock signal to be generated;

[0007] Determine a frequency parameter of a frequency adjustment unit according to the frequency association relationship, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, so that the frequency adjustment unit generates a target clock signal according to the frequency parameter and the third clock signal frequency of the preset clock source;

[0008] Counting the generated target clock signal and the source clock signal of the original clock source respectively to obtain a first count value of the source clock signal and a second count value of the target clock signal;

[0009] Determining whether the original clock source is in an abnormal state according to the first count value and the second count value;

[0010] When the original clock source is in a non-abnormal state, the frequency parameter is updated according to the first count value and the second count value, so that the frequency adjustment unit generates a subsequent target clock signal according to the updated frequency parameter.

[0011] In an optional implementation, the target clock signal and the source clock signal are counted according to a preset counter, and the respectively counting of the generated target clock signal and the source clock signal of the original clock source includes:

[0012] Determining a target counting threshold value from a counting range of the preset counter;

[0013] Counting a source clock signal of the original clock source to obtain a first count value of the source clock signal;

[0014] When the first count value reaches the target count threshold, the target clock signal is counted to obtain a second count value of the target clock signal.

[0015] In an optional implementation, determining whether the original clock source is in an abnormal state according to the first count value and the second count value includes:

[0016] Determine a preset upper boundary abnormality threshold and a preset lower boundary abnormality threshold according to the target counting threshold and the first threshold interval;

[0017] Calculating a count difference between the first count value and the second count value;

[0018] When the count difference value is greater than the preset upper boundary abnormal threshold or the count difference value is less than the preset lower boundary abnormal threshold, it is determined that the original clock source is in an abnormal state.

[0019] In an optional implementation manner, updating the frequency parameter according to the first count value and the second count value includes:

[0020] Determine a target upper boundary threshold and a target lower boundary threshold according to the target counting threshold and the second threshold interval;

[0021] When the count difference between the first count value and the second count value is greater than the target upper boundary threshold or the count difference is less than the target lower boundary threshold, the frequency parameter is updated according to the count difference.

[0022] In an optional implementation manner, updating the frequency parameter according to the count difference includes:

[0023] Determining a target frequency parameter adjustment mode from at least two preset frequency parameter adjustment modes according to a comparison result of the count difference value with the target upper boundary threshold and the target lower boundary threshold;

[0024] Determining a parameter adjustment region corresponding to the target frequency parameter adjustment method according to the count difference;

[0025] The parameter value corresponding to the parameter adjustment area in the frequency parameter is updated.

[0026] In an optional implementation, before counting the generated target clock signal and the source clock signal of the original clock source respectively, the method further includes:

[0027] Determining a frequency adjustment parameter corresponding to the original clock source according to the frequency association relationship;

[0028] The frequency of the first clock signal of the original clock source is adjusted according to the frequency adjustment parameter corresponding to the original clock source to obtain a source clock signal after frequency adjustment.

[0029] In an optional implementation, the method further includes:

[0030] If no clock edge of the source clock signal is detected within a preset time, determining that the original clock source is in an abnormal state;

[0031] In the case where it is determined that the original clock source is in an abnormal state, the frequency parameter is set to a preset frequency parameter, so that the frequency adjustment unit generates a subsequent target clock signal according to the preset frequency parameter.

[0032] A second aspect of the present disclosure provides a clock signal generating device, the device comprising:

[0033] A determination module, used to determine a frequency correlation relationship between a first clock signal frequency of an original clock source and a second clock signal frequency of a target clock signal to be generated;

[0034] a generating module, configured to determine a frequency parameter of a frequency adjusting unit according to the frequency association relationship, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, so that the frequency adjusting unit generates a target clock signal according to the frequency parameter and the third clock signal frequency of the preset clock source;

[0035] A counting module, used for counting the generated target clock signal and the source clock signal of the original clock source respectively, to obtain a first count value of the source clock signal and a second count value of the target clock signal;

[0036] A judging module, configured to determine whether the original clock source is in an abnormal state according to the first count value and the second count value;

[0037] The updating module is used to update the frequency parameter according to the first count value and the second count value when the original clock source is in a non-abnormal state, so that the frequency adjustment unit generates a subsequent target clock signal according to the updated frequency parameter.

[0038] A third aspect of the present disclosure provides an electronic device, including:

[0039] one or more processors;

[0040] A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the above-mentioned clock signal generation method;

[0041] One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

[0042] A fourth aspect of the present disclosure provides a computer-readable medium having a computer program stored thereon, wherein the program implements the above-mentioned clock signal generating method when executed by a processor.

[0043] The present disclosure has the following advantages:

[0044] In an embodiment of the present disclosure, first, a frequency correlation relationship between a first clock signal frequency of an original clock source and a second clock signal frequency of a target clock signal to be generated is determined; then, based on the frequency correlation relationship, the first clock signal frequency of the original clock source, and the third clock signal frequency of a preset clock source, a frequency parameter of a frequency adjustment unit is determined, so that the frequency adjustment unit generates a target clock signal based on the frequency parameter and the third clock signal frequency of the preset clock source; secondly, the generated target clock signal and the source clock signal of the original clock source are counted respectively to obtain a first count value of the source clock signal and a second count value of the target clock signal; finally, based on the first count value and the second count value, it is determined whether the original clock source is in an abnormal state; thereby, when the original clock source is in a non-abnormal state, the frequency parameter is updated based on the first count value and the second count value, so that the frequency adjustment unit generates a subsequent target clock signal based on the updated frequency parameter.

[0045] It can be seen that the embodiment of the present disclosure generates a target clock signal through a frequency adjustment unit according to frequency parameters and a preset clock source rather than an original clock source, and the embodiment of the present disclosure updates the frequency parameters according to the first count value of the source clock signal of the original clock source and the second count value of the target clock signal only when the original clock source is in a non-abnormal state. On the one hand, it ensures that when the original clock source is in a non-abnormal state, a target clock signal having a frequency correlation with the source clock signal of the original clock source can be generated. On the other hand, even if the original clock source is in an abnormal state, a stable target clock signal can be generated according to the frequency parameters and the preset clock source to avoid clock loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are used to provide further understanding of the present disclosure and constitute a part of the specification. They are used to explain the present disclosure together with the following detailed description, but do not constitute a limitation of the present disclosure.

[0047] Figure 1 A flowchart of a clock signal generation method provided by an embodiment of the present disclosure;

[0048] Figure 2 A schematic diagram of frequency parameter adjustment in an embodiment of the present disclosure;

[0049] Figure 3 A flowchart of a clock signal generation method provided by an embodiment of the present disclosure;

[0050] Figure 4 A schematic diagram of a clock signal generation method provided by an embodiment of the present disclosure;

[0051] Figure 5 A block diagram of a clock signal generating device provided by an embodiment of the present disclosure;

[0052] Figure 6 A block diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0054] As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure.As used in the present disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0056] When the terms “comprising” and / or “made of…” are used in the present disclosure, it specifies the existence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0057] The embodiments described in the present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic diagrams of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as those commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0059] In clock signal application scenarios, such as video matrix scenarios, the clock frequencies of the source clock and the output clock need to satisfy a frequency correspondence relationship. For example, the clock frequency of the output clock is a fixed multiple of the clock frequency of the source clock.

[0060] However, in the traditional clock signal generation method, only the frequency of the source clock can be adjusted to generate the output clock. Once the source clock is disordered, the output clock will also become abnormal.

[0061] In view of this, the embodiments of the present disclosure provide a clock signal generating method, a generating device, an electronic device and a readable medium, wherein a target clock signal is generated according to a frequency parameter and a preset clock source instead of an original clock source through a frequency adjustment unit, and the frequency parameter is updated according to a first count value of a source clock signal of the original clock source and a second count value of a target clock signal only when the original clock source is in a non-abnormal state. On the one hand, it is ensured that when the original clock source is in a non-abnormal state, a target clock signal having a frequency correlation with the source clock signal of the original clock source can be generated. On the other hand, even when the original clock source is in an abnormal state, a stable target clock signal can be generated according to the frequency parameter and the preset clock source to avoid clock loss.

[0062] In a first aspect, an embodiment of the present disclosure provides a method for generating a clock signal.

[0063] Figure 1 A flowchart of a clock signal generation method provided in an embodiment of the present disclosure, referring to Figure 1 , the method comprising:

[0064] Step S110: Determine a frequency correlation relationship between a first clock signal frequency of an original clock source and a second clock signal frequency of a target clock signal to be generated.

[0065] The original clock source is a signal source that generates a source clock signal, that is, a source clock. The first clock signal frequency of the original clock source refers to the number of times the original clock source generates a source clock signal per unit time.

[0066] The target clock signal is a clock signal to be generated. The second clock signal frequency of the target clock signal is the number of times the target clock signal is generated per unit time.

[0067] It should be noted that the frequency correlation relationship between the second clock signal frequency and the first clock signal frequency is used to characterize a preset numerical relationship between the second clock signal frequency and the first clock signal frequency.

[0068] For example, the ratio of the second clock signal frequency to the first clock signal frequency is a preset multiplier value, or the second clock signal frequency is equal to the first clock signal frequency, which is not limited in the embodiment of the present disclosure.

[0069] It should also be noted that the frequency association relationship needs to be adaptively determined according to the actual application scenario, and the embodiments of the present disclosure do not limit this.

[0070] For example, in a video matrix scenario, it is necessary to achieve consistent frame rates for different display devices by converting the clock signal frequency of the clock source.

[0071] Therefore, for two display devices A and display device B, it is assumed that the clock signal of display device A is a source clock signal generated by an original clock source, and its clock signal frequency is a first clock signal frequency.

[0072] Then, in order to achieve the same frame rate between display device A and display device B, a target clock signal needs to be generated for display device B, and the frequency correlation relationship between the second clock signal frequency and the first clock signal frequency of the target clock signal can be determined in the following way:

[0073]

[0074] Among them, the input horizontal pixel count and the input vertical pixel count are the number of pixels displayed by display device A in the horizontal direction and the vertical direction respectively, and the output horizontal pixel count and the output vertical pixel count are the number of pixels displayed by display device B in the horizontal direction and the vertical direction respectively. Therefore, through the above-mentioned frequency association relationship, the frame rates of display device A and display device B are kept consistent.

[0075] Step S120: Determine the frequency parameter of the frequency adjustment unit according to the frequency association relationship, the first clock signal frequency of the original clock source and the third clock signal frequency of the preset clock source, so that the frequency adjustment unit generates a target clock signal according to the frequency parameter and the third clock signal frequency of the preset clock source.

[0076] The preset clock source is a reference clock required by the frequency adjustment unit when generating a target clock signal.

[0077] It should be noted that since the original clock source, such as the chip input clock, has poor stability, it is easy for the original clock source to fail. Therefore, in order to improve the stability of the preset clock source, a stable clock such as a crystal oscillator clock can be selected as the preset clock source.

[0078] The third clock signal frequency of the preset clock source is used to represent the number of times the preset clock source generates a clock signal within a unit time.

[0079] The frequency parameter of the frequency adjustment unit is used to characterize the correlation between the third clock signal frequency of the preset clock source and the second clock signal frequency of the target clock signal to be generated.

[0080] That is, assuming that the third clock signal frequency of the preset clock source is f1, the second clock signal frequency of the target clock signal to be generated by the frequency adjustment unit is n*f1, where n is a frequency parameter of the frequency adjustment unit, and n is greater than 0.

[0081] Correspondingly, the input of the frequency adjustment unit is the clock signal generated by the preset clock source, and the output of the frequency adjustment unit is the target clock signal.

[0082] It should be noted that the frequency parameter can be determined according to the first clock signal frequency, the third clock signal frequency and the frequency association relationship.

[0083] For example, assuming that the frequency association relationship is the ratio between the second clock signal frequency and the first clock signal frequency, the frequency parameter can be obtained by multiplying the frequency association relationship by the frequency ratio between the first clock signal frequency and the third clock signal frequency.

[0084] Therefore, after determining the frequency parameters of the frequency adjustment unit, by continuously inputting the clock signal generated by the preset clock source into the frequency adjustment unit, the frequency adjustment unit can adjust the third clock signal frequency of the preset clock source according to the frequency parameters and continuously generate the corresponding target clock signal.

[0085] It should also be noted that the frequency adjustment unit is a circuit device for adjusting the frequency of an input signal, and a corresponding frequency adjustment unit can be adaptively selected according to the frequency adjustment requirements.

[0086] For example, when the clock signal frequency of the input signal needs to be amplified, a frequency multiplier can be selected as the frequency adjustment unit. When the clock signal frequency of the input signal needs to be reduced, a frequency divider can be selected as the frequency adjustment unit. The embodiments of the present disclosure do not limit this.

[0087] Step S130: Count the generated target clock signal and the source clock signal of the original clock source respectively to obtain a first count value of the source clock signal and a second count value of the target clock signal.

[0088] A preset counter may be used to count the target clock signal and the source clock signal.

[0089] Specifically, the preset counter adds 1 to the second count value of the target clock signal when a clock edge of the target clock signal is detected.

[0090] The preset counter increases the first count value of the source clock signal by 1 when a clock edge of the source clock signal is detected.

[0091] In an optional implementation, in order to avoid frequent updates of the frequency parameters, a target counting threshold may be set to delay counting of the target clock signal.

[0092] Correspondingly, the generated target clock signal and the source clock signal of the original clock source are counted respectively, including: determining a target counting threshold from a counting range of a preset counter; counting the source clock signal of the original clock source to obtain a first counting value of the source clock signal; and when the first counting value reaches the target counting threshold, counting the target clock signal to obtain a second counting value of the target clock signal.

[0093] The counting range of the preset counter is determined by the number of bits of the preset counter.

[0094] By selecting the target count threshold, it is convenient to determine the preset numerical relationship between the first count value and the second count value. Assuming that the second clock signal frequency of the generated target clock signal and the first clock signal frequency of the original clock source are always in a stable state, the count difference between the first count value and the second count value should be the target count threshold.

[0095] It should be noted that when determining the target counting threshold from the counting range of the preset counter, it can be adaptively selected according to actual needs, and the embodiments of the present disclosure do not limit this.

[0096] Exemplarily, the middle value of the counting range can be selected as the target counting threshold. The target clock signal will only be counted when the first counting value reaches the middle value of the counting range. Therefore, the frequency parameter will not be updated before the first counting value reaches the middle value of the counting range, effectively avoiding frequent updates of the frequency parameters.

[0097] It should also be noted that since the preset counter will give priority to counting the source clock signal, when the first count value reaches the counting range of the preset counter, the first count value and the second count value need to be reset, that is, re-counted, to avoid the counting disorder phenomenon that the source clock signal has been re-counted while the target clock signal is still continuing to count.

[0098] Step S140: Determine whether the original clock source is in an abnormal state according to the first count value and the second count value.

[0099] The original clock source being in an abnormal state means that the original clock source has clock disorder, clock failure, clock loss, etc.

[0100] Since the preset clock source of the embodiment of the present disclosure is a stable clock, when the original clock source is in a non-abnormal state, the numerical relationship between the first count value and the second count value should be within a preset numerical range.

[0101] Therefore, by calculating the numerical relationship between the first count value and the second count value and comparing the numerical relationship with the preset numerical range, it can be determined whether the original clock source is in an abnormal state.

[0102] Exemplarily, if the numerical relationship between the first count value and the second count value is a difference relationship, the preset numerical range can be determined by the upper boundary abnormal threshold and the lower boundary abnormal threshold corresponding to the difference relationship.

[0103] If the numerical relationship between the first count value and the second count value is a ratio relationship, the preset numerical range can be determined by the upper boundary abnormal threshold and the lower boundary abnormal threshold corresponding to the ratio relationship.

[0104] Step S150: When the original clock source is in a normal state, the frequency parameter is updated according to the first count value and the second count value, so that the frequency adjustment unit generates a subsequent target clock signal according to the updated frequency parameter.

[0105] Among them, when the original clock source is in a non-abnormal state, by comparing the first count value with the second count value, it is possible to determine whether the clock signal frequency of the target clock signal generated by the frequency adjustment unit has a frequency correlation relationship with the clock signal frequency of the original clock source based on the numerical relationship between the first count value and the second count value.

[0106] Thus, according to the first count value and the second count value, the frequency parameters of the frequency adjustment unit are updated, so that the frequency adjustment unit can adjust the third clock signal frequency of the preset clock source according to the updated frequency parameters to generate a subsequent target clock signal, thereby achieving the effect that the target clock signal follows the source clock signal.

[0107] It should also be noted that when the first count value or the second count value reaches the count range of the preset counter, or after the frequency parameters are updated, the generated target clock signal and the source clock signal need to be recounted. Therefore, the above steps S130 to S150 can be executed repeatedly to continuously detect whether the original clock source is in an abnormal state and continuously update the frequency parameters, so that the frequency adjustment unit can continuously fine-tune and generate subsequent target clock signals according to the updated frequency parameters.

[0108] In the disclosed embodiment, a target clock signal is generated by a frequency adjustment unit based on frequency parameters and a preset clock source instead of an original clock source, and the frequency parameters are updated based on a first count value of a source clock signal of the original clock source and a second count value of a target clock signal only when the original clock source is in a non-abnormal state. On the one hand, it is ensured that a target clock signal having a frequency correlation with the source clock signal of the original clock source can be generated when the original clock source is in a non-abnormal state. On the other hand, even when the original clock source is in an abnormal state, a stable target clock signal can be generated based on the frequency parameters and the preset clock source to avoid clock loss.

[0109] In addition, those skilled in the art may also make various modifications and variations to the method disclosed herein:

[0110] In an optional implementation, in order to accurately determine whether the original clock source is in an abnormal state, the abnormal threshold can be determined based on the target counting threshold and the threshold interval, so that by comparing the count difference between the first counting value and the second counting value with the abnormal threshold, it can be determined whether the original clock source is in an abnormal state.

[0111] Correspondingly, based on the first count value and the second count value, it is determined whether the original clock source is in an abnormal state, including: determining a preset upper boundary abnormal threshold and a preset lower boundary abnormal threshold according to the target count threshold and the first threshold interval; calculating the count difference between the first count value and the second count value; and determining that the original clock source is in an abnormal state when the count difference is greater than the preset upper boundary abnormal threshold or the count difference is less than the preset lower boundary abnormal threshold.

[0112] The target counting threshold is a counting threshold selected from a counting range of a preset counter, and its specific explanation is referred to the above description and will not be repeated here.

[0113] The preset upper boundary abnormal threshold is an upper boundary value for determining that the original clock source is in an abnormal state. When the count difference between the first count value and the second count value is greater than the preset upper boundary abnormal threshold, it is determined that the original clock source is in an abnormal state.

[0114] The preset lower boundary abnormal threshold is a lower boundary value for determining that the original clock source is in an abnormal state. When the count difference between the first count value and the second count value is less than the preset lower boundary abnormal threshold, it is determined that the original clock source is in an abnormal state.

[0115] That is to say, the preset upper boundary abnormal threshold must be greater than the preset lower boundary abnormal threshold.

[0116] It should be noted that in order to make the preset upper boundary abnormality threshold and the preset lower boundary abnormality threshold within a reasonable range, the preset upper boundary abnormality threshold and the preset lower boundary abnormality threshold need to be determined according to the target counting threshold and the first threshold interval.

[0117] Wherein, when the original clock source is in a non-abnormal state, the count difference between the first count value and the second count value needs to be the same as the target count threshold, or has only a small deviation from the target count threshold.

[0118] Therefore, by determining the first threshold interval, and thereby increasing or decreasing the target count threshold by the first threshold interval, the preset upper boundary abnormality threshold and the preset lower boundary abnormality threshold can be obtained.

[0119] Among them, the first threshold interval can be adaptively set according to actual application needs. For example, by reducing the value of the first threshold interval, the preset upper boundary abnormal threshold is reduced and the preset lower boundary abnormal threshold is increased, so as to expand the threshold interval of the count difference when determining that the original clock source is in an abnormal state.

[0120] In an optional implementation, in order to improve the adjustment efficiency of the frequency parameters, a second threshold interval can be set to determine the target upper boundary threshold and the target lower boundary threshold according to the target count threshold and the second threshold interval, thereby determining whether to update the frequency parameters according to the target upper boundary threshold and the target lower boundary threshold.

[0121] The second threshold interval is used to represent the allowable deviation between the count difference and the target count threshold.

[0122] The target upper boundary threshold is used to determine the upper boundary value of the frequency parameter to be updated. When the count difference between the first count value and the second count value is greater than the target upper boundary threshold, it indicates that the deviation between the count difference and the target count threshold is large, and the frequency parameter needs to be updated.

[0123] The target lower boundary threshold is used to determine the lower boundary value of the frequency parameter to be updated. When the count difference between the first count value and the second count value is less than the target lower boundary threshold, it also indicates that the deviation between the count difference and the target count threshold is large, and the frequency parameter needs to be updated.

[0124] It should be noted that the target upper boundary threshold and the target lower boundary threshold can be obtained by increasing or decreasing the target counting threshold by the second threshold interval.

[0125] Moreover, the second threshold interval can be adaptively set according to actual application needs. For example, by increasing the value of the second threshold interval, the target upper boundary threshold is increased and the target lower boundary threshold is reduced, so as to reduce the threshold interval in which the count difference is located when determining that the frequency parameter needs to be updated.

[0126] It should also be noted that the second threshold interval must be smaller than the first threshold interval, that is, the preset upper boundary abnormal threshold must be greater than the target upper boundary threshold, and the preset lower boundary abnormal threshold must be less than the target lower boundary threshold. Figure 2 FIG. 1 shows a schematic diagram of frequency parameter adjustment in an embodiment of the present disclosure, referring to FIG. Figure 2 .

[0127] Among them, m is the target counting threshold, Threshold1 is the target upper boundary threshold, Threshold2 is the target lower boundary threshold, Threshold3 is the preset upper boundary abnormal threshold, Threshold4 is the preset lower boundary abnormal threshold, diff is the count difference between the first count value and the second count value, and T is the clock period of the preset clock source.

[0128] from Figure 2 It can be seen that when the count difference diff is in the threshold interval between the preset upper boundary abnormal threshold Threshold3 and the preset lower boundary abnormal threshold Threshold4, it is determined that the frequency adjustment unit is in a non-abnormal state.

[0129] Furthermore, when the count difference diff is in the threshold interval between the target upper boundary threshold Threshold1 and the target lower boundary threshold Threshold2, the frequency parameter will not be updated; when the count difference diff is greater than the target upper boundary threshold Threshold1, the frequency parameter will be increased to increase the clock signal frequency of the generated target clock signal; when the count difference diff is less than the target lower boundary threshold Threshold2, the frequency parameter will be reduced to reduce the clock signal frequency of the generated target clock signal.

[0130] In an optional implementation, in order to improve the adjustment flexibility and accuracy of the frequency parameters, the frequency parameter adjustment method and the parameter adjustment area corresponding to the frequency parameter adjustment method can be determined according to the count difference, so that the frequency parameters are updated by updating the parameter value corresponding to the parameter adjustment area in the frequency parameters.

[0131] Correspondingly, the frequency parameters are updated according to the count difference, including: determining a target frequency parameter adjustment method from at least two preset frequency parameter adjustment methods according to a comparison result of the count difference with the target upper boundary threshold and the target lower boundary threshold; determining a parameter adjustment area corresponding to the target frequency parameter adjustment method according to the count difference; and updating the parameter value corresponding to the parameter adjustment area in the frequency parameters.

[0132] The comparison result between the count difference value and the target upper boundary threshold value and the target lower boundary threshold value is used to characterize the deviation size of the count difference value.

[0133] Among them, the frequency parameter adjustment method is used to characterize the fine granularity of the frequency parameter adjustment, for example, a first frequency parameter adjustment method for fine-tuning the frequency parameter, a second frequency parameter adjustment method for moderately adjusting the frequency parameter, and a third frequency parameter adjustment method for larger adjustment of the frequency parameter.

[0134] Furthermore, according to the comparison result of the count difference value with the target upper boundary threshold value and the target lower boundary threshold value, the target frequency parameter adjustment method can be determined.

[0135] For example, when the count difference deviation is small, the first frequency parameter adjustment method can be selected as the target frequency parameter adjustment method, and when the count difference deviation is large, the third frequency parameter adjustment method can be selected as the target frequency parameter adjustment method.

[0136] The parameter adjustment area is used to represent the adjustment position of the frequency parameter. Specifically, the parameter adjustment area can be an integer area, a decimal area, or a preset digit area.

[0137] It should be noted that different frequency parameter adjustment modes correspond to different parameter adjustment areas. For example, in the first frequency parameter adjustment mode, the corresponding parameter adjustment area may be a decimal area or a first preset digit area. In the second frequency parameter adjustment mode, the corresponding parameter adjustment area may be a second preset digit area. In the third frequency parameter adjustment mode, the corresponding parameter adjustment area may be an integer area or a third preset digit area.

[0138] It should also be noted that, under different frequency parameter adjustment modes, the preset number of bits can be adaptively selected and the corresponding preset number of bits area can be set.

[0139] Furthermore, according to the count difference, a parameter adjustment region corresponding to the target frequency parameter adjustment method can be determined.

[0140] For example, when the count difference deviation is small (such as the difference between the count difference and the target upper boundary threshold or the target lower boundary threshold is in the first difference range), the decimal area is selected as the parameter adjustment area, or the first preset digit area, such as the area after the decimal point, is selected as the parameter adjustment area.

[0141] For another example, when the count difference deviation is moderate (eg, the difference between the count difference and the target upper boundary threshold or the target lower boundary threshold is in the second difference interval), a second preset digit area, such as the ones digit area, is selected as the parameter adjustment area.

[0142] It should be noted that after determining the parameter adjustment area, the specific adjustment parameter value corresponding to the parameter adjustment area can also be determined according to the count difference. The adjustment parameter value can be a positive value or a negative value, which is not limited in the embodiments of the present disclosure.

[0143] For example, if the count difference is less than the target lower boundary threshold, the adjustment parameter value may be set to a negative value, and if the count difference deviation is small, the absolute value of the adjustment parameter value may be set to a smaller value.

[0144] Thus, by updating the parameter value corresponding to the parameter adjustment area in the frequency parameter, the updated frequency parameter can be obtained. For example, the parameter adjustment area is a decimal area, the parameter value corresponding to the decimal area in the frequency parameter is 0.5, and the adjustment parameter value is -0.1, so the parameter value corresponding to the decimal area in the updated frequency parameter is 0.4.

[0145] In an optional implementation, in order to improve the efficiency of judging the abnormal state of the original clock source and the efficiency of updating the frequency parameters, when the frequency correlation relationship between the first clock signal frequency of the original clock source and the second clock signal frequency of the target clock signal to be generated is a non-equivalent relationship, the first clock signal frequency of the original clock source can be adjusted according to the frequency correlation relationship to obtain a frequency-adjusted source clock signal so as to count the frequency-adjusted source clock signal.

[0146] Correspondingly, before counting the generated target clock signal and the source clock signal of the original clock source respectively, it also includes: determining the frequency adjustment parameter corresponding to the original clock source according to the frequency association relationship; adjusting the first clock signal frequency of the original clock source according to the frequency adjustment parameter corresponding to the original clock source to obtain the source clock signal after frequency adjustment.

[0147] The frequency association relationship represents the numerical relationship between the first clock signal frequency of the original clock source and the second clock signal frequency of the target clock signal to be generated.

[0148] Specifically, if the first clock signal frequency of the original clock source and the second clock signal frequency of the target clock signal to be generated are not equivalent, the frequency adjustment parameter corresponding to the original clock source is determined according to the frequency association relationship.

[0149] The frequency adjustment parameter corresponding to the original clock source represents the adjustment ratio of the clock signal frequency of the original clock source. For example, if the frequency adjustment parameter is m, m>0, and the first clock signal frequency of the original clock source is f2, then the adjusted clock signal frequency of the original clock source is m*f2.

[0150] It should be noted that the frequency of the first clock signal of the original clock source can be adjusted according to the frequency adjustment parameter corresponding to the original clock source by a preset frequency adjustment unit to obtain a source clock signal after frequency adjustment.

[0151] For example, by inputting the source clock signal of the original clock source into a preset frequency adjustment unit, such as a preset multiplier or a preset divider, the preset frequency adjustment unit adjusts the frequency of the first clock signal of the original clock source according to the frequency adjustment parameter, and outputs the source clock signal after frequency adjustment, so that the source clock signal after frequency adjustment can be subsequently counted to obtain a first count value.

[0152] When the frequency correlation relationship is a non-equivalent relationship, if the source clock signal of the original clock source is counted directly, the count difference between the first count value and the second count value needs to be proportionally converted according to the frequency correlation relationship, so as to determine whether the original clock source is in an abnormal state and whether to update the frequency parameters based on the count difference after proportional conversion.

[0153] Therefore, the embodiment of the present disclosure pre-adjusts the first clock signal frequency of the original clock source according to the frequency association relationship, so that the clock signal frequency of the source clock signal after frequency adjustment can be equal to the second clock signal frequency of the target clock signal to be generated, thereby counting the source clock signal after frequency adjustment to avoid frequent proportional conversion of the count difference between the first count value and the second count value, thereby effectively improving the efficiency of judging the abnormal state of the original clock source and the frequency parameter update efficiency.

[0154] In an optional implementation, in order to accurately determine whether the original clock source is in an abnormal state, a preset time can be set so that when the clock edge of the source clock signal is not detected within the preset time, it means that the original clock source is lost. At this time, by determining that it is in an abnormal state, the frequency adjustment unit can generate a stable target clock signal with preset frequency parameters.

[0155] Correspondingly, the clock signal generation method of the embodiment of the present disclosure also includes: when the clock edge of the source clock signal is not detected within a preset time, determining that the original clock source is in an abnormal state; when it is determined that the original clock source is in an abnormal state, setting the frequency parameter to a preset frequency parameter so that the frequency adjustment unit generates a subsequent target clock signal according to the preset frequency parameter.

[0156] The preset time can be adaptively set according to actual detection requirements, and the embodiments of the present disclosure do not limit this. For example, the preset time can be set to 5s, 10s, etc.

[0157] If the clock edge of the source clock signal is not detected within the preset time, it means that the original clock source does not generate the source clock signal within the preset time, and accordingly, the first count value of the source clock signal will not change.

[0158] Therefore, in this case, it can be determined that the original clock source has a clock loss phenomenon and that the original clock source is in an abnormal state.

[0159] Accordingly, when the original clock source is in an abnormal state, the first count value of the source clock signal will deviate. If the frequency parameter is still updated according to the first count value and the second count value, the target clock signal generated by the frequency adjustment unit will also become abnormal.

[0160] Therefore, when the original clock source is in an abnormal state, the frequency parameter can be set to a preset frequency parameter, so that the frequency adjustment unit generates a subsequent target clock signal according to the preset frequency parameter.

[0161] The preset frequency parameter may be an initial frequency parameter used by the frequency adjustment unit when generating the target clock signal for the first time, or may be a current frequency parameter corresponding to the frequency adjustment unit in the current state, which is not limited in the embodiment of the present disclosure.

[0162] That is to say, when the original clock source is in an abnormal state, the frequency adjustment unit can use the initial frequency parameters to generate subsequent target clock signals, or the frequency adjustment unit can maintain the current frequency parameters to generate subsequent target clock signals so that the generated subsequent target clock signals are in a stable state.

[0163] To facilitate understanding, an example is used below to introduce the implementation of the above embodiment.

[0164] For video matrix products that require consistent input and output frame rates, a frame lock solution is usually used to achieve a fixed frequency relationship between the input clock and the output clock.

[0165] In the above solution, the chip input clock is used as a reference, and a frequency multiplier is used to generate a fixed-rate output clock, so that the output is periodic and the frame rate always follows the timing information of the input clock. However, when the input clock is lost, the frequency multiplier will change with the input clock, resulting in abnormal or lost chip output. In order to solve the problem of abnormal output clock when the source input clock is lost, this example proposes a clock signal generation method. Figure 3 A flowchart of a clock signal generation method provided for this example, refer to Figure 3 , the method comprising:

[0166] Step S300: determining a frequency correlation relationship between a first clock signal frequency of an original clock source and a second clock signal frequency of a target clock signal to be generated.

[0167] Among them, in the video matrix scenario, since the frame rate = pixel clock frequency / (horizontal number of pixels in the image * vertical number of pixels in the image), in order to achieve consistent frame rates of the two display devices, the frequency correlation relationship between the first clock signal frequency of device A and the second clock signal frequency of device B must satisfy: second clock signal frequency / first clock signal frequency = horizontal number of pixels of device B * vertical number of pixels of device B / (horizontal number of pixels of device A * vertical number of pixels of device A).

[0168] Therefore, by detecting the clock signal frequency, horizontal pixel count, and vertical pixel count of device A, and the horizontal pixel count and vertical pixel count of known device B, the frequency correlation relationship can be determined.

[0169] Step S301: Determine the frequency parameters of the frequency adjustment unit according to the frequency association relationship, the first clock signal frequency of the original clock source and the third clock signal frequency of the preset clock source, so that the frequency adjustment unit generates a target clock signal according to the frequency parameters and the third clock signal frequency of the preset clock source.

[0170] Among them, in the traditional clock signal generation method, the original clock source is directly used as the reference clock of the frequency adjustment unit, so as to generate the target clock signal by using the above-mentioned frequency correlation relationship.

[0171] Finally, the output timing is generated according to the horizontal pixel count, vertical pixel count and target clock signal of device B, so that the output timing that is consistent with the frame rate of device A and always follows the timing of device A can be obtained.

[0172] However, in the above clock signal generation method, once the input clock is disordered or lost, the generated target clock signal will be abnormal, which will cause the device display to be abnormal or interrupted.

[0173] Therefore, in the clock signal generation method of this example, the preset clock source rather than the original clock source is used as the reference clock of the frequency adjustment unit.

[0174] Therefore, according to the determined frequency correlation, the first clock signal frequency of the original clock source, the third clock signal frequency of the preset clock source, the frequency parameter of the frequency adjustment unit is set, and the frequency parameter is the initial frequency parameter.

[0175] Step S302: Determine the frequency adjustment parameter corresponding to the original clock source according to the frequency association relationship.

[0176] Step S303: adjusting the frequency of the first clock signal of the original clock source according to the frequency adjustment parameter corresponding to the original clock source to obtain a source clock signal after frequency adjustment.

[0177] Among them, when the frequency association relationship is a non-equivalent relationship, the first clock signal frequency of the original clock source can be adjusted according to the frequency association relationship, so that the clock signal frequency of the source clock signal after frequency adjustment: the second clock signal frequency of the target clock signal to be generated is 1:1.

[0178] Step S304: Determine a target counting threshold from the counting range of the preset counter.

[0179] The preset counter is used to count the target clock signal and the source clock signal. The counting range of the preset counter is determined according to the number of bits of the preset counter. For example, if the preset counter is 13 bits, its counting range is 2^13.

[0180] For ease of processing, the target count threshold can be taken as the median of the count range.

[0181] Step S305: Count the source clock signal of the original clock source to obtain a first count value of the source clock signal.

[0182] Specifically, a preset counter src_cnt is used to count the source clock signal src_clk from 0, and each time a source clock signal is detected, the first count value is increased by 1.

[0183] Step S306: When the first count value reaches the target count threshold, the target clock signal is counted to obtain a second count value of the target clock signal.

[0184] Specifically, when the first count value reaches the middle value of the count range, the preset counter dst_cnt is used to count the target clock signal dst_clk from 0, and the second count value is increased by 1 each time a target clock signal is detected.

[0185] Step S307: Determine whether the original clock source is in an abnormal state according to the first count value and the second count value.

[0186] By calculating the count difference between the first count value and the second count value, it is determined whether the original clock source is in an abnormal state according to the relationship between the count difference and the preset abnormal threshold (preset upper boundary abnormal threshold, preset lower boundary abnormal threshold).

[0187] Step S308: When the original clock source is in a normal state, the frequency parameter is updated according to the first count value and the second count value, so that the frequency adjustment unit generates a subsequent target clock signal according to the updated frequency parameter.

[0188] If the count difference between the first count value and the second count value is between the target upper boundary threshold and the target lower boundary threshold, the frequency parameter is not updated;

[0189] If the count difference is greater than the target upper boundary threshold but less than the preset upper boundary abnormal threshold, the frequency parameter is increased to increase the clock signal frequency of the generated target clock signal, thereby reducing the count difference;

[0190] If the count difference is less than the target lower boundary threshold but greater than the preset lower boundary abnormal threshold, the frequency parameter is reduced to reduce the clock signal frequency of the generated target clock signal, thereby increasing the count difference.

[0191] Step S309: when the original clock source is in an abnormal state, the frequency parameter is set to a preset frequency parameter, so that the frequency adjustment unit generates a subsequent target clock signal according to the preset frequency parameter.

[0192] When the original clock source is in an abnormal state, it indicates that the count difference is greater than the preset upper boundary abnormal threshold or the count difference is less than the preset lower boundary abnormal threshold. For example, if the original clock source is lost, the count difference will become smaller and smaller until it is less than the preset lower boundary abnormal threshold.

[0193] At this time, the frequency parameter may be set to a preset frequency parameter, which may be an initial frequency parameter, so that a frequency adjustment unit such as a frequency multiplier operates at the initial frequency parameter and outputs a target clock signal with a fixed frequency.

[0194] Likewise, if the original clock source is detected to be lost (eg, the clock edge of the source clock signal is not detected within a preset time), the frequency parameters are also set to preset frequency parameters, so that the frequency adjustment unit such as the multiplier operates at the initial frequency parameters.

[0195] Figure 4 A schematic diagram showing the clock signal generation method in this example is shown, referring to Figure 4: The input clock is the original clock source, the crystal oscillator clock is the preset clock source, the multiplier is a frequency adjustment unit for generating a target clock signal, and the divider is used to adjust the first clock signal frequency of the original clock source, so that the clock signal frequency of the source clock signal src_clk output by the divider: the clock signal frequency of the target clock signal dst_clk output by the multiplier is 1:1.

[0196] Therefore, by counting the source clock signal src_clk and the target clock signal dst_clk, a first count value and a second count value are obtained, so as to update the frequency parameter of the frequency multiplier according to the first count value and the second count value.

[0197] Specifically, when updating the frequency parameters, the parameter adjustment region may be determined, for example, only the integer region or the decimal region of the frequency parameters may be updated to improve the adjustment flexibility of the frequency parameters.

[0198] In the disclosed embodiment, by selecting a preset clock source (e.g., a crystal oscillator clock) as a reference clock, the frequency parameters are updated using the second count value of the source clock signal of the original clock source and the first count value of the generated target clock signal only when the original clock source is in a non-abnormal state, so that the frequency adjustment unit continuously fine-tunes the generated target clock signal according to the updated frequency parameters, so as to achieve the effect that the target clock signal follows the source clock signal within a certain range; and when the original clock source is in an abnormal state, by setting the frequency parameters to the preset frequency parameters, the frequency adjustment unit can generate a fixed-frequency target clock signal according to the preset frequency parameters to avoid clock loss.

[0199] The step division of the above methods is only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this patent.

[0200] In a second aspect, an embodiment of the present disclosure provides a clock signal generating device. Figure 5 A block diagram of a clock signal generating device provided in an embodiment of the present disclosure, referring to Figure 5 , the device comprises:

[0201] A determination module 51, configured to determine a frequency correlation relationship between a first clock signal frequency of an original clock source and a second clock signal frequency of a target clock signal to be generated;

[0202] A generating module 52, configured to determine a frequency parameter of a frequency adjustment unit according to the frequency association relationship, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, so that the frequency adjustment unit generates a target clock signal according to the frequency parameter and the third clock signal frequency of the preset clock source;

[0203] A counting module 53, used to count the generated target clock signal and the source clock signal of the original clock source respectively, to obtain a first count value of the source clock signal and a second count value of the target clock signal;

[0204] A judging module 54, configured to determine whether the original clock source is in an abnormal state according to the first count value and the second count value;

[0205] The updating module 55 is used to update the frequency parameter according to the first count value and the second count value when the original clock source is in a non-abnormal state, so that the frequency adjustment unit generates a subsequent target clock signal according to the updated frequency parameter.

[0206] In an optional implementation, the target clock signal and the source clock signal are counted according to a preset counter, and the counting module 53 counts the generated target clock signal and the source clock signal of the original clock source respectively, including: determining a target counting threshold from the counting range of the preset counter; counting the source clock signal of the original clock source to obtain a first counting value of the source clock signal; and when the first counting value reaches the target counting threshold, counting the target clock signal to obtain a second counting value of the target clock signal.

[0207] In an optional implementation, the judgment module 54 determines whether the original clock source is in an abnormal state based on the first count value and the second count value, including: determining a preset upper boundary abnormal threshold and a preset lower boundary abnormal threshold based on the target count threshold and the first threshold interval; calculating the count difference between the first count value and the second count value; and determining that the original clock source is in an abnormal state when the count difference is greater than the preset upper boundary abnormal threshold or the count difference is less than the preset lower boundary abnormal threshold.

[0208] In an optional implementation, the update module 55 updates the frequency parameter according to the first count value and the second count value, including: determining the target upper boundary threshold and the target lower boundary threshold according to the target count threshold and the second threshold interval; when the count difference between the first count value and the second count value is greater than the target upper boundary threshold or the count difference is less than the target lower boundary threshold, updating the frequency parameter according to the count difference.

[0209] In an optional implementation, updating the frequency parameter according to the count difference includes: determining a target frequency parameter adjustment method from at least two preset frequency parameter adjustment methods according to a comparison result of the count difference with the target upper boundary threshold and the target lower boundary threshold; determining a parameter adjustment area corresponding to the target frequency parameter adjustment method according to the count difference; and updating the parameter value corresponding to the parameter adjustment area in the frequency parameter.

[0210] In an optional implementation, before the counting module 53 counts the generated target clock signal and the source clock signal of the original clock source respectively, the device is also used to: determine the frequency adjustment parameter corresponding to the original clock source according to the frequency association relationship; adjust the first clock signal frequency of the original clock source according to the frequency adjustment parameter corresponding to the original clock source to obtain the source clock signal after frequency adjustment.

[0211] In an optional implementation, the device is also used to: determine that the original clock source is in an abnormal state when no clock edge of the source clock signal is detected within a preset time; and when it is determined that the original clock source is in an abnormal state, set the frequency parameter to a preset frequency parameter so that the frequency adjustment unit generates a subsequent target clock signal according to the preset frequency parameter.

[0212] The functions or modules included in the device provided in the embodiments of the present disclosure can be used to execute the method described in the first aspect of the method embodiment above. Its specific implementation and technical effects can be referred to the description of the method embodiment above. For the sake of brevity, they will not be repeated here.

[0213] It should be noted that all modules involved in this embodiment are logic modules. In practical applications, a logic unit may be a physical unit, or a part of a physical unit, or may be implemented as a combination of multiple physical units. In addition, in order to highlight the innovative part of the present disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by the present disclosure, but this does not mean that there are no other units in this embodiment.

[0214] Reference Figure 6 , an embodiment of the present disclosure provides an electronic device, comprising:

[0215] One or more processors 601;

[0216] A memory 602, on which one or more programs are stored, and when the one or more programs are executed by one or more processors, the one or more processors implement any one of the above-mentioned clock signal generation methods;

[0217] One or more I / O interfaces 603 are connected between the processor and the memory and are configured to implement information exchange between the processor and the memory.

[0218] Among them, the processor 601 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 602 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 603 is connected between the processor 601 and the memory 602, and can realize information interaction between the processor 601 and the memory 602, including but not limited to a data bus (Bus), etc.

[0219] In some embodiments, the processor 601 , the memory 602 , and the I / O interface 603 are connected to each other through a bus, and further connected to other components of the computing device.

[0220] This embodiment also provides a computer-readable medium on which a computer program is stored. When the program is executed by a processor, the clock signal generation method provided in this embodiment is implemented. To avoid repeated description, the specific steps of the clock signal generation method are not repeated here.

[0221] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the invented method described above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0222] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0223] Those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present embodiment and to form different embodiments.

[0224] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A clock signal generation method, characterized in that: The method comprises: Determine a frequency correlation relationship between a first clock signal frequency of an original clock source and a second clock signal frequency of a target clock signal to be generated; Determine a frequency parameter of a frequency adjustment unit according to the frequency association relationship, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, so that the frequency adjustment unit generates a target clock signal according to the frequency parameter and the third clock signal frequency of the preset clock source; Counting the generated target clock signal and the source clock signal of the original clock source respectively to obtain a first count value of the source clock signal and a second count value of the target clock signal; Determining whether the original clock source is in an abnormal state according to the first count value and the second count value; When the original clock source is in a non-abnormal state, the frequency parameter is updated according to the first count value and the second count value, so that the frequency adjustment unit generates a subsequent target clock signal according to the updated frequency parameter.

2. The clock signal generating method according to claim 1, characterized in that: The target clock signal and the source clock signal are counted according to a preset counter, and the respectively counting of the generated target clock signal and the source clock signal of the original clock source includes: Determining a target counting threshold value from a counting range of the preset counter; Counting a source clock signal of the original clock source to obtain a first count value of the source clock signal; When the first count value reaches the target count threshold, the target clock signal is counted to obtain a second count value of the target clock signal.

3. The clock signal generating method according to claim 2, characterized in that: The determining, according to the first count value and the second count value, whether the original clock source is in an abnormal state includes: Determine a preset upper boundary abnormality threshold and a preset lower boundary abnormality threshold according to the target counting threshold and the first threshold interval; Calculating a count difference between the first count value and the second count value; When the count difference value is greater than the preset upper boundary abnormal threshold or the count difference value is less than the preset lower boundary abnormal threshold, it is determined that the original clock source is in an abnormal state.

4. The clock signal generating method according to claim 2, characterized in that: The updating of the frequency parameter according to the first count value and the second count value includes: Determine a target upper boundary threshold and a target lower boundary threshold according to the target counting threshold and the second threshold interval; When the count difference between the first count value and the second count value is greater than the target upper boundary threshold or the count difference is less than the target lower boundary threshold, the frequency parameter is updated according to the count difference.

5. The clock signal generating method according to claim 4, characterized in that: The updating of the frequency parameter according to the count difference includes: Determining a target frequency parameter adjustment mode from at least two preset frequency parameter adjustment modes according to a comparison result of the count difference value with the target upper boundary threshold and the target lower boundary threshold; Determining a parameter adjustment region corresponding to the target frequency parameter adjustment method according to the count difference; The parameter value corresponding to the parameter adjustment area in the frequency parameter is updated.

6. The clock signal generating method according to any one of claims 1 to 5, characterized in that: Before counting the generated target clock signal and the source clock signal of the original clock source respectively, the method further includes: Determining a frequency adjustment parameter corresponding to the original clock source according to the frequency association relationship; The frequency of the first clock signal of the original clock source is adjusted according to the frequency adjustment parameter corresponding to the original clock source to obtain a source clock signal after frequency adjustment.

7. The clock signal generating method according to any one of claims 1 to 5, characterized in that: The method further comprises: If no clock edge of the source clock signal is detected within a preset time, determining that the original clock source is in an abnormal state; In the case where it is determined that the original clock source is in an abnormal state, the frequency parameter is set to a preset frequency parameter, so that the frequency adjustment unit generates a subsequent target clock signal according to the preset frequency parameter.

8. A clock signal generating device, characterized in that: The device comprises: A determination module, used to determine a frequency correlation relationship between a first clock signal frequency of an original clock source and a second clock signal frequency of a target clock signal to be generated; a generating module, configured to determine a frequency parameter of a frequency adjusting unit according to the frequency association relationship, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, so that the frequency adjusting unit generates a target clock signal according to the frequency parameter and the third clock signal frequency of the preset clock source; A counting module, used for counting the generated target clock signal and the source clock signal of the original clock source respectively, to obtain a first count value of the source clock signal and a second count value of the target clock signal; A judging module, configured to determine whether the original clock source is in an abnormal state according to the first count value and the second count value; The updating module is used to update the frequency parameter according to the first count value and the second count value when the original clock source is in a non-abnormal state, so that the frequency adjustment unit generates a subsequent target clock signal according to the updated frequency parameter.

9. An electronic device, characterized in that: include: one or more processors; A storage device having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7; One or more I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

10. A computer readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 7.

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