Processors and methods implemented by host instruction set architecture platforms

Abstract

The application relates to a processor and a method implemented by a host instruction set architecture platform. The processor is configured as the host instruction set architecture platform, which is operable to execute a second operation instruction under a host instruction set architecture when a first operation instruction under a simulation guest instruction set architecture related to generation or update of a plurality of condition flags, wherein the first operation instruction is an operation instruction for performing an operation on a first operand from a first source address and a second operand from a second source address, and the second operation instruction is an operation instruction for performing an operation on the first operand from the first source address and the second operand from the second source address and storing the plurality of condition flags to a first destination address according to an operation result.

Description

Technical Field

[0001] This disclosure generally relates to the field of computers, and more particularly to a processor and a method implemented by a host instruction set architecture platform. Background Technology

[0002] A Reduced Instruction Set Computer (RISC) processor is a type of processor that executes fewer types of computer instructions. The fundamental principle of RISC processors is to reduce the complexity of hardware design by streamlining the machine instruction set, while simultaneously increasing instruction execution speed. In RISC processors, both simple and complex operations are performed by blocks of simple instructions. Summary of the Invention

[0003] The processor according to an embodiment of the present disclosure is configured as a host instruction set architecture platform, which is operable to: execute a second operation instruction under the host instruction set architecture when simulating a first operation instruction under a client instruction set architecture related to the generation or updating of multiple condition flags, wherein the first operation instruction is an operation instruction that performs an operation on a first operand from a first source address and a second operand from a second source address, and the second operation instruction is an operation instruction that performs an operation on the first operand from the first source address and the second operand from the second source address and stores multiple condition flags to a first destination address according to the operation result.

[0004] A method implemented by a host instruction set architecture platform according to an embodiment of the present disclosure includes: when simulating a first operation instruction under a client instruction set architecture related to the generation or updating of multiple condition flags, executing a second operation instruction under the host instruction set architecture, wherein the first operation instruction is an operation instruction that performs an operation on a first operand from a first source address and a second operand from a second source address, and the second operation instruction is an operation instruction that performs an operation on the first operand from the first source address and the second operand from the second source address and stores multiple condition flags to a first destination address according to the operation result.

[0005] A computer-readable storage medium according to an embodiment of the present disclosure stores computer-executable instructions thereon, wherein, when executed by one or more processors, the computer-executable instructions cause one or more processors to perform the method implemented by the host instruction set architecture platform described above.

[0006] A computer program product according to an embodiment of the present disclosure includes computer-executable instructions, wherein, when executed by one or more processors, the computer-executable instructions cause one or more processors to perform the method implemented by the host instruction set architecture platform described above. Attached Figure Description

[0007] Embodiments of this disclosure will be illustrated in the accompanying drawings by way of example rather than limitation, wherein similar reference numerals refer to similar elements.

[0008] Figure 1 This is a flowchart illustrating an operation instruction emulation method implemented by a processor configured as a host instruction set architecture platform, according to an embodiment of the present disclosure.

[0009] Figure 2 This is a block diagram illustrating an example computing device in which a processor according to various embodiments of the present disclosure may be used. Detailed Implementation

[0010] Various aspects of the illustrative embodiments will be described using terminology commonly used by those skilled in the art to convey the essence of this disclosure to others skilled in the art. However, it will be apparent to those skilled in the art that many alternative embodiments can be implemented using portions of the described aspects. Specific figures, materials, and configurations are given for illustrative purposes to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that alternative embodiments can be implemented without these specific details. In other instances, well-known features may be omitted or simplified to avoid obscuring the illustrative embodiments.

[0011] Furthermore, the various operations are described sequentially as a plurality of discrete operations in a manner most conducive to understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations must be sequentially related. In particular, these operations do not need to be performed in the order presented.

[0012] The phrases “in an embodiment,” “in one embodiment,” and “in some embodiments” are used repeatedly throughout this document. These phrases do not generally refer to the same embodiment; however, they may refer to the same embodiment. Unless the context otherwise requires, the terms “comprising,” “having,” and “including” are synonyms. The phrases “A or B” and “A / B” mean “(A), (B), or (A and B).”

[0013] Using binary translation technology, applications based on client instruction set architectures can run on host instruction set architecture platforms. For example, applications based on advanced RISC machine (ARM) or x86 instruction set architectures can run on a fifth-generation RISC (RISC-V) platform. To emulate instructions from other instruction set architectures on the RISC-V platform, it is necessary to emulate condition flags for that architecture on the RISC-V platform, store these condition flags in memory or registers, and update these condition flags with reference to the source and result operands. Since the RISC-V platform does not support condition flags, updating and using these condition flags on the RISC-V platform requires complex pure software operations.

[0014] In view of the above, a processor according to an embodiment of the present disclosure is proposed that, when configured as a host instruction set architecture platform that does not support condition flags, can simulate operation instructions under a client instruction set architecture that supports condition flags with fewer operation instructions.

[0015] Figure 1 This is a flowchart illustrating a method for simulating operational instructions executed by a processor configured as a host instruction set architecture platform, according to an embodiment of this disclosure. Figure 1 As shown, the operation instruction simulation method 100 includes: S102, when simulating a first operation instruction under a client instruction set architecture related to the generation or update of multiple condition flags, executing a second operation instruction under a host instruction set architecture, wherein the first operation instruction is an operation instruction that performs an operation on a first operand from a first source address and a second operand from a second source address, and the second operation instruction is an operation instruction that performs an operation on the first operand from the first source address and the second operand from the second source address and stores multiple condition flags to a first destination address according to the operation result.

[0016] In some embodiments, where the first operation instruction is associated with a logical AND operation on the first operand and the second operand, the second operation instruction is an operation instruction that performs a logical AND operation on the first operand and the second operand and stores a plurality of condition flags to a first destination address based on the operation result.

[0017] In some embodiments, when the first operation instruction is associated with a comparison operation on the first operand and the second operand, and both the first operand and the second operand are integer operands, the second operation instruction is an operation instruction that performs an integer comparison operation on the first operand and the second operand and stores a plurality of condition flags to a first destination address based on the operation result.

[0018] In some embodiments, when the first operation instruction is associated with a comparison operation on the first operand and the second operand, and both the first operand and the second operand are floating-point operands, the second operation instruction is an operation instruction that performs a floating-point comparison operation on the first operand and the second operand and stores a plurality of condition flags to a first destination address based on the operation result.

[0019] In some embodiments, such as Figure 1 As shown, the operation instruction simulation method 100 may further include: S104, when simulating a first conditional operation instruction under a client instruction set architecture based on one or more condition flags among a plurality of condition flags, executing a branch operation instruction under a host instruction set architecture, wherein the first conditional operation instruction is an operation instruction that performs a specified operation when one or more condition flags satisfy a first predetermined condition, and the branch operation instruction is an operation instruction that references a plurality of condition flags stored in a first destination address and jumps to a specified address when one or more condition flags satisfy the first predetermined condition.

[0020] In some embodiments, such as Figure 1 As shown, the operation instruction simulation method 100 may further include: S106, when simulating a second conditional operation instruction under a client instruction set architecture based on one or more of a plurality of condition flags, executing a transfer operation instruction under a host instruction set architecture, wherein the second conditional operation instruction is an operation instruction that copies the content in a third source address to a second destination address when one or more condition flags satisfy a second predetermined condition, and the transfer operation instruction is an operation instruction that copies the content in a third source address to a second destination address by referring to a plurality of condition flags stored in a first destination address and when one or more condition flags satisfy the second predetermined condition.

[0021] In some embodiments, the host instruction set architecture platform can be implemented as a reduced instruction set architecture platform (e.g., a RISC-V platform). In other words, the host instruction set architecture can be a reduced instruction set architecture (e.g., a RISC-V instruction set architecture).

[0022] In some embodiments, the client instruction set architecture may be an x86 instruction set architecture (e.g., x86_64 instruction set architecture). In this case, multiple condition flags include a carry (CF) flag, an overflow (OF) flag, a signed (SF) flag, a zero (ZF) flag, and a parity (PF) flag.

[0023] In some embodiments, the client instruction set architecture may be an advanced reduced instruction set architecture (e.g., ARM64 instruction set architecture). In this case, multiple condition flags include a carry (CF) flag, an overflow (VF) flag, a negative (NF) flag, and a zero (ZF) flag.

[0024] In one example, the host instruction set architecture is RISC-V, and the client instruction set architecture is x86. In this case:

[0025] I. When the first operation instruction is associated with a logical AND operation on the first and second operands, the second operation instruction is an operation instruction that performs a logical AND operation on the first and second operands and stores the CF flag, OF flag, SF flag, ZF flag, and PF flag into a specified address in a general-purpose register based on the operation result. In this case, the CF flag = 0; the OF flag = 0; if the sign bit of the operation result is 1, then the SF flag = 1, otherwise the SF flag = 0; if all bits of the operation result are 0, then the ZF flag = 1, otherwise the ZF flag = 0; if the operation result has an even number of set bits, then the PF flag = 1, and if the operation result has an odd number of set bits, then the PF flag = 0.

[0026] II. When the first operation instruction is associated with a comparison operation on the first and second operands, and both the first and second operands are integer operands, the second operation instruction is an operation instruction that performs an integer comparison operation on the first and second operands and stores at least the CF flag, OF flag, SF flag, and PF flag in a specified address in a general-purpose register based on the operation result. In this case, if the operation result indicates that the second operand is greater than the first operand when it is an unsigned number, then the CF flag = 1; otherwise, the CF flag = 0. If the operation result overflows, then the OF flag = 1; otherwise, the OF flag = 0. If the sign bit of the operation result is 1, then the SF flag = 1; otherwise, the SF flag = 0. If the operation result has an even number of set bits, then the PF flag = 1; if the operation result has an odd number of set bits, then the PF flag = 0.

[0027] III. When the first operation instruction is associated with a comparison operation on the first and second operands, and both the first and second operands are floating-point operands, the second operation instruction is an operation instruction that performs a floating-point comparison operation on the first and second operands and stores the CF flag, OF flag, SF flag, ZF flag, and PF flag into a specified address in a general-purpose register based on the operation result. In this case, if the operation result indicates that the first operand is less than the second operand or that the first and / or second operands are invalid floating-point numbers, then the CF flag = 1; otherwise, the CF flag = 0; the OF flag = 0; and the SF flag = 0. If the operation result indicates that the first operand is equal to the second operand or that the first and / or second operands are invalid floating-point numbers, then the ZF flag = 1; otherwise, the ZF flag = 0. If the first and / or second operands are invalid floating-point numbers, then the PF flag = 1; otherwise, the PF flag = 0.

[0028] IV. Branch operation instructions are operation instructions that refer to the CF flag, OF flag, SF flag, ZF flag, and PF flag stored at a specified address in a general-purpose register and jump to the corresponding specified address when one or more of the flags meet one of the following conditions (note that different conditions may correspond to the same or different specified addresses): (1) CF flag = 1; (2) CF flag = 0; (3) ZF flag = 1; (4) ZF flag = 0; (5) SF flag = OF flag; (6) SF flag != OF flag; (7) CF flag = 0 and ZF flag = 0; (8) CF flag = 1 or ZF flag = 1; (9) ZF flag = 0 and SF flag = OF flag; (10) ZF flag = 1 or SF flag != OF flag; (11) SF flag = 1; (12) SF flag = 0; (13) PF flag = 1; (14) PF flag = 0; (15) OF flag = 1; (16) OF flag = 0.

[0029] V. The transfer operation instruction is an operation instruction that references the CF flag, OF flag, SF flag, ZF flag, and PF flag stored at a specified address in a general-purpose register and copies the contents of a third source address to a second destination address when one or more of the flags satisfy one of the following conditions: (1) CF flag = 1; (2) CF flag = 0; (3) ZF flag = 1; (4) ZF flag = 0; (5) SF flag = OF flag; (6) SF flag != OF flag; (7) CF flag = 0 and ZF flag = 0; (8) CF flag = 1 or ZF flag = 1; (9) ZF flag = 0 and SF flag = OF flag; (10) ZF flag = 1 or SF flag != OF flag; (11) SF flag = 1; (12) SF flag = 0; (13) PF flag = 1; (14) PF flag = 0; (15) OF flag = 1; (16) OF flag = 0.

[0030] In another example, the host instruction set architecture is RISC-V, and the client instruction set architecture is ARM. In this case:

[0031] I. When the first operation instruction is associated with a logical AND operation on the first and second operands, the second operation instruction is an operation instruction that performs a logical AND operation on the first and second operands and stores the CF flag, VF flag, NF flag, and ZF flag into a specified address in a general-purpose register based on the operation result. In this case, the CF flag = 0; the VF flag = 0; if the sign bit of the operation result is 1, then the NF flag = 1, otherwise the NF flag = 0; if all bits of the operation result are 0, then the ZF flag = 1, otherwise the ZF flag = 0.

[0032] II. When the first operation instruction is associated with a comparison operation on the first and second operands, and both the first and second operands are integer operands, the second operation instruction is an operation instruction that performs an integer comparison operation on the first and second operands and stores the CF flag, VF flag, NF flag, and ZF flag into a specified address in a general-purpose register based on the operation result. In this case, if the operation result indicates that the first operand is greater than the second operand when it is an unsigned number, then the CF flag = 1; otherwise, the CF flag = 0. If the operation result overflows, then the VF flag = 1; otherwise, the VF flag = 0. If the sign bit of the operation result is 1, then the NF flag = 1; otherwise, the NF flag = 0. If the operation result indicates that the first operand is equal to the second operand, then the ZF flag = 1; otherwise, the ZF flag = 0.

[0033] III. When the first operation instruction is associated with a comparison operation on the first and second operands, and both the first and second operands are floating-point operands, the second operation instruction is an operation instruction that performs a floating-point comparison operation on the first and second operands and stores the CF flag, VF flag, NF flag, and ZF flag into a specified address in a general-purpose register based on the operation result. In this case, if the operation result indicates that the first operand is less than the second operand or that the first and / or second operands are illegal floating-point numbers, then the CF flag = 1; otherwise, the CF flag = 0; the VF flag = 0; and the NF flag = 0. If the operation result indicates that the first operand is equal to the second operand or that the first and / or second operands are illegal floating-point numbers, then the ZF flag = 1; otherwise, the ZF flag = 0.

[0034] IV. Branch operation instructions are operation instructions that refer to the CF flag, VF flag, NF flag, and ZF flag stored at a specified address in a general-purpose register and jump to the corresponding specified address when one or more of the flags meet one of the following conditions (note that different conditions may correspond to the same or different specified addresses): (1) ZF flag = 1; (2) ZF flag = 0; (3) CF flag = 1; (4) CF flag = 0; (5) NF flag = 1; (6) NF flag = 0; (7) VF flag = 1; (8) VF flag = 0; (9) CF flag = 1 and ZF flag = 0; (10) CF flag = 0 or ZF flag = 1; (11) NF flag = VF flag; (12) NF flag != VF flag; (13) ZF flag = 0 and NF flag = VF flag; (14) ZF flag = 1 or NF flag != VF flag; (15) Other conditions.

[0035] V. A transfer operation instruction is an operation instruction that references the CF flag, VF flag, NF flag, and ZF flag stored at a specified address in a general-purpose register and copies the contents of a third source address to a second destination address when one or more of the flags satisfy one of the following conditions: (1) ZF flag = 1; (2) ZF flag = 0; (3) CF flag = 1; (4) CF flag = 0; (5) NF flag = 1; (6) NF flag = 0; (7) VF flag = 1; (8) VF flag = 0; (9) CF flag = 1 and ZF flag = 0; (10) CF flag = 0 or ZF flag = 1; (11) NF flag = VF flag; (12) NF flag != VF flag; (13) ZF flag = 0 and NF flag = VF flag; (14) ZF flag = 1 or NF flag != VF flag; (15) Other conditions.

[0036] In some embodiments, a host instruction set architecture platform can simultaneously support multiple client instruction set architectures. For example, a RISC-V platform, as a host instruction set architecture platform, can simultaneously support both the x86 instruction set architecture and the ARM instruction set architecture, and can store the CF, OF, SF, ZF, and PF flags under the x86 instruction set architecture and the CF, VF, NF, and ZF flags under the ARM instruction set architecture at different addresses in the same general-purpose register.

[0037] In some embodiments, the host instruction set architecture platform can support multiple client instruction set architectures and can store a type flag of the currently supported client instruction set architecture in the control and status register (CSR). For example, the RISC-V platform, as the host instruction set architecture platform, can support the x86 instruction set architecture and the ARM instruction set architecture as client instruction set architectures, and can store a type flag of the currently supported client instruction set architecture in the CSR (e.g., if the type flag is 1, the currently supported client instruction set architecture is the x86 instruction set architecture; otherwise, the currently supported client instruction set architecture is the ARM instruction set architecture).

[0038] Figure 2 This is a block diagram illustrating an example computing device in which a processor according to various embodiments of the present disclosure can be used. Figure 2 As shown, computing device 200 includes one or more processors (or processor cores) 210, one or more memory / storage devices 220, and one or more communication resources 230, wherein these processors, memory / storage devices, and communication resources can be communicatively coupled to each other via bus 240 or other interface circuitry. In embodiments utilizing node virtualization (e.g., network function virtualization, NFV), a hypervisor 202 can be executed to provide an execution environment for one or more network slices / subslices, thereby utilizing the hardware resources of computing device 200.

[0039] Processor 210 may include, for example, processor 212 and processor 214. Processor 210 may be, for example, a central processing unit (CPU), a RISC processor, a complex instruction set computer (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a radio frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.

[0040] Memory / storage device 220 may include main memory, disk storage devices, or any suitable combination thereof. Memory / storage device 220 may include, but is not limited to, any type of volatile, non-volatile, or semi-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state memory, etc.

[0041] Communication resource 230 may include interconnect or network interface controllers, components, or other suitable devices for communicating with one or more peripheral devices 204 or one or more databases 206 or other network elements via network 208. For example, communication resource 230 may include wired communication components (e.g., for coupling via universal serial bus (USB), Ethernet, etc.), cellular communication components, near field communication (NFC) components, Bluetooth® (or Bluetooth® Low Energy) components, Wi-Fi® components, and other communication components.

[0042] Instructions 250 may include software, programs, application programs, applets, or other executable code for causing at least any one of the processors 210 to perform various processing procedures. Instructions 250 may reside wholly or partially within processor 210 (e.g., in the processor's cache), memory / storage device 220, or any suitable combination thereof. Furthermore, any portion of instructions 250 may be transferred from any combination of peripheral device 204 or database 206 to hardware resource 200. Therefore, the memory of processor 210, memory / storage device 220, peripheral device 204, and database 206 are examples of computer-readable and machine-readable media.

[0043] While certain embodiments have been illustrated and described herein for purposes of description, various alternative and / or equivalent embodiments or implementations that achieve the same purpose may be substituted for the illustrated and described embodiments without departing from the scope of this disclosure. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, the embodiments described herein are clearly limited only by the appended claims and their equivalents.

Claims

1. A processor configured as a host instruction set architecture platform, the host instruction set architecture platform being operable for: When simulating a first operation instruction related to the generation or update of multiple condition flags under a client instruction set architecture, a second operation instruction under a host instruction set architecture is executed, wherein... The first operation instruction is an operation instruction that performs an operation on a first operand from a first source address and a second operand from a second source address. The second operation instruction is an operation instruction that performs an operation on the first operand from the first source address and the second operand from the second source address and stores the plurality of condition flags into a first destination address based on the operation result. as well as When simulating a first conditional operation instruction based on one or more of the plurality of condition flags under the client instruction set architecture, a branch operation instruction under the host instruction set architecture is executed. The first conditional operation instruction is an operation instruction that performs a specified operation when one or more condition flags satisfy a first predetermined condition. The branch operation instruction is an operation instruction that references the plurality of condition flags stored in the first destination address and jumps to a specified address when one or more condition flags satisfy the first predetermined condition. The host instruction set architecture platform supports multiple client instruction set architectures. The host instruction set architecture platform can also be operated to store the type flag of the client instruction set architecture in the control status register. For different client instruction set architectures among the multiple client instruction set architectures, the first destination address is different.

2. The processor according to claim 1, wherein, The first operation instruction is associated with a logical AND operation on the first operand and the second operand, and the second operation instruction is an operation instruction that performs a logical AND operation on the first operand and the second operand and stores the plurality of condition flags to the first destination address based on the operation result.

3. The processor according to claim 1, wherein, The first operation instruction is associated with a comparison operation on the first operand and the second operand, and both the first operand and the second operand are integer operands. The second operation instruction is an operation instruction that performs an integer comparison operation on the first operand and the second operand and stores the plurality of condition flags into the first destination address based on the operation result.

4. The processor according to claim 1, wherein, The first operation instruction is associated with a comparison operation on the first operand and the second operand, and both the first operand and the second operand are floating-point operands. The second operation instruction is an operation instruction that performs a floating-point comparison operation on the first operand and the second operand and stores the plurality of condition flags into the first destination address based on the operation result.

5. The processor according to any one of claims 1 to 4, wherein, The host instruction set architecture platform can also be operated for: When simulating a second conditional operation instruction under the client instruction set architecture based on one or more of the plurality of condition flags, a transfer operation instruction under the host instruction set architecture is executed. The second conditional operation instruction is an operation instruction that copies the content of a third source address to a second destination address when the one or more condition flags satisfy a second predetermined condition. The transfer operation instruction is an operation instruction that copies the content of the third source address to the second destination address with reference to the plurality of condition flags stored in the first destination address and when the one or more condition flags satisfy the second predetermined condition.

6. The processor according to any one of claims 1 to 4, wherein, The host instruction set architecture is a reduced instruction set architecture.

7. The processor according to any one of claims 1 to 4, wherein, The client instruction set architecture is the x86 instruction set architecture, and the multiple condition flags include a carry flag, an overflow flag, a sign flag, a zero flag, and a parity flag.

8. The processor according to any one of claims 1 to 4, wherein, The client instruction set architecture is an advanced reduced instruction set architecture, and the multiple condition flags include a carry flag, an overflow flag, a negative flag, and a zero flag.

9. The processor according to any one of claims 1 to 4, wherein, The first destination address is an address in a general-purpose register.

10. A method implemented by a host instruction set architecture platform, comprising: When executing a first operation instruction related to the generation or update of multiple condition flags under a simulated client instruction set architecture, a second operation instruction under a host instruction set architecture is executed. The first operation instruction is an operation instruction that performs an operation on a first operand from a first source address and a second operand from a second source address. The second operation instruction is an operation instruction that performs an operation on the first operand from the first source address and the second operand from the second source address and stores the multiple condition flags to a first destination address based on the operation result. When simulating a first conditional operation instruction based on one or more of the plurality of condition flags under the client instruction set architecture, a branch operation instruction under the host instruction set architecture is executed. The first conditional operation instruction is an operation instruction that performs a specified operation when one or more condition flags satisfy a first predetermined condition. The branch operation instruction is an operation instruction that references the plurality of condition flags stored in the first destination address and jumps to a specified address when one or more condition flags satisfy the first predetermined condition. The host instruction set architecture platform supports multiple client instruction set architectures, and the method further includes: storing a type flag of the client instruction set architecture in the processor's control status register. The first destination address is different for different client instruction set architectures among the multiple client instruction set architectures.

11. The method according to claim 10, wherein, The first operation instruction is associated with a logical AND operation on the first operand and the second operand, and the second operation instruction is an operation instruction that performs a logical AND operation on the first operand and the second operand and stores the plurality of condition flags to the first destination address based on the operation result.

12. The method according to claim 10, wherein, The first operation instruction is associated with a comparison operation on the first operand and the second operand, and both the first operand and the second operand are integer operands. The second operation instruction is an operation instruction that performs an integer comparison operation on the first operand and the second operand and stores the plurality of condition flags into the first destination address based on the operation result.

13. The method according to claim 10, wherein, The first operation instruction is associated with a comparison operation on the first operand and the second operand, and both the first operand and the second operand are floating-point operands. The second operation instruction is an operation instruction that performs a floating-point comparison operation on the first operand and the second operand and stores the plurality of condition flags into the first destination address based on the operation result.

14. The method according to any one of claims 10 to 13, further comprising: When simulating a second conditional operation instruction under the client instruction set architecture based on one or more of the plurality of condition flags, a transfer operation instruction under the host instruction set architecture is executed. The second conditional operation instruction is an operation instruction that copies the content of a third source address to a second destination address when the one or more condition flags satisfy a second predetermined condition. The transfer operation instruction is an operation instruction that copies the content of the third source address to the second destination address with reference to the plurality of condition flags stored in the first destination address and when the one or more condition flags satisfy the second predetermined condition.

15. A computer-readable storage medium having stored thereon computer-executable instructions, wherein, When executed by one or more processors, the computer-executable instructions cause the one or more processors to perform the method according to any one of claims 10 to 14.

16. A computer program product comprising computer-executable instructions, wherein, When executed by one or more processors, the computer-executable instructions cause the one or more processors to perform the method according to any one of claims 10 to 14.

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