Display panel, display module, electronic equipment and driving method thereof

Abstract

The embodiment of the invention provides a display panel, a display module, electronic equipment and a driving method thereof, relates to the technical field of electronics, and is used for realizing non-inductive switching between a normal mode and an AOD mode under the condition of meeting the low power consumption requirement. By adopting a larger fundamental frequency as a driving time sequence of normal display, the requirement of high refresh rate can be met. A small fundamental frequency is used as a driving time sequence for keeping display, so that the power consumption for keeping display can be reduced. Meanwhile, under the condition of mode switching, voltage compensation is carried out on the transition frame, flicker-free, color-cast-free and black-insertion-free scene switching is achieved, and therefore the low-power-consumption and high-effect AOD mode is achieved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a display panel, a display module, an electronic device and a driving method thereof. Background Art

[0002] With the development of display technology, display panels can use different refresh rates for display in different modes to balance display effect and display power consumption. For example, in normal mode, a higher refresh rate is used to drive the display of dynamic images to ensure the smoothness of the displayed images. In always on display (AOD) mode, a lower refresh rate is used to drive the display of static images to reduce the power consumption of the display panel. In this way, the display effect and display power consumption are balanced.

[0003] However, how to achieve seamless switching between the normal mode and the AOD mode is a difficult problem that needs further study by those skilled in the art. Summary of the invention

[0004] The present application provides a display panel, a display module, an electronic device and a driving method thereof, which are used to achieve seamless switching between a normal mode and an AOD mode while meeting low power consumption requirements.

[0005] According to a first aspect of an embodiment of the present application, a display panel is provided. The display panel includes a gate driving circuit and a plurality of rows of pixel circuits.

[0006] The gate drive circuit is used to receive a first scan start signal and a first clock signal to generate a first gate scan signal; the multi-row pixel circuit is used to receive a first voltage signal and a first gate scan signal to control the display panel to display a first picture in a first mode; in an image frame, the base frequency of the first scan start signal and the first clock signal is a first frequency, and the width of a plurality of pulses included in the first gate scan signal is a first fixed value. For example, the gate drive circuit outputs the same pulse width of the gate scan signal to each row, and the display panel enters the first mode and can display the picture normally.

[0007] The gate driving circuit is used to receive the second scanning start signal and the second clock signal, and generate the first sub-gate scanning signal, the second sub-gate scanning signal and the third sub-gate scanning signal; the first row of pixel circuits is used to receive the first compensation voltage signal and the first sub-gate scanning signal, the Mth row of pixel circuits is used to receive the second compensation voltage signal and the second sub-gate scanning signal, and the last row of pixel circuits is used to receive the third compensation voltage signal and the third sub-gate scanning signal, so as to control the display panel to display the second picture; the Mth row of pixel circuits is any row of pixel circuits located between the first row of pixel circuits and the last row of pixel circuits; in an image frame, the base frequency of the second scanning start signal and the second clock signal is the second frequency; the width of the multiple pulses included in the first sub-gate scanning signal is the first fixed value, the width of the multiple pulses included in the third sub-gate scanning signal is the second fixed value, and the width of the multiple pulses included in the second sub-gate scanning signal is not equal and is within the range from the first fixed value to the second fixed value. That is, the pulse width of the gate scanning signal output by the gate driving circuit to different rows will gradually change, and gradually transition from the pulse timing of the first gate scanning signal to the pulse timing of the second gate scanning signal to complete the mode switching.

[0008] The gate drive circuit is also used to generate a second gate scan signal according to the second scan start signal and the second clock signal; the multi-row pixel circuit is used to receive the second voltage signal and the second gate scan signal to control the display panel to display a third picture in the second mode; in an image frame, the base frequency of the second scan start signal and the second clock signal is the second frequency; the width of the plurality of pulses included in the second gate scan signal is the second fixed value. That is, in the second mode, the pulse width of the gate scan signal output by the gate drive circuit to each row is equal. The second mode can be, for example, a display mode that is always maintained.

[0009] In the display panel provided by the embodiment of the present application, in different modes, the gate scanning signal output by the gate driving circuit to the pixel circuit is different. For daily conventional display scenes, such as the first mode, a larger base frequency, such as the first frequency, is used as the driving timing of the normal display mode, so as to meet the conventional display requirements of high refresh rate. For display scenes that always keep displaying, such as the second mode, a low-power base frequency, such as the second frequency, is used as the driving timing of the display mode to meet the requirements of reducing power consumption of digital circuits and analog circuits. On this basis, in the process of switching between the first frequency and the second frequency, seamless switching is achieved through the transition frame, and the voltage signal is compensated in the transition frame so that the brightness of the second picture displayed by the transition frame is as close as possible to the brightness of the picture displayed by the first frame of the target switching mode, so that no black insertion is required when switching scenes, but the brightness remains stable, and almost no flicker, no color deviation, no black insertion and no change scene switching can be achieved, thereby achieving a low-power and high-effect always-maintaining display mode.

[0010] In a possible implementation, the compensation coefficients of the first compensation voltage signal, the second compensation voltage signal, and the third compensation voltage signal are different. That is, in the transition frame, the compensation degrees of the compensation voltage signals received by the pixel circuits of different rows may be different. Since the pulse widths of the sub-gate scanning signals received by the pixel circuits of different rows are different, the luminescence degrees of the pixel circuits of different rows are different. Therefore, by assigning different compensation coefficients to the pixel circuits of different rows, the pixel circuits of different rows are compensated to different degrees, so that the luminescence brightness of each row of the compensation frame is more uniform.

[0011] In a possible implementation, the compensation coefficients of the first compensation voltage signal, the second compensation voltage signal, and the third compensation voltage signal are adjusted to the first set of values ​​so that the second picture and the third picture are the same. Exemplarily, the display process of the display panel is: displaying the first picture in the first mode - displaying the second picture of the transition frame - displaying the second picture (third picture) in the second mode. After the baseband changes, the display panel has no intermediate picture, which can be called voltage compensation. If the second picture and the third picture are the same, then the image data of the second picture and the third picture themselves are the same. The compensation target of the compensation voltage signal is to compensate the brightness of the transition frame to be as close as possible to the brightness of the first frame in the second mode. Only brightness compensation is required to simplify the compensation scheme.

[0012] In a possible implementation, the compensation coefficients of the first compensation voltage signal, the second compensation voltage signal, and the third compensation voltage signal are adjusted to a second set of values ​​so that the second picture and the third picture are different. Exemplarily, the display process of the display panel is: display the first picture in the first mode - display the second picture of the transition frame - display the third picture in the second mode. If the second picture and the third picture are different, then the image data of the second picture and the third picture themselves are different. Based on the different image data, for example, voltage compensation can also be performed. That is, on the basis of displaying different pictures, the brightness of the transition frame can also be compensated to be as close as possible to the brightness of the first frame in the second mode. Therefore, a second picture different from the third picture is inserted in the transition frame. Since the pictures themselves are different, the flicker caused by the different luminous brightness can be reduced, thereby improving the user experience.

[0013] In a possible implementation, the voltage compensation method for the transition frame includes data voltage compensation. The first voltage signal includes a first data voltage signal, the second voltage signal includes a second data voltage signal, the first compensation voltage signal includes a first compensation data voltage signal, the second compensation voltage signal includes a second compensation data voltage signal, and the third compensation voltage signal includes a third compensation data voltage signal. The data voltage compensation method is used to adjust the luminous brightness in the second mode, which is mature, easy to implement, and has a good compensation effect.

[0014] In a possible implementation, the voltage compensation for the transition frame includes initialization voltage compensation. The first voltage signal includes a first initialization voltage signal, the second voltage signal includes a second initialization voltage signal, the first compensation voltage signal includes a first compensation initialization voltage signal, the second compensation voltage signal includes a second compensation initialization voltage signal, and the third compensation voltage signal includes a third compensation initialization voltage signal. The compensation initialization voltage is used to adjust the luminous brightness in the second mode, with a large range of variation, high precision, and good compensation effect.

[0015] In a possible implementation, the first frequency is greater than the second frequency; the base frequency of the display panel changes from the first frequency to the second frequency, and the widths of the multiple pulses included in the second sub-gate scanning signal increase; the base frequency of the display panel changes from the second frequency to the first frequency, and the widths of the multiple pulses included in the second sub-gate scanning signal decrease. The pulse width has a regular change trend, and the compensation coefficient of the corresponding input compensation voltage is also easy to determine, and the driving scheme is simple and easy to implement.

[0016] In a possible implementation, in the second mode, in the first N image frames, the multiple rows of pixel circuits receive the fourth compensation voltage signal and the second gate scanning signal to control the display panel to display the fourth picture; starting from the N+1th image frame, the multiple rows of pixel circuits receive the second voltage signal and the second gate scanning signal to control the display panel to display the third picture; N is a positive integer. That is, after entering the second mode, in the first N image frames, the voltage signal received by the display panel is a compensated voltage signal. Starting from the N+1th image frame, the voltage signal received by the display panel is an uncompensated voltage signal. That is, in the case of switching from the first mode to the third mode, the first N image frames after entering the third mode also need to compensate for the voltage signal, further increase the image frames with brightness transition, so that the display brightness of the display panel transitions smoothly, so as to realize the seamless switching of the row from the last image frame of the current mode to the image frame of the transition mode, then to the first N image frames of the target mode, and finally to the N+1th image frame of the target mode, and finally achieve the purpose of switching between different modes as seamlessly as possible.

[0017] In a possible implementation, the pixel circuit of the Mth row includes a plurality of pixel circuits, the second compensation voltage signal includes a plurality of sub-compensation voltage signals, the plurality of pixel circuits are used to receive the plurality of sub-compensation voltage signals, and the compensation coefficients of the plurality of sub-compensation voltage signals are the same. The compensation coefficients of the sub-compensation voltage signals received by the pixel circuits in the same row are the same, so that the compensation scheme can be simplified without affecting the display effect.

[0018] In a second aspect of the embodiments of the present application, a display module is provided, the display module comprising a display driver integrated circuit and a display panel; the display driver integrated circuit is coupled to the display panel, and the display panel comprises the display panel of any one of the first aspects. The beneficial effects of the display module provided by the embodiments of the present application are the same as the beneficial effects of the display panel of the first aspect, and will not be repeated here.

[0019] In one possible implementation, the display driver integrated circuit is used to output the first clock signal, the first scan start signal and the first voltage signal required for displaying the first picture to the display panel; the display driver integrated circuit is also used to output the second clock signal, the second scan start signal, the first compensation voltage signal, the second compensation voltage signal and the third compensation voltage signal required for displaying the second picture to the display panel; the display driver integrated circuit is also used to output the second clock signal, the second scan start signal and the second voltage signal required for displaying the third picture to the display panel.

[0020] According to a third aspect of an embodiment of the present application, an electronic device is provided. The electronic device includes a driving controller and a display module. The driving controller is coupled to the display module, and the display module includes the display module of the second aspect.

[0021] In a possible implementation, the driving controller is used to send a first base frequency instruction to the display module to control the display module to output a first clock signal and a first scan start signal. The driving controller is also used to send a second base frequency instruction to the display module to control the display module to output a second clock signal and a second scan start signal.

[0022] In a fourth aspect of an embodiment of the present application, a driving method of an electronic device is provided, wherein the electronic device includes a driving controller, a display driver integrated circuit and a display panel, and the display panel includes a gate driving circuit and a plurality of rows of pixel circuits; the driving method includes: the driving controller sends a first base frequency instruction, and the display driver integrated circuit outputs a first scan start signal, a first clock signal and a first voltage signal according to the first base frequency instruction; the gate driving circuit receives the first scan start signal and the first clock signal to generate a first gate scan signal, and the plurality of rows of pixel circuits receive the first gate scan signal and the first voltage signal, and controls the display panel to display a first picture in a first mode; in an image frame, the base frequency of the first scan start signal and the first clock signal is a first frequency, and the width of a plurality of pulses included in the first gate scan signal is a first fixed value. The driving controller sends a second base frequency instruction, and the display driving integrated circuit outputs a second start scanning signal, a second clock signal, a first compensation voltage signal, a second compensation voltage signal and a third compensation voltage signal according to the second base frequency instruction. The gate driving circuit receives the second start scanning signal and the second clock signal, and generates a first sub-gate scanning signal, a second sub-gate scanning signal and a third sub-gate scanning signal; the first row of pixel circuits receives the first compensation voltage signal and the first sub-gate scanning signal, the Mth row of pixel circuits receives the second compensation voltage signal and the second sub-gate scanning signal, and the last row of pixel circuits receives the third compensation voltage signal and the third sub-gate scanning signal, and controls the display panel to display a second picture; the Mth row of pixel circuits is any row of pixel circuits located between the first row of pixel circuits and the last row of pixel circuits; in an image frame, the base frequencies of the second scanning start signal and the second clock signal are the second frequency; the widths of the multiple pulses included in the first sub-gate scanning signal are the first fixed value, the widths of the multiple pulses included in the third sub-gate scanning signal are the second fixed value, and the widths of the multiple pulses included in the second sub-gate scanning signal are unequal and are within the range from the first fixed value to the second fixed value. The display driver integrated circuit also outputs a second start scan signal, a second clock signal, and a second voltage signal according to the second base frequency instruction. The gate driver circuit receives the second scan start signal and the second clock signal to generate a second gate scan signal. The multi-row pixel circuit receives the second voltage signal and the second gate scan signal to control the display panel to display a third picture in the second mode. In an image frame, the base frequency of the second scan start signal and the second clock signal is the second frequency. The width of the multiple pulses included in the second gate scan signal is a second fixed value. The beneficial effects of the driving method provided in the embodiment of the present application are the same as those of the display panel of the first aspect, and will not be repeated here.

[0023] In a possible implementation manner, the second picture and the third picture are the same.

[0024] In a possible implementation manner, the second picture and the third picture are different.

[0025] In one possible implementation, in the second mode, in the first N image frames, the display driver integrated circuit outputs a second start scan signal, a second clock signal and a fourth compensation voltage signal according to the second base frequency instruction, and the gate drive circuit receives the second scan start signal and the second clock signal to generate a second gate scan signal; multiple rows of pixel circuits receive the fourth compensation voltage signal and the second gate scan signal to control the display panel to display the fourth picture; starting from the N+1th image frame, multiple rows of pixel circuits receive the second voltage signal and the second gate scan signal to control the display panel to display the third picture; N is a positive integer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0027] Figure 2A A schematic diagram of a topological structure of a pixel circuit provided in an embodiment of the present application;

[0028] Figure 2B A schematic diagram of the structure of a light emitting control signal generating circuit provided in an embodiment of the present application;

[0029] Figure 2C A driving timing diagram of a pixel circuit provided in an embodiment of the present application;

[0030] Figure 3A Switch the scene graph for a mode;

[0031] Figure 3B Switch the scene graph for another mode;

[0032] Figure 4 A driving timing diagram of a display panel provided in an embodiment of the present application;

[0033] Figure 5A Another mode switching scene diagram provided in an embodiment of the present application;

[0034] Figure 5B Another mode switching scene diagram provided in an embodiment of the present application;

[0035] Figure 6 A driving timing diagram of another display panel provided in an embodiment of the present application;

[0036] Figure 7 A luminous brightness waveform diagram provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0038] In the following, the terms "second", "first", etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "second", "first", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0039] The embodiment of the present application provides an electronic device, which may be, for example, a folding electronic device. The electronic device may be, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial electronic product. Among them, consumer electronic products may be, for example, mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, mixed reality (MR) electronic devices, artificial intelligence (AI) electronic devices, drones, etc. Home electronic products may be, for example, smart door locks, televisions, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products may be, for example, vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial electronic products may be, for example, ATM machines, electronic devices for self-service transactions, etc.

[0040] The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic device. For the convenience of explanation, the following embodiments are all illustrated by taking the electronic device as a mobile phone.

[0041] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0042] like Figure 1 As shown, the electronic device 1 includes a display module 40 and a driving controller 30. In some embodiments, the electronic device 1 also includes a power management integrated circuit (power management IC, PMIC) ( Figure 1 The PIMC is used to supply power to the display driver integrated circuit 20 and the driver controller 30.

[0043] The drive controller 30 is the core of the electronic device 1 and is used for overall system processing control. The drive controller 30 is coupled to the display module 40, and the drive controller 30 receives image signals and control signals (for example, provided by a central processing unit (CPU)). The drive controller 30 outputs image data that matches the interface specifications of the display module 40 according to the image signal. The drive controller 30 includes, for example, a system on chips (SOC). The drive controller 30 can be coupled to the display module 40 via a mobile industry processor interface (MIPI) interface. Of course, the drive controller 30 can also be coupled to the display module 40 via other serial / deserial (SerDes) high-speed interfaces.

[0044] The display module 40 , for example, includes a display panel 10 and a display driver integrated circuit 20 . The display driver integrated circuit 20 serves as a control core of the display panel 10 , and is used to drive the display panel 10 to work and receive data from the driver controller 30 .

[0045] The display driver integrated circuit 20 is coupled to the driver controller 30, receives the signal output by the driver controller 30, and provides the display panel 10 with the scanning signal and data signal required for emitting light. The signal sent by the display driver integrated circuit 20 will be described below in combination with the structure of the pixel circuit.

[0046] For example, the display driver integrated circuit 20 receives a data control signal and image data from the driver controller 30. The display driver integrated circuit 20 converts the image data into a data signal and outputs the data signal to a plurality of data signal lines. The data signal is an analog voltage corresponding to the grayscale value of the image data. The display driver integrated circuit 20 is also used to output a scanning control signal such as a clock signal, a gate start signal STV, a reset signal, etc. required for display to the display panel 10. The display driver integrated circuit 20 includes, for example, a display driver chip (display drive integrated circuit, DDIC).

[0047] As the screen refresh frequency changes, the display driver integrated circuit 20 sends a tearing effect (TE) signal to the driver controller 30, and the driver controller 30 sends image data to the display driver integrated circuit 20 according to the frequency of the TE signal. The TE signal can make the frequency at which the driver controller 30 sends image data consistent with the frequency at which the display driver integrated circuit 20 needs to receive image data, so that the actual screen refresh frequency can respond to the image refresh frequency of the driver controller 30 (that is, the theoretical screen refresh frequency) in a timely manner.

[0048] The display panel 10 is used as a display data presentation unit to present the display and control data sent by the driving controller 30. For example, the display panel 10 is a self-luminous display module 40 such as an organic light emitting diode (OLED) display module 40, an active-matrix organic light-emitting diode (AMOLED) display module 40, a mini organic light-emitting diode (Mini-OLED) display module 40, a micro light-emitting diode (Micro-LED) display module 40, a micro organic light-emitting diode (Micro-OLED) display module 40, a quantum dot light emitting diode (QLED) display module 40, etc. For example, the display panel 10 can be a rigid display panel, and the display panel 10 can also be a flexible display panel.

[0049] For any of the above display panels 10, the display panel 10 includes an active display area (AA) and a non-display area BB located around the active display area AA. The active display area AA is used to display an image, and the active display area AA includes a plurality of sub pixels (SP), each of which is provided with a pixel circuit 11, and the pixel circuit 11 receives a data signal provided by a display driver integrated circuit 20. The non-display area BB includes a drive circuit, and the drive circuit receives a scan control signal provided by the display driver integrated circuit 20.

[0050] In the present application, the pixel circuits 11 are described by taking a matrix arrangement as an example. The pixel circuits 11 arranged in a row along the horizontal direction X are called pixel circuits 11 in the same row, and the pixel circuits 11 arranged in a row along the vertical direction Y are called pixel circuits 11 in the same column.

[0051] In some embodiments, the pixel circuit 11 generally includes a driving circuit and a light-emitting device composed of multiple transistors, and the driving circuit generates a driving current to drive the light-emitting device to emit light, so as to realize the light emission of the pixel circuit 11. Multiple pixel circuits 11 are arranged in an array on a substrate. For example, a structure including a substrate and multiple driving circuits arranged in an array is called an array substrate. Multiple light-emitting devices are arranged on the array substrate, and the light-emitting devices are coupled to the pixel circuits in a one-to-one correspondence. Alternatively, it can be understood that the display panel 10 includes an array substrate and multiple light-emitting devices, and the array substrate includes a substrate and a driving circuit arranged in an array, and the driving circuit and the light-emitting device are coupled to form the pixel circuit 11.

[0052] Figure 2A A schematic diagram of a topological structure of a pixel circuit provided in an embodiment of the present application.

[0053] In some embodiments, Figure 2A As shown, the pixel circuit 11 includes an anode reset circuit 111 , a second node initialization circuit 112 , a first node initialization circuit 113 , a writing and threshold compensation circuit 114 , a light emitting control circuit 115 and a light emitting device 116 . Figure 2A The pixel circuit 11 shown is only for illustration and is not intended to be limiting.

[0054] The anode reset circuit 111 includes a seventh transistor T7, the second node initialization circuit 112 includes an eighth transistor T8, the first node initialization circuit 113 includes a fourth transistor T4 and a third transistor T3, the write and threshold compensation circuit 114 includes a second transistor T2, a first transistor T1, a third transistor T3, and a storage capacitor Cst, and the light control circuit 115 includes a fifth transistor T5 and a sixth transistor T6. The first transistor T1 is a driving transistor, and the remaining transistors are switch transistors. The first node initialization circuit 113 and the write and threshold compensation circuit 114 share the third transistor T3. The light emitting device 116 is, for example, an OLED. The gates of the seventh transistor T7 and the eighth transistor T8 are controlled by the first control signal terminal S1, the gate of the fourth transistor T4 is controlled by the second control signal terminal S2, the gate of the third transistor T3 is controlled by the third control signal terminal S3, and the gate of the second transistor T2 is controlled by the fourth control signal terminal S4.

[0055] In some embodiments, the display panel 10 includes an array substrate and a plurality of light-emitting devices 116 disposed on the array substrate, the array substrate includes a substrate and an anode reset circuit 111, a second node initialization circuit 112, a first node initialization circuit 113, a write and threshold compensation circuit 114, and a light-emitting control circuit 115 disposed on the substrate.

[0056] The light emitting device 116 includes a first electrode layer, a first light emitting layer, a conductive connection layer, a second light emitting layer and a second electrode layer which are sequentially arranged on the array substrate. Such a display panel 10 is known in the art as a single OLED panel.

[0057] In some other embodiments, the light emitting device 116 includes a first electrode layer, a first light emitting layer, a conductive connection layer, a second light emitting layer, and a second electrode layer sequentially disposed on the array substrate. Such a display panel 10 is referred to in the art as a tandem OLED panel. Exemplarily, the light emitting device 116 is equivalent to including a first sub-light emitting device and a second sub-light emitting device connected in series, and the first sub-light emitting device and the second sub-light emitting device are connected in series through a conductive connection layer.

[0058] The first light-emitting layer and the second light-emitting layer are used to emit light of the same color. Taking the first light-emitting layer as an example, the first light-emitting layer includes an organic light-emitting layer, and the first light-emitting layer may also include at least one of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The organic light-emitting layer in the first light-emitting layer and the organic light-emitting layer in the second light-emitting layer may be used to emit light of the same color or different colors. Of course, the light-emitting device 116 may include more light-emitting layers, and a conductive connection layer is provided between adjacent light-emitting layers.

[0059] For example, the first electrode layer serves as the anode of the light-emitting device 116, and the second electrode layer serves as the cathode of the light-emitting device 116. A relatively high potential is applied to the first electrode layer, and a relatively low potential is applied to the second electrode layer. Then, holes are injected from the first electrode layer into the first light-emitting layer, and electrons are injected from the second electrode layer into the first light-emitting layer via the conductive connection layer. The energy generated by the recombination of holes and electrons in the first light-emitting layer can excite the first light-emitting layer to emit light. Similarly, holes are injected from the first electrode layer into the second light-emitting layer via the conductive connection layer, and electrons are injected from the second electrode layer into the second light-emitting layer. The energy generated by the recombination of holes and electrons in the second light-emitting layer can excite the second light-emitting layer to emit light. Both the second electrode layer and the conductive connection layer are transparent conductive layers. Light of the same color emitted by the first light-emitting layer and the second light-emitting layer is superimposed and emitted from the second electrode layer side.

[0060] like Figure 1 As shown, in some embodiments, the display panel 10 further includes a light emitting control signal generating circuit 12 , and the light emitting control signal generating circuit 12 is used to transmit a light emitting control signal em to the light emitting control signal terminals EM of the plurality of pixel circuits 11 in the display panel 10 .

[0061] Figure 2B A schematic diagram of the structure of a light emitting control signal generating circuit provided in an embodiment of the present application.

[0062] In some embodiments, Figure 2BAs shown, the light-emitting control signal generating circuit 12 includes at least two stages of cascaded shift registers RS(1) to RS(n). The signal input terminal VI of the first stage shift register RS(1) is used to receive the light-emitting control start signal STV-em. Except for the first stage shift register RS(1), the signal input terminal VI of each stage shift register RS(m) is coupled to the output terminal GO of the previous stage shift register RS(m-1). When the light-emitting control start signal STV-em is a start signal, the first stage shift register RS1 of the light-emitting control signal generating circuit 12 starts to work, and then the multi-stage shift registers start to work step by step.

[0063] For example, the light emission control start signal STV-em is provided by the display driver integrated circuit 20. The display panel 10 is used to receive the light emission control start signal STV-em sent by the display driver integrated circuit 20, and generate the light emission control signal em required by the pixel circuit 11. The timing of the light emission control signal em received by each row of pixel circuits is the same as the timing of the light emission control start signal STV-em.

[0064] Similarly, in some embodiments, the display panel 10 further includes a first control signal generating circuit (or understood as an anode reset control signal generating circuit) 13, and the first control signal generating circuit 13 is used to transmit a first control signal s1 to each row of pixel circuits 11. The reset start signal STV-s1 required by the first control signal generating circuit 13 is provided by the display driver integrated circuit 20. The timing of the first control signal s1 received by each row of pixel circuits is the same as the timing of the reset start signal STV-s1.

[0065] The display panel 10 further includes a second control signal generating circuit 14, which is used to transmit a second control signal s2 to each row of pixel circuits 11. The initialization start signal STV-s2 required by the second control signal generating circuit 14 is provided by the display driver integrated circuit 20. The timing of the second control signal s2 received by each row of pixel circuits is the same as the timing of the initialization start signal STV-s2.

[0066] The display panel 10 further includes a third control signal generating circuit 15, which is used to transmit a third control signal s3 to each row of pixel circuits 11. The compensation start signal STV-s3 required by the third control signal generating circuit 15 is provided by the display driver integrated circuit 20. The timing of the third control signal s3 received by each row of pixel circuits is the same as the timing of the compensation start signal STV-s3.

[0067] The display panel 10 further includes a fourth control signal generating circuit 16, which is used to transmit a fourth control signal s4 to each row of pixel circuits 11. The write start signal STV-s4 required by the fourth control signal generating circuit 16 is provided by the display driver integrated circuit 20. The timing of the fourth control signal s4 received by each row of pixel circuits is the same as the timing of the write start signal STV-s4.

[0068] Therefore, by adjusting the timing of the light emission control start signal STV-em, the reset start signal STV-s1, the initialization start signal STV-s2, the compensation start signal STV-s3 and the writing start signal STV-s4, the display state of the display panel 10 can be adjusted.

[0069] Figure 2C A driving timing diagram of a pixel circuit provided in an embodiment of the present application.

[0070] Combination Figure 2A and Figure 2C As shown, the light emitting process of the pixel circuit 11 in one frame can be divided into an initialization stage t1, a threshold compensation stage t2, a light emitting stage t3 and an anode reset stage t4.

[0071] In the initialization phase t1:

[0072] The second control signal s2 of the second control signal terminal S2 and the third control signal s3 of the third control signal terminal S3 change from low level to high level, and then change from high level to low level. Therefore, the fourth transistor T4 and the third transistor T3 change from off to on, and then change from on to off. The first control signal s1 of the first control signal terminal S1, the fourth control signal s4 of the fourth control signal terminal S4 and the light emitting control signal em of the light emitting control signal terminal EM all maintain a high level, so the seventh transistor T7, the eighth transistor T8, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 all maintain an off state.

[0073] In the initialization stage t1, the first transistor T1, the third transistor T3 and the fourth transistor T4 are turned on respectively, and the voltage control of the fourth node N4, the second node N2 and the first node N1 is realized. Since the third transistor T3 and the fourth transistor T4 are respectively used as switch tubes, the first node N1 is electrically connected to the control electrode of the first transistor T1, and the second node N2 is electrically connected to the fourth node N4, so in the initialization stage t1, the control electrode voltage control of the first transistor T1, the voltage control of the first node N1, the voltage control of the second node N2 and the voltage control of the fourth node N4 are realized, so that the control electrode voltage of the first transistor T1, the voltage of the first node N1, the voltage of the second node N2 and the voltage of the fourth node N4 are respectively the first initialization voltage of the first initialization voltage terminal Vinit1, that is, the control electrode of the first transistor T1, the first node N1, the second node N2 and the fourth node N4 are reset.

[0074] In the threshold compensation phase t2:

[0075] The first control signal s1 of the first control signal terminal S1 changes from a high level to a low level, and then from a low level to a high level. Thus, the second transistor T2 changes from off to on, and then from on to off. The third control signal s3 of the third control signal terminal S3 changes from a low level to a high level, and then from a high level to a low level. Thus, the third transistor T3 changes from off to on, and then from on to off. The first control signal s1 of the first control signal terminal S1 and the light-emitting control signal em of the light-emitting control signal terminal EM both maintain a high level, and the second control signal s2 of the second control signal terminal S2 maintains a low level. Therefore, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5, the sixth transistor T6 and the fourth transistor T4 all remain in an off state.

[0076] In the threshold compensation stage t2, the second transistor T2, the third transistor T3 and the first transistor T1 are turned on respectively, so that the data voltage of the data voltage terminal Vd is stored in the storage capacitor Cst, and the writing of the data voltage is completed. The threshold voltage of the first transistor T1 is compensated. The compensation process of the threshold voltage of the first transistor T1 can be considered as the process of the first transistor T1 changing from the on state to the off state.

[0077] In the light-emitting phase t3:

[0078] The light emitting control signal em of the light emitting control signal terminal EM changes from a high level to a low level, and then changes from a low level to a high level. Thus, the sixth transistor T6 and the fifth transistor T5 change from being turned off to being turned on, and then from being turned on to being turned off. The second control signal s2 of the second control signal terminal S2 and the third control signal s3 of the third control signal terminal S3 respectively maintain a low level, and the fourth transistor T4 and the third transistor T3 both maintain an off state. The first control signal s1 of the first control signal terminal S1 and the fourth control signal s4 of the fourth control signal terminal S4 respectively maintain a high level, and the seventh transistor T7, the eighth transistor T8 and the second transistor T2 all maintain an off state.

[0079] In the light emitting stage t3 , the fifth transistor T5 , the first transistor T1 and the sixth transistor T6 are turned on respectively to transmit the driving current to the light emitting device 116 , and the light emitting device 116 emits light under the driving current.

[0080] Anode reset phase t:

[0081] The first control signal s1 of the first control signal terminal S1 changes from a high level to a low level, and then changes from a low level to a high level. Thus, the seventh transistor T7 and the eighth transistor T8 change from off to on, and then from on to off. The second control signal s2 of the second control signal terminal S2 and the third control signal s3 of the third control signal terminal S3 always maintain a low level, and the fourth control signal s4 of the fourth control signal terminal S4 and the light-emitting control signal em of the light-emitting control signal terminal EM always maintain a high level. The third transistor T3, the fourth transistor T4, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 all remain in the off state.

[0082] In the anode reset stage t, the seventh transistor T7 and the eighth transistor T8 are turned on, realizing the control of the voltage of the second node N2 and the control of the anode voltage of the light-emitting device 116, so that the voltage of the second node N2 is the third initialization voltage of the third initialization voltage terminal Vinit3, and the voltage of the anode of the light-emitting device 116 is the second initialization voltage of the second initialization voltage terminal Vinit2, realizing the resetting of the second node N2 and the anode voltage of the light-emitting device 116.

[0083] When the display panel 10 displays at different brightness, the control signal or voltage received by the pixel circuit 11 in the display panel 10 will be dynamically adjusted in real time.

[0084] In order to improve the user experience, the current electronic device 1 will use the always on display (AOD) mode to display some time, picture and other information on the display panel 10 of the electronic device 1. This requires the AOD mode to have low power consumption and be continuous during the switching process with the normal mode to achieve a dynamic optimal display experience.

[0085] Figure 3A Switches the scene graph for one mode or another.

[0086] In some embodiments, Figure 3A As shown, a full-screen AOD mode with a low refresh rate is used for display. Normal display is performed in normal mode, and a refresh rate of 1HZ is used for display in AOD mode. In other words, AOD mode is a normal mode at 1HZ. In this way, lossless switching between normal mode and AOD mode can be achieved. However, in full-screen AOD mode, the baseband frequency of the display panel 10 remains unchanged (the frequency of the clock signal remains unchanged), resulting in relatively high power consumption of the display panel 10. Moreover, the baseband frequency of the AOD mode and the normal mode is the same, but the refresh rate is different, resulting in the AOD mode directly returning to the normal mode when some dynamic displays are displayed, and power saving cannot be achieved.

[0087] Figure 3B Switches the scene graph for another mode.

[0088] In other embodiments, Figure 3B As shown, the all-day AOD mode with a low baseband is used for display. In the normal mode, the display panel 10 uses a higher baseband, and in the all-day AOD mode, the baseband of the display panel 10 is reduced, so the power consumption of the display panel 10 can be greatly reduced. However, since the baseband in the all-day AOD mode is different from that in the normal mode, in order to eliminate flicker and color deviation problems, a full black picture is inserted when switching between the all-day AOD mode and the normal mode, but this will also affect the user experience.

[0089] An embodiment of the present application provides an electronic device for achieving flicker-free, black-out-free switching between the AOD mode and the normal mode on the basis of adopting a method of reducing the base frequency as the basic driving frequency of the AOD mode, thereby ultimately achieving low power consumption and high effect of the electronic device 1.

[0090] Figure 4 A driving timing diagram of a display panel provided in an embodiment of the present application.

[0091] The embodiment of the present application provides a display panel 10, which includes a gate driving circuit and a plurality of rows of pixel circuits 11. The gate driving circuit may be, for example, a light-emitting control signal generating circuit 12 in the display panel 10, and the gate scanning signal output by the gate driving circuit is a light-emitting control signal em. The gate driving circuit may be, for example, a first control signal generating circuit 13 in the display panel 10, and the gate scanning signal output by the gate driving circuit is a first control signal s1. The gate driving circuit may be, for example, a second control signal generating circuit 14 in the display panel 10, and the gate scanning signal output by the gate driving circuit is a second control signal s2. The gate driving circuit may be, for example, a third control signal generating circuit 15 in the display panel 10, and the gate scanning signal output by the gate driving circuit is a third control signal s3. The gate driving circuit may be, for example, a fourth control signal generating circuit 16 in the display panel 10, and the gate scanning signal output by the gate driving circuit is a fourth control signal s4.

[0092] Gate drive circuit for receiving Figure 4 The first scanning start signal stv1 and the first clock signal clk1 shown generate the first gate scanning signal vo1. The multi-row pixel circuit 11 is used to receive the first voltage signal v1 and the first gate scanning signal vo1, and control the display panel 10 to display the first picture in the first mode. Then, each row of sub-pixels in the display panel 10 is refreshed with the first frequency as the basic refresh frequency. The timing of the gate scanning signal received by each row of pixel circuits 11 is the same, and the size of the first voltage signal v1 received by each row of pixel circuits 11 is related to the image to be displayed. For example, the first voltage signal v1 is a voltage signal that is not compensated.

[0093] The base frequency can be understood as the basic refresh frequency of the display panel 10. The base frequency multiplied by the number of pulses in an image frame equals the refresh rate of the display panel 10. Figure 4 For example, the first mode is the normal mode, the first frequency of the display panel 10 is 120 Hz, one image frame includes 3 pulses, and the refresh rate of the display panel 10 is 360 (3*120) Hz.

[0094] In the first mode, in an image frame, the base frequencies of the first clock signal clk1 and the first gate scanning signal stv1 are the first frequency (e.g., 120 Hz), and the widths of the plurality of first scanning pulses included in the first gate scanning signal stv1 are the first fixed value. The embodiment of the present application does not limit the specific value of the first fixed value, and the value of the first fixed value in different electronic devices 1 may be different.

[0095] In the embodiment of the present application, the pulse width can be understood as the duration of a start signal in a pulse cycle, such as a low-level signal.

[0096] The gate drive circuit is also used to receive a second scan start signal stv2 and a second clock signal clk2 to generate a second gate scan signal vo2. The multi-row pixel circuit 11 is used to receive a second voltage signal v2 and a second gate scan signal vo2 to control the display panel 10 to display a third picture in the second mode. Then, each row of sub-pixels in the display panel 10 is refreshed with the second base frequency as the basic refresh frequency. The timing of the gate scan signal received by each row of pixel circuits 11 is the same, and the size of the second voltage signal v2 received by each row of pixel circuits 11 is related to the image to be displayed. For example, the second voltage signal v2 is a voltage signal that is not compensated.

[0097] by Figure 4 For example, the second mode is the AOD mode, the second base frequency of the display panel 10 is 30 Hz, an image frame includes 3 pulses, and the refresh rate of the display panel 10 is 90 (3*30) Hz. In the second mode, in an image frame, the base frequencies of the second scan start signal stv2 and the second clock signal clk2 are the second frequency (for example, 30 Hz), and the widths of the multiple second scan pulses included in the second gate scan signal stv2 are the second fixed values. The embodiment of the present application does not limit the specific value of the second fixed value, and the values ​​of the second fixed value in different electronic devices 1 may be different.

[0098] When switching from the first mode to the second mode, the baseband frequency of the display panel 10 changes, and there will be a transition frame in the middle, and the display image will flicker in the transition frame.

[0099] Based on this, in some embodiments, the gate drive circuit is also used to receive Figure 4The second scanning start signal stv2 and the second clock signal clk2 shown generate the first sub-gate scanning signal vo31, the second sub-gate scanning signal vo32 and the third sub-gate scanning signal vo33, and control the display panel 10 to display the transition frame picture. The transition frame picture can be understood as a transition picture inserted in the middle when the first mode and the second mode are switched between each other. The width of the multiple first sub-gate pulses included in the first sub-gate scanning signal vo31 is the same as the width of the first gate pulse included in the first gate scanning signal vo1, and both are the first fixed value. The width of the multiple third sub-gate pulses included in the third sub-gate scanning signal vo33 is the same as the width of the second gate pulse included in the second gate scanning signal vo2, and both are the second fixed value, so as to complete the transition of the base frequency change. The widths of the multiple second sub-gate pulses included in the second sub-gate scanning signal vo32 are not equal and are located in the interval from the first fixed value to the second fixed value. That is, the width of the second sub-gate pulse can be equal to the first fixed value, the width of the second sub-gate pulse can also be equal to the second fixed value, and the width of the second sub-gate pulse can also be equal to any value in the interval from the first fixed value to the second fixed value. The widths of the plurality of second sub-gate pulses included in the second sub-gate scanning signal vo32 may be completely unequal, that is, the widths of the plurality of second sub-gate pulses are different, for example: Figure 4 The widths of the second sub-gate pulses included in the second sub-gate scanning signal vo32 may not be completely equal, that is, the widths of some second sub-gate pulses may be equal, for example Figure 4 The gate scanning signal received by the second row of pixel circuits in .

[0100] The first row pixel circuit 11 is used to receive the first compensation voltage signal v 补偿1 and the first sub-gate scanning signal vo31, the pixel circuit 11 of the Mth row is used to receive the second compensation voltage signal v 补偿2 and the second sub-gate scanning signal vo32, the last row of pixel circuits 11 is used to receive the third compensation voltage signal v 补偿3 and the third sub-gate scanning signal vo33 to control the display panel 10 to display the second picture.

[0101] The Mth row of pixel circuits is any row of pixel circuits located between the first row of pixel circuits 11 and the last row of pixel circuits 11. When M takes different values, the width of the second sub-gate pulse included in the second sub-gate scanning signal vo32 may be different. For example, the larger the value of M, the closer the width of each second sub-gate pulse included in the second sub-gate scanning signal vo32 is to the second fixed value.

[0102] The flickering problem of the display panel 10 is improved by compensating the voltage signal in the transition frame.

[0103] In some embodiments, the first compensation voltage signal v 补偿1 , the second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficients are not completely the same or completely different. For example, the first compensation voltage signal v 补偿1 The compensation coefficient is 0, and the second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficient is an integer greater than 0, and the second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficient of M is different. When the value of M is different, the second compensation voltage signal v 补偿2 The compensation coefficients may also be different.

[0104] Since the pulse widths of the sub-gate scanning signals received by the pixel circuits 11 in different rows are different, the luminescence levels of the pixel circuits 11 in different rows are different. Therefore, by assigning different compensation coefficients to the pixel circuits 11 in different rows, the pixel circuits 11 in different rows are compensated to different degrees, so that the luminescence brightness of each row in the compensation frame is more uniform.

[0105] The frequency of the TE signal is consistent with the refresh rate of the display panel 10 , and the frequency of the TE signal is the frequency required by the display driver integrated circuit 20 to receive image data.

[0106] Of course, the embodiment of the present application is illustrated by taking each row of pixel circuits 11 receiving the same gate scanning signal as an example. It is also possible that multiple adjacent rows of pixel circuits 11 receive the same gate scanning signal. For example, the multiple rows of pixel circuits 11 can be regarded as a whole.

[0107] In the display panel 10 provided in the embodiment of the present application, the gate scanning signal output by the gate driving circuit to the pixel circuit 11 is different in different modes. For daily conventional display scenes, a larger base frequency, such as the first frequency, is used as the driving timing for normal display, so as to meet the conventional display requirements of high refresh rate. For the AOD display scene, a low-power base frequency, such as the second base frequency, is used as the driving timing to maintain the display, so as to meet the requirements of reducing power consumption of digital circuits and analog circuits. On this basis, in the process of switching between the first frequency and the second frequency, seamless switching is achieved through the transition frame, and the voltage signal is compensated in the transition frame so that the brightness of the second picture displayed by the transition frame is as close as possible to the brightness of the picture displayed by the first frame of the target switching mode, so that there is no need to insert black when switching scenes, but the brightness remains stable, and almost no flicker, no color deviation, no black insertion and no change scene switching can be achieved, thereby achieving a low-power and high-effect AOD mode.

[0108] In some embodiments, when the base frequency of the display panel 10 switches from the first frequency to the second frequency, the first compensation voltage signal v 补偿1 , the second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficient is a first set of values, and the second picture displayed by the display panel 10 in the transition frame is the same as the third picture displayed by the display panel 10 in the second mode.

[0109] The first set of values ​​includes the first compensation voltage signal v 补偿1 , the second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficients of each. The compensation coefficient can be greater than 1 or less than 1. For example, when the brightness needs to be increased, the compensation coefficient is greater than 1. When the brightness needs to be reduced, the compensation coefficient is less than 1.

[0110] For example, the image data of the second picture and the third picture are the same, and the compensation target of the compensation voltage signal is to compensate the brightness of the transition frame to be as close as possible to the brightness of the first frame in the second mode, and only brightness compensation is required to simplify the compensation scheme. Figure 5A As shown, the display process of the display panel 10 is: displaying the first picture in the first mode - displaying the third picture of the transition frame - displaying the third picture in the second mode. After the baseband changes, the display panel 10 has no intermediate picture, which can be called voltage compensation.

[0111] In some other embodiments, when the base frequency of the display panel 10 is switched from the first frequency to the second frequency, the first compensation voltage signal v 补偿1 , the second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficient is a second set of values, and the second picture displayed by the display panel 10 in the transition frame and the third picture displayed by the display panel 10 in the second mode are different.

[0112] For example, the image data of the second picture and the third picture are different. Based on the different image data, voltage compensation can be performed. That is, on the basis of displaying different pictures, the brightness of the transition frame can be compensated to be as close as possible to the brightness of the first frame in the second mode. Figure 5B As shown, the display process of the display panel 10 is: displaying the first picture in the first mode - displaying the second picture in the transition frame - displaying the third picture in the second mode. After the baseband changes, the display panel 10 has an intermediate picture, which can be called user interface (UI) compensation. The second picture different from the third picture is inserted in the transition frame. Since the pictures themselves are different, the flicker caused by the different luminous brightness can be reduced, thereby improving the user experience.

[0113] The second set of values ​​includes the first compensation voltage signal v 补偿1 , the second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 The compensation coefficients of the respective compensation voltages when the second picture and the third picture are the same may be different from the compensation coefficients of the respective compensation voltages when the second picture and the third picture are the same. The two solutions may be applied to different electronic devices 1, for example.

[0114] In some embodiments, the voltage signal includes a data voltage signal. For example, the first voltage signal v1 includes a first data voltage signal, the second voltage signal v2 includes a second data voltage signal, and the first compensation voltage signal v 补偿1 Including a first compensation data voltage signal, a second compensation voltage signal v 补偿2 Including a second compensation data voltage signal, a third compensation voltage signal v 补偿3 A third data voltage signal is included.

[0115] For example, by measuring the data voltage during the scene switching process and comparing the data voltage of the transition frame with the data voltage in the target mode, it can be confirmed whether there is data voltage compensation during the switching process. The embodiment of the present application does not limit the method of determining the data voltage compensation coefficient, and the solutions in the related art that achieve uniform display brightness by compensating the data voltage are all applicable to the embodiment of the present application.

[0116] The scheme for compensating the transition frame includes compensating the data voltage in the transition frame. By compensating the data voltage in the transition frame, the brightness of the display screen is compensated, and flicker-free switching is achieved.

[0117] In some other embodiments, the voltage signal includes an initialization voltage signal. The first voltage signal v1 includes a first initialization voltage signal, the second voltage signal v2 includes a second initialization voltage signal, and the first compensation voltage signal v 补偿1 Including a first compensation initialization voltage signal, a second compensation voltage signal v 补偿2 Including the second compensation initialization voltage signal, the third compensation voltage signal v 补偿3 A third initialization voltage signal is included.

[0118] The initialization voltage signal includes one or more of the first initialization voltage of the first initialization voltage terminal Vinit1, the second initialization voltage of the second initialization voltage terminal Vinit2, or the third initialization voltage of the third initialization voltage terminal Vinit3. That is, when compensating the initialization voltage, one or more of the first initialization voltage, the second initialization voltage, and the third initialization voltage may be compensated, and when compensating multiple initialization voltages, for pixel circuits 11 in different rows, the compensation coefficients of the multiple initialization voltages may be completely different or not completely the same.

[0119] By measuring the initialization voltage during the scene switching process and comparing the initialization voltage of the transition frame with the initialization voltage in the target mode, it can be confirmed whether there is compensation for the initialization voltage during the switching process. The embodiment of the present application does not limit the method for determining the initialization voltage compensation coefficient, and the solutions in the related art for achieving uniform display brightness by compensating the initialization voltage are all applicable to the embodiment of the present application.

[0120] The scheme for compensating the transition frame includes compensating the initialization voltage in the transition frame. By compensating the initialization voltage of the transition frame, high brightness compensation of the display screen is achieved, and flicker-free switching is achieved.

[0121] Table 1 shows that when the display brightness is 200 nit, the grayscale of each pixel row of an electronic device 1 in AOD mode is L1, and in the transition frame, the grayscale of each pixel row is L2 through compensation of the data voltage and / or the initialization voltage provided by the embodiment of the present application.

[0122] In some embodiments, as shown in Table 1, the compensation coefficients of the voltage signals received by the pixel circuits 11 in different rows are not completely the same. From the above description, it can be seen that in the transition frame, the timing of the sub-gate scanning signals received by the pixel circuits 11 in different rows is different. Therefore, by performing different degrees of data voltage compensation on the pixel circuits 11 in different rows, the uniformity of the full-screen brightness can be improved.

[0123] In some embodiments, as shown in Table 1, the compensation coefficients of the voltage signals received by the pixel circuits 11 in the same row are the same. For example, the pixel circuits 11 in the Mth row include a plurality of pixel circuits 11, and the second compensation voltage signal v 补偿2 The plurality of sub-compensation voltage signals are included, and the plurality of pixel circuits 11 are used to receive the plurality of sub-compensation voltage signals, and the compensation coefficients of the plurality of sub-compensation voltage signals are the same, so that the luminous brightness of the sub-pixels in the same row can be kept consistent.

[0124] Table 1 Luminous brightness 200nit

[0125]

[0126] Table 2 Luminous brightness 90nit

[0127]

[0128] Table 2 shows an embodiment of the present application, when the display brightness is 90 nit, the grayscale of each pixel row of an electronic device 1 in the AOD mode is L1, and in the transition frame, the grayscale of each pixel row is L2 through compensation of the data voltage and / or the initialization voltage. Comparing Table 1 and Table 2, it can be seen that in some embodiments, the compensation coefficient of the voltage signal under different luminous brightness may also be different. That is to say, in the embodiment of the present application, the compensation of the voltage signal has great flexibility.

[0129] In some embodiments, the first frequency is 120 Hz, and the refresh rate of the display panel 10 can be, for example, 360 Hz or an integer multiple of 360 Hz, so as to switch from 90 Hz to 120 Hz in the first mode to meet the normal display requirements. The second frequency is 30 Hz, which can reduce power consumption while meeting the display requirements in the AOD mode.

[0130] In some embodiments, the first frequency is greater than the second frequency, the base frequency of the display panel 10 changes from the first frequency to the second frequency, and the widths of the plurality of second sub-gate pulses included in the second sub-gate scanning signal vo32 tend to increase.

[0131] For example, the second sub-gate scanning signal vo32 includes three second sub-gate pulses. According to different values ​​of M, the widths of the three second sub-gate pulses may be increased in sequence. Alternatively, the widths of the first two second sub-gate pulses may be the same, and the width of the third second sub-gate pulse may be increased. Alternatively, the width of the second second sub-gate pulse may be greater than the width of the first second sub-gate pulse and equal to the width of the third second sub-gate pulse.

[0132] For example, the scanning time of a row is 8.33ms, and the time difference of each row is 0.03ms. In the second sub-gate scanning signal vo32 received by the pixel circuit of the Mth row, the width of the second sub-gate pulse appearing in the first (8.33-M*0.33)ms is a first fixed value, and the width of the second sub-gate pulse appearing in the remaining M*0.33ms is greater than the first fixed value and less than or equal to the second fixed value.

[0133] In some other embodiments, the first frequency is greater than the second frequency, the first mode is the normal mode, and the second mode is the AOD mode. For example, the first frequency is 120 Hz, and the second frequency is 30 Hz. The base frequency of the display panel 10 changes from the second frequency to the first frequency, and the widths of the plurality of second sub-gate pulses included in the second sub-gate scanning signal vo32 tend to decrease.

[0134] For example, the second sub-gate scanning signal vo32 includes three second sub-gate pulses. According to different values ​​of M, the widths of the three second sub-gate pulses may decrease in sequence. Alternatively, the widths of the first two second sub-gate pulses may be the same, and the width of the third second sub-gate pulse may decrease. Alternatively, the width of the second second sub-gate pulse may be less than or greater than the width of the first second sub-gate pulse and equal to the width of the third second sub-gate pulse.

[0135] Figure 6 A driving timing diagram of another display panel provided in an embodiment of the present application.

[0136] In some embodiments, Figure 6 As shown, the base frequency of the display panel 10 changes from the first frequency to the second frequency, and the gate drive circuit receives the second scanning start signal stv2 and the second clock signal clk2 to generate the second gate scanning signal vo2. In the first N image frames, the multiple rows of pixel circuits 11 receive the fourth compensation voltage signal v 补偿4 , and the second gate scanning signal vo2, control the display panel 10 to display the fourth picture. Starting from the N+1th image frame, the multi-row pixel circuit 11 receives the second voltage signal v2 and the second gate scanning signal vo2, and controls the display panel 10 to display the third picture. N is a positive integer, and N can be equal to 1, 2, 3, 4, etc. The fourth picture and the third picture can be the same or different, and the embodiment of the present application is not limited to this.

[0137] That is, after entering the second mode, in the first N image frames, the voltage signal received by the display panel 10 is a compensated voltage signal. Starting from the N+1th image frame, the voltage signal received by the display panel 10 is an uncompensated voltage signal. That is, in the case of switching from the first mode to the second mode, the first N image frames after entering the second mode also need to be compensated for the voltage signal, further increasing the image frames with brightness transition, so that the display brightness of the display panel 10 transitions smoothly, so as to achieve as much as possible no flicker to the naked eye when switching scenes.

[0138] For example, when switching from the normal mode to the AOD mode, the first N image frames after entering the AOD mode need to be compensated for voltage signals. Or, for example, when switching from the AOD mode to the normal mode, the first N image frames after entering the normal mode need to be compensated for voltage signals.

[0139] When N is greater than 1, the voltage signals of multiple image frames after entering the second mode need to be compensated. The compensation coefficients of the voltage signals in the multiple image frames may be the same or different. For example, the compensation coefficient of the voltage signal may be determined based on the brightness difference between the two image frames. In addition, in the same image frame, the compensation coefficients of the voltage signals received by the pixel circuits 11 in different rows may also be different.

[0140] Figure 7 A luminous brightness waveform diagram provided in an embodiment of the present application.

[0141] For example, Figure 7 As shown, taking the grayscale of the normal mode frame as L64 and the grayscale of the AOD mode frame as L57 as an example, when switching from the normal mode to the AOD mode, there will naturally be a transition frame. By performing voltage signal compensation on the transition frame, or further performing voltage signal compensation on the first frame or more frames of the AOD mode, the instantaneous brightness of the last frame of the normal mode, the instantaneous brightness of the transition mode frame, the instantaneous brightness of the first frame of the AOD mode, and the instantaneous brightness of the subsequent frames of the AOD mode can be different, but the average brightness finally presented by the last frame of the normal mode, the average brightness finally presented by the first frame of the AOD mode, and the average brightness finally presented by the subsequent frames of the AOD mode are almost the same or the purpose of smooth transition is achieved, so as to achieve seamless switching between different modes.

[0142] The display panel 10 provided in the embodiment of the present application can be applied to the display module 40 provided in the embodiment of the present application. The display driver integrated circuit 20 is coupled to the display panel 10 to provide the above-mentioned scanning start signal and clock signal to the display panel 10 .

[0143] For example, the display driver integrated circuit 20 is used to output the first clock signal clk1 , the first scanning start signal stv1 , and the first voltage signal v1 required for displaying the first picture to the display panel 10 .

[0144] For example, the driving controller 30 in the electronic device 1 is used to send a first base frequency instruction to the display driver integrated circuit 20 to control the display driver integrated circuit 20 to output a first clock signal clk1 and a first scanning start signal stv1 with a first base frequency. The first base frequency instruction indicates that the display panel 10 enters the first mode.

[0145] The display driver integrated circuit 20 is also used to output the second clock signal clk2, the second scanning start signal stv2, and the first compensation voltage signal v required for displaying the second picture to the display panel 10. 补偿1 , the second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 .

[0146] The display driver integrated circuit 20 is further configured to output a second clock signal clk2 , a second scanning start signal stv2 , and a second voltage signal v2 required for displaying the third picture to the display panel 10 .

[0147] For example, the driving controller 30 in the electronic device 1 is used to send a second base frequency instruction to the display driver integrated circuit 20 to control the display driver integrated circuit 20 to output a second clock signal clk2 with a second base frequency and a second scanning start signal stv2. The second base frequency instruction indicates that the display panel 10 enters the second mode.

[0148] When the electronic device 1 provided in the embodiment of the present application includes the above-mentioned display panel 10, the driving method of the electronic device 1 provided in the embodiment of the present application includes:

[0149] The driving controller 30 sends a first baseband instruction, and the display driving integrated circuit 20 outputs the first scanning start signal stv1, the first clock signal clk1 and the first voltage signal v1 to the display panel 10 according to the first baseband instruction, so as to drive the display panel 10 to display the first picture in the first mode. For example, the display enters the normal mode and displays the picture normally.

[0150] The driving controller 30 sends a second base frequency instruction, and the display driving integrated circuit 20 outputs the second start scanning signal stv2, the second clock signal clk2, and the first compensation voltage signal v to the display panel 10 according to the second base frequency instruction. 补偿1 , the second compensation voltage signal v 补偿2 and the third compensation voltage signal v 补偿3 , control the display panel 10 to display the second picture.

[0151] The display driver integrated circuit 20 continues to follow the second baseband instruction, continuously outputs the second start scanning signal stv2, the second clock signal clk2 and the second voltage signal v2 to the display panel 10, and controls the display panel 10 to display the third picture in the second mode. For example, the display enters the AOD mode and displays the picture at a low frequency.

[0152] In some embodiments, the driving method of the electronic device 1 further includes: in the second mode, in the first N image frames, the display driver integrated circuit 20 outputs the second start scanning signal stv2, the second clock signal clk2 and the fourth compensation voltage signal v 补偿4 , controls the display panel 10 to display the fourth picture after voltage compensation. Starting from the N+1th image frame, the display driver integrated circuit 20 outputs the second start scanning signal stv2, the second clock signal clk2 and the second voltage signal v2, and controls the display panel 10 to display the third picture without voltage compensation. The image data of the third picture and the fourth picture can be the same.

[0153] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: The display panel includes a gate driving circuit and a plurality of rows of pixel circuits; The gate driving circuit is used to receive a first scanning start signal and a first clock signal to generate a first gate scanning signal; the multi-row pixel circuit is used to receive a first voltage signal and the first gate scanning signal to control the display panel to display a first picture in a first mode; in an image frame, the base frequencies of the first scanning start signal and the first clock signal are a first frequency, and the widths of the multiple pulses included in the first gate scanning signal are a first fixed value; The gate driving circuit is used to receive a second scan start signal and a second clock signal, and generate a first sub-gate scan signal, a second sub-gate scan signal and a third sub-gate scan signal; the pixel circuit in the first row is used to receive a first compensation voltage signal and the first sub-gate scan signal, the pixel circuit in the Mth row is used to receive a second compensation voltage signal and the second sub-gate scan signal, and the pixel circuit in the last row is used to receive a third compensation voltage signal and the third sub-gate scan signal, so as to control the display panel to display a second picture; the pixel circuit in the Mth row is any row of pixel circuits located between the pixel circuits in the first row and the pixel circuits in the last row; in an image frame, the base frequency of the second scan start signal and the second clock signal is the second frequency; the width of the multiple pulses included in the first sub-gate scan signal is the first fixed value, the width of the multiple pulses included in the third sub-gate scan signal is the second fixed value, and the width of the multiple pulses included in the second sub-gate scan signal is unequal and is within the range from the first fixed value to the second fixed value; The gate drive circuit is also used to generate a second gate scan signal based on the second scan start signal and the second clock signal; the multi-row pixel circuit is used to receive the second voltage signal and the second gate scan signal to control the display panel to display a third picture in the second mode; in an image frame, the base frequency of the second scan start signal and the second clock signal is the second frequency; the width of the multiple pulses included in the second gate scan signal is the second fixed value.

2. The display panel according to claim 1, characterized in that: The compensation coefficients of the first compensation voltage signal, the second compensation voltage signal, and the third compensation voltage signal are different.

3. The display panel according to claim 1 or 2, characterized in that: The second picture is the same as the third picture; or, The second picture is different from the third picture.

4. The display panel according to any one of claims 1 to 3, characterized in that: The first voltage signal includes a first data voltage signal, the second voltage signal includes a second data voltage signal, the first compensation voltage signal includes a first compensation data voltage signal, the second compensation voltage signal includes a second compensation data voltage signal, and the third compensation voltage signal includes a third compensation data voltage signal.

5. The display panel according to any one of claims 1 to 4, characterized in that: The first voltage signal includes a first initialization voltage signal, the second voltage signal includes a second initialization voltage signal, the first compensation voltage signal includes a first compensation initialization voltage signal, the second compensation voltage signal includes a second compensation initialization voltage signal, and the third compensation voltage signal includes a third compensation initialization voltage signal.

6. The display panel according to any one of claims 1 to 5, characterized in that: The first frequency is greater than the second frequency; The base frequency of the display panel changes from the first frequency to the second frequency, and the widths of the plurality of pulses included in the second sub-gate scanning signal increase; The base frequency of the display panel changes from the second frequency to the first frequency, and the widths of the plurality of pulses included in the second sub-gate scanning signal show a decreasing trend.

7. The display panel according to any one of claims 1 to 6, characterized in that: In the second mode, in the first N image frames, the multiple rows of pixel circuits receive the fourth compensation voltage signal and the second gate scan signal to control the display panel to display the fourth picture; starting from the N+1th image frame, the multiple rows of pixel circuits receive the second voltage signal and the second gate scan signal to control the display panel to display the third picture; N is a positive integer.

8. The display panel according to any one of claims 1 to 7, characterized in that: The pixel circuit in the Mth row includes a plurality of the pixel circuits, the second compensation voltage signal includes a plurality of sub-compensation voltage signals, the plurality of pixel circuits are used to receive the plurality of sub-compensation voltage signals, and the compensation coefficients of the plurality of sub-compensation voltage signals are the same.

9. A display module, characterized in that: The display module includes a display driver integrated circuit and a display panel; the display driver integrated circuit is coupled to the display panel, and the display panel includes the display panel according to any one of claims 1-8.

10. The display module according to claim 9, characterized in that: The display driver integrated circuit is used to output the first clock signal, the first scanning start signal and the first voltage signal required for displaying the first picture to the display panel; The display driver integrated circuit is further used to output the second clock signal, the second scanning start signal, the first compensation voltage signal, the second compensation voltage signal and the third compensation voltage signal required for displaying the second picture to the display panel; The display driver integrated circuit is further configured to output the second clock signal, the second scanning start signal and the second voltage signal required for displaying the third picture to the display panel.

11. An electronic device, characterized in that: The electronic device comprises a driving controller and a display module, wherein the driving controller is coupled to the display module, and the display module comprises the display module according to claim 9.

12. The electronic device according to claim 11, characterized in that: The driving controller is used to send a first base frequency instruction to the display module to control the display module to output the first clock signal and the first scanning start signal; The driving controller is further used to send a second base frequency instruction to the display module to control the display module to output the second clock signal and the second scanning start signal.

13. A method for driving an electronic device, characterized in that: The electronic device comprises a driving controller, a display driving integrated circuit and a display panel, wherein the display panel comprises a gate driving circuit and a plurality of rows of pixel circuits; The driving method comprises: The driving controller sends a first base frequency instruction, and the display driving integrated circuit outputs a first scanning start signal, a first clock signal and a first voltage signal according to the first base frequency instruction; the gate driving circuit receives the first scanning start signal and the first clock signal to generate a first gate scanning signal, and the multi-row pixel circuit receives the first gate scanning signal and the first voltage signal to control the display panel to display a first picture in a first mode; in an image frame, the base frequencies of the first scanning start signal and the first clock signal are the first frequency, and the widths of the multiple pulses included in the first gate scanning signal are the first fixed value; The driving controller sends a second base frequency instruction, and the display driving integrated circuit outputs a second start scanning signal, a second clock signal, the first compensation voltage signal, the second compensation voltage signal and the third compensation voltage signal according to the second base frequency instruction. The gate driving circuit receives the second start scanning signal and the second clock signal, and generates a first sub-gate scanning signal, a second sub-gate scanning signal and a third sub-gate scanning signal; the pixel circuits in the first row receive the first compensation voltage signal and the first sub-gate scanning signal, the pixel circuits in the Mth row receive the second compensation voltage signal and the second sub-gate scanning signal, and the pixel circuits in the last row receive the third compensation voltage signal and the third sub-gate scanning signal, and control the display panel to display a second picture; the pixel circuits in the Mth row are any row of pixel circuits located between the pixel circuits in the first row and the pixel circuits in the last row; in an image frame, the base frequencies of the second scanning start signal and the second clock signal are the second frequency; the widths of the multiple pulses included in the first sub-gate scanning signal are the first fixed value, the widths of the multiple pulses included in the third sub-gate scanning signal are the second fixed value, and the widths of the multiple pulses included in the second sub-gate scanning signal are not equal and are within the range from the first fixed value to the second fixed value; The display driver integrated circuit also outputs a second start scan signal, a second clock signal, and a second voltage signal according to the second base frequency instruction; the gate drive circuit receives the second scan start signal and the second clock signal to generate a second gate scan signal; the multi-row pixel circuit receives the second voltage signal and the second gate scan signal to control the display panel to display a third picture in the second mode; in an image frame, the base frequency of the second scan start signal and the second clock signal is the second frequency; the width of the multiple pulses included in the second gate scan signal is the second fixed value.

14. The driving method according to claim 13, characterized in that: The second picture is the same as the third picture; or the second picture is different from the third picture.

15. The driving method according to claim 13 or 14, characterized in that: In the second mode, in the first N image frames, the display driver integrated circuit outputs the second start scanning signal, the second clock signal and the fourth compensation voltage signal according to the second base frequency instruction, and the gate driver circuit receives the second scanning start signal and the second clock signal to generate a second gate scanning signal; the multi-row pixel circuit receives the fourth compensation voltage signal and the second gate scanning signal to control the display panel to display the fourth picture; starting from the N+1th image frame, the multi-row pixel circuit receives the second voltage signal and the second gate scanning signal to control the display panel to display the third picture; N is a positive integer.

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