Relaxation oscillator and calibration circuit

Abstract

The invention discloses a relaxation oscillator and a calibration circuit, in an oscillator circuit, a bias circuit comprises a resistor R1 and MOS tubes M0, M1 and M2, and is used for generating bias current; the current mirror comprises three MOS (Metal Oxide Semiconductor) tubes M7, M8 and M9 which are connected in sequence, and is used for accurately copying bias current generated by the bias circuit and charging a capacitor of the relaxation oscillator; the back gate of the M0 is connected with the output of the operational amplifier, the back gate of the M2 generates an ERROR voltage under the condition that the layout is not matched, and the back gate voltage of the M0 is adjusted through the operational amplifier; and the MOS tubes M5 and M6 are connected to the differential input end of the operational amplifier and are connected with the current mirror to form negative feedback to adjust the threshold voltage of the M0, so that the gate-source voltage of the M0 and the gate-source voltage of the M2 are equal, and the bias current is recovered to a normal value. According to the relaxation oscillator, the layout matching requirement can be reduced through the calibration circuit, the back gate voltage of the M0 is adjusted through a loop under the condition that the layout is difficult to match, and the precision of a clock signal is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of relaxation oscillators, and in particular to a relaxation oscillator and a calibration circuit. Background Art

[0002] In modern electronic systems, many low-cost monolithic applications require on-chip oscillators to provide stable clock signals. Traditional CMOS standard processes provide a variety of oscillator design options to meet this requirement, including RC ring oscillators and relaxation oscillators.

[0003] RC ring oscillators are favored by some applications for their simple structure and low cost. However, the frequency stability of such oscillators is usually affected by the changes in the resistance and capacitance values, especially under environmental factors such as temperature changes and power supply voltage fluctuations (PVT: Process, Voltage, Temperature), and their frequency stability will be significantly reduced, thus limiting their use in applications that require high-precision clock signals.

[0004] In contrast, relaxation oscillators are widely popular among engineers due to their high accuracy and relatively easy implementation. Relaxation oscillators generate oscillation signals by controlling the charging and discharging process of capacitors, and their frequency stability mainly depends on the matching degree of capacitors and current sources. In order to improve the PVT stability of relaxation oscillators, many engineers have proposed various innovative designs, such as constant current sources and temperature compensation circuits.

[0005] However, these designs require a high degree of matching between devices, especially the matching of capacitors and current sources, which increases the difficulty of layout design. In actual production, due to factors such as process deviations and temperature gradients, the performance of the actual products produced often declines, resulting in the oscillator's frequency accuracy failing to meet the design requirements. To solve this problem, many engineers rely on trimming methods to ensure the accuracy of the oscillator. Trimming methods usually involve fine-tuning the circuit after production to compensate for the effects of process deviations and temperature changes on circuit performance. However, trimming methods not only increase production costs and complexity, but also fail to fundamentally solve the device matching problem.

[0006] Therefore, how to design a relaxation oscillator with high PVT stability, reduce the impact of matching between key components of the relaxation oscillator on accuracy, and reduce process dependence has become an important technical challenge in current low-cost single-chip applications. Summary of the invention

[0007] The problem to be solved by the present invention is to provide a relaxation oscillator and a calibration circuit, enhance the matching degree between components through circuit design, reduce the influence of the matching degree between key components of the relaxation oscillator on the accuracy, and reduce the dependence on the process.

[0008] The present invention adopts the following technical solution: a relaxation oscillator calibration circuit, comprising: a bias circuit, a current mirror, and an operational amplifier; The bias circuit includes: a resistor R1 and MOS tubes M0, M1, and M2, which are used to generate a bias current; the current mirror includes three MOS tubes M7, M8, and M9 connected in sequence, which are used to replicate the bias current generated by the bias circuit; the bias current is replicated by the current mirror to charge the capacitor of the relaxation oscillator; The back gate of the MOS tube M0 is connected to the output of the operational amplifier. In the case of layout mismatch, the back gate of the MOS tube M2 generates an ERROR voltage. The back gate voltage of the MOS tube M0 is adjusted by the operational amplifier to make the gate-source voltage of the MOS tube M0 equal to the gate-source voltage of the MOS tube M2, and the bias current is restored to the matching value. The operational amplifier includes MOS tubes M3, M4, M5, and M6; MOS tubes M3 and M4 are load tubes; the gates of MOS tubes M5 and M6 are connected to the differential input terminals of the operational amplifier, and the sources are connected to the current mirror; the operational amplifier is used to form negative feedback to adjust the threshold voltage of the MOS tube M0.

[0009] Preferably, the MOS tubes M0, M1, and M2 are NMOS tubes of the same size, the two ends of the resistor R1 are respectively connected to the sources of the MOS tubes M0 and M1, the drain of the MOS tube M0 is connected to the drain of the MOS tube M7, the drain of the MOS tube M2 is connected to the drain of the MOS tube M8; the drain of the MOS tube M1 is connected to the source of the MOS tube M2.

[0010] Preferably, in the current mirror, the three MOS tubes M7, M8, and M9 are all PMOS tubes, the sources of the three MOS tubes are connected, and the gates are also connected and connected to the drain of the MOS tube M0; the drain of the MOS tube M7 is connected to the drain of the MOS tube M0, the drain of the MOS tube M8 is connected to the drain of the MOS tube M2, and the drain of the MOS tube M9 is connected to the sources of the MOS tubes M5 and M6.

[0011] Preferably, the same-direction input terminal of the op amp is connected to a fixed voltage The reverse input terminal is connected between the resistor R1 and the source of the MOS tube M0, and the output terminal is connected to the back gate of the MOS tube M0. When the layout does not match, an ERROR voltage is generated between the drain of the MOS tube M1 and the source of the MOS tube M2.

[0012] Preferably, in the calibration circuit, the MOS tubes M5 and M6 are PMOS tubes, and the MOS tubes M5 and M6 are used to connect to the differential input terminal of the operational amplifier, the MOS tube M5 is the reverse input terminal, and the MOS tube M6 is the non-inverting input terminal.

[0013] The MOS tubes M3 and M4 are NMOS tubes, the drain of the MOS tube M3 is connected to the drain of the MOS tube M5, the drain of the MOS tube M4 is connected to the drain of the MOS tube M6, and the sources of the MOS tubes M3 and M4 are connected to the source of the MOS tube M1.

[0014] Preferably, the gate of MOS tube M3 is connected to the gate of MOS tube M1 as a current mirror load to copy the current of MOS tube M1; the gate of MOS tube M4 is connected to the drain of MOS tube M4 to form a diode, and the drain of MOS tube M4 is equal to the fixed ; The gate of the MOS tube M6 is connected to the drain of the MOS tube M6, and the same-direction input voltage is fixed to the gate-source voltage of the MOS tube M4; The drains of the MOS tube M3 and the MOS tube M5 are connected to each other, and are connected to the back gate of the MOS tube M0 as an output to form a loop, and the threshold voltage of the MOS tube M0 is adjusted through negative feedback.

[0015] Furthermore, the negative feedback adjusts the threshold voltage of the MOS tube M0 as follows: When the threshold voltage of the MOS tube M0 is higher than the threshold voltage of the MOS tube M2, the voltage of the resistor R1 is lower than the threshold voltage of the MOS tube M1, the voltage of the same-direction input terminal of the operational amplifier increases, the output voltage increases, the back gate voltage of the MOS tube M0 increases, the threshold voltage decreases, and the voltage of the resistor R1 increases; When the threshold voltage of the MOS tube M2 is higher than the threshold voltage of the MOS tube M0, the voltage of the resistor R1 is higher than the threshold voltage of the MOS tube M1, the voltage at the reverse input terminal of the operational amplifier increases, the output voltage decreases, the back gate voltage of the MOS tube M0 decreases, the threshold voltage increases, and the voltage of the resistor R1 decreases.

[0016] The back gate voltages of MOS tubes M1, M3, and M4 are the same and highly matched in the layout.

[0017] The technical solution of the present invention also provides a relaxation oscillator, including any calibration circuit as described above, wherein a bias current is generated by the bias circuit, the bias current generated by the bias circuit is copied by the current mirror to charge the capacitor of the relaxation oscillator, and negative feedback is formed by the operational amplifier to adjust the back gate voltage of the MOS tube M0.

[0018] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects: 1. The relaxation oscillator proposed in the present invention can achieve a relatively high-precision oscillation frequency. By using an RC device that is independent of the operating temperature, an oscillation frequency that is substantially independent of PVT changes can be achieved.

[0019] 2. The calibration circuit proposed in the present invention can reduce the requirements for layout matching. When the layout is difficult to match, the back gate voltage of the MOS tube M0 is adjusted through a loop to improve the accuracy of the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of the working principle of the relaxation oscillator; Figure 2 Figure 2 is the schematic diagram of the relaxation oscillator circuit; Figure 3 is a schematic diagram of a bias circuit of the present invention; Figure 4 This is a schematic diagram of the relaxation oscillator calibration circuit of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the application is further elaborated in detail below in conjunction with the accompanying drawings. The described embodiments are only a part of the embodiments involved in the present invention. All non-innovative embodiments of other researchers in the field on this embodiment belong to the protection scope of the present invention. At the same time, for the step numbering in the embodiment of the present invention, it is only set for the convenience of explanation, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0022] The basic working principle of the existing relaxation oscillator is as follows: Figure 1 As shown, the relaxation oscillator includes: a first current source , the second current source ,switch ,switch , capacitor, comparator, and the relaxation oscillator achieves oscillation by repeatedly charging and discharging the capacitor through a current source.

[0023] The relaxation oscillator working cycle is divided into the following two stages: Phase 1: Switch Closed, current source The capacitor is charged and the capacitor voltage rises. When the capacitor voltage is higher than When , the comparator flips, the switch is disconnected, and the capacitor stops charging; Phase 2: Switch Close, the capacitor begins to discharge, and the capacitor voltage drops. When the capacitor voltage is lower than When the comparator flips, it enters the first stage again.

[0024] The relaxation oscillator schematic diagram is shown in Figure 2. Figure 2As shown, MOS tubes M0, M1, M2 and R1 form a bias circuit for generating a current for charging the capacitor, MOS tubes M7-M12 are current mirrors for accurately replicating the current generated by the bias circuit, and the remaining devices are comparators and combinational logic.

[0025] In the bias circuit, MOS tubes M0, M1, and M2 are matched transistors with the same size. The bias current generated by the bias circuit is: ; in, is the gate-source voltage of MOS tubes M0, M1, and M2, is the resistance value of resistor R1. The bias current is copied by the current mirror to charge capacitors C0 and C1.

[0026] Figure 2 In the figure, X0, X1, and X2 are all inverters. X0 and X1 are connected in sequence and connected to the gate of MOS tube M3. X2 is connected to the gate of MOS tube M5. NAND gates X3 and X4 form an RS trigger. MOS tubes M4 and M6 are used as the input terminals of the common source amplifier. When the pull-down delay is ignored, capacitors C0 and C1 are charged to When , MOS tubes M4 and M6 are turned on, the comparator flips, and the input levels of X3 and X4 are changed. When the transmission delay of the comparator is ignored, the period of the relaxation oscillator is: ; Wherein, R is the resistance value of R1, and C is the capacitance value of capacitors C0 and C1.

[0027] Under ideal conditions, the oscillation frequency of the relaxation oscillator is determined by RC. However, in the layout, since the back gates of MOS tubes M0, M1, and M2 are connected to different potentials, these three devices need to be placed in different wells during layout implementation, making it difficult to match the devices. Unmatched devices cause the bias current to deviate from the ideal value, which in turn affects the oscillation frequency.

[0028] Therefore, the present invention proposes a relaxation oscillator calibration circuit, which solves the problem of difficult matching on the layout through circuit design, enhances the matching degree between devices, and is used to reduce the impact of the matching degree between key devices of the relaxation oscillator on the accuracy, thereby reducing the process dependence.

[0029] In one embodiment of the present invention, the calibration circuit, such as Figure 4 As shown, it includes: bias circuit, current mirror, and operational amplifier.

[0030] The bias circuit includes: a resistor R1 and MOS tubes M0, M1, and M2, which are used to generate a bias current; an operational amplifier includes MOS tubes M3, M4, M5, and M6; and a current mirror includes three MOS tubes M7, M8, and M9 connected in sequence, which are used to accurately replicate the bias current generated by the bias circuit.

[0031] Furthermore, the bias circuit is as follows Figure 3 As shown, MOS tubes M0, M1, and M2 are NMOS tubes of the same size, two ends of the resistor R1 are respectively connected to the sources of the MOS tubes M0 and M1, the drain of the MOS tube M0 is connected to the drain of the MOS tube M7, the drain of the MOS tube M2 is connected to the drain of the MOS tube M8; the drain of the MOS tube M1 is connected to the source of the MOS tube M2.

[0032] The back gate of MOS tube M0 is connected to the output of the op amp, and the same-direction input of the op amp is connected to a fixed voltage The reverse input terminal is connected between the resistor R1 and the source of the MOS tube M0, and the output terminal is connected to the back gate of the MOS tube M0. When the layout does not match, an ERROR voltage is generated between the drain of the MOS tube M1 and the source of the MOS tube M2. The ERROR voltage is equivalent to the error caused by the layout mismatch.

[0033] In the case of layout mismatch, the back gate of MOS tube M2 generates ERROR voltage. The back gate voltage of MOS tube M0 is adjusted by adding an op amp to make the gate-source voltage of MOS tube M0 equal to the gate-source voltage of MOS tube M2, and restore the bias current to the matching value. The op amp has a fixed voltage at the same input terminal. , the reverse input terminal is connected to the voltage across resistor R1, and the output is connected to the back gate of M0.

[0034] Preferably, in the current mirror, the three MOS tubes M7, M8, and M9 are all PMOS tubes, the sources of the three MOS tubes are connected, and the gates are also connected and connected to the drain of the MOS tube M0; the drain of the MOS tube M7 is connected to the drain of the MOS tube M0, the drain of the MOS tube M8 is connected to the drain of the MOS tube M2, and the drain of the MOS tube M9 is connected to the sources of the MOS tubes M5 and M6.

[0035] Preferably, in the calibration circuit, MOS tubes M5 and M6 are PMOS tubes, and MOS tubes M3 and M4 are NMOS tubes; MOS tubes M3 and M4 are load tubes, and MOS tubes M5 and M6 serve as differential input terminals of an operational amplifier.

[0036] Among them, MOS tube M5 is the reverse input terminal, MOS tube M6 is the non-inverting input terminal, MOS tubes M3 and M4 are load tubes, and the gate of MOS tube M3 is connected to the gate of MOS tube M1 to serve as a current mirror load to copy the current of MOS tube M1.

[0037] MOS tubes M4 and M6 are both connected by diodes. The gate and drain of MOS tubes M4 and M6 are short-circuited, and the drain of MOS tube M4 is equal to a fixed voltage. , the same-direction input voltage Vg of MOS tube M6 = Vd, and is fixed at Vd and , where Vg is the gate voltage and Vd is the drain voltage.

[0038] The drains of the MOS tubes M3 and M5 are connected to the back gate of the MOS tube M0 as outputs, and the threshold voltage of M0 is adjusted through negative feedback.

[0039] In this circuit, the back gate voltages of MOS tubes M1, M3, and M4 are the same and can be highly matched in the layout.

[0040] Specifically, if the threshold voltage of the MOS tube M0 is higher than the threshold voltage of the MOS tube M2, the voltage of the resistor R1 is lower than the threshold voltage of M1, that is, the gate of the MOS tube M6, the op amp's non-inverting input terminal increases, the output increases, the back gate voltage of the MOS tube M0 increases, the threshold voltage decreases, and the voltage of the resistor R1 increases.

[0041] On the contrary, if the threshold voltage of the MOS tube M2 is higher than the threshold voltage of the MOS tube M0, the voltage of the resistor R1 is higher than the threshold voltage of the MOS tube M1, the reverse input terminal of the operational amplifier increases, the output decreases, the back gate voltage of the MOS tube M0 decreases, the threshold voltage increases, and the voltage of the resistor R1 decreases.

[0042] This embodiment also proposes a relaxation oscillator, including the above-mentioned calibration circuit, wherein a bias current is generated by a bias circuit in the calibration circuit, and the bias current generated by the bias circuit is accurately copied by a current mirror in the calibration circuit to charge the capacitor of the relaxation oscillator, and negative feedback is formed by the operational amplifier to adjust the back gate voltage of the MOS tube M0.

[0043] The relaxation oscillator proposed in this embodiment can achieve a relatively high-precision oscillation frequency. By using an RC device that is independent of the operating temperature, an oscillation frequency that is basically independent of PVT changes can be achieved. The proposed calibration circuit can reduce the requirements for layout matching. When the layout is difficult to match, the back gate voltage of the MOS tube M0 is adjusted through a loop to achieve stability of the bias circuit.

[0044] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A relaxation oscillator calibration circuit, characterized in that: Applied to relaxation oscillator, including: bias circuit, current mirror, operational amplifier; The bias circuit includes: a resistor R1 and MOS tubes M0, M1, and M2, which are used to generate a bias current; the current mirror includes three MOS tubes M7, M8, and M9 connected in sequence, which are used to replicate the bias current generated by the bias circuit; the bias current is replicated by the current mirror to charge the capacitor of the relaxation oscillator; The back gate of the MOS tube M0 is connected to the output of the operational amplifier. In the case of layout mismatch, the back gate of the MOS tube M2 generates an ERROR voltage. The back gate voltage of the MOS tube M0 is adjusted by the operational amplifier to make the gate-source voltage of the MOS tube M0 equal to the gate-source voltage of the MOS tube M2, and the bias current is restored to the matching value. The operational amplifier includes MOS tubes M3, M4, M5, and M6; MOS tubes M3 and M4 are load tubes; the gates of MOS tubes M5 and M6 are connected to the differential input terminals of the operational amplifier, and the sources are connected to the current mirror; the operational amplifier is used to form negative feedback to adjust the threshold voltage of the MOS tube M0.

2. The relaxation oscillator calibration circuit according to claim 1, characterized in that: In the bias circuit, MOS tubes M0, M1, and M2 are NMOS tubes of the same size, two ends of the resistor R1 are respectively connected to the sources of the MOS tubes M0 and M1, the drain of the MOS tube M0 is connected to the drain of the MOS tube M7, the drain of the MOS tube M2 is connected to the drain of the MOS tube M8; the drain of the MOS tube M1 is connected to the source of the MOS tube M2.

3. The relaxation oscillator calibration circuit according to claim 2, characterized in that: In the current mirror, the three MOS tubes M7, M8, and M9 are all PMOS tubes, the sources of the three MOS tubes are connected, and the gates are also connected and connected to the drain of the MOS tube M0; the drain of the MOS tube M7 is connected to the drain of the MOS tube M0, the drain of the MOS tube M8 is connected to the drain of the MOS tube M2, and the drain of the MOS tube M9 is connected to the sources of the MOS tubes M5 and M6.

4. The relaxation oscillator calibration circuit according to claim 3, characterized in that: The same-inverting input terminal of the op amp is connected to a fixed voltage The reverse input terminal is connected between the resistor R1 and the source of the MOS tube M0, and the output terminal is connected to the back gate of the MOS tube M0. When the layout does not match, an ERROR voltage is generated between the drain of the MOS tube M1 and the source of the MOS tube M2.

5. The relaxation oscillator calibration circuit according to claim 4, characterized in that: MOS tubes M5 and M6 are PMOS tubes, and are used to access the differential input terminals of the operational amplifier. MOS tube M5 is the reverse input terminal, and MOS tube M6 is the non-inverting input terminal.

6. The relaxation oscillator calibration circuit according to claim 5, characterized in that: The MOS tubes M3 and M4 are NMOS tubes, the drain of the MOS tube M3 is connected to the drain of the MOS tube M5, the drain of the MOS tube M4 is connected to the drain of the MOS tube M6, and the sources of the MOS tubes M3 and M4 are connected to the source of the MOS tube M1.

7. The relaxation oscillator calibration circuit according to claim 6, characterized in that: The gate of MOS tube M3 is connected to the gate of MOS tube M1 as a current mirror load to copy the current of MOS tube M1; the gate of MOS tube M4 is connected to the drain of MOS tube M4 to form a diode. The drain of MOS tube M4 is equal to a fixed voltage. ; The gate of the MOS tube M6 is connected to the drain of the MOS tube M6, and the same-direction input voltage is fixed to the gate-source voltage of the MOS tube M4; The drains of the MOS tube M3 and the MOS tube M5 are connected to each other, and are connected to the back gate of the MOS tube M0 as an output to form a loop, and the threshold voltage of the MOS tube M0 is adjusted through negative feedback.

8. The relaxation oscillator calibration circuit according to claim 7, characterized in that: The negative feedback adjusts the threshold voltage of the MOS tube M0 as follows: When the threshold voltage of the MOS tube M0 is higher than the threshold voltage of the MOS tube M2, the voltage of the resistor R1 is lower than the threshold voltage of the MOS tube M1, the voltage of the same-direction input terminal of the operational amplifier increases, the output voltage increases, the back gate voltage of the MOS tube M0 increases, the threshold voltage decreases, and the voltage of the resistor R1 increases; When the threshold voltage of the MOS tube M2 is higher than the threshold voltage of the MOS tube M0, the voltage of the resistor R1 is higher than the threshold voltage of the MOS tube M1, the voltage at the reverse input terminal of the operational amplifier increases, the output voltage decreases, the back gate voltage of the MOS tube M0 decreases, the threshold voltage increases, and the voltage of the resistor R1 decreases.

9. The relaxation oscillator calibration circuit according to claim 8, characterized in that: The back gate voltages of the MOS tubes M1, M3, and M4 are the same.

10. A relaxation oscillator, characterized in that: The relaxation oscillator includes a calibration circuit as described in any one of claims 1 to 9, a bias current is generated by the bias circuit, the bias current generated by the bias circuit is copied by the current mirror to charge the capacitor of the relaxation oscillator, and negative feedback is formed by the operational amplifier to adjust the back gate voltage of the MOS tube M0.

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