32G Fiber Channel Forward Error Correction Codec Device

Abstract

The present invention discloses a 32G fiber channel forward error correction encoding and decoding device, comprising: a 64B / 66B encoding module, a 256B / 257B encoding module, a 514b / 330b bit width conversion module, an RS encoding and decoding module, a PN5280 scrambling and descrambling module, a 330b / 66b bit width conversion module, a receiving synchronization module, a 256B / 257B decoding module, a 64B / 66B decoding module and a high-speed serial transceiver; the RS encoding and decoding module adds check bit information to the data by encoding to form a complete FEC code block, and the RS encoding and decoding module at the receiving end completes RS decoding according to the check bit information combined with the RS decoding algorithm, completes the recovery of limited errors occurring during the transmission process, and outputs an indication signal of whether the decoding is correct for each FEC code block. The 32G fiber channel forward error correction encoding and decoding device of the present invention supports the forward error correction encoding and decoding function, completes the recovery function of limited errors during data transmission through the error correction function of the RS encoding and decoding, and ensures high-speed and reliable transmission of data.

Description

Technical Field

[0001] The present invention belongs to the technical field of network communications, and in particular relates to a 32G optical fiber channel forward error correction encoding and decoding device. Background Art

[0002] Fibre Channel (FC) is a high-speed serial point-to-point transmission protocol used in storage area networks and avionics systems. It is an open network technology with high bandwidth, high reliability, low latency, flexible topology, and long transmission distance. Similar to the general OSI model, Fibre Channel also adopts a layered structure, and its hierarchy can be divided into FC-0, FC-1, FC-2, FC-3, and FC-4 layers from bottom to top. At the same time, Fibre Channel also provides mapping interfaces for multiple upper-layer protocols, which are classified in the ULPs layer.

[0003] Currently, fiber channel technology has been widely used in the commercial field and provides support for the construction of the next generation of unified networks for avionics systems. At present, the mainstream fiber channel rates in China are 8G, 16G and 32G. During high-speed signal transmission, various signal integrity problems will occur due to transmission medium loss, conductor loss, conductor surface roughness and other reasons. With the continuous increase in data transmission rate, signal integrity problems have become more and more significant, and bit errors are inevitable. Summary of the invention

[0004] The present invention provides a 32G fiber channel forward error correction encoding and decoding device to solve the above-mentioned technical problems, and specifically adopts the following technical solutions:

[0005] A 32G fiber channel forward error correction encoding and decoding device, comprising: a 64B / 66B encoding module, a 256B / 257B encoding module, a 514b / 330b bit width conversion module, an RS encoding and decoding module, a PN5280 scrambling and descrambling module, a 330b / 66b bit width conversion module, a receiving synchronization module, a 256B / 257B decoding module, a 64B / 66B decoding module and a high-speed serial transceiver; the 64B / 66B encoding module, the 64B / 66B decoding module, the 256B / 257B encoding module and the 256B / 257B decoding module are used to perform corresponding encoding or decoding operations; the 514b / 330b bit width conversion module and the 330b / 66b bit width conversion module are used to perform corresponding bit width conversion operations;

[0006] The 64B / 66B encoding module is used to complete 64B / 66B encoding and scrambling of the FC transmission word transmitted from the data link layer;

[0007] The 256B / 257B encoding module is used to group the code blocks after the 64B / 66B encoding, and then perform 256B / 257B encoding to reserve the check bit data width for the subsequent RS encoding;

[0008] The 514b / 330b bit width conversion module is used to perform bit width conversion on the code block after 256B / 257B encoding to adapt to the data bit width of the RS encoding and decoding module, and to perform bit width conversion on the data after RS ​​decoding to adapt to the data bit width of the 256B / 257B decoding module;

[0009] The RS encoding and decoding module is used to perform RS encoding on the FEC code block and add check bit information. The RS encoding and decoding module at the receiving end completes RS decoding according to the check bit information combined with the RS decoding algorithm, completes the recovery of limited errors occurring during the transmission process, and outputs an indication signal indicating whether the decoding is correct or not for each FEC code block;

[0010] The PN5280 scrambling and descrambling module is used to scramble the FEC code block after RS ​​encoding, and descramble the data converted by the 330b / 66b bit width conversion module to complete the recovery of the original FEC code block data;

[0011] The 330b / 66b bit width conversion module is used to perform bit width conversion on the data after PN5280 scrambling to adapt to the data bit width of the high-speed serial transceiver transmission channel, and to perform bit width conversion on the data received by the high-speed serial transceiver to adapt to the data bit width of the PN5280 scrambling and descrambling module;

[0012] The receiving synchronization module is used to complete the receiving end synchronization of the forward error correction encoding and decoding channel;

[0013] The 256B / 257B decoding module is used to perform 256B / 257B decoding on the data after RS ​​decoding and bit width conversion, recover the discarded transmission word type value information and recover the original 64B / 66B code block;

[0014] The 64B / 66B decoding module is used to descramble and 64B / 66B decode the code blocks after 256B / 257B decoding, and feed back transmission word error indication information to the data link layer;

[0015] The high-speed serial transceiver is used for sending data after encoding and receiving data before decoding, and cooperates with the receiving synchronization module to complete the data bit shift operation.

[0016] Further, the 64B / 66B encoding module includes an encoding module and a scrambling module;

[0017] The encoding module is used to perform 64B / 66B encoding on the FC transmission word transmitted from the data link layer and append a 2-bit synchronization header;

[0018] The scrambling module is used to scramble the code block data part after 64B / 66B encoding to increase the randomness of the data and ensure the consistency of the number of 0 and 1 during data transmission. The scrambling process does not scramble the synchronization header.

[0019] Furthermore, the 256B / 257B encoding module is used to reassemble and perform 256B / 257B encoding on four code blocks after completing 64B / 66B encoding, and reserve data bit width for subsequent RS encoding to fill in check bits.

[0020] Further, the 514b / 330b bit width conversion module includes a 514bto330b bit width conversion module and a 330bto514b bit width conversion module;

[0021] The 514bto330b bit width conversion module is used to perform bit width conversion on the code block after completing 256B / 257B encoding, and convert it into data with a data bit width of 330 bits, which is input to the subsequent RS encoding and decoding module for encoding;

[0022] The 330bto514b bit width conversion module is used to perform bit width conversion on the data after RS ​​decoding, converting the data into data with a bit width of 514 bits and inputting it into the subsequent 256B / 257B decoding module for decoding.

[0023] Furthermore, the RS encoding and decoding module includes an RS encoding module and an RS decoding module;

[0024] The RS encoding module is used to perform RS encoding on the data after completing 256B / 257B encoding and 514b to 330b bit width conversion, and add 140-bit check bits to each FEC code block to form a complete FEC code block;

[0025] The RS decoding module is used to perform RS decoding on the data after the bit width conversion from 66b to 330b, recover the limited errors in the transmission process according to the 140-bit check information attached to the FEC code block, and output an indication of whether the decoding is correct for each decoded FEC code block to complete the synchronization of the receiving end.

[0026] Further, the PN5280 scrambling and descrambling module includes a PN5280 scrambling module and a PN5280 descrambling module;

[0027] The PN5280 scrambling module is used to scramble the complete FEC code block after RS ​​encoding to increase the randomness of the data inside the FEC code block and ensure the DC balance during data transmission;

[0028] The PN5280 descrambling module is used to descramble the data after the bit width conversion from 66b to 330b to restore the original FEC code block.

[0029] Further, the 330b / 66b bit width conversion module includes a 330bto66b bit width conversion module and a 66bto330b bit width module;

[0030] The 330bto66b bit width conversion module is used to perform bit width conversion on the data after PN5280 scrambling, and convert the data into data with a data bit width of 66 bits and hand it over to the high-speed serial transceiver for data transmission;

[0031] The 66bto330b bit width conversion module is used to perform bit width conversion on the data received by the high-speed serial transceiver, converting the data into data with a data bit width of 330 bits for subsequent PN5280 descrambling.

[0032] Furthermore, the receiving synchronization module is used to complete the synchronization of the receiving end, and judge whether the current parallel data segmentation method is correct according to the indication mark of whether the decoding is correct or not output by the RS encoding and decoding module. When the data segmentation method is incorrect, a data bit shift indication is fed back to the high-speed serial transceiver, and the high-speed serial transceiver performs data bit shift according to the bit shift indication.

[0033] Furthermore, the 256B / 257B decoding module is used to perform 256B / 257B decoding on the data after RS ​​decoding and 330b to 514b bit width conversion, decode the fourth bit of the transmission word type value of the first control code block discarded during the encoding process, complete data splitting, and restore the original 64B / 66B code block.

[0034] Further, the 64B / 66B decoding module includes a decoding module and a descrambling module;

[0035] The decoding module is used to perform 64B / 66B decoding on the descrambled code blocks, restore the data to the form of FC transmission words, and feed back various errors that occur during the decoding process to the data link layer;

[0036] The descrambling module is used to descramble the data after 256B / 257B decoding to restore the original data. The descrambling process does not descramble the synchronization header.

[0037] The benefit of the present invention lies in that the 32G fiber channel forward error correction encoding and decoding device provided supports the sixth-generation fiber channel protocol standard, the data transmission mode is duplex, the line rate is 28.05Gbps, and the forward error correction encoding and decoding function is supported. The error correction function of RS (528, 514) encoding and decoding completes the recovery function of limited errors in the data transmission process, ensuring high-speed and reliable data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 It is a schematic diagram of the overall structure of a 32G fiber channel forward error correction encoding and decoding device of the present invention;

[0040] Figure 2 A schematic diagram of the structure of a 64B / 66B encoding module of a 32G fiber channel forward error correction encoding and decoding device of the present invention;

[0041] Figure 3 A corresponding relationship between a 64B / 66B coded transmission word type value and a transmission word combination of a 32G fiber channel forward error correction encoding and decoding device of the present invention;

[0042] Figure 4 A schematic diagram of 257B / 257B encoding of a 32G fiber channel forward error correction encoding and decoding device of the present invention;

[0043] Figure 5 This is a schematic diagram of the structure of a 514 / 330 bit width conversion module of a 32G fiber channel forward error correction encoding and decoding device of the present invention;

[0044] Figure 6 The RS encoder principle of a 32G fiber channel forward error correction encoding and decoding device of the present invention;

[0045] Figure 7 A schematic diagram of PN5280 scrambling of a 32G fiber channel forward error correction encoding and decoding device of the present invention;

[0046] Figure 8 A state transition diagram of a receiving synchronization control state machine of a 32G fiber channel forward error correction encoding and decoding device of the present invention;

[0047] Fig. 9The present invention is a schematic diagram of the structure of a 64B / 66B decoding module of a 32G fiber channel forward error correction encoding and decoding device. DETAILED DESCRIPTION

[0048] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0049] The "FC transmission word" described in this application refers to a basic unit of data input in a 32G fiber channel forward error correction encoding and decoding device. Each FC transmission word is 4 bytes, including FC primitives and FC frames.

[0050] The "FC primitives" described in this application refer to a series of FC transmission words with special meanings specified in the FC protocol, consisting of 1 K code and 3 D codes. During the link initialization process, the communicating parties complete reception synchronization and link establishment through primitive interaction.

[0051] The RS (528, 514) coding described in this application refers to Reed-Solomon coding, which is a common checksum code with error detection and correction capabilities used for storage and large-block data transmission.

[0052] The FEC described in this application refers to forward error correction coding. There are many ways to implement forward error correction coding. This application uses RS coding required by the protocol standard.

[0053] It should be noted that the RS encoding method is not limited to RS (528, 514) encoding, and different types of RS encoding methods can be used according to different application scenarios and protocol standards.

[0054] Figure 1The figure shows a schematic diagram of the overall structure of a 32G fiber channel forward error correction encoding and decoding device of the present application. A 32G fiber channel forward error correction encoding and decoding device is based on the sixth-generation fiber channel protocol standard and implements part of the functions of the 32GFC transmission coding layer according to the forward error correction encoding and decoding mechanism proposed in the protocol. Specifically, a 32G fiber channel forward error correction encoding and decoding device includes: a 64B / 66B encoding module, a 256B / 257B encoding module, a 514b / 330b bit width conversion module, an RS encoding and decoding module, a PN5280 scrambling and descrambling module, a 330b / 66b bit width conversion module, a receiving synchronization module, a 256B / 257B decoding module, a 64B / 66B decoding module and a high-speed serial transceiver. The 64B / 66B encoding module, the 64B / 66B decoding module, the 256B / 257B encoding module and the 256B / 257B decoding module are used to perform corresponding encoding or decoding operations. The 514b / 330b bit width conversion module and the 330b / 66b bit width conversion module are used to perform corresponding bit width conversion operations.

[0055] Among them, the 64B / 66B encoding module receives the data with a data bit width of 512 bits in the unit of FC transmission words transmitted from the data link layer, performs 64B / 66B encoding, and then scrambles the data part after encoding (does not scramble the synchronization header part) to increase the randomness of the data. The 256B / 257B encoding module groups the data completed by 64B / 66B encoding and performs 256B / 257B encoding. After that, the data bit width conversion is completed by the 514b / 330b bit width conversion module, and the complete 5280-bit FEC code block is divided into 16 beats of 330-bit data and handed over to the RS (528, 514) encoding and decoding module to complete RS (528, 514) encoding. In this application, the RS encoding and decoding module is specifically an RS (528, 514) encoding and decoding module, which performs RS (528, 514) encoding and decoding, and adds 140-bit check bits to each FEC code block to form a complete FEC code block. Then the PN5280 scrambling and descrambling module completes the scrambling operation of the complete FEC code block. Finally, the 330b / 66b bit width conversion module performs bit width conversion on the scrambled data, and finally outputs the data to the high-speed serial transceiver to complete data transmission. At the receiving end, the receiving synchronization module determines the correctness of the data segmentation method based on the indication signal of whether the RS (528, 514) decoding is correct or not, and feeds back the bit shift signal to the high-speed serial transceiver. The high-speed serial transceiver performs data bit shift operation according to the data bit shift signal, and finally completes the receiving synchronization. Then the data is input into the 330b / 66b bit width conversion module to complete the bit width conversion, and the converted data is input into the PN5280 scrambling and descrambling module to complete the descrambling, so as to realize the recovery of the original data of the FEC code block. After that, the RS (528, 514) decoding is completed through the RS (528, 514) encoding and decoding module, and the limited errors in the transmission process are recovered according to the 140-bit check information attached to the FEC code block, and the indication of whether the decoding is correct or not is output for each decoded FEC code block to complete the synchronization of the receiving end. Then the bit width conversion is completed through the 514b / 330b bit width conversion module, and the 256B / 257B decoding module completes the 256B / 257B decoding of the data to restore the original 64B / 66B code block. Finally, the 64B / 66B decoding module completes the data descrambling and 64B / 66B decoding operations, and the data and related transmission word error indication information are handed over to the data link layer. The high-speed serial transceiver is used to send data after encoding and receive data before decoding, and cooperates with the receiving synchronization module to complete the data bit shift operation.

[0056] like Figure 2As shown, as a preferred implementation, the 64B / 66B encoding module includes: an encoding module and a scrambling module. The data link layer inputs a 512-bit transmission word stream, combines two FC transmission words into a 64-bit code block, inputs the encoding module to complete the 64B / 66B encoding of each 64-bit code block, and after the encoding is completed, the data is recombined and input into the scrambling module. The scrambling module scrambles the data part according to the polynomial specified by the FC protocol.

[0057] The encoding module performs 64B / 66B encoding on each 64-bit data, and adds a 2-bit synchronization header after encoding. The 64-bit data is divided into two 32-bit FC transmission words, and different synchronization headers are assigned according to different combinations of the two FC transmission words (Note: if both transmission words are data, the synchronization header is 2'b01, otherwise as long as one of the two transmission words is a control transmission word, the synchronization header is 2'b10, and the synchronization headers of other combinations are invalid synchronization headers) and 8-bit transmission word type values. The corresponding relationship between the transmission word type value and the transmission word content can be found in Figure 3 The encoding of each transmission word can be divided into three cases: (1) Data transmission word: no encoding; (2) IDLE: encoded as 4 7-bit control codes; (3) Other control transmission words: encoded as 4-bit ordered code and 3 8-bit modifier codes. After the encoding is completed, the data is reorganized according to the encoding specification based on the content of the transmission word, and finally 66-bit encoded data is formed.

[0058] The scrambling module scrambles the data after 64B / 66B encoding. The data after 64B / 66B encoding lacks data randomness. If it is transmitted directly, it is very likely to cause data errors at the receiving end. Therefore, the data needs to be scrambled after 64B / 66B encoding. Scrambling is to rearrange and randomize the data to achieve a random distribution of "0" and "1", further reducing inter-code interference. The synchronization header is used for synchronization at the receiving end, so scrambling is only performed on the part other than the synchronization header. The scrambling uses the polynomial G(x) = x 58 + x 39 + 1.

[0059] As a preferred implementation, the 256B / 257B encoding module compresses and combines the four 64B / 66B encoded code blocks to reserve the check bit data width for RS (528, 514) encoding. Figure 4, the highest bit of the 256B / 257B encoded data code block represents whether it contains a control code block. If it contains a control code block, the highest bit is 0; if it is all data, the highest bit is 1. In the first case, all four code blocks are data. After the highest bit is set to 1, the data parts of the four 64B / 66B code blocks are reassembled. In the second case, it contains both control code blocks and data code blocks. The highest bit is set to 0, and each bit from bit 255 to bit 252 represents whether the corresponding code block is a control code block or a data code block. 0 represents that the corresponding code block is a control code block, otherwise it represents a data code block. At the same time, remove the lower four bits of the transmission digital type value of the first control code block, and then reassemble the four code blocks in order.

[0060] like Figure 5 As shown, as a preferred implementation, the 514 / 330 bit width conversion module includes: a 514b to 330b bit width conversion module and a 330b to 514b bit width conversion module.

[0061] The 514bto330b bit width conversion module writes the 514-bit data after 256B / 257B encoding into the 514bto330b bit width conversion clock isolation FIFO. When the FIFO is about to be full, the prog_full signal is used to notify the data link layer module to stop sending data. In order to ensure the continuity of the RS encoding process, a certain amount of data margin must be ensured in the FIFO before starting RS encoding. A complete FEC code block is 5280 bits, corresponding to 10 beats of 514-bit data. Therefore, the data reading control state machine detects the prog_empty signal of the FIFO. When the FIFO is not empty and the lower-level FIFO is not full, the control increases the count value of the counter, reads data from the FIFO, and the data selector selects the data output at the corresponding position according to the value of the counter to complete the bit width conversion.

[0062] The 330bto514b bit width conversion module combines the 330-bit data after RS ​​(528, 514) decoding. The data write control state machine counts the valid input data, and the data selector completes the data combination according to the count value, and writes the combined data into the 330bto514b bit width conversion clock isolation FIFO according to the write instruction of the state machine. The FIFO read side reads data from the FIFO for output when the prog_empty signal of the FIFO is pulled low.

[0063] As a preferred implementation, the RS (528, 514) encoding and decoding module includes: an RS (528, 514) encoding module and an RS (528, 514) decoding module.

[0064] The RS (528,514) encoding module performs RS (528,514) encoding on the data after 256B / 257B encoding and bit width conversion. RS (528,514) encoding is performed in the finite field Galois field. A complete FEC code block contains 528 code elements, each code element consists of 10 binary bits, a total of 5280 bits. It contains 514 information code elements and 14 check code elements. The calculation of the check code element is realized by shift registers. For details, see Figure 6 . Where mi is a 10-bit bit vector. Bit0 of the first encoding block output from the previous stage corresponds to bit0 of mk-1, and bit256 of the last encoding block corresponds to bit9 of m0. Pi is the output check code, and each position is set to 0 before encoding. When the given information codeword is processed, the final output codeword ci is the information codeword mi plus the check codeword pi.

[0065] The RS (528, 514) decoding module performs RS (528, 514) decoding on the data after PN5280 descrambling. The error correction capability of RS (528, 514) is 7. As long as the number of error bits in a complete FEC code block during transmission does not exceed 7, the error can be located and corrected, and no error information needs to be fed back to the sender. After the decoding is completed, the receiving synchronization module will be fed back with an indication of whether the decoding is correct or not.

[0066] like Figure 7 As shown, as a preferred implementation, the PN5280 scrambling and descrambling module includes: a PN5280 scrambling module and a PN5280 descrambling module.

[0067] The PN5280 scrambling module scrambles the complete FEC code block after RS ​​(528, 514) encoding. The 256B / 257B encoding changes the header information and recombines the data, which affects the randomness of the data. In order to ensure that the data has enough jumps and the receiver can recover the clock information from the data, the data needs to be further scrambled. The scrambling is achieved through shift registers and XOR operations. The polynomial used is still G(x) = x 58 + x 39 + 1.

[0068] The PN5280 descrambling module descrambles the data received by the high-speed serial transceiver after the bit width conversion to restore the original complete FEC code block. The descrambling principle and structure are exactly the same as those of the scrambling.

[0069] As a preferred implementation, the 330b / 66b bit width conversion module includes: a 330b to 66b bit width conversion module and a 66b to 330b bit width conversion module.

[0070] The 330bto66b bit width conversion module writes the PN5280 scrambled data into the 330bto66b bit width conversion clock isolation FIFO. When the FIFO is full, it feeds back the prog_full signal to the front-end module to notify it to stop RS encoding. When the FIFO is not empty, it reads a 330-bit data every five transmit clock cycles, and selects different 66-bit data according to the clock beat counter to hand it over to the high-speed serial transceiver to complete the data transmission.

[0071] The 66b to 330b bit width conversion module combines the data received by the high-speed serial transceiver, and combines each received 5 valid 66-bit data into a 330-bit data and writes it into the clock isolation FIFO. The FIFO read side reads the data when the FIFO is not empty and performs the subsequent PN5280 descrambling.

[0072] like Figure 8 As shown, as a preferred implementation scheme, the receiving synchronization module completes the FEC code block synchronization of the received data according to the indication flag of whether the decoding is correct or not fed back by the RS (528, 514) decoding module. Specifically, the receiving synchronization module determines whether the current parallel data segmentation method is correct according to the indication flag of whether the decoding is correct or not output by the RS encoding and decoding module, and feeds back the data bit shift indication to the high-speed serial transceiver when the data segmentation method is incorrect, and the high-speed serial transceiver performs data bit shift according to the bit shift indication. The receiving synchronization control state machine includes five states: initialization state, candidate state, synchronization test state, bit shift state and receiving synchronization state. After valid received data is detected in the initialization state, the candidate state is entered. In the candidate state, the FEC code block decoding correct indication is attempted to be received, and the synchronization test state is entered after the decoding correct indication is received. If a decoding error indication is received, the error count value is increased by 1, and it is determined whether the error count value exceeds the threshold value. If it exceeds the threshold value, it means that the current data segmentation method is incorrect, and the bit shift state is entered; otherwise, it continues to stay in the candidate state. In the synchronous test state, continue to wait for the decoding indication. If a correct decoding indication is received, the correct count value is increased by 1 to determine whether the correct count value exceeds the threshold. If the threshold is exceeded, it means that the receiving synchronization is completed and enters the receiving synchronization state. Otherwise, continue to stay in the synchronous test state and continue the receiving synchronization test. If a decoding error indication is received, the correct count value is cleared, the error count value is increased by 1, and the candidate state is returned. In the bit shift state, the count value is cleared and the bit shift indication is fed back to the high-speed serial transceiver.

[0073] As a preferred implementation, the 256B / 257B decoding module performs 256B / 257B decoding on the data after RS ​​(528, 514) decoding and bit width conversion. 256B / 257B decoding is also divided into two categories. The first category is the case of pure data. According to bit256 being 1, it can be determined that the four code blocks are all data code blocks. The data is taken out according to the filling position of the data code block, and each data code block is assigned a synchronization header of 2'b01. The second category is the case of mixed data and control code blocks. According to bit256-252, the position of the first control code block can be determined. The key to decoding this type of situation is to recover the lower four bits of the transmission word type value discarded by the first control code block. The method used is that the upper four bits and the lower four bits of each 64B / 66B encoded transmission word type value have a unique corresponding relationship. The data received by the 256B / 257B decoding module is scrambled data. Therefore, the upper four bits of the transmission word type value are descrambled through the relationship with the adjacent data bits, and then the discarded 4-bit information is determined through the unique corresponding relationship between the upper four bits and the lower four bits of the transmission word type value to complete data recovery. After that, different synchronization headers can be assigned according to the type of each code block.

[0074] like Fig. 9 As shown, as a preferred implementation, the 64B / 66B decoding module includes: a decoding module and a descrambling module.

[0075] The decoding module first determines the transmission word type value in each 64B / 66B code block. If the transmission word type value is wrong, or the transmission word type value is correct but the transmission word data cannot correctly match the transmission word type, the notintable indication is output, and the subsequent data link layer word validity judgment and primitive detection module will identify the transmission word as an invalid transmission word. After that, the data decoding is completed according to the transmission word type value, and the K code indication flag is added to the control transmission word.

[0076] The descrambling module descrambles the data part after 256B / 257B decoding, and restores the original data after 64B / 66B encoding for subsequent 64B / 66B decoding. Descrambling is only performed on the data part.

[0077] As a preferred implementation scheme, the high-speed serial transceiver transmits the data after the 330b to 66b bit width conversion, and the receiving end receives the data before decoding as the data receiving interface. At the same time, the data shift operation is performed according to the bit shift signal fed back by the receiving synchronization module, and the receiving end synchronization is completed in cooperation with the receiving synchronization module.

[0078] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims

1. A 32G fiber channel forward error correction encoding and decoding device, characterized in that: Contains: 64B / 66B encoding module, 256B / 257B encoding module, 514b / 330b bit width conversion module, RS encoding and decoding module, PN5280 scrambling and descrambling module, 330b / 66b bit width conversion module, receiving synchronization module, 256B / 257B decoding module, 64B / 66B decoding module and high-speed serial transceiver; The 64B / 66B encoding module receives the data transmitted from the data link layer in the unit of FC transmission word, performs 64B / 66B encoding on the data, and then transmits it to the 256B / 257B encoding module. The 256B / 257B encoding module performs 256B / 257B encoding on the data encoded by the 64B / 66B encoding module, and then transmits it to the 514b / 330b bit width conversion module. The 514b / 330b bit width conversion module performs bit width conversion on the data encoded by the 256B / 257B encoding module, and then transmits it to the 514b / 330b bit width conversion module. The received FEC code block is input to the RS encoding and decoding module, and the RS encoding and decoding module performs RS decoding on the received FEC code block, and adds a check bit to form a complete FEC code block, and then inputs it to the PN5280 scrambling module. The PN5280 scrambling module is used to scramble the FEC code block after RS ​​encoding and transmit it to the 330b / 66b bit width conversion module. The 330b / 66b bit width conversion module performs bit width conversion on the data scrambled by the PN5280 scrambling module and transmits it to the high-speed serial transceiver to complete data transmission; The high-speed serial transceiver is used to receive data and transmit it to the 330b / 66b bit width conversion module. The high-speed serial transceiver performs a data bit shift operation according to the bit shift signal fed back by the receiving synchronization module to complete the receiving synchronization. The 330b / 66b bit width conversion module performs bit width conversion on the data received from the high-speed serial transceiver and inputs it to the PN5280 scrambling and descrambling module. The PN5280 scrambling and descrambling module descrambles the received data to realize the recovery of the original data of the FEC code block and inputs it to the RS encoding and decoding module. The RS encoding and decoding module performs RS decoding on the FEC code block received from the PN5280 scrambling and descrambling module, and according to the F The check information attached after the EC code block completes the recovery of limited errors in the transmission process and is input into the 514b / 330b bit width conversion module. The 514b / 330b bit width conversion module performs bit width conversion on the data decoded by the RS encoding and decoding module and transmits it to the 256B / 257B encoding module. The 256B / 257B decoding module completes the 256B / 257B decoding of the data, recovers the original 64B / 66B code block and inputs it into the 64B / 66B decoding module. The 64B / 66B decoding module completes the data descrambling and 64B / 66B decoding operations, and sends the data and related transmission word error indication information to the data link layer.

2. The 32G fiber channel forward error correction encoding and decoding device according to claim 1, characterized in that: The 64B / 66B encoding module includes an encoding module and a scrambling module; The encoding module is used to perform 64B / 66B encoding on the FC transmission word transmitted from the data link layer and append a 2-bit synchronization header; The scrambling module is used to scramble the code block data part after 64B / 66B encoding to increase the randomness of the data and ensure the consistency of the number of 0 and 1 during data transmission. The scrambling process does not scramble the synchronization header.

3. The 32G fiber channel forward error correction encoding and decoding device according to claim 2, characterized in that: The 256B / 257B encoding module is used to reassemble and perform 256B / 257B encoding on four code blocks after completing 64B / 66B encoding, and reserve data bit width for subsequent RS encoding to fill in check bits.

4. The 32G fiber channel forward error correction encoding and decoding device according to claim 3, characterized in that: The 514b / 330b bit width conversion module includes a 514b to 330b bit width conversion module and a 330b to 514b bit width conversion module; The 514bto330b bit width conversion module is used to perform bit width conversion on the code block after completing 256B / 257B encoding, and convert it into data with a data bit width of 330 bits, which is input to the subsequent RS encoding and decoding module for encoding; The 330bto514b bit width conversion module is used to perform bit width conversion on the data after RS ​​decoding, converting the data into data with a bit width of 514 bits and inputting it into the subsequent 256B / 257B decoding module for decoding.

5. The 32G fiber channel forward error correction encoding and decoding device according to claim 4, characterized in that: The RS encoding and decoding module includes an RS encoding module and an RS decoding module; The RS encoding module is used to perform RS encoding on the data after completing 256B / 257B encoding and 514b to 330b bit width conversion, and add 140-bit check bits to each FEC code block to form a complete FEC code block; The RS decoding module is used to perform RS decoding on the data after the bit width conversion from 66b to 330b, recover the limited errors in the transmission process according to the 140-bit check information attached to the FEC code block, and output an indication of whether the decoding is correct for each decoded FEC code block to complete the synchronization of the receiving end.

6. The 32G fiber channel forward error correction encoding and decoding device according to claim 5, characterized in that: The PN5280 scrambling and descrambling module includes a PN5280 scrambling module and a PN5280 descrambling module; The PN5280 scrambling module is used to scramble the complete FEC code block after RS ​​encoding to increase the randomness of the data inside the FEC code block and ensure the DC balance during data transmission; The PN5280 descrambling module is used to descramble the data after the bit width conversion from 66b to 330b to restore the original FEC code block.

7. The 32G fiber channel forward error correction encoding and decoding device according to claim 5, characterized in that: The 330b / 66b bit width conversion module includes a 330b to 66b bit width conversion module and a 66b to 330b bit width conversion module; The 330bto66b bit width conversion module is used to perform bit width conversion on the data after PN5280 scrambling, and convert the data into data with a data bit width of 66 bits and hand it over to the high-speed serial transceiver for data transmission; The 66bto330b bit width conversion module is used to perform bit width conversion on the data received by the high-speed serial transceiver, converting the data into data with a data bit width of 330 bits for subsequent PN5280 descrambling.

8. The 32G fiber channel forward error correction encoding and decoding device according to claim 5, characterized in that: The receiving synchronization module is used to complete the synchronization of the receiving end, and judge whether the current parallel data segmentation method is correct according to the indication mark of whether the decoding is correct or not output by the RS encoding and decoding module. When the data segmentation method is incorrect, the high-speed serial transceiver is fed back with a data bit shift indication, and the high-speed serial transceiver performs data bit shift according to the bit shift indication.

9. The 32G fiber channel forward error correction encoding and decoding device according to claim 1, characterized in that: The 256B / 257B decoding module is used to perform 256B / 257B decoding on the data after RS ​​decoding and 330b to 514b bit width conversion, decode the fourth bit of the transmission word type value of the first control code block discarded during the encoding process, complete data splitting, and restore the original 64B / 66B code block.

10. The 32G fiber channel forward error correction encoding and decoding device according to claim 1, characterized in that: The 64B / 66B decoding module includes a decoding module and a descrambling module; The decoding module is used to perform 64B / 66B decoding on the descrambled code blocks, restore the data to the form of FC transmission words, and feed back various errors that occur during the decoding process to the data link layer; The descrambling module is used to descramble the data after 256B / 257B decoding to restore the original data. The descrambling process does not descramble the synchronization header.

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