Display panel, display driving method, and display device

Abstract

This application belongs to the field of display driving technology, and particularly relates to a display panel, a display driving method, and a display device. The display panel includes N rows of scan lines, M columns of data lines, and a 2N-row × 2M-column pixel circuit; each pixel circuit includes a pixel unit and a control unit. When a first scan signal is output on the nth row of scan lines, the data signal on the mth column of data lines controls either the control unit at the (2m - 1)th column and the (2n - 1)th row or the control unit at the 2mth column and the (2n - 1)th row to conduct or conduct alternately in a time-sharing manner; when a second scan signal is output on the nth row of scan lines, the data signal on the mth column of data lines controls either the control unit at the (2m - 1)th column and the 2nth row or the control unit at the 2mth column and the 2nth row to conduct or conduct alternately in a time-sharing manner; in this application, under the display condition of the same resolution, the number of scan lines and the number of data lines are both reduced by at least half, which not only reduces the power consumption and cost of the panel, but also improves the refresh rate and aperture ratio.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display driving, and particularly relates to a display panel, a display driving method, and a display device. Background Art

[0002] In the current display panel, pixel units are arranged in a matrix, and each pixel unit requires a data line for providing a data signal and a scan line for controlling the pixel unit to turn on and off; with the continuous update and iteration of display technologies, high-resolution panels have gradually become the mainstream products in the market. High resolution means more data lines and scan lines, which continuously increases the RC Loading (resistance-capacitance load, abbreviated as capacitive load) of the display panel, resulting in the problem of high power consumption of the display panel.

[0003] It can be seen that how to reduce the power consumption of the display panel is an urgent problem to be solved currently. Summary of the Invention

[0004] The present application provides a display panel, a display driving method, and a display device, which solve the problem of high power consumption of the display panel. Under the display condition of the same resolution, the number of scan lines and the number of data lines in the present application are both reduced by at least half, which not only reduces the power consumption and cost of the panel, but also improves the refresh rate and aperture ratio.

[0005] In a first aspect, the present application provides a display panel, which includes: N rows of scan lines, M columns of data lines, and 2N rows × 2M columns of pixel circuits; each pixel circuit includes a pixel unit and a control unit, and the control unit is used to charge the pixel unit with the data signal on the data line when in a conducting state; the control unit includes a first control end, a second control end, an input end, and an output end; the first control ends of the control units in the (2n - 1)-th row and the first control ends of the control units in the 2n-th row are respectively connected to the n-th row of scan lines, and the second control ends of the control units in the (2m - 1)-th column, the input ends of the control units in the (2m - 1)-th column, the second control ends of the control units in the 2m-th column, and the input ends of the control units in the 2m-th column are all connected to the m-th column of data lines; the output end of each control unit is connected to the input end of the corresponding pixel unit; when the n-th row of scan lines outputs a first scan signal, the data signal on the m-th column of data lines controls any one of the control units in the (2m - 1)-th column and the (2n - 1)-th row and the control units in the 2m-th column and the (2n - 1)-th row to conduct or conduct alternately in a time-sharing manner; when the n-th row of scan lines outputs a second scan signal, the data signal on the m-th column of data lines controls any one of the control units in the (2m - 1)-th column and the 2n-th row and the control units in the 2m-th column and the 2n-th row to conduct or conduct alternately in a time-sharing manner; where n = [1,..., N], m = [1,..., M], and both N and M are positive integers greater than 1.

[0006] Optionally, the control unit includes: a first switching transistor, a control end of the first switching transistor is connected to the data line, and a first end of the first switching transistor is connected to the scanning line; a second switching transistor, a control end of the second switching transistor is connected to a second end of the first switching transistor, a first end of the second switching transistor is connected to the data line, and a second end of the second switching transistor is connected to the pixel unit; wherein, in the same row of pixel circuits, turn-on voltages of the first switching transistors of the control units in the (2m - 1)-th column and the (2m)-th column are opposite to each other, and in the same column of pixel circuits, turn-on voltages of the second switching transistors of the control units in the (2n - 1)-th row and the (2n)-th row are opposite to each other.

[0007] Optionally, the pixel unit includes a liquid crystal capacitor, and a pixel electrode of the liquid crystal capacitor is connected to an output end of the control unit.

[0008] Optionally, the pixel unit includes: a storage capacitor, a driving transistor, and a light-emitting diode, a first end of the storage capacitor is connected to an output end of the control unit, a second end of the storage capacitor is connected to a power supply terminal, a control end of the driving transistor is connected to the first end of the storage capacitor, a first end of the driving transistor is connected to the second end of the storage capacitor, an anode of the light-emitting diode is connected to a second end of the driving transistor, and a cathode of the light-emitting diode is grounded.

[0009] Optionally, pixel units in the (3i + 1)-th column are first color sub-pixels, pixel units in the (3i + 2)-th column are second color sub-pixels, and pixel units in the (3i + 3)-th column are third color sub-pixels; wherein, i = [0, 1, 2, …, I], when 2M is a multiple of 3 Otherwise denotes the result of rounding down.

[0010] Optionally, pixel units in the (3j + 1)-th row are first color sub-pixels, pixel units in the (3j + 2)-th row are second color sub-pixels, and pixel units in the (3j + 3)-th row are third color sub-pixels; wherein, j = [0, 1, 2, …, J], when 2N is a multiple of 3 Otherwise denotes the result of rounding down.

[0011] Optionally, during the on-time period of the n-th scan line of the current frame, a first scan signal and a second scan signal are alternately output on the n-th scan line, and when the first scan signal is output on the n-th scan line, a corresponding first data signal and a second data signal are alternately output on each column data line, and when the second scan signal is output on the n-th scan line, a corresponding first data signal and a second data signal are alternately output on each column data line; wherein, the polarities of the first scan signal and the second scan signal are opposite, and the polarities of the first data signal and the second data signal are opposite.

[0012] Optionally, during the on-time period of the n-th scan line of the current frame, a first scan signal is output on the n-th scan line, and when the first scan signal is output on the n-th scan line, a corresponding first data signal and a second data signal are alternately output on each column data line; wherein, the polarities of the first data signal and the second data signal are opposite.

[0013] Optionally, during the on-time period of the n-th scan line of the current frame, a first scan signal and a second scan signal are alternately output on the n-th scan line, and a corresponding first data signal is output on each column data line during the on-time period of the n-th scan line; wherein, the polarities of the first scan signal and the second scan signal are opposite.

[0014] Optionally, during the on-time period of the n-th scan line of the current frame, a first scan signal and a second scan signal are alternately output on the n-th scan line, and when the first scan signal is output on the n-th scan line, a corresponding first data signal is output on each column data line, and when the second scan signal is output on the n-th scan line, a corresponding second data signal is output on each column data line; wherein, the polarities of the first scan signal and the second scan signal are opposite, and the polarities of the first data signal and the second data signal are opposite.

[0015] In a second aspect, the present application provides a display driving method, the display driving method includes: obtaining a first target conduction polarity corresponding to the first control end of each control unit in the display panel and a second target conduction polarity corresponding to the second control end of each control unit; generating a corresponding scan signal on each row scan line and a corresponding data signal on each column data line according to all the first target conduction polarities, all the second target conduction polarities and the display picture of the current frame, so that when the first scan signal is output on the n-th scan line, the data signal on the m-th column data line controls any one of the control units at the (2m - 1)-th column and the (2n - 1)-th row and the control unit at the 2m-th column and the (2n - 1)-th row to conduct or conduct alternately in a time-sharing manner; when the second scan signal is output on the n-th scan line, the data signal on the m-th column data line controls any one of the control units at the (2m - 1)-th column and the 2n-th row and the control unit at the 2m-th column and the 2n-th row to conduct or conduct alternately in a time-sharing manner.

[0016] In a third aspect, the present application provides a display device, which includes: a gate driving circuit for outputting a scanning signal; a source driving circuit for outputting a data signal; and a display panel, wherein the scanning lines of the display panel are connected to the gate driving circuit, and the data lines of the display panel are connected to the source driving circuit.

[0017] The technical solution provided by the present application has at least the following beneficial effects:

[0018] 1. In the present application, adjacent two rows of pixel circuits share one scanning line, and adjacent two columns of pixel circuits share the same data line, and the pixel circuits connected to the same scanning line and the same data line are controlled by the data line and the scanning line together so as not to be turned on simultaneously. Under the display condition of the same resolution, the number of scanning lines and the number of data lines are both reduced by at least half, so that the RC Loading on the scanning lines and data lines in the panel is also reduced accordingly, thereby greatly reducing the power consumption of the display panel.

[0019] 2. In the present application, by reducing the number of scanning lines and the number of data lines by half at the same time, not only the manufacturing cost of the display panel is reduced, but also the refresh rate and aperture ratio of the panel are improved, thereby enhancing the market competitiveness of the product.

[0020] 3. Since the RC loading value of the display panel is proportional to the noise value, in the present application, while reducing the panel RC Loading, the panel noise can also be reduced, and the display accuracy can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0022] Figure 1 Shown is a schematic structural diagram of a display panel provided by an embodiment of the present application.

[0023] Figure 2 Shown is a schematic circuit diagram of a first pixel circuit provided by an embodiment of the present application.

[0024] Figure 3 Shown is a schematic signal output diagram provided by an embodiment of the present application.

[0025] Figure 4 Shown is a schematic circuit diagram of a second pixel circuit provided by an embodiment of the present application.

[0026] Figure 5The figure shows a schematic flowchart of a display driving method provided by an embodiment of the present application.

[0027] Figure 6 The figure shows a first display screen and a waveform schematic diagram provided by an embodiment of the present application.

[0028] Figure 7 The figure shows a second display screen and a waveform schematic diagram provided by an embodiment of the present application.

[0029] Figure 8 The figure shows a third display screen and a waveform schematic diagram provided by an embodiment of the present application.

[0030] Figure 9 The figure shows a fourth display screen and a waveform schematic diagram provided by an embodiment of the present application.

[0031] Figure 10 The figure shows a schematic diagram of a pixel structure of a display panel provided by an embodiment of the present application.

[0032] Description of reference numerals:

[0033] 100, display panel; 110, scan line; 120, data line; 130, pixel circuit; 131, control unit; 132, pixel unit;

[0034] T0, driving transistor; T1, first switching transistor; T2, second switching transistor; T3, third switching transistor; Cc, storage capacitor; Cs, pixel capacitor; Ct, energy storage capacitor; OLED, light emitting diode. Detailed implementation manners

[0035] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art.

[0036] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be used. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0037] The present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present application, and should not be construed as a limitation to the present application.

[0038] Figure 1 The following is a schematic structural diagram of a display panel provided by an embodiment of the present application; as Figure 1 shown, the display panel 100 includes: N row scan lines 110, M column data lines 120, and pixel circuits 130 arranged in an array; wherein, the number of columns of the pixel circuits 130 is 2M columns, and the number of rows is 2N rows; that is to say, the number of columns and rows of the pixel circuits 130 in the display panel 100 are 2 times that of the data lines 120 and the scan lines 110 respectively. Among them, Figure 1 the scan lines 110 and the data lines 120 in cross but are not connected, Figure 1 G1, G2, and GN in respectively represent the first row scan line, the second row scan line, and the Nth row scan line, and S1 and SM respectively represent the first column data line and the Mth column data line.

[0039] In one embodiment, each pixel circuit 130 includes a pixel unit 132 and a control unit 131. The control unit 131 is configured to input the data signal on the data line 120 into the pixel unit 132 when in the conducting state, so as to charge the pixel unit 132 through the data signal on the data line 120; on the contrary, when the control unit 131 is in the off state (i.e., non-conducting state), the data signal on the data line 120 cannot be input into the pixel unit 132, so as not to charge the pixel unit 132; it should be noted that the display panel 100 can be a liquid crystal display (LCD, Liquid Crystal Display), or an OLED (Organic Light-Emitting Diode) display; when the display panel 100 is a liquid crystal display, the pixel unit 132 includes liquid crystal molecules; when the display panel 100 is an OLED display, the pixel unit 132 includes light-emitting diodes.

[0040] As Figure 1As shown, the control unit 131 includes a first control terminal K1, a second control terminal K2, an input terminal Vi, and an output terminal Vo; the first control terminals K1 of the control units 131 in the (2n - 1)-th row and the first control terminals K1 of the control units 131 in the 2n-th row are respectively connected to the n-th row scanning line 110; the second control terminals K2 of the control units 131 in the (2m - 1)-th column, the input terminals Vi of the control units 131 in the (2m - 1)-th column, the second control terminals K2 of the control units 131 in the 2m-th column, and the input terminals Vi of the control units 131 in the 2m-th column are all connected to the m-th column data line; the output terminal Vo of each control unit 131 is connected to the input terminal of the corresponding pixel unit 132.

[0041] It should be noted that both n and m in this embodiment are variables, while N and M are constants. The value range of the variable n is from 1 to N, and the value range of the variable m is from 1 to M. Both N and M are positive integers greater than 1. Additionally, in this embodiment, the control units 131 in adjacent two rows are both connected to the corresponding same scanning line 110. Adjacent two rows refer to the (2n - 1)-th row and the 2n-th row, and the corresponding same scanning line 110 refers to the n-th row scanning line 110. The control units 131 in adjacent two columns in this embodiment are both connected to the corresponding same data line 120. Adjacent two columns refer to the (2m - 1)-th column and the 2m-th column, and the corresponding same data line 120 refers to the m-th column data line 120.

[0042] For example: when n = 1, the first control terminals K1 of the control units 131 in the first row and the second row are both connected to the first row scanning line 110; when n = 2, the first control terminals K1 of the control units 131 in the third row and the fourth row are both connected to the second row scanning line 110; and so on. When n = N, the first control terminals K1 of the control units 131 in the (2N - 1)-th row and the 2N-th row are both connected to the N-th row scanning line 110.

[0043] When m = 1, the second control terminals K2 of all the control units 131 in the first column and the second control terminals K2 of all the control units in the second column are both connected to the first column data line 120, and the input terminals Vi of all the control units 131 in the first column and the input terminals Vi of all the control units 131 in the second column are also both connected to the first column data line 120; when m = 2, the second control terminals K2 of all the control units 131 in the third column and the second control terminals K2 of all the control units in the fourth column are both connected to the second column data line 120, and the input terminals Vi of all the control units 131 in the third column and the input terminals Vi of all the control units 131 in the fourth column are also both connected to the second column data line 120; when m = M, the second control terminals K2 of all the control units 131 in the (2M - 1)th column and the second control terminals K2 of all the control units in the 2Mth column are both connected to the Mth column data line 120, and the input terminals Vi of all the control units 131 in the (2M - 1)th column and the input terminals Vi of all the control units 131 in the 2Mth column are also both connected to the Mth column data line 120.

[0044] In the same row of pixel circuits, the on - off states of the control unit 131 in the (2m - 1)th column and the control unit 131 in the 2mth column at the same moment are opposite; in the same column of pixel circuits, the on - off states of the control unit in the (2n - 1)th row and the control unit in the 2nth row at the same moment are opposite, so that: when the first scan signal is output on the nth row scan line 110, the data signal on the mth column data line 120 controls either the control unit 131 in the (2m - 1)th column and the (2n - 1)th row or the control unit 131 in the 2mth column and the (2n - 1)th row to conduct or conduct alternately in a time - sharing manner; when the second scan signal is output on the nth row scan line, the data signal on the mth column data line controls either the control unit in the (2m - 1)th column and the 2nth row or the control unit in the 2mth column and the 2nth row to conduct or conduct alternately in a time - sharing manner.

[0045] It should be noted that the on / off state of the control unit 131 in this embodiment is controlled by the scanning line 110 and the data line 120 simultaneously through the first control terminal K1 and the second control terminal K2. Moreover, in the same row of pixel circuits, adjacent two-column control units are controlled by the same column of data lines, and in the same column of pixel circuits, adjacent two-row control units are controlled by the same row of scanning lines. Therefore, in the case where the first scanning signal is output on the same row of scanning lines, one of the adjacent two-column control units of one row of pixel circuits in the adjacent two rows of pixel circuits is conducted arbitrarily or alternately in a time-sharing manner through the data signal on the data line. In the case where the second scanning signal is output on the same row of scanning lines, one of the adjacent two-column control units of the other row of pixel circuits in the adjacent two rows of pixel circuits is also conducted arbitrarily or alternately in a time-sharing manner through the data signal on the data line, thereby avoiding the situation where two adjacent control units are charged simultaneously. Among them, the time-sharing alternate conduction includes that one control unit 131 is first conducted for a first duration and then the other control unit 131 is conducted for a second duration. The polarities of the first scanning signal and the second scanning signal are opposite. For example, if the first scanning signal is at a high level, the second scanning signal is at a low level, or if the first scanning signal is at a low level, the second scanning signal is at a high level.

[0046] In summary, the display panel provided by this embodiment has at least the following beneficial effects:

[0047] 1. In this application, adjacent two rows of pixel circuits share one scanning line, and adjacent two columns of pixel circuits share the same data line. The pixel circuits connected to the same scanning line and the same data line are not opened simultaneously by jointly controlling the data line and the scanning line. Under the display condition of the same resolution, the number of scanning lines and the number of data lines are both reduced by at least half, so that the RC Loading on the scanning lines and data lines in the panel is also reduced accordingly, thereby greatly reducing the power consumption of the display panel.

[0048] 2. By reducing the number of scanning lines and the number of data lines by half at the same time, this application not only reduces the manufacturing cost of the display panel, but also improves the refresh rate and aperture ratio of the panel, thereby enhancing the market competitiveness of the product.

[0049] 3. Since the RC loading value of the display panel is proportional to the noise value, this application can reduce the panel noise and improve the display accuracy while reducing the panel RCLoading.

[0050] Figure 2 The following shows the circuit schematic diagram of the first pixel circuit provided by the embodiment of the present application; as Figure 2As shown in the figure, the control unit 131 includes: a first switching transistor T1 and a second switching transistor T2; the control terminal of the first switching transistor T1 is connected to the data line 120, and the first terminal of the first switching transistor T1 is connected to the scanning line 110; the control terminal of the second switching transistor T2 is connected to the second terminal of the first switching transistor T1, the first terminal of the second switching transistor T2 is connected to the data line 120, and the second terminal of the second switching transistor T2 is connected to the pixel unit 132; wherein, in the control unit of the (2m - 1)-th column in the same row of pixel circuits, the turn-on voltage of the first switching transistor T1 of the control unit of the (2m - 1)-th column is opposite to that of the first switching transistor T1 of the control unit of the 2m-th column, and in the control unit of the (2n - 1)-th row in the same column of pixel circuits, the turn-on voltage of the second switching transistor T2 of the control unit of the (2n - 1)-th row is opposite to that of the second switching transistor T2 of the control unit of the 2n-th row.

[0051] It should be noted that the fact that the turn-on voltage of the first switching transistor T1 of the control unit of the (2m - 1)-th column in the same row of pixel circuits is opposite to that of the first switching transistor T1 of the control unit of the 2m-th column means that the types of the first switching transistors T1 between two control units 131 in the same row and connected to the same data line are different, that is, the first switching transistor T1 of one control unit 131 is a P-type MOS transistor, and the first switching transistor T1 of the other control unit 131 is an N-type MOS transistor; for example: the first switching transistor of the control unit in the first row and the first column is an NMOS transistor, and the first switching transistor of the control unit in the first row and the second column is a PMOS transistor; when the first switching transistor of the control unit in the second row and the first column is an NMOS transistor, the first switching transistor of the control unit in the second row and the second column is a PMOS transistor.

[0052] The fact that the turn-on voltage of the second switching transistor T2 of the control unit of the (2n - 1)-th row in the same column of pixel circuits is opposite to that of the second switching transistor T2 of the control unit of the 2n-th row means that the types of the second switching transistors T2 between two control units 131 in the same column and connected to the same scanning line are different, that is, the second switching transistor T2 of one control unit 131 is a P-type MOS transistor, and the second switching transistor T2 of the other control unit 131 is an N-type MOS transistor; for example: when the second switching transistor of the control unit in the first column and the first row is an NMOS transistor, the second switching transistor of the control unit in the first column and the second row is a PMOS transistor; when the second switching transistor of the control unit in the second column and the first row is an NMOS transistor, the second switching transistor of the control unit in the second column and the second row is a PMOS transistor.

[0053] In addition, in this embodiment, the 2n - 1 row control units in the (2m - 1)-th column, the 2n - 1 row control units in the 2m-th column, the 2n row control units in the (2m - 1)-th column, and the 2n row control units in the 2m-th column are regarded as four adjacent control units; among these four adjacent control units, the type of the first switching transistor in the 2n - 1 row control unit in the (2m - 1)-th column is exactly opposite to the type of the first switching transistor in the 2n - 1 row control unit in the 2m-th column, the type of the first switching transistor in the 2n row control unit in the (2m - 1)-th column is exactly opposite to the type of the first switching transistor in the 2n row control unit in the 2m-th column, the type of the second switching transistor in the 2n - 1 row control unit in the (2m - 1)-th column is exactly opposite to the type of the second switching transistor in the 2n row control unit in the (2m - 1)-th column, and the type of the second switching transistor in the 2n - 1 row control unit in the 2m-th column is exactly opposite to the type of the second switching transistor in the 2n row control unit in the 2m-th column.

[0054] It can be seen from this that among the four adjacent control units, there are many different combination ways of the first switching transistor and the second switching transistor. Here, one of the combination ways is used for exemplary illustration: taking Figure 2 the first switching transistor in the 2n - 1 row of the (2m - 1)-th column in [ ] as NMOS and the second switching transistor as PMOS, the first switching transistor in the 2n - 1 row of the 2m-th column as PMOS and the second switching transistor as NMOS, the first switching transistor in the 2n row of the (2m - 1)-th column as NMOS and the second switching transistor as PMOS, and the first switching transistor in the 2n row of the 2m-th column as PMOS and the second switching transistor as PMOS as an example, combined with Figure 3 the signal output schematic diagrams of Gn and Sm in [ ], the working process of these four adjacent control units is as follows:

[0055] (1) During the period when the n-th row scan line Gn outputs a high level, when the data signal output by the m-th column data line Sm is a high level, the first switching transistor in the 2n - 1 row of the (2m - 1)-th column is turned on, and the second switching transistor is turned on through the high level on Gn. At this time, the 2n - 1 row control unit in the (2m - 1)-th column is in a conducting state, so that the data signal output by the m-th column data line Sm charges the 2n - 1 row pixel units in the (2m - 1)-th column; when the data signal output by the m-th column data line Sm is a low level, the first switching transistor in the 2n - 1 row of the 2m-th column is turned on, and the second switching transistor in the 2n - 1 row of the 2m-th column is turned on through the high level on Gn. At this time, the 2n - 1 row control unit in the 2m-th column is in a conducting state, so that the data signal output by the m-th column data line Sm charges the 2n - 1 row pixel units in the 2m-th column.

[0056] (2) Conversely, during the period when the n-th row scanning line Gn outputs a low level, when the data signal output by the m-th column data line Sm is at a high level, the first switching transistor in the 2n-th row of the 2m - 1-th column is turned on, and the second switching transistor is turned on by the low level on Gn. At this time, the control unit in the 2n-th row of the 2m - 1-th column is in a conducting state, so that the data signal output by the m-th column data line Sm charges the pixel unit in the 2n-th row of the 2m - 1-th column; when the data signal output by the m-th column data line Sm is at a low level, the first switching transistor in the 2n-th row of the 2m-th column is turned on, and the second switching transistor in the 2n-th row of the 2m-th column is turned on by the low level on Gn. At this time, the control unit in the 2n-th row of the 2m-th column is in a conducting state, so that the data signal output by the m-th column data line Sm charges the pixel unit in the 2n-th row of the 2m-th column.

[0057] It can be seen from this that the switching states of the first switching transistor T1 and the second switching transistor T2 affect the on-off state of the control unit 131. That is, when both the first switching transistor T1 and the second switching transistor T2 are turned on, the control unit 131 is in a conducting state; when at least one of the first switching transistor T1 and the second switching transistor T2 is turned off, the control unit 131 is in a disconnected state.

[0058] In this embodiment, by setting different types of first switching transistors between two control units connected to the same data line in the same row pixel circuit, and setting different types of second switching transistors between two control units connected to the same scanning line in the same column pixel circuit, it is possible to control one of the adjacent four control units to be in a conducting state at the same time under the data signal and the scanning signal, avoiding the problem of pixel mischarging.

[0059] In addition, it should be noted that currently, for the switching transistor formed by a-si (amorphous silicon), its conduction (turn-on) voltage can be about 0.2V; for the lowest gray-scale display, the data voltage given by the data line 120 is generally not 0V, but about 0.3V. Therefore, for the lowest gray-scale display, the first switching transistor T1 can also be turned on, and the scanning line 110 gives a voltage of about 20V, so that the first switching transistor T1 enters the saturation region, and the voltage of the scanning line 110 is applied to the gate of the second switching transistor T2 through the first switching transistor T1 to control the second switching transistor T2 to conduct.

[0060] In addition, generally, the voltage of the previous gray scale of the lowest gray scale display is 0.5V, and other higher gray scale voltages are sufficient to turn on the first switching transistor T1, and with the voltage given by the scanning line 110, the first switching transistor T1 can work in the saturation region. Therefore, when no data voltage is given, the voltage on the data line 120 can be maintained at 0V.

[0061] In an embodiment of the present application, as Figure 2As shown, the pixel unit 132 includes: a storage capacitor Cc, a driving transistor T0, and a light-emitting diode OLED. The first end of the storage capacitor Cc is connected to the output terminal Vo of the control unit 131, and the second end of the storage capacitor Cc is connected to the power supply terminal VDD. The control terminal of the driving transistor T0 is connected to the first end of the storage capacitor Cc, and the first end of the driving transistor T0 is connected to the second end of the storage capacitor Cc. The anode of the light-emitting diode OLED is connected to the second end of the driving transistor T0, and the cathode of the light-emitting diode OLED is grounded to VSS.

[0062] In this embodiment, when the control unit 131 is in the conducting state, the storage capacitor Cc is charged through the data signal on the data line 120. Under the action of the driving voltage output by the power supply terminal, the driving transistor T0 outputs a corresponding driving current to drive the light-emitting diode OLED to emit light.

[0063] Figure 4 The following is a schematic circuit diagram of the second pixel circuit provided by the embodiment of the present application. As Figure 4 shown, the pixel unit 132 includes a liquid crystal capacitor Cs. The pixel electrode of the liquid crystal capacitor Cs is connected to the output terminal Vo of the control unit 131. Among them, the liquid crystal capacitor Cs generally includes a pixel electrode, a common electrode, and liquid crystal molecules between the pixel electrode and the common electrode. By applying data signals of different magnitudes on the pixel electrode, the liquid crystal molecules are rotated to different angles to realize the brightness adjustment of the pixel unit 132.

[0064] In this embodiment, the pixel unit 132 further includes a storage capacitor Ct. The pixel electrode of the storage capacitor Ct is connected to the output terminal Vo of the control unit 131, and is used to realize the holding of the charging voltage.

[0065] Figure 5 The following is a schematic flow diagram of a display driving method provided by the embodiment of the present application. As Figure 5 shown, applied to the display panel of the above embodiment, the display driving method specifically includes the following steps:

[0066] Step S100, obtain the first target conduction polarity corresponding to the first control terminal of each control unit in the display panel and the second target conduction polarity corresponding to the second control terminal of each control unit.

[0067] In this embodiment, the first target conduction polarity represents the voltage polarity for turning on the second switching transistor, and the second target conduction polarity represents the voltage polarity for turning on the first switching transistor. If the second switching transistor is a PMOS transistor, the corresponding first target conduction polarity is a negative polarity. If the first switching transistor is an NMOS transistor, the corresponding second target conduction polarity is a positive polarity. The first target conduction polarity corresponding to the first control terminal and the second target conduction polarity corresponding to the second control terminal can be obtained through the transistor types of the first switching transistor and the second switching transistor in each control unit.

[0068] Step S200: Generate the scanning signals corresponding to each row of scanning lines and the data signals corresponding to each column of data lines according to all the first target conduction polarities, all the second target conduction polarities, and the display screen of the current frame, so that when the first scanning signal is output on the nth row of scanning lines, the data signal on the mth column of data lines controls either the control unit at the (2m - 1)th column and the (2n - 1)th row or the control unit at the 2mth column and the (2n - 1)th row to conduct or conduct alternately in a time-sharing manner; when the second scanning signal is output on the nth row of scanning lines, the data signal on the mth column of data lines controls either the control unit at the (2m - 1)th column and the 2nth row or the control unit at the 2mth column and the 2nth row to conduct or conduct alternately in a time-sharing manner.

[0069] In this embodiment, the display screen of the current frame can include various situations. For example, all pixel units are fully lit, half of the pixel units in adjacent two rows are lit, half of the pixel units in adjacent two columns are lit, and half of the adjacent four pixels are lit in a cross pattern. Here, this embodiment takes N = 1 and M = 3 as an example to illustrate multiple display screens:

[0070] (1) Case 1: When the display screen of the current frame is the case where all pixel units are fully lit: During the on-time period of the nth row of scanning lines in the current frame, the first scanning signal and the second scanning signal are alternately output on the nth row of scanning lines. And when the first scanning signal is output on the nth row of scanning lines, the first data signal and the second data signal corresponding to each column of data lines are alternately output. When the second scanning signal is output on the nth row of scanning lines, the first data signal and the second data signal corresponding to each column of data lines are alternately output. The waveforms of G1 and S1 are as shown in Figure 6 Figure 6a, and the fully lit display screen is as shown in Figure 6 Figure 6b; among them, the waveforms of S2 and S3 are similar to that of S1, and will not be elaborated here.

[0071] (2) Case 2: When the display screen of the current frame is such that adjacent two rows of pixel units are half-bright: During the on-time period of the nth row scan line in the current frame, a first scan signal is output on the nth row scan line, and when the first scan signal is output on the nth row scan line, the corresponding first data signal and second data signal are alternately output on each column data line; wherein, the first scan signal of the current frame can be a high level or a low level, and the polarity of the first scan signal is determined according to the conduction polarity of the second switching transistor; The waveforms output by G1 and S1 are as shown in Figure 7 Figure 7a in, and the display screen where adjacent two rows of pixel units are half-bright is as shown in Figure 7 Figure 7b in; In addition, in the display screen of the next frame, adjacent two rows of pixel units are half-bright symmetrically on the other half; In this case, by outputting different scan signals on the scan lines in the current frame and the next frame, it can be realized that only the odd-row pixel units are charged in the current frame, and only the even-row pixel units are charged in the next frame. Based on the full-bright display screen in Case 1, the power consumption can be further reduced by half or the refresh rate can be doubled; In addition, the interlaced display of adjacent two frames can also prevent picture crosstalk.

[0072] (3) Case 3: When the display screen of the current frame is such that adjacent two columns of pixel units are half-bright: During the on-time period of the nth row scan line in the current frame, the first scan signal and the second scan signal are alternately output on the nth row scan line, and the corresponding first data signal is output on each column data line during the on-time period of the nth row scan line; wherein, the polarities of the first scan signal and the second scan signal are opposite, and the first data signal can be a high level or a low level, and the polarity of the first data signal is determined according to the conduction polarity of the first switching transistor; The waveforms output by G1 and S1 are as shown in Figure 8 Figure 8a in, and the display screen where adjacent two columns of pixel units are half-bright is as shown in Figure 8 Figure 8b in; In addition, in the display screen of the next frame, adjacent two columns of pixel units are half-bright symmetrically on the other half; In this case, while the power consumption can be reduced by half, all data lines can be charged simultaneously to save the scan time, and the interlaced display of the upper and lower frames can prevent picture crosstalk.

[0073] (4) Case 4: When the display screen of the current frame is such that adjacent four pixels are half-bright in a cross pattern: During the on-time period of the nth row scan line in the current frame, the first scan signal and the second scan signal are alternately output on the nth row scan line, and the corresponding first data signal is output on each column data line when the first scan signal is output on the nth row scan line, and the corresponding second data signal is output on each column data line when the second scan signal is output on the nth row scan line; wherein, the polarities of the first scan signal and the second scan signal are opposite, and the polarities of the first data signal and the second data signal are opposite. The waveforms output by G1 and S1 are as shown in Figure 9As shown in 9a, the display screen where the adjacent four pixel units in the current frame are half-bright and cross-lit is as Figure 9 shown in 9b; in addition, in the display screen of the next frame, the other half where the adjacent four pixel units are symmetrically cross-lit; in this case, while the power consumption can be reduced by half, all data lines can be charged simultaneously to save the scanning time, and the interlaced display of the upper and lower frames can prevent picture crosstalk.

[0074] In an embodiment of the present application, the pixel units in the (3i + 1)-th column are the first color sub-pixels, the pixel units in the (3i + 2)-th column are the second color sub-pixels, and the pixel units in the (3i + 3)-th column are the third color sub-pixels; where i = [0, 1, 2, …, I], when 2M is a multiple of 3 otherwise denotes the result of rounding down.

[0075] It should be noted that when i = 0, the pixel units in the 1st column are the first color sub-pixels, the pixel units in the 2nd column are the second color sub-pixels, and the pixel units in the 3rd column are the third color sub-pixels, and so on. The first color sub-pixels, the second color sub-pixels, and the third color sub-pixels are arranged at column intervals; the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels can be red sub-pixels, green sub-pixels, and blue sub-pixels respectively; as Figures 6 - 9 shown, the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels can also be blue sub-pixels, green sub-pixels, and red sub-pixels respectively; in addition, the result of rounding down represents taking the integer part of 2M divided by 3. For example, when M = 7, then

[0076] In an embodiment of the present application, the pixel units in the (3j + 1)-th row are the first color sub-pixels, the pixel units in the (3j + 2)-th row are the second color sub-pixels, and the pixel units in the (3j + 3)-th row are the third color sub-pixels; where j = [0, 1, 2, …, J], when 2N is a multiple of 3 otherwise denotes the result of rounding down; it should be noted that when j = 0, all the pixel units in the 1st row are the first color sub-pixels, all the pixel units in the 2nd row are the second color sub-pixels, and all the pixel units in the 3rd row are the third color sub-pixels, and so on. The first color sub-pixels, the second color sub-pixels, and the third color sub-pixels are arranged at row intervals; the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels can be red sub-pixels, green sub-pixels, and blue sub-pixels respectively; in addition, the result of rounding down represents taking the integer part of (2N - 1) divided by 3. For example, when N = 6, then

[0077] For example: As Figure 10 shown, in this embodiment, taking N = 3 and M = 2 as an example, each row of pixel units represents a red sub-pixel, a green sub-pixel, and a blue sub-pixel in sequence; Figure 10 R1, G1, and B1 in [[ ]] respectively represent the red sub-pixel unit, the green sub-pixel unit, and the blue sub-pixel unit in the first column. Similar explanations apply to other R2, G3, B4, etc., and will not be elaborated here.

[0078] In this application, the same scan line and the same data line can simultaneously control the charging of adjacent four pixel units, so that the number of scan lines and the number of data lines can be reduced by at least half, greatly reducing the RCLoading in the display panel and solving the problem of high power consumption of the display panel; in addition, combined with the driving method of lighting half of the pixel units in one frame and lighting the other half of the pixel units in the next frame, the power consumption of the display panel can be further reduced and the refresh rate of the display panel can be further increased. The panel driving method provided in this embodiment can be applied to liquid crystal displays and OLED displays, improving the market competitiveness of the product.

[0079] In one embodiment, this application provides a display device, which includes: a gate driving circuit, a source driving circuit, and the display panel shown in the above embodiment; the gate driving circuit is used to output a scan signal; the source driving circuit is used to output a data signal; the scan lines of the display panel are connected to the gate driving circuit, and the data lines of the display panel are connected to the source driving circuit.

[0080] In addition, terms such as "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality" means two or more, unless otherwise specifically defined.

[0081] In the description of this specification, the description with reference to terms such as "some embodiments", "exemplarily", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0082] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and the specification of the present application shall fall within the scope covered by the patent of the present application.

Claims

1. A display panel, characterized in that, The display panel includes: N row scanning lines, M column data lines, and a 2N-row × 2M-column pixel circuit; each pixel circuit includes a pixel unit and a control unit, and the control unit is used to charge the pixel unit with a data signal on the data line when in a conducting state; The control unit includes a first control terminal, a second control terminal, an input terminal, and an output terminal; the first control terminals of the control units in the (2n - 1)-th row are respectively connected to the n-th row scanning line, and the second control terminals, the input terminals of the control units in the (2m - 1)-th column, the second control terminals, and the input terminals of the control units in the 2m-th column are all connected to the m-th column data line; the output terminal of each control unit is connected to the input terminal of the corresponding pixel unit; When the n-th row scanning line outputs a first scanning signal, the data signal on the m-th column data line controls either the control unit in the (2m - 1)-th column and the (2n - 1)-th row or the control unit in the 2m-th column and the (2n - 1)-th row to conduct or conduct alternately in a time-sharing manner; When the n-th row scanning line outputs a second scanning signal, the data signal on the m-th column data line controls either the control unit in the (2m - 1)-th column and the 2n-th row or the control unit in the 2m-th column and the 2n-th row to conduct or conduct alternately in a time-sharing manner; where n = [1,..., N], m = [1,..., M], and both N and M are positive integers greater than 1; Wherein, the control unit includes: A first switching transistor, the control terminal of the first switching transistor is connected to the data line, and the first terminal of the first switching transistor is connected to the scanning line; A second switching transistor, the control terminal of the second switching transistor is connected to the second terminal of the first switching transistor, the first terminal of the second switching transistor is connected to the data line, and the second terminal of the second switching transistor is connected to the pixel unit; Wherein, the turn-on voltages of the first switching transistors of the control units in the (2m - 1)-th column in the same row of pixel circuits are opposite to those of the first switching transistors of the control units in the 2m-th column, and the turn-on voltages of the second switching transistors of the control units in the (2n - 1)-th row in the same column of pixel circuits are opposite to those of the second switching transistors of the control units in the 2n-th row.

2. The display panel according to claim 1, wherein The pixel unit includes a liquid crystal capacitor, and the pixel electrode of the liquid crystal capacitor is connected to the output terminal of the control unit; Or, the pixel unit includes: a storage capacitor, a driving transistor, and a light-emitting diode, the first terminal of the storage capacitor is connected to the output terminal of the control unit, the second terminal of the storage capacitor is connected to a power supply terminal, the control terminal of the driving transistor is connected to the first terminal of the storage capacitor, the first terminal of the driving transistor is connected to the second terminal of the storage capacitor, the anode of the light-emitting diode is connected to the second terminal of the driving transistor, and the cathode of the light-emitting diode is grounded.

3. The display panel according to claim 1, wherein The pixel units in the (3i + 1)-th column are first color sub-pixels, the pixel units in the (3i + 2)-th column are second color sub-pixels, and the pixel units in the (3i + 3)-th column are third color sub-pixels; where, , when 2M is a multiple of 3, I = -1, otherwise I = denotes the result of rounding down; Or, the pixel units in the (3j + 1)-th row are first color sub-pixels, the pixel units in the (3j + 2)-th row are second color sub-pixels, and the pixel units in the (3j + 3)-th row are third color sub-pixels; where when 2N is a multiple of 3 = -1, otherwise = , denotes the result of taking the floor of.

4. The display panel according to claim 1, wherein During the on-time period of the n-th scan line in the current frame, a first scan signal and a second scan signal are alternately output on the n-th scan line, and when the first scan signal is output on the n-th scan line, a corresponding first data signal and a second data signal are alternately output on each column data line, and when the second scan signal is output on the n-th scan line, a corresponding first data signal and a second data signal are alternately output on each column data line; wherein, the polarities of the first scan signal and the second scan signal are opposite, and the polarities of the first data signal and the second data signal are opposite.

5. The display panel according to claim 1, wherein During the on-time period of the n-th scan line in the current frame, a first scan signal is output on the n-th scan line, and when the first scan signal is output on the n-th scan line, a corresponding first data signal and a second data signal are alternately output on each column data line; wherein, the polarities of the first data signal and the second data signal are opposite.

6. The display panel according to claim 1, wherein During the on-time period of the n-th scan line in the current frame, a first scan signal and a second scan signal are alternately output on the n-th scan line, and a corresponding first data signal is output on each column data line during the on-time period of the n-th scan line; wherein, the polarities of the first scan signal and the second scan signal are opposite.

7. The display panel according to claim 1, wherein During the on-time period of the n-th scan line in the current frame, a first scan signal and a second scan signal are alternately output on the n-th scan line, and a corresponding first data signal is output on each column data line when the first scan signal is output on the n-th scan line, and a corresponding second data signal is output on each column data line when the second scan signal is output on the n-th scan line; wherein, the polarities of the first scan signal and the second scan signal are opposite, and the polarities of the first data signal and the second data signal are opposite.

8. A display driving method, characterized in that, Applied to the display panel according to any one of claims 1-7, the display driving method includes: Obtaining a first target conduction polarity corresponding to the first control terminal of each control unit in the display panel and a second target conduction polarity corresponding to the second control terminal of each control unit; Generating corresponding scan signals on each row scan line and corresponding data signals on each column data line according to all the first target conduction polarities, all the second target conduction polarities and the display picture of the current frame, so that when the first scan signal is output on the n-th scan line, the data signal on the m-th column data line controls any one of the control units at the (2m-1)-th column and the (2n-1)-th row and the control unit at the 2m-th column and the (2n-1)-th row to conduct or conduct alternately in a time-sharing manner; when the second scan signal is output on the n-th scan line, the data signal on the m-th column data line controls any one of the control units at the (2m-1)-th column and the 2n-th row and the control unit at the 2m-th column and the 2n-th row to conduct or conduct alternately in a time-sharing manner.

9. A display device, characterized in that, The display device includes: A gate driving circuit for outputting scan signals; A source driving circuit for outputting data signals; The display panel according to any one of claims 1-7, wherein the scan lines of the display panel are connected to the gate driving circuit, and the data lines of the display panel are connected to the source driving circuit.

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