Amplification circuit

Abstract

The invention provides an amplifier circuit capable of suppressing deterioration of characteristics. The amplifier circuit includes: a distributor that distributes an input signal into a first signal and a second signal; the first amplifier is used for amplifying the first signal and outputting the amplified signal to a first node as a third signal; the second amplifier is used for amplifying the second signal and outputting the amplified signal to a second node as a fourth signal; a synthesizer which synthesizes the third signal and the fourth signal and outputs the synthesized signal as an output signal to an output terminal; and a processing circuit having an input node to which the first node and the second node are electrically coupled, the degree of coupling between the first node and the input node being greater than the degree of coupling between the second node and the input node. A signal input to the input node and having a frequency lower than the operating frequency bands of the first amplifier and the second amplifier is passed through a reference potential.

Description

Technical Field

[0001] The invention relates to an amplifier circuit. Background Art

[0002] It is known that in an amplifier circuit such as a Doherty amplifier circuit in which two amplifiers are connected in parallel, VBW (Video Bandwidth) circuits are provided at the output ends of the two amplifiers (for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-138983

[0006] The VBW circuit (also called a difference frequency short circuit, video bypass circuit, or envelope frequency termination circuit) is a circuit that processes frequencies lower than the operating frequency band of the amplifier. If a VBW circuit is provided for each amplifier, the amplifier circuit will be larger. If a VBW circuit is provided for two amplifiers in common, the characteristics will deteriorate. Summary of the invention

[0007] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to suppress degradation of characteristics.

[0008] One embodiment of the present disclosure is an amplifier circuit, which includes: a distributor that distributes an input signal into a first signal and a second signal; a first amplifier that amplifies the first signal and outputs the amplified signal as a third signal to a first node; a second amplifier that amplifies the second signal and outputs the amplified signal as a fourth signal to a second node; a synthesizer that synthesizes the third signal and the fourth signal and outputs the synthesized signal as an output signal to an output terminal; and a processing circuit that includes an input node for electrically coupling the first node and the second node, the coupling degree between the first node and the input node being greater than the coupling degree between the second node and the input node, and the processing circuit allows a signal input to the input node having a frequency lower than an operating frequency band of the first amplifier and the second amplifier to pass through a reference potential.

[0009] Effects of the Invention

[0010] According to the present disclosure, degradation of characteristics can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a block diagram of the amplifier circuit of Example 1.

[0012] Figure 21 is a schematic diagram showing Example 1 of the coupler in Example 1.

[0013] Figure 3 It is a schematic diagram showing Example 2 of the coupler in Example 1.

[0014] Figure 4 This is a circuit diagram of Example 1 of the VBW circuit in Example 1.

[0015] Figure 5 This is a circuit diagram of Example 2 of the VBW circuit in Example 1.

[0016] Figure 6 This is a circuit diagram of Example 3 of the VBW circuit in Example 1.

[0017] Figure 7 2 is a block diagram of an amplifier circuit of Comparative Example 1.

[0018] Figure 8 This is a block diagram of an amplifier circuit according to Modification 1 of Embodiment 1.

[0019] Fig. 9 This is a block diagram of the coupler and processing circuit of the amplifier circuit according to the first modification of the first embodiment.

[0020] Fig.10 This is a block diagram of an amplifier circuit according to a second variation of the first embodiment.

[0021] Fig.11 This is a block diagram of the coupler and processing circuit of the amplifier circuit according to the second modification of the first embodiment.

[0022] Fig.12 This is a block diagram of the amplifier circuit of Example 2.

[0023] Fig.13 This is a graph showing the drain efficiency of each amplifier in Example 2 with respect to input power.

[0024] Fig.14 This is a block diagram of an amplifier circuit according to a first variation of the second embodiment.

[0025] Fig.15 This is a block diagram of the amplifier circuit of Example 3.

[0026] Fig.16 A diagram showing a simulated amplifier circuit.

[0027] Fig.17 : is a graph showing the passing characteristic of the simulated sample A.

[0028] Fig.18 : is a graph showing the passing characteristic of the simulated sample B.

[0029] Fig.193 is a diagram showing the isolation characteristics of sample A and sample B in simulation.

[0030] Description of reference numerals:

[0031] 10, 12, 14: amplifier;

[0032] 16: Allocator;

[0033] 18: Synthesizer;

[0034] 20: Coupler;

[0035] 22: Processing circuit;

[0036] 24: VBW circuit;

[0037] 31, 32, 33, 34, 39: matching circuit;

[0038] 35, 36, 37, 38: bias circuit;

[0039] 41, 42, 46a, 46b, 46c: lines;

[0040] 43, 44, 43a, 43b, 43c, 43d: bonding lines;

[0041] 45a, 45b, 45c, 45d, 45e, 45f, 45g: solder pads;

[0042] 46d, 46e, 50, 51, 52, 53: transmission lines;

[0043] 100, 101, 102, 103, 104, 105, 108, 110: amplifier circuit. DETAILED DESCRIPTION

[0044] [Description of Embodiments of the Present Disclosure]

[0045] First, the contents of the embodiments of the present disclosure will be listed and described.

[0046] (1) One embodiment of the present disclosure is an amplifier circuit, which includes: a distributor that distributes an input signal into a first signal and a second signal; a first amplifier that amplifies the first signal and outputs the amplified signal as a third signal to a first node; a second amplifier that amplifies the second signal and outputs the amplified signal as a fourth signal to a second node; a synthesizer that synthesizes the third signal and the fourth signal and outputs the synthesized signal as an output signal to an output terminal; and a processing circuit that includes an input node for electrically coupling the first node and the second node, the coupling degree between the first node and the input node being greater than the coupling degree between the second node and the input node, and the processing circuit allows a signal input to the input node having a frequency lower than the operating frequency band of the first amplifier and the second amplifier to pass through a reference potential. As a result, the insertion loss of the operating frequency band of the second amplifier can be reduced. In addition, the isolation characteristics between the first amplifier and the second amplifier can be improved.

[0047] (2) In the above (1), the first node and the input node may be electrically connected, and the second node and the input node may be electromagnetically coupled in a coupler. Thus, the coupling degree between the second node and the input node can be made smaller than the coupling degree between the first node and the input node.

[0048] (3) In the above (2), the coupler may include: a first line electrically connected to the first node and the input node; and a second line electrically connected to the second node, which is not electrically connected to the first line but is electromagnetically coupled to the first line. Thus, the second node and the input node can be electromagnetically coupled in the coupler.

[0049] (4) In any of the above (1) to (3), the processing circuit may include a capacitor connected in series between the input node and the reference potential. Thus, the processing circuit can suppress low-frequency signals of the first amplifier and the second amplifier.

[0050] (5) In the above (4), the absolute value of the impedance between the first node and the capacitor at the center frequency of the operating frequency band may be greater than the absolute value of the impedance of the capacitor at a frequency corresponding to the bandwidth of the operating frequency band, and the absolute value of the impedance between the second node and the capacitor at the center frequency may be greater than the absolute value of the impedance of the capacitor at a frequency corresponding to the bandwidth of the operating frequency band. Thus, the insertion loss of the operating frequency band of the second amplifier can be reduced. In addition, the isolation characteristics between the first amplifier and the second amplifier can be improved.

[0051] (6) In any of the above (1) to (5), the second amplifier may be capable of operating at an input power lower than an input power of the first amplifier. Thus, the insertion loss of the second amplifier with low distortion can be suppressed. In addition, the isolation characteristics between the first amplifier and the second amplifier can be improved.

[0052] (7) In any of the above (1) to (6), the amplifier circuit may be a Doherty amplifier circuit, the first amplifier may be a peak amplifier, and the second amplifier may be a main amplifier. Thus, the insertion loss of the main amplifier can be suppressed. In addition, the isolation characteristics between the main amplifier and the peak amplifier can be improved.

[0053] (8) In any one of the above (1) to (6), the amplifier circuit may include a third amplifier, the distributor distributes the input signal into the first signal, the second signal, and the fifth signal, the third amplifier amplifies the fifth signal and outputs the amplified signal as the sixth signal to the third node, and the synthesizer synthesizes the third signal, the fourth signal, and the sixth signal and outputs the synthesized signal as the output signal. Thus, the low-frequency signals of at least two amplifiers can be suppressed.

[0054] (9) In the above (8), no node electrically coupled to the input node may be provided between the third amplifier and the combiner. This can suppress the insertion loss of the third amplifier. In addition, the isolation characteristics between the third amplifier and the first amplifier and the second amplifier can be improved.

[0055] (10) In the above (8), the third node may be electrically coupled to the input node, and the coupling degree between the third node and the input node may be smaller than the coupling degree between the second node and the input node. Thus, the signals in the low frequency band of the first amplifier, the second amplifier, and the third amplifier can be suppressed. In addition, the insertion loss of the third amplifier can be suppressed. In addition, the isolation characteristics between the third amplifier and the first amplifier and the second amplifier can be improved.

[0056] (11) In the above (9) or (10), the second amplifier may be capable of operating at an input power lower than that of the first amplifier, and the third amplifier may be capable of operating at an input power lower than that of the second amplifier. Thus, the insertion loss of the third amplifier having low distortion can be suppressed. In addition, the isolation characteristics between the third amplifier and the first amplifier and the second amplifier can be improved.

[0057] (12) In any one of the above (9) to (11), the amplifier circuit may be a Doherty amplifier circuit, the third amplifier may be a main amplifier, and the first amplifier and the second amplifier may be peak amplifiers. Thus, the insertion loss of the main amplifier can be suppressed. In addition, the isolation characteristics between the main amplifier and the peak amplifier can be improved.

[0058] [Details of the embodiments of the present disclosure]

[0059] Hereinafter, specific examples of amplifier circuits according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0060] [Example 1]

[0061] As an amplifier circuit, a high-output high-frequency amplifier circuit used in a base station for mobile communication will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. Figure 1 is a block diagram of the amplifier circuit of Example 1. Figure 1 As shown, the amplifier circuit 100 includes an amplifier 10 , an amplifier 12 , a distributor 16 , a combiner 18 , a coupler 20 , a processing circuit 22 , a line L01 , a line L02 , matching circuits 31 to 34 , and bias circuits 35 to 38 .

[0062] The amplifier 10 and the amplifier 12 are connected in parallel between the input terminal Tin and the output terminal Tout. A high frequency signal is input to the input terminal Tin as the input signal Sin. The distributor 16 distributes the input signal Sin input to the input terminal Tin into a signal S1 (first signal) and a signal S2 (second signal). The distributor 16 is, for example, a Wilkinson type distributor.

[0063] The signal S1 passes through the matching circuit 31 and is input to the amplifier 10. The matching circuit 31 matches the impedance from the distributor 16 to the matching circuit 31 and the impedance from the matching circuit 31 to the amplifier 10. The amplifier 10 (first amplifier) ​​amplifies the signal S1 and outputs the amplified signal S3 (third signal). The signal S3 amplified by the amplifier 10 passes through the matching circuit 33 and is output to the synthesizer 18. The matching circuit 33 matches the impedance from the amplifier 10 to the matching circuit 33 and the impedance from the matching circuit 33 to the synthesizer 18. The bias circuit 35 is connected between the node between the matching circuit 31 and the amplifier 10 and the bias terminal. The bias circuit 35 supplies the gate bias voltage VG1 to the amplifier 10 to suppress the signal S1 from leaking to the bias terminal. The bias circuit 37 is connected between the node between the amplifier 10 and the matching circuit 33 and the bias terminal. The bias circuit 37 supplies the drain bias voltage VD1 to the amplifier 10 to suppress the signal S3 from leaking to the bias terminal.

[0064] The signal S2 passes through the matching circuit 32 and is input to the amplifier 12. The matching circuit 32 matches the impedance of the distributor 16 toward the matching circuit 32 with the impedance of the matching circuit 32 toward the amplifier 12. The amplifier 12 (second amplifier) ​​amplifies the signal S2 and outputs the amplified signal S4 (fourth signal). The signal S4 amplified by the amplifier 12 passes through the matching circuit 34 and is output to the synthesizer 18. The matching circuit 34 matches the impedance of the amplifier 12 toward the matching circuit 34 with the impedance of the matching circuit 34 toward the synthesizer 18. The bias circuit 36 ​​is connected between the node between the matching circuit 32 and the amplifier 12 and the bias terminal. The bias circuit 36 ​​supplies the gate bias voltage VG2 to the amplifier 12 to suppress the signal S2 from leaking to the bias terminal. The bias circuit 38 is connected between the node between the amplifier 12 and the matching circuit 34 and the bias terminal. The bias circuit 38 supplies the drain bias voltage VD2 to the amplifier 12 to suppress the signal S4 from leaking to the bias terminal. The synthesizer 18 synthesizes the signal S3 and the signal S4 and outputs the synthesized signal as an output signal Sout to the output terminal Tout.

[0065] The amplifiers 10 and 12 are, for example, FETs (Field Effect Transistors), with their sources grounded, high-frequency signals input to their gates, and signals output from their drains. FETs are, for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOSs (Laterally Diffused Metal Oxide Semiconductors).

[0066] The first end of the line L01 is electrically connected to a node N1 (first node) between the amplifier 10 and the matching circuit 33. The first end of the line L02 is electrically connected to a node N2 (second node) between the amplifier 12 and the matching circuit 34. The input port P1 of the coupler 20 is electrically connected to the second end of the line L01. The coupling port P3 of the coupler 20 is electrically connected to the second end of the line L02. The output port P2 of the coupler 20 is electrically connected to an input node P5 of the processing circuit 22. The processing circuit 22 allows a signal having a frequency lower than the operating frequency band (referred to as a low frequency band) among the signals input to the input node P5 to pass through a reference potential.

[0067] [Coupler Example 1]

[0068] Figure 2 Schematic diagram showing Example 1 of the coupler in Example 1. Figure 2 As shown, the coupler 20 is a directional coupler. Lines 41 and 42 are provided on a dielectric substrate 40. The dielectric substrate 40 is, for example, a circuit substrate carrying the amplifiers 10 and 12, or a substrate of a chip mounted on a package carrying the amplifiers 10 and 12. Lines 41 and 42 are, for example, signal lines of microstrip lines or coplanar lines. Lines 41 and 42 form a transmission line with a reference potential such as ground (grand). The input port P1 is connected to the first end of the line 41, and the output port P2 is connected to the second end of the line 41. The coupling port P3 is connected to the first end of the line 42, and the isolation port P4 is connected to the second end of the line 42. The isolation port P4 is terminated by a reference impedance R0 (for example, 50Ω). Lines 41 and 42 are magnetically coupled. The high-frequency signal input to the input port P1 is output to the output port P2. A portion of the high-frequency signal input to the coupling port P3 is output to the output port P2 according to the coupling degree between the line 41 and the line 42.

[0069] [Coupler Example 2]

[0070] Figure 3 Schematic diagram showing Example 2 of the coupler in the embodiment. Figure 3As shown, pads 45a to 45d are provided. Pads 45a to 45d are, for example, pads on the upper surface of a chip mounted on a package. Pad 45a is electrically connected to input port P1, pad 45b is electrically connected to output port P2, pad 45c is electrically connected to coupling port P3, and pad 45d is electrically connected to isolation port P4. Bonding wire 43 electrically connects pad 45a to pad 45b. Bonding wire 44 electrically connects pad 45c to pad 45d. Bonding wire 43 and bonding wire 44 are arranged adjacent to each other and are magnetically coupled. A high-frequency signal input to input port P1 is output to output port P2. A portion of the high-frequency signal input to coupling port P3 is output to output port P2 according to the degree of coupling between bonding wire 43 and bonding wire 44.

[0071] [VBW circuit example 1]

[0072] Figure 4 1 is a circuit diagram of Example 1 of the VBW circuit in the embodiment. Figure 4 , the coupler 20 is omitted. The VBW circuit 24 includes a line L01 or a line L02 and a processing circuit 22. A first end of the line L01 or the line L02 is electrically connected to the node N1 or the node N2, and a second end of the line L01 or the line L02 is electrically connected to the input node P5. The processing circuit 22 includes a capacitor C1 connected in series between the input node P5 and the reference potential.

[0073] The VBW circuit 24 is a circuit for improving VBW (video bandwidth). The video bandwidth is used as an indicator of the frequency band of distortion. When the VBW is small, if the third-order intermodulation distortion (IMD3: 3rd order InterModulation Distortion) of the two-tone signal corresponding to the bandwidth of the amplifier (for example, 400MHz) is measured, the signal strength will be different between the IMD3 component on the low-frequency side and the IMD3 component on the high-frequency side. In this way, if IMD3 is asymmetric, even if distortion compensation is performed by DPD (Digital Predistortion), the improvement of distortion will be reduced, and sufficient distortion characteristics cannot be obtained. As a cause of the asymmetry of the IMD3, the second-order intermodulation distortion IMD2 component generated by the difference frequency component of the two-tone signal is known. Therefore, the impedance in the low-frequency band between the node N1 and the node N2 and the reference potential is reduced by setting the VBW circuit 24. As a result, the video bandwidth becomes larger and the IMD2 component is suppressed. This can improve the asymmetry of IMD3 and enable sufficient distortion compensation to be performed by DPD.

[0074] Line L01 and line L02 are inductors or transmission lines. Line L01 and line L02 suppress the leakage of signals in the operating frequency band from node N1 and node N2 to coupler 20. Therefore, the impedance of line L01 and line L02 is high at the frequency of the operating frequency band. Capacitor C1 allows signals in a low frequency band lower than the operating frequency band to pass through a reference potential from input node P5. Therefore, capacitor C1 has a large capacitance so as to become a low impedance in a low frequency band (for example, a frequency corresponding to a bandwidth). The operating frequency band is, for example, between 0.5 GHz and 10 GHz, and the bandwidth of the operating frequency band is, for example, greater than 0 MHz and less than or equal to 400 MHz. The processing circuit 22 allows the signal to pass through the reference potential, for example, at a frequency lower than the operating frequency band of amplifiers 10 and 12, for example, less than 1 / 2 or less than 1 / 5 of the center frequency of the operating frequency band.

[0075] [VBW circuit example 2]

[0076] Figure 5 2 is a circuit diagram of Example 2 of the VBW circuit in Example 1. Figure 5 As shown, the resistor R1 and the inductor L2 are connected in series between the input node P5 and the capacitor C1. The first end of the resistor R1 is electrically connected to the input node P5, the second end of the resistor R1 is electrically connected to the first end of the inductor L2, and the second end of the inductor L2 is electrically connected to the first end of the capacitor C1. The other connection relationships are the same as Figure 4 The inductor L2 corresponds to a line such as a bonding wire that electrically connects the capacitor C1 and the resistor R1. The resistor R1 is a damping resistor. For example, if a capacitor (such as a parasitic capacitor) is connected in parallel with the capacitor C1 and the inductor L2, an unnecessary resonance may occur. The unnecessary resonance can be suppressed by setting the resistor R1.

[0077] [VBW circuit example 3]

[0078] Figure 6 is a circuit diagram of Example 3 of the VBW circuit in Example 1. Figure 6 As shown, the first end of the inductor L3 is electrically connected to the input node P5, the second end of the inductor L3 is electrically connected to the first end of the resistor R1, the first end of the capacitor C2 is electrically connected to the node between the inductor L3 and the line L01 or the line L02, and the second end of the capacitor C2 is electrically connected to the reference potential. Other connection relationships are similar to Figure 5 same.

[0079] Inductor L3 corresponds to a line such as a bonding wire that electrically connects capacitor C2 and resistor R1. Capacitor C2 has a capacitance different from that of capacitor C1. This can increase the frequency band to be suppressed by VBW circuit 24. Resistor R1 is a damping resistor for suppressing unnecessary resonance caused by capacitor C1 and capacitor C2.

[0080] [Comparative Example 1]

[0081] Figure 7 is a block diagram of the amplifier circuit of Comparative Example 1. Figure 7 As shown, the amplifier circuit 110 of Comparative Example 1 is not provided with a coupler 20. The second end of line L01, the second end of line L02, and the input node P5 of the processing circuit 22 are electrically connected to the node N5. As a result, the low-frequency band signals in the signal S3 and the signal S4 will pass through the node N5 and pass through the reference potential from the processing circuit 22. Therefore, the low-frequency band signals can be suppressed. However, although the line L01 and the line L02 suppress the passage of the signal in the working frequency band, a part of the signal in the working frequency band will pass through the line L01 and the line L02 and flow to the reference potential. In addition, the low-frequency band signal flows between the node N1 and the node N2. As a result, the insertion loss of the working frequency band of the signal S3 and the signal S4 passing through the node N1 and the node N2 becomes larger. In addition, the isolation between the working frequency band and the low frequency band between the node N1 and the node N2 will deteriorate. On the other hand, sometimes the degree of suppression of the low-frequency band signal in the signal S3 and the signal S4 may be different.

[0082] [Description of Example 1]

[0083] In Embodiment 1, the processing circuit 22 allows a signal having a frequency lower than the operating frequency band of the amplifier 10 and the amplifier 12 to pass through the reference potential. The node N1 is electrically connected to the input port P1, and the node N2 is electrically connected to the coupling port P3. Therefore, the processing circuit 22 is coupled to the node N1 more than the node N2. Therefore, the processing circuit 22 suppresses the signal of the low frequency band in the signal S4 more than the signal of the low frequency band in the signal S3. On the other hand, the signal of the operating frequency band in the signal S4 is less likely to leak to the reference potential than the signal of the operating frequency band in the signal S3. Therefore, the insertion loss of the node N2 is smaller than the insertion loss of the node N1. For example, when the distortion of the amplifier 10 is greater than the distortion of the amplifier 12, in the amplifier 10, the asymmetry of IMD3 is improved by suppressing the signal of the low frequency band. On the other hand, in the amplifier 12, even if the signal of the low frequency band is not suppressed like the amplifier 10, the asymmetry of IMD3 is improved. Therefore, the node N2 is electrically connected to the coupling port P3. Thus, although the signal of the low frequency band of the amplifier 12 is not suppressed as much as the low frequency band of the amplifier 10, the insertion loss of the operating frequency band at the node N2 of the amplifier 12 can be reduced. In addition, the isolation characteristics of the operating frequency band and the low frequency band between the node N1 of the amplifier 10 and the node N2 of the amplifier 12 can be improved.

[0084] In addition, the VBW circuit 24 can be realized by the line L01 and the line L02 and the processing circuit 22. The absolute value of the impedance of each of the line L01 and the line L02 at the center frequency of the operating frequency band is made larger than the absolute value of the impedance of the capacitor C1 at the frequency corresponding to the bandwidth of the operating frequency band. Thus, the line L01 and the line L02 can suppress the signal of the operating frequency band in the signal S3 and the signal S4 from leaking to the reference potential, and the capacitor C1 can make the signal of the low frequency band pass through the reference potential.

[0085] [Variation 1 of Example 1]

[0086] Figure 8 is a block diagram of an amplifier circuit of a variation 1 of the embodiment 1. Figure 8 As shown, in the amplifier circuit 101 of the modification 1 of the embodiment 1, the input node P5 of the processing circuit 22 is electrically connected to the node N1 via the line L01. The input port P1 of the coupler 20 is electrically connected to the node N1, and the output port P2 is electrically connected to the matching circuit 33. The node N2 is electrically connected to the coupling port P3 of the coupler 20. The line L01 and the processing circuit 22 form a VBW circuit 24. The other configurations are the same as those of the embodiment 1 and the description thereof is omitted.

[0087] Fig. 9 FIG. 1 is a block diagram of a coupler and a processing circuit of an amplifier circuit according to a modification example 1 of the first embodiment. Fig. 9 As shown, a line 41, a line 42, and a line 46a to a line 46c are provided on a dielectric substrate 40. The line 41, the line 42, and the line 46a to the line 46c are signal lines of transmission lines such as microstrip lines or coplanar lines. The line 41 and the line 42 form a coupler 20. The input port P1 corresponding to the first end of the line 41 is electrically connected to the node N1. The output port P2 corresponding to the second end of the line 41 is electrically connected to the matching circuit 33. The coupling port P3 corresponding to the first end of the line 42 is electrically connected to the node N2 via the line 46b. The isolation port P4 corresponding to the second end of the line 42 is connected to the reference potential via the reference impedance R0. The node N2 is electrically connected to the matching circuit 34 via the line 46a. The node N1 is electrically connected to the pad 45f via the line 46c and the bonding wire 43a, and the pad 45f is equivalent to the input node P5 of the processing circuit 22. The line 46c and the bonding wire 43a are connected to the Figure 8 Corresponding to line L01.

[0088] The node N1 is electrically connected to the processing circuit 22 without passing through the coupler 20. Therefore, the processing circuit 22 can suppress the low-frequency signal of the node N1. The node N2 is connected to the processing circuit 22 via the magnetic field coupling between the line 42 and the line 41 of the coupler 20. Therefore, although the suppression of the low-frequency signal of the node N2 is small, the insertion loss at the node N2 can be suppressed.

[0089] [Variation 2 of Example 1]

[0090] Fig.10 FIG. 1 is a block diagram of an amplifier circuit of a second variation of the first embodiment. Fig.10 As shown, in the amplifier circuit 102 of the second variation of the first embodiment, the second end of the line L01 is electrically connected to the node N5. The node N5 is electrically connected to the input node P5 of the processing circuit 22 and the input port P1 of the coupler 20. The second end of the line L02 is electrically connected to the isolation port P4 of the coupler 20. The other configurations are the same as those of the first embodiment and the description thereof is omitted.

[0091] Fig.11 FIG. 2 is a block diagram of a coupler and a processing circuit of an amplifier circuit according to a second variation of the first embodiment. Fig.11 As shown, node N1 is electrically connected to pad 45f via transmission line 46e and bonding wire 43d, and pad 45f corresponds to input node P5 of processing circuit 22. Node N2 is electrically connected to pad 45g via transmission line 46d and bonding wire 43b. Pad 45f is electrically connected to pad 45e via bonding wire 43c. Pads 45e and 45g are respectively connected to a reference potential via reference impedance R0. Bonding wires 43b and 43c are electrically connected to pad 45g. Fig.10 The pads 45f, 45e, 45g and the end of the transmission line 46d correspond to the input port P1, the output port P2, the coupling port P3 and the isolation port P4, respectively. The transmission line 46e and the bonding wire 43d correspond to Fig.10 The transmission line 46d corresponds to the line L01, and the transmission line 46d corresponds to the line L02.

[0092] The node N1 is electrically connected to the processing circuit 22 without passing through the coupler 20. Therefore, the processing circuit 22 can suppress the low-frequency signal of the node N1. The node N2 is connected to the processing circuit 22 via the magnetic field coupling of the bonding wire 43c and the bonding wire 43b of the coupler 20. Therefore, although the suppression of the low-frequency signal of the node N2 is small, the insertion loss at the node N2 can be suppressed.

[0093] According to the first embodiment and its variant, the input node P5 of the processing circuit 22 is electrically coupled to the node N1 and the node N2. The coupling degree between the node N1 and the input node P5 is greater than the coupling degree between the node N2 and the input node P5. Thus, although the signal of the low frequency band of the amplifier 12 is not suppressed as the low frequency band of the amplifier 10, the insertion loss of the operating frequency band at the node N2 of the amplifier 12 can be reduced. In addition, the isolation characteristics between the node N1 of the amplifier 10 and the node N2 of the amplifier 12 can be improved.

[0094] The difference between the coupling degree between the node N1 and the input node P5 and the coupling degree between the node N2 and the input node P5 can be set to 1 dB or more, 2 dB or more, or 5 dB or more. From the perspective of coupling the node N2 and the input node P5, the difference between the coupling degree between the node N1 and the input node P5 and the coupling degree between the node N2 and the input node P5 can be set to 20 dB or less. The coupling degree between the node N1 and the input node P5 is, for example, 5 dB or more or 3 dB or more. The coupling degree between the node N2 and the input node P5 is, for example, 5 dB or less or 10 dB or less.

[0095] like Figure 2 , Figure 3 , Fig. 9 as well as Fig.11 In this way, the node N1 and the input node P5 are electrically connected. The node N2 and the input node P5 are electromagnetically coupled in the coupler 20. Thus, the coupling degree between the node N2 and the input node P5 can be made smaller than the coupling degree between the node N1 and the input node P5. The node N1 and the input node P5 are electrically connected, for example, the node N1 and the input node P5 are DC-connected.

[0096] like Figure 2 , Figure 3 , Fig. 9 as well as Fig.11 In this way, in the coupler 20, the first line (line 41, bonding wire 43, and bonding wire 43c) is electrically connected to the node N1 and the input node P5. The second line (line 42, bonding wire 44, and bonding wire 43b) is electrically connected to the node N2, and is not electrically connected to the first line but is electromagnetically coupled to the first line. Thus, the node N2 and the input node P5 can be electromagnetically coupled via the coupler 20.

[0097] The processing circuit 22 includes a capacitor C1 connected in series between the input node P5 and the reference potential. Thus, the processing circuit 22 can suppress the low-frequency signals of the amplifiers 10 and 12 .

[0098] The absolute value ZL1 of the impedance at the center frequency of the operating frequency band between the node N1 and the capacitor C1 is greater than the absolute value ZC of the impedance of the capacitor C1 at the frequency corresponding to the bandwidth of the operating frequency band. The absolute value ZL2 of the impedance at the center frequency of the operating frequency band between the node N2 and the capacitor C1 is greater than the absolute value ZC of the impedance of the capacitor C1 at the frequency corresponding to the bandwidth of the operating frequency band. Thus, the signal of the operating frequency band in the signal S3 and the signal S4 can be suppressed from leaking to the reference potential, and the signal of the low frequency band can pass through the reference potential through the capacitor C1. Therefore, the insertion loss of the operating frequency band of the amplifier 12 can be reduced. In addition, the isolation characteristics between the amplifier 10 and the amplifier 12 can be improved.

[0099] Each of ZL1 and ZL2 can be set to be 5 times or more, 20 times or more, or 50 times or more of ZC.

[0100] The center frequency of the operating frequency band is, for example, 0.5 GHz to 10 GHz, and as an example, 3.5 GHz. The frequency of the low frequency band is, for example, 0 MHz to 500 MHz, and as an example, 400 MHz. In Example 1, when line L01 and line L02 are inductors, the inductance of line L01 and line L02 is, for example, 1 nH or more. Thus, the impedance of line L01 and line L02 at the center frequency (3.5 GHz) of the operating frequency band becomes 22 Ω. The impedance of line L01 and line L02 at the center frequency of the operating frequency band can be set to 5 Ω or more, and can be set to 20 Ω or more. When line L01 and line L02 are transmission lines, for example, the electrical length of line L01 and line L02 is set to λ / 4. Here, λ is the wavelength of the center frequency of the operating frequency band. Thus, the signals of the operating frequency band in signal S3 and signal S4 are not transmitted from node N1 and node N2 to line L01 and line L02. The electrical length of the line L01 and the line L02 may be greater than λ / 8 and less than 3λ / 8, and may be greater than 3λ / 16 and less than 5λ / 16, or greater than 7λ / 32 and less than 9λ / 32.

[0101] The capacitance of capacitor C1 is, for example, 1 nF or more. Therefore, the impedance of capacitor C1 at a frequency corresponding to the bandwidth of the operating frequency band (400 MHz) is 0.36 Ω. The impedance of capacitor C1 at a frequency corresponding to the bandwidth of the operating frequency band can be set to 1 Ω or more, and can be set to 0.5 Ω or more.

[0102] Amplifier 12 can operate at an input power lower than the input power of amplifier 10. For example, gate bias voltage VG2 is increased negatively compared to gate bias voltage VG1. In this case, amplifier 12 has less distortion than amplifier 10. Therefore, the asymmetry of IMD3 of amplifier 10 can be improved by increasing the coupling degree between node N1 and input node P5. The insertion loss of amplifier 12 with less distortion can be suppressed by reducing the coupling degree between node N2 and input node P5. In addition, the isolation characteristics between amplifier 10 and amplifier 12 can be improved. For example, the input power at which amplifier 12 can operate can be lower by more than 1 dB, or lower by more than 3 dB, than the input power at which amplifier 10 can operate. For example, the difference between gate bias voltage VG1 and gate bias voltage VG2 is more than 1 / 10, or more than 1 / 5 of the pinch off voltage of amplifier 10 and amplifier 12.

[0103] When the amplifier circuits 100 to 102 are Doherty amplifier circuits, the amplifier 10 is a peak amplifier and the amplifier 12 is a main amplifier. The amplifier 12 performs a class AB or class B operation, and the amplifier 10 performs a class C operation. When the input power of the input signal Sin is small, the amplifier 12 mainly amplifies the input signal Sin. If the input power increases, in addition to the amplifier 12, the amplifier 10 also amplifies the peak value of the input signal Sin. Thus, the amplifiers 10 and 12 amplify the input signal Sin.

[0104] The amplifier 10 performs a Class C operation, so the distortion is large. Therefore, the asymmetry of MD3 of the amplifier 10 can be improved by electrically connecting the node N1 to the processing circuit 22. The insertion loss of the main amplifier can be suppressed by coupling the node N2 to the processing circuit 22 via the electromagnetic field coupling in the coupler 20. In addition, the isolation characteristics between the main amplifier and the peak amplifier can be improved.

[0105] [Example 2]

[0106] Fig.12 is a block diagram of the amplifier circuit of Example 2. Fig.12 The input matching circuit and bias circuit are omitted in the figure. Fig.12 As shown, in the amplifier circuit 103 of Example 2, the distributor 16 distributes the input signal Sin into the signal S1, the signal S2 and the signal S5. The amplifier 14 (third amplifier) ​​amplifies the signal S5 (fifth signal) and outputs the amplified signal S6 (sixth signal). The signal S6 amplified by the amplifier 14 passes through the matching circuit 39 and is output to the synthesizer 18. The matching circuit 39 matches the impedance from the amplifier 14 to the matching circuit 39 with the impedance from the matching circuit 39 to the synthesizer 18. The synthesizer 18 synthesizes the signal S3, the signal S4 and the signal S6, and outputs the synthesized signal as the output signal Sout. In this way, it is also possible to set the VBW circuit 24 in at least two amplifiers 10 and the amplifier 12 in the amplifier circuit 103 having three amplifiers 10, 12 and 14 to suppress the signal in the low frequency band. The other structures are the same as those in Example 1 and the description is omitted.

[0107] In the second embodiment, no node connected to the input node P5 of the processing circuit 22 is provided between the amplifier 14 and the synthesizer 18. Thus, the amplifier circuit 103 can be miniaturized without providing the VBW circuit 24 in the amplifier 14. In addition, the insertion loss of the amplifier 14 can be suppressed. The isolation characteristics between the amplifier 14 and the amplifiers 10 and 12 can be improved.

[0108] Fig.13Graph showing the drain efficiency of each amplifier in Example 2 relative to input power. Fig.13 As shown, when the input power increases, the amplifier 14 starts to operate first. The amplifier 12 starts to operate near the input power at which the drain efficiency of the amplifier 14 becomes maximum. The amplifier 10 starts to operate near the input power at which the drain efficiency of the amplifier 12 becomes maximum. When the amplifiers 10, 12, and 14 reach saturation power, the drain efficiencies of the amplifiers 10, 12, and 14 become maximum. In this way, the amplifier 12 can operate at an input power smaller than the input power of the amplifier 10, and the amplifier 14 can operate at an input power smaller than the input power of the amplifier 12. Such operation can be achieved, for example, by increasing the gate bias voltage VG3 of the amplifier 14 more negatively than the gate bias voltage VG2 of the amplifier 12, and increasing the gate bias voltage VG2 of the amplifier 12 more negatively than the gate bias voltage VG1 of the amplifier 10. In this case, the distortion of the amplifier 14 is smaller than that of the amplifier 12, and the distortion of the amplifier 12 is smaller than that of the amplifier 10. Therefore, the VBW circuit 24 may not be provided in the amplifier 14. Therefore, the insertion loss of the amplifier 14 having small distortion can be suppressed. The isolation characteristics between the amplifier 14 and the amplifiers 10 and 12 can be improved.

[0109] [Variation 1 of Example 2]

[0110] Modification 1 of Embodiment 2 is an example of a Doherty amplifier circuit. Fig.14 FIG. 1 is a block diagram of an amplifier circuit according to a first variation of the second embodiment. Fig.14 The illustration of the matching circuit and the bias circuit is omitted, and the transmission line is shown.

[0111] The amplifier circuit 104 of the modification 1 of the embodiment 2 is a Doherty amplifier circuit, the amplifier 14 is a main amplifier, and the amplifiers 10 and 12 are peak amplifiers. The transmission line 50 is electrically connected between the distributor 16 and the amplifier 10, and the transmission line 51 is electrically connected between the distributor 16 and the amplifier 12. The synthesizer 18 includes a transmission line 52 and a transmission line 53. The transmission line 52 is electrically connected between the node N6 at which the signal S3 and the signal S6 are synthesized and the amplifier 14. The transmission line 53 is provided between the node N7 at which the signal S3, the signal S6, and the signal S4 are synthesized and the node N6.

[0112] The characteristic impedance of the transmission line 50 and the transmission line 51 is a reference impedance R0 (e.g., 50Ω). The length of the transmission line 50 is λ / 4, and the length of the transmission line 51 is λ / 2. The transmission line 52 and the transmission line 53 are impedance conversion circuits, and the lengths of the transmission line 52 and the transmission line 53 are λ / 4. The characteristic impedance of the transmission line 52 and the transmission line 53 is appropriately set according to the impedance to be converted. The transmission line 50 and the transmission line 51 are used to adjust the phase shifted by the transmission line 52 and the transmission line 53. The other configurations are the same as those of the embodiment 2. Fig.12 The same and the description are omitted.

[0113] As in the first variation of the second embodiment, when the amplifier circuit 104 is a Doherty amplifier circuit, the amplifier 14 is a main amplifier, and the amplifiers 10 and 12 are peak amplifiers. In this case, the amplifier 14 performs a class A or class B operation, and the amplifiers 10 and 12 perform a class C operation. The drain efficiency of each amplifier relative to the input power is, for example, Fig.13 Therefore, the amplifier 14 has a smaller distortion than the amplifier 10 and the amplifier 12. Therefore, the VBW circuit 24 is not provided in the amplifier 14. Thus, the insertion loss of the main amplifier can be suppressed. In addition, the isolation characteristics between the main amplifier and the peak amplifier can be improved.

[0114] [Example 3]

[0115] Fig.15 is a block diagram of the amplifier circuit of Example 3. Fig.15 The input matching circuit and bias circuit are omitted in the figure. Fig.15 As shown, in the amplifier circuit 105 of the third embodiment, the coupler 20 has two coupling ports P3a and P3b. The second end of the line L02 is electrically connected to the coupling port P3a. The first end of the line L03 is electrically connected to the node N3 (third node) between the amplifier 14 and the matching circuit 39, and the second end of the line L03 is electrically connected to the coupling port P3b. The other structures are the same as those of the second embodiment. Fig.12 The same and the description are omitted.

[0116] The absolute value of the impedance of line L03 at the center frequency of the operating frequency band is made greater than the absolute value of the impedance of capacitor C1 at a frequency corresponding to the bandwidth of the operating frequency band. Thus, the signal of the operating frequency band in signal S6 can be suppressed from leaking to the reference potential through line L03, and the signal of the low frequency band can pass through the reference potential through capacitor C1.

[0117] According to the third embodiment, the node N3 is electrically coupled to the input node P5 of the processing circuit 22. The coupling degree between the node N3 and the input node P5 is smaller than the coupling degree between the node N2 and the input node P5. Thus, the VBW circuit 24 can be connected to the amplifier 14, and the signals in the low frequency band of the amplifiers 10, 12, and 14 can be suppressed. In addition, the insertion loss of the amplifier 14 can be suppressed. The isolation characteristics between the amplifier 14 and the amplifiers 10 and 12 can be improved.

[0118] The difference between the coupling degree between the node N2 and the input node P5 and the coupling degree between the node N3 and the input node P5 can be set to 1 dB or more, 2 dB or more, or 5 dB or more. From the perspective of coupling the node N3 and the input node P5, the difference between the coupling degree between the node N1 and the input node P5 and the coupling degree between the node N3 and the input node P5 can be set to 20 dB or less. The coupling degree between the node N3 and the input node P5 is, for example, 5 dB or less, or 10 dB or less.

[0119] When the distortion of amplifier 12 is greater than that of amplifier 14, for example, amplifier 14 can operate at an input power lower than that of amplifier 12. As a result, the signal in the low frequency band of amplifier 14, where distortion is less likely to be a problem, is not suppressed compared to the signal in the low frequency band of amplifier 12, and the insertion loss of amplifier 14 can be reduced. In addition, the isolation characteristics between amplifier 14 and amplifiers 10 and 12 can be improved.

[0120] When the amplifier circuit 105 is a Doherty amplifier circuit such as the first variation of the second embodiment, the amplifier 14 is a main amplifier, and the amplifiers 10 and 12 are peak amplifiers. This can suppress the loss of the main amplifier and improve the isolation characteristics between the main amplifier and the peak amplifier.

[0121] In the second embodiment and its modified example, and the third embodiment, the connection relationship between the coupler 20 and the processing circuit 22 may be the connection relationship of the modified example 1 and the modified example 2 of the first embodiment.

[0122] [simulation]

[0123] A simulation was performed for Example 1. Fig.16 is a diagram showing a simulated amplifier circuit. Fig.16 As shown, in the amplifier circuit 108, inductors are provided as the line L01 and the line L02. As the coupler 20, as shown in FIG. Figure 2 In this way, a line 41 and a line 42 are provided on a dielectric substrate 40. As a processing circuit 22, Figure 6Similarly, inductor L2, inductor L3, capacitor C1, capacitor C2 and resistor R1 are provided. Amplifier 10 and amplifier 12 are GaN HEMTs, and gate bias voltage VG1 and gate bias voltage VG2 are set to be the same. The center frequency of the passband is set to 2.1 GHz, and the frequency suppressed by VBW circuit 24 is set to 300 MHz.

[0124] Sample A Figure 7 In this case, the coupler 20 is not provided, and the second ends of the line L01 and the line L02 are connected to the processing circuit 22. Sample B is Fig.16 The amplifier circuit 108 of the first embodiment is shown in FIG. Fig.17 is the pass characteristic of the simulated sample A. The pass characteristic is the gain from the amplifier 10 and the amplifier 12, from the distributor 16 to the synthesizer 18. Fig.17 As shown, the pass characteristics are the same in amplifier 10 and amplifier 12. At 2.1 GHz, which is the center frequency of the passband, the gain of amplifier 10 and amplifier 12 is 7.417 dB. At a frequency of 300 MHz suppressed by VBW circuit 24, the gain of amplifier 10 and amplifier 12 can be reduced to 4.785 dB.

[0125] Fig.18 is the pass characteristic of the simulated sample B. The pass characteristic is the gain from the distributor 16 to the synthesizer 18. Fig.18 As shown, the gains of amplifier 10 and amplifier 12 at 2.1 GHz are 7.323 dB and 7.404 dB, respectively, and the gain of amplifier 12 is slightly larger than that of amplifier 10. The gains of amplifier 10 and amplifier 12 at 300 MHz are 3.999 dB and 4.768 dB, respectively, and the gain of amplifier 12 is larger than that of amplifier 10. In this way, the signal in the low frequency band of amplifier 10 can be suppressed, and the loss in the working frequency band of amplifier 12 can be suppressed.

[0126] Fig.19 is the isolation characteristic of the simulated sample A and sample B. The isolation characteristic is the isolation between the node N1 and the node N2. In one example, the isolation characteristic of 200 MHz, where the amplifier circuit is prone to oscillation, is improved. Fig.19 As shown, the isolation characteristics of sample A and sample B at 200 MHz are respectively -23 dB and -30 dB. In sample B provided with the coupler 20, the isolation characteristics can be improved.

[0127] As shown in the above simulation, in the sample B provided with the coupler 20 , the insertion loss of the amplifier 12 can be suppressed and the isolation characteristic between the node N1 and the node N2 can be improved compared with the sample A not provided with the coupler 20 .

[0128] The embodiments disclosed herein are illustrative and non-restrictive in all aspects. The scope of the present disclosure is indicated by the claims rather than the above meaning, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. An amplifier circuit comprising: a distributor for distributing an input signal inputted into a first signal and a second signal; a first amplifier, amplifying the first signal, and outputting the amplified signal as a third signal to the first node; a second amplifier, amplifying the second signal, and outputting the amplified signal as a fourth signal to a second node; a synthesizer, which synthesizes the third signal and the fourth signal, and outputs the synthesized signal as an output signal to an output terminal; as well as A processing circuit includes an input node for electrically coupling the first node and the second node, wherein the coupling degree between the first node and the input node is greater than the coupling degree between the second node and the input node, and the processing circuit allows a signal having a frequency lower than an operating frequency band of the first amplifier and the second amplifier and input to the input node to pass through a reference potential.

2. The amplifier circuit according to claim 1, wherein: The first node is electrically connected to the input node, The second node is coupled to the input node by an electromagnetic field in the coupler.

3. The amplifier circuit according to claim 2, wherein: The coupler includes: a first line electrically connected to the first node and the input node; and a second line electrically connected to the second node, which is not electrically connected to the first line but is electromagnetically coupled to the first line.

4. The amplifier circuit according to any one of claims 1 to 3, wherein: The processing circuit includes a capacitor connected in series between the input node and the reference potential.

5. The amplifier circuit according to claim 4, wherein: an absolute value of an impedance between the first node and the capacitor at a center frequency of the operating frequency band is greater than an absolute value of an impedance of the capacitor at a frequency corresponding to a bandwidth of the operating frequency band, An absolute value of an impedance between the second node and the capacitor at the center frequency is greater than an absolute value of an impedance of the capacitor at a frequency corresponding to a bandwidth of the operating frequency band.

6. The amplifier circuit according to any one of claims 1 to 3, wherein: The second amplifier is operable at an input power that is less than an input power of the first amplifier.

7. The amplifier circuit according to any one of claims 1 to 3, wherein: The amplifier circuit is a Doherty amplifier circuit. The first amplifier is a peak amplifier, The second amplifier is a main amplifier.

8. The amplifier circuit according to claim 1, comprising: The third amplifier, The distributor distributes the input signal into the first signal, the second signal, and the fifth signal, The third amplifier amplifies the fifth signal and outputs the amplified signal as a sixth signal to the third node. The synthesizer synthesizes the third signal, the fourth signal, and the sixth signal, and outputs the synthesized signal as the output signal.

9. The amplifier circuit according to claim 8, wherein: No node electrically coupled to the input node is provided between the third amplifier and the synthesizer.

10. The amplifier circuit according to claim 8, wherein: The third node is electrically coupled to the input node, and a coupling degree between the third node and the input node is smaller than a coupling degree between the second node and the input node.

11. The amplifier circuit according to claim 9 or 10, wherein: The second amplifier is capable of operating at an input power lower than the input power of the first amplifier, The third amplifier is operable at an input power that is less than an input power of the second amplifier.

12. The amplifier circuit according to claim 9 or 10, wherein: The amplifier circuit is a Doherty amplifier circuit. The third amplifier is a main amplifier, The first amplifier and the second amplifier are peak amplifiers.

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