Timing recovery for in-band communication in inductive power transfer systems

Abstract

The invention relates to timing recovery for in-band communication in inductive power transfer systems. A clock recovery system for recovering an in-band communication clock in a wireless power transfer system may include: a phase-locked loop; and a bit decision block and a multiplexer that cooperate to selectively provide an error signal to the loop filter in response to a bit detected in the in-band communication bit stream. The phase-locked loop may also include a phase detector that calculates an error signal as a function of a difference between the instantaneous peak position and an estimated peak position related to a symbol in the in-band communication bitstream; a loop filter that selectively receives the error signal; and a voltage-controlled oscillator that adjusts its output frequency in response to the output of the loop filter.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 580,774, filed on September 6, 2023, entitled “Timing Recovery for In-Band Communication in Inductive Power Transfer Systems,” which is incorporated herein by reference in its entirety. Background Art

[0003] Electronic devices such as smart phones, tablet computers, smart watches, wireless headphones, styluses, etc. can use wireless power transmission to facilitate charging of batteries within the device. In some applications, the wireless power transmitting device and the wireless power receiving device can use in-band communication, where the parameters of the wirelessly transmitted power are modulated to allow communication between the devices, such as power feedback control. Summary of the invention

[0004] A clock recovery system for recovering an in-band communication clock in a wireless power transmission system may include: a phase-locked loop; and a bit decision block and a multiplexer, the bit decision block and the multiplexer cooperate to selectively provide an error signal to a loop filter in response to a bit detected in an in-band communication bit stream. The phase-locked loop may also include: a phase detector that calculates an error signal based on a difference between an instantaneous peak position and an estimated peak position associated with a symbol in the in-band communication bit stream; a loop filter that selectively receives the error signal; and a voltage-controlled oscillator that adjusts its output frequency in response to an output of the loop filter.

[0005] The multiplexer may receive the error signal at a first input and a zero signal at a second input. The bit decision block may be responsive to a known bit in the in-band communication bit stream. The multiplexer and the bit decision block and the multiplexer may cooperate to provide the error signal to the loop filter in response to the known bit and to provide the zero signal to the loop filter in response to a bit other than the known bit. The known bit may be a stop bit. The known bit may be a 1 bit. The known bit may be a 0 bit.

[0006] The multiplexer may receive the error signal at a first input and the error signal plus an offset signal at a second input. The bit decision block may be responsive to a known bit in the in-band communication bit stream. The multiplexer and the bit decision block and the multiplexer may cooperate to provide the error signal to the loop filter in response to the known bit and to provide the error signal plus the offset signal to the loop filter in response to a bit other than the known bit. The known bit may be a 1 bit and the bit other than the known bit may be a 0 bit. The known bit may be a 0 bit and the bit other than the known bit may be a 1 bit.

[0007] The phase-locked loop and the bit decision block can be implemented using digital circuits. The phase-locked loop and the bit decision block can be implemented using programmable circuits.

[0008] A clock recovery system for recovering an in-band communication clock in a wireless power transmission system may include: a phase-locked loop; and an interpolation block that applies interpolation to multiple samples of the in-band communication bit stream to improve timing accuracy at low sampling rates. The phase-locked loop may also include: a phase detector that calculates an error signal based on a difference between an instantaneous peak position and an estimated peak position associated with a symbol in the in-band communication bit stream; a loop filter that selectively receives the error signal; and a voltage-controlled oscillator that adjusts its output frequency in response to an output of the loop filter. The interpolation may be a quadratic interpolation.

[0009] The clock recovery system may also include a bit decision block and a multiplexer, the bit decision block and the multiplexer cooperate to selectively provide an error signal to the loop filter in response to a bit detected in the in-band communication bit stream. The bit decision block may be responsive to a known bit in the in-band communication bit stream, and the known bit may be a 1 bit. The multiplexer may receive the error signal at a first input and receive the error signal plus an offset signal at a second input. The bit decision block may be responsive to a known bit in the in-band communication bit stream. The multiplexer and the bit decision block and the multiplexer may cooperate to provide the error signal to the loop filter in response to the known bit, and provide the error signal plus the offset signal to the loop filter in response to a bit other than the known bit. The known bit may be a 1 bit, and the bit other than the known bit may be a 0 bit. The known bit may be a 0 bit, and the bit other than the known bit may be a 1 bit.

[0010] A method for recovering a clock from an in-band communication signal in a wireless power transmission system, the method being performed by a communication module of a wireless power transmission device, may include selectively applying an error signal representing a difference between an instantaneous peak position and an estimated peak position associated with a symbol sample of a bit stream of the in-band communication signal to a phase-locked loop. Selectively applying the error signal to the phase-locked loop may include providing the error signal in response to a known bit in the bit stream. The method may also include performing secondary interpolation of multiple samples of the bit stream to improve timing accuracy at low sampling rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A simplified block diagram of a wireless power transfer system is shown.

[0012] Figure 2 An encoding scheme for communication from a wireless power receiver (PRx) to a wireless power transmitter (PTx) is shown.

[0013] Figure 3 A correlator for recovering ASK / Manchester coded communications from a wireless power receiver to a wireless power transmitter is conceptually shown.

[0014] Figure 4 The correlator output is shown, which is shown as above for Figure 2 The difference between the encoded "1" and "0".

[0015] Figure 5 An exemplary bit stream for communication from PRx to PTx is shown.

[0016] Figure 6 An improved clock recovery scheme using a stop bit tracking PLL is shown.

[0017] Figure 7 An improved clock recovery scheme using "1" bit tracking with a decision-directed PLL is shown.

[0018] FIG. 8A to FIG. 8B An improved clock recovery scheme for "1" bit tracking of a decision-directed PLL with offset tracking is shown.

[0019] FIG. 9A to FIG. 9B An improved clock recovery scheme using quadratic interpolation is shown. DETAILED DESCRIPTION

[0020] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the disclosed concepts. As part of this description, some of the drawings in the drawings of the present disclosure represent structures and devices in block diagram form for simplicity. For the sake of clarity, not all features of actual implementations are described in the present disclosure. In addition, the language used in the present disclosure is selected for readability and instructional purposes and has not been selected to describe or limit the disclosed subject matter. Instead, the attached claims are intended for this purpose.

[0021] Various embodiments of the disclosed concepts are described by way of example, and are not limited to individual drawings, in which similar reference numerals indicate similar elements. For simplicity and clarity of description, reference numerals are repeated in different drawings to indicate corresponding or similar elements, where appropriate. In addition, many specific details are shown in order to provide a full understanding of the specific implementation described herein. In other cases, methods, procedures, and components are not described in detail to avoid blurring the related functions described. Mentioning "one", "a kind of" or "another" embodiment in this disclosure is not necessarily the same or different embodiments, and this means at least one. A given drawing may be used to illustrate more than one embodiment or more than one type of features of the present disclosure, and all elements in the drawings may not be required for a given embodiment or type. When provided in a given drawing, the reference numeral refers to the same element throughout several drawings, but it may not be repeated in each drawing. Unless otherwise specified, the drawings are not drawn to scale, and the proportions of certain components may be enlarged to better illustrate the details and features of the present disclosure.

[0022] Figure 1 A simplified block diagram of a wireless power transmission system 100 is shown. The wireless power transmission system includes a power transmitter (PTx) 110 that transmits power wirelessly to a power receiver (PRx) 120, such as via an inductive coupling 130. The power transmitter 110 can receive input power converted into an AC voltage having a specific voltage and frequency characteristic by an inverter 114. The inverter 114 can be controlled by a controller / communication module 116, which operates as described further below. In various embodiments, the inverter controller and the communication module can be implemented in a common system (such as a system based on a microprocessor, a microcontroller, etc.). In other embodiments, the inverter controller can be implemented by a separate controller module and a communication module with a communication device therebetween. The inverter 114 can be constructed using any suitable circuit topology (e.g., full bridge, half bridge, etc.) and can be implemented using any suitable semiconductor switch device technology (e.g., MOSFET, IGBT, etc. manufactured using silicon, silicon carbide, or gallium nitride devices).

[0023] The inverter 114 can deliver the generated AC voltage to the transmitter coil 112. In addition to allowing magnetic coupling to the wireless coil of the receiver, Figure 1 The transmitter coil block 112 shown may include tuning circuits (such as additional inductors and capacitors) that facilitate operation of the transmitter under different conditions (such as different degrees of magnetic coupling to the receiver, different operating frequencies, etc.). The wireless coil itself can be constructed in a variety of different ways. In some embodiments, the wireless coil can be formed as a winding of wire around a suitable bobbin. In other embodiments, the wireless coil can be formed as a trace on a printed circuit board. Other arrangements are also possible and can be used in conjunction with the various embodiments described herein. The wireless transmitter coil may also include a magnetically permeable material (e.g., ferrite) core that is configured to affect the flux pattern of the coil in a manner suitable for a particular application. The teachings herein may be applied in conjunction with any of a variety of transmitter coil arrangements suitable for a given application.

[0024] The PTx controller / communication module 116 may monitor the transmitter coil and use information derived therefrom to control the inverter 114 to suit a given situation. For example, the controller / communication module may be configured to cause the inverter 114 to operate at a given frequency or output voltage depending on the particular application. In some embodiments, the controller / communication module may be configured to receive information from the PRx device and control the inverter 114 accordingly. This information may be received via the power transmission coil (i.e., in-band communication) or may be received via a separate communication channel (not shown, i.e., out-of-band communication). For in-band communication, the controller / communication module 116 may detect and decode signals (such as voltage, frequency, or load changes) applied by the PRx on the magnetic link to receive information, and may instruct the inverter to modulate the delivered power by manipulating various parameters of the generated voltage (such as voltage, frequency, etc.) to transmit information to the PRx. In some embodiments, the controller / communication module may be configured to employ frequency shift keying (FSK) communication to convey data to the PRx, in which the frequency of the inverter signal is modulated. The controller / communication module 116 may be configured to detect amplitude shift keying (ASK) communications or load modulation based communications from the PRx. In either case, the controller / communication module 126 may be configured to vary the current drawn on the receiver side to manipulate the waveform seen on the Tx coil, thereby delivering information from the PRx to the PTx. For out-of-band communications, additional modules may be provided that allow communication between the PTx and PRx, such as WiFi, Bluetooth, or other radio links, or any other suitable communication channel.

[0025] As described above, the controller / communication module 116 can be a single module, for example, disposed on a single integrated circuit, or can be constructed from a plurality of modules / devices disposed on different integrated circuits or a combination of integrated circuits and discrete circuits having analog components and digital components. The teachings herein are not limited to any particular arrangement of controller / communication circuits.

[0026] The PTx device 110 may optionally include other systems and components, such as a separate communication ("comms") module 118. In some embodiments, the communication module 118 may communicate with a corresponding module in the PRx via a power transmission coil. In other embodiments, the communication module 118 may communicate with a corresponding module using a separate physical channel 138. The communication functions described herein may be implemented using a communication module that is part of the combined controller / communication module 116 as described above, or a separate communication module 118.

[0027] As mentioned above, the wireless power transmission system also includes a wireless power receiver (PRx) 120. The wireless power receiver may include a receiver coil 122 that may be magnetically coupled 130 to the transmitter coil 112. As discussed above, the transmitter coil 112, Figure 1 The receiver coil block 122 shown may include tuning circuits (such as additional inductors and capacitors) that facilitate operation of the transmitter under different conditions (such as different degrees of magnetic coupling to the receiver, different operating frequencies, etc.). The wireless coil itself can be constructed in a variety of different ways. In some embodiments, the wireless coil can be formed as a winding of wire around a suitable bobbin. In other embodiments, the wireless coil can be formed as a trace on a printed circuit board. Other arrangements are also possible and can be used in conjunction with the various embodiments described herein. The wireless receiver coil may also include a magnetically permeable material (e.g., ferrite) core that is configured to affect the flux pattern of the coil in a manner suitable for a particular application. The teachings herein may be applied in conjunction with any of a variety of receiver coil arrangements suitable for a given application.

[0028] The receiver coil 122 outputs an AC voltage induced therein by magnetic induction via the transmitter coil 112. The output AC voltage may be provided to a rectifier 124, which provides DC output power to one or more loads associated with the PRx device. The rectifier 124 may be controlled by a controller / communication module 126, which operates as further described below. In various embodiments, the rectifier controller and the communication module may be implemented in a common system (such as a system based on a microprocessor, a microcontroller, etc.). In other embodiments, the rectifier controller may be implemented by a separate controller module and a communication module with a communication device therebetween. The rectifier 124 may be constructed using any suitable circuit topology (e.g., full bridge, half bridge, etc.) and may be implemented using any suitable semiconductor switching device technology (e.g., MOSFETs, IGBTs, etc. manufactured using silicon, silicon carbide, or gallium nitride devices).

[0029] The PRx controller / communication module 126 may monitor the receiver coil and use the information derived therefrom to control the rectifier 124 to suit a given situation. For example, the controller / communication module may be configured to cause the rectifier 124 to provide a given output voltage depending on the particular application. In some embodiments, the controller / communication module may be configured to transmit information to the PTx device to effectively control the power delivered to the receiver. This information may be transmitted via the power transmission coil (i.e., in-band communication) or may be transmitted via a separate communication channel (not shown, i.e., out-of-band communication). For in-band communication, the controller / communication module 126 may, for example, modulate the load current or other electrical parameters of the received power to transmit the information to the PTx. In some embodiments, the controller / communication module 126 may be configured to detect and decode signals (such as voltage, frequency, or load changes) imposed on the magnetic link by the PTx to receive information from the PTx. In some embodiments, the controller / communication module 126 may be configured to receive frequency shift keying (FSK) communications in which the frequency of the inverter signal has been modulated to convey data to the PRx. The controller / communication module 126 may be configured to generate amplitude shift keying (ASK) communications or load modulation based communications from the PRx. In either case, the controller / communication module 126 may be configured to vary the current drawn on the receiver side to manipulate the waveform seen on the Tx coil, thereby delivering information from the PRx to the PTx. For out-of-band communications, additional modules may be provided that allow communication between the PTx and PRx, such as WiFi, Bluetooth, or other radio links, or any other suitable communication channel.

[0030] As described above, the controller / communication module 126 can be a single module, for example, disposed on a single integrated circuit, or can be constructed from a plurality of modules / devices disposed on different integrated circuits or a combination of integrated circuits and discrete circuits having analog components and digital components. The teachings herein are not limited to any particular arrangement of controller / communication circuits. The PRx device 120 may optionally include other systems and components, such as a communication module 128. In some embodiments, the communication module 128 may communicate with a corresponding module in the PTx via a power transmission coil. In other embodiments, the communication module 128 may communicate with a corresponding module or tag using a separate physical channel 138. The communication functionality described herein may be implemented using a communication module that is part of the combined controller / communication module 126 as described above or a separate communication module 128.

[0031] Many variations and enhancements of the wireless power transmission system 100 described above are possible, and the following teachings apply to any of such variations and enhancements.

[0032] As described above, the in-band communication channel can be implemented in various ways. As an example, the PRx device 120 using its associated communication module 128 can use ASK (amplitude shift keying) modulation of the received power / current to send information to the PTx device 110 and its communication module 118. In some implementations, these ASK communications can occur at relatively low data rates (e.g., approximately 1 to 2 kbps). In some implementations, higher data rates, such as approximately 20 kbps, may be desired. When communicating from a relatively low data rate / frequency to a relatively high data rate / communication, certain properties of the physical channel (i.e., the inductive link) may cause problems with communication.

[0033] More specifically, Figure 2 A Manchester / Bi-Phase encoding scheme 200 for communication from a wireless power receiver (PRx) to a wireless power transmitter (PTx) is shown. In the encoding scheme 200, each bit period may include a single digital value 131, which may be either "1" or "0". The start of each bit period, depicted by the vertical solid line 132, will include a transition from low to high or vice versa, regardless of the previous bit value and / or the next bit value. A 0 bit may be encoded using only this start of the bit transition, while a 1 bit may be encoded by an additional transition at the middle of the bit period, represented by the dashed line 133. Thus, a 0 bit will have only the start of the bit transition, while a 1 bit will have the start of the bit transition and an additional intermediate bit transition, as shown in FIG. Figure 2 Therefore, Figure 2The illustrated "1010011100" bit sequence may be encoded by a waveform 134 including transitions as described above. This waveform may be used to modulate the load current / power received by the PRx 120 to communicate information back to the PTx 110.

[0034] Applying the above coding scheme will generate a square wave with a frequency equal to the data rate of the stream of all 1 bits, and a square wave with half the sampling rate of the stream of all 0 bits. Therefore, for a 2kbps data rate, a stream of all 1s will generate something similar to a 2kHz square wave, and a stream of all 0s will generate something similar to a 1kHz square wave. Similarly, for a data rate of 20kbps, a stream of all 1s will generate a square wave similar to 20kHz, and a stream of all 0s will generate a square wave similar to 10kHz. The inductive link between PTx110 and PRx 120, as the physical channel of these communication signals, can be characterized as a low-pass filter. In the case of lower data rates, the difference between 1 and 0 bits may not be substantially changed by the physical channel. However, this may not be the case in the case of higher data rates, where the low-pass nature of the physical channel may result in significant differences in both the gain and phase of the corresponding symbols. For example, the higher frequency content associated with a 1 bit may result in a lower amplitude and phase shift relative to a 0 bit.

[0035] Such differences between symbols can affect communications, including clock recovery. More specifically, the PTx 110 (e.g., via its communication module 118) may have a clock signal for decoding the received data stream. However, the clock may have a relatively large tolerance (e.g., + / - 3%), which may cause problems if the clock is sufficiently different from and / or drifts relative to the clock signal used by the PRx 120 (and its communication module 128) to generate the data stream. Based on an exemplary 3% tolerance, a 20 kbps data rate may actually be between 19.4 kbps and 20.6 kbps. Because the divergence of the corresponding transmitter and receiver clocks may make it impossible to successfully decode communications, it is desirable that a method by which the PTx 120 / communication module 118 can recover the clock from the received data signal. One technique for doing so may include the use of a phase-locked loop (PLL).

[0036] Figure 3 Conceptually shown is the recovery of ASK / Manchester encoded communications from a wireless power receiver to a wireless power transmitter. Figure 3A graph 300 is included showing a single half cycle of a sine wave corresponding to a filtered correlator output signal. Low pass filtering the square wave may produce a substantially sinusoidal signal. The correlator circuit may be implemented using any suitable combination of analog, digital and / or programmable circuits and may be part of the communication module 118 of the PTx device 110. Although shown as a continuous waveform, the received signal is actually a sequence of samples. The sampling rate may vary, although it must generally be slightly higher than the data rate. For example, for a data rate of 20 kpbs, a sampling rate of approximately 200 kS / s (thousand samples per second) may result in approximately 10 samples per bit period. These 10 samples may then be analyzed to detect a peak. The peak may be detected on time 335b, meaning that the actual timing of the peak corresponds to the detection timing of the peak. Alternatively, the peak may be detected earlier 335a, meaning that the actual timing of the peak is later than the detection timing of the peak; or the peak may be detected later 335c, meaning that the actual timing of the peak is earlier than the detection timing of the peak. In either of the latter two cases, the detected value will be lower than the actual peak, resulting in a lower signal-to-noise ratio (SNR). To overcome this, a phase-locked loop (PLL) can be used to compensate for errors in peak detection (early or late) and adjust the clock signal accordingly to remain in phase with the received signal.

[0037] However, as described above, phase effects of the inductive power transmission channel may cause the peak value associated with a 0 bit to shift from the peak value associated with a 1 bit. Figure 4 The correlator output 400 is shown, which shows the same as described above with respect to Figure 2 The difference between the "1" and "0" encoded in the above. Specifically, the received signal may be subjected to IQ decomposition, which may produce an I component 136 and a Q component 137. Because the inductive power transmission channel exhibits low-pass characteristics, such as lower gain at higher frequencies, and the encoded 1 bit includes a higher frequency component, the 1 bit is associated with a smaller peak 136b, while the 0 bit is associated with a larger peak 136a. In addition, there may also be a phase shift between the peak (136b) associated with the 1 bit and the peak (136a) associated with the 0 bit. In a bit stream containing an arbitrary sequence of 1 bits and 0 bits, this phase difference between the corresponding peaks may cause difficulties for a PLL used as part of a clock recovery process. In some cases, the PLL may not be able to maintain synchronization, and successful decoding of the communication may become impossible. In order to overcome this problem, one or more of the following modified PLL implementations may be adopted. Each of these modifications may utilize known characteristics of the bit stream, as described in more detail below.

[0038] Figure 5An exemplary bitstream 500 for communication from PRx to PTx is shown. This bitstream may be specified in a standard such as the Qi wireless power transfer standard published by the Wireless Power Consortium. In other cases, a device may implement the bitstream syntax according to an alternative specification, which may be an industry standard or a proprietary protocol definition. For the purposes of the following discussion, the bitstream syntax specified in the Qi standard will be used. Figure 5 The bit stream format is as follows. Figure 5 As shown, the bit stream 500 may include a preamble 541 followed by a series of packets. Each packet may include a start bit 543, a payload 545 (8 bits in this case), a parity bit 547, and a stop bit 549. In the example shown, the preamble 541 is a sequence of 1 bits (e.g., eleven consecutive 1 bits). The start bit may be defined as zero, as specified in the Qi standard. The payload 545 may be an arbitrary sequence of 8 bits. The subsequent parity bit 547 may be determined based on the value of the previous 8 bits and may be used to detect transmission or decoding errors. Finally, the stop bit 549 may be defined as always 1. Therefore, for each packet of eleven bits, there will be a known start bit of zero, nine arbitrary bits (i.e., eight data bits and one parity bit), and a stop bit of 1. These known characteristics of the bit stream may be used to enhance the performance of the PLL in various ways described below.

[0039] Figure 6 An improved clock recovery scheme using a stop bit tracking PLL 600 is shown. The stop bit tracking PLL 600 may include a phase detector 651. The phase detector 651 may receive an instantaneous peak position at one input. The phase detector 651 may also receive an estimated peak position associated with a symbol sample at a second input. The difference between the two may be an error signal e. In a conventional PLL, the error signal e may be provided to a loop filter 653, wherein the output of the loop filter 653 is provided to a voltage controlled oscillator (VCO) 655, the output frequency of which is controlled by the output voltage of the loop filter 653. Although the principles described herein will also apply to other VCO types, in the example shown herein, the VCO is implemented as a discrete time VCO. The implementation of such a phase locked loop, filter and VCO in analog, digital and / or mixed domains is known to those skilled in the art, and therefore will not be repeated here.

[0040] The stop bit tracking PLL 600 differs from a conventional PLL in that the error signal from the phase detector 651 is only intermittently or periodically applied to the loop filter 653. More specifically, the error signal e, which is the output of the phase detector 651, can be provided to one input of a multiplexer 659. A zero value can be provided to another input of the multiplexer 659. The multiplexer 659 can be controlled by a stop bit decision block 657. The stop bit decision block 657 can be implemented using digital circuits and / or programmable circuits that monitor the received and decoded bit stream. For example, the stop bit decision block 657 can be implemented as part of the communication module 118 of the PTx device 110. The stop bit decision block 657 can monitor the decoded bit stream to determine when the stop bit 549 is detected and trigger the multiplexer 659 to switch its output from a zero value binary state at its first input to an error signal at its second input. The effect of this configuration is that the error signal from phase detector 651 will trigger an adjustment to the PLL clock output from VCO 655 only on stop bit 549. As described above, stop bit 549 always has a value of 1. Thus, the PLL will only respond to error signals associated with a 1 bit, so the relative phase offset between a 1 bit and a 0 bit will not adversely affect PLL tracking.

[0041] References Figure 6 The system described can be modified to adjust the PLL only on bit 0 instead of only on bit 1. For example, Figure 5 The known start bit 543 shown may be detected by the start bit decision block instead of the stop bit decision block 657. In the above decoding scheme, tracking of the 1 bit may be more advantageous because the 0 bits have a higher signal-to-noise ratio due to their lower frequency content and the increased gain of the induced power channel's low-pass effect. Therefore, any phase tracking error associated with the peak detection of the 0 bit based on feedback from the 1 bit to the PLL will be less likely to cause a decoding error than the reverse case. However, for the reference Figure 2 A zero tracking configuration may be preferred for coding schemes that are different from the ones described and / or for systems where the communication channels exhibit different characteristics.

[0042] Figure 7An improved clock recovery scheme using "1" bit tracking with a decision-directed PLL 700 is shown. The decision-directed PLL 700 may include a phase detector 751. The phase detector 751 may receive an instantaneous peak position at one input. The phase detector 751 may also receive an estimated peak position associated with a symbol sample at a second input. The difference between the two may be an error signal e. In a conventional PLL, the error signal e may be provided to a loop filter 753, wherein the output of the loop filter 753 is provided to a voltage-controlled oscillator (VCO) 755, the output frequency of which is controlled by the output voltage of the loop filter 753. Although the principles described herein will also apply to other VCO types, in the example shown herein, the VCO is implemented as a discrete time VCO. The implementation of such a phase-locked loop, filter, and VCO in analog, digital, and / or hybrid domains is known to those skilled in the art, and therefore will not be repeated here.

[0043] The decision-directed PLL 700 differs from a conventional PLL in that the error signal from the phase detector 751 is only intermittently or periodically applied to the loop filter 753. More specifically, the error signal e, which is the output of the phase detector 751, may be provided to one input of a multiplexer 759. A zero value may be provided to another input of the multiplexer 759. The multiplexer 759 may be controlled by a bit decision block 757. The bit decision block 757 may be implemented using a digital circuit and / or a programmable circuit that monitors a received and decoded bit stream. For example, the bit decision block 757 may be implemented as part of the communication module 118 of the PTx device 110. The bit decision block 757 may monitor the decoded bit stream to determine when any 1 bit is detected and trigger the multiplexer 759 to switch its output from a zero value binary state at its first input to an error signal at its second input. The effect of this configuration is that the error signal from the phase detector 751 will trigger adjustments to all 1 bits of the PLL clock output from the VCO 755, not just the stop bit 549 as in the above-described embodiment. Thus, the PLL will only respond to error signals associated with 1 bits, so the relative phase offset between 1 bits and 0 bits will not adversely affect PLL tracking, but the increased frequency of 1 bits relative to only stop bits can allow the PLL to have improved tracking relative to the above-described embodiment. In contrast to the stop bit detector, this may be at the expense of increased complexity of the bit decision block 757, since 1 bits can be detected, rather than just stop bits at packet boundaries.

[0044] and Figure 6 The same implementation scheme as above reference Figure 7 The described system may be modified to adjust the PLL only on bit 0 instead of only bit 1, which may be advantageous in systems with different coding schemes, packet structures, and / or channel characteristics.

[0045] FIG. 8A to FIG. 8B An improved clock recovery scheme for "1" bit tracking of a decision-directed PLL with offset tracking is shown. Fig. 8A A block diagram of a modified decision-directed / excursion tracking PLL 800a is shown. Figure 8B An offset tracking feature for tracking the offset between a 1-bit and a 0-bit is shown. The decision-directed / offset tracking PLL 800a may include a phase detector 851. The phase detector 851 may receive an instantaneous peak position at one input. The phase detector 851 may also receive an estimated peak position associated with a symbol sample at a second input. The difference between the two may be an error signal e. In a conventional PLL, the error signal e may be provided to a loop filter 853, wherein the output of the loop filter 853 is provided to a voltage-controlled oscillator (VCO) 855, the output frequency of which is controlled by the output voltage of the loop filter 853. Although the principles described herein will also apply to other VCO types, in the example shown herein, the VCO is implemented as a discrete time VCO. The implementation of such a phase-locked loop, filter, and VCO in analog, digital, and / or hybrid domains is known to those skilled in the art, and therefore will not be repeated here.

[0046] The decision-directed / offset tracking PLL 800a differs from a conventional PLL in that the error signal from the phase detector 851 is only intermittently or periodically applied to the loop filter 853. More specifically, the error signal e, which is the output of the phase detector 851, may be provided to one input of a multiplexer 859. An incremental value e+ may be provided to another input of the multiplexer 859. The incremental value may be a determined phase offset between a 1 bit and a 0 bit, which may be determined as described below. The multiplexer 859 may be controlled by a bit decision block 857. The bit decision block 857 may be implemented using digital circuits and / or programmable circuits that monitor the received and decoded bit stream. For example, the bit decision block 857 may be implemented as part of the communication module 118 of the PTx device 110. The bit decision block 857 may monitor the decoded bit stream to determine when any 1 bit is detected and trigger the multiplexer 859 to switch its output from a zero-value binary state at its first input to an error signal at its second input. The effect of this configuration is that the error signal from the phase detector 851 will trigger an adjustment to the PLL clock output from the VCO 755 based on the error signal e on all 1 bits from the phase detector 851. Similarly, the zero bit will trigger an adjustment to the PLL clock output based on the e+increment / offset error signal. Therefore, the PLL will only respond to the error signal associated with both the 1 bit and the 0 bit, where the offset is taken into account so that the relative phase offset between the 1 bit and the 0 bit will not adversely affect the PLL tracking. This configuration can also allow for improved PLL tracking at the expense of increased complexity of the bit decision block 857.

[0047] As described above, the decision-directed / offset tracking PLL 800a can determine the offset 839 between the 0 bit and the 1 bit, such as Figure 8B shown. Figure 8B Including corresponding to the above reference Figure 4 Graph 800b of an IQ signal of the output of the correlator in question. Graph 836 represents the "I" signal and graph 837 represents the "Q" signal. A 1 bit is represented by a lower amplitude / higher frequency sine wave and a 0 bit is represented by a higher amplitude / lower frequency sine wave. As described above, the system can learn the offset 839 between the peaks of the 1 bit and the 0 bit. One way to do this is to use known characteristics of the bit stream to measure / learn the offset 839 between the 0 bit and the 1 bit. For example, using Figure 5 , and described above, it is known that the start bit 543 will always be a 0 bit, followed by a 1 bit (or a string of 1 bits) from the preamble 541. Similarly, for subsequent packets, a start bit with a value of 0 is always followed by a stop bit with a value of 1. These known characteristics of the bit stream can be used to identify a phase offset between a 1 bit and a 0 bit, which can be provided to the multiplexer 859 and selectively provided to the loop filter 853, as described above. In an alternative embodiment, the bit stream structure / grammar can be modified so that the preamble sequence (rather than all 1 bits as shown) can be alternating 1 bits and 0 bits. Therefore, the preamble itself can be used for offset learning.

[0048] and Figure 6 The same implementation scheme as above reference Figure 7 The described system can be modified to adjust the PLL only on the 0 bit instead of only on the 1 bit, which may be advantageous in systems with different coding schemes, packet structures and / or channel characteristics. Such a system may be useful in high signal-to-noise ratio schemes. In this case, the bit decision block 857 and the multiplexer can operate in a manner opposite to that described above with respect to the bit decision block 757 (i.e., the bit decision block 857 can detect the zero bit and apply the detected offset in this case), while responding to the 1 bit without applying an offset or applying a pre-learned offset.

[0049] In some applications, the bit decision block and multiplexer may be configured to provide adaptive operation depending on channel conditions, etc. For example, a programmable bit decision block may be provided that is selectively configurable to detect a stop bit, a start bit, all 1 bits, all 0 bits, or to distinguish between 1 and 0 bits. Such a configurable bit decision block may selectively trigger a multiplexer that receives an offset measurement and an additional offset value and / or a zero error value from a phase detector. The configurable bit decision block may cause the multiplexer to selectively apply a measured error, a predetermined offset error, and / or a zero error signal to cause the loop filter to track any of these values. Thus, optimized offset error correction may be applied regardless of operating conditions.

[0050] FIG. 9A to FIG. 9B An improved clock recovery scheme using quadratic interpolation is shown. In addition to the phase offset problem described above, another clock recovery problem that may occur in a wireless power transmission system involves a limited sampling rate. The primary function of a wireless power transmission system is the delivery of power. In-band communication between PRx and PTx is a necessary but auxiliary function. Therefore, in many applications, it may be desirable to limit things such as the sampling rate of the received in-band communication signal by the PTx communication module to reduce the power consumption of sampling and subsequent processing of the sampled data. However, this reduced sampling rate may make it more difficult to successfully recover the unknown timing of the bit stream received from PRx. One way to solve this problem is to provide a quadratic interpolation of the received samples. This quadratic interpolation can be applied independently of or in combination with any of the above-mentioned phase offset compensation techniques.

[0051] Fig.9A PLL 900a used with interpolation scheme is shown. Interpolation PLL 900a may include phase detector 951. Phase detector 951 may receive instantaneous peak position at one input. Phase detector 951 may also receive an estimated peak position associated with symbol sampling at a second input. The difference between the two may be an error signal e. As in a conventional PLL, error signal e may be provided to loop filter 953, wherein the output of loop filter 953 is provided to voltage controlled oscillator (VCO) 955, the output frequency of which is controlled by the output voltage of loop filter 953. Although the principles described herein will also apply to other VCO types, in the example shown herein, the VCO is implemented as a discrete time VCO. The implementation of such phase-locked loop, filter and VCO in analog, digital and / or mixed domains is known to those skilled in the art, so it will not be repeated here. In any case, the output of VCO 955 may be used to specify the sampling instant of the interpolated symbol value from the correlator as described above.

[0052] In some embodiments, quadratic interpolation may be employed. That is, using known analysis techniques, the three sample points may have a quadratic curve fitted to them. More specifically, the general quadratic form is y=ax 2 +bx+c. By inserting the three sample values ​​and their sampling times, the resulting system of three formulas can be used to solve for the three coefficients a, b, and c. The inventors have observed that quadratic interpolation provides a good balance between computational tractability / performance and accuracy. However, in some applications, interpolation using lower order (e.g., linear) or higher order (cubic, quartic, etc.) polynomials may be employed. Likewise, in some cases, fits other than polynomial curves may be appropriate.

[0053] The quantization problem caused by low sampling rate can be referred to Fig. 9B To understand, Fig. 9B 961 and 962 show PLL traces without interpolation and with interpolation. Using the above example bit rate of 20 kbps and a sample rate of 200 ksamples / sec, a nominal sample rate of 10 bits per sample is expected. However, due to timing tolerances / errors, the deviation between the measured rate and the actual rate will vary. For example, if the sample clock and bit stream clock deviations are such that there are 10.2 samples per bit on average, there may be a sequence of four bits with 10 samples followed by a bit with 11 samples. This may manifest itself as Fig. 9B 961, where the symbols exhibit periodic jumps 963, 964, 965, 966. This results in "jitter" in the effective sampling time. In contrast, by applying the above-described interpolation, a smoother track can be achieved as shown in graph 962.

[0054] Various features and embodiments of timing recovery in wireless power transmission systems are described above. Such arrangements can be used in a variety of applications, but can be particularly advantageous when used in conjunction with electronic devices (such as mobile phones, tablet computers, laptops or notebook computers) and accessories (such as wireless headsets, styluses, etc.). In addition, although many specific features and various embodiments have been described, it should be understood that various features and embodiments can be arranged and combined in various combinations in specific implementations unless otherwise specified as mutually exclusive. Therefore, the various embodiments described above are provided only by way of example and should not be interpreted as limiting the scope of the present disclosure. Various modifications and changes may be made to the principles and embodiments of this document without departing from the scope of the present disclosure and without departing from the scope of the claims.

[0055] The above describes an exemplary embodiment of a wireless power transmission system capable of transmitting certain information between a PTx and a PRx in a wireless power transmission system. The present disclosure contemplates that the transfer of specific information improves the ability of devices to provide wireless power signals to each other in an efficient manner to facilitate battery charging, such as by providing power feedback control data packets. To the extent that any sensitive information is used in a particular implementation, entities implementing the present technology should be careful to ensure compliance with established privacy policies and / or privacy practices. In particular, such entities will be expected to implement and consistently apply privacy practices that are generally recognized as meeting or exceeding the requirements of the industry or government that maintain user privacy. In addition, implementers should inform users where personally identifiable information is expected to be sent in the wireless power transmission system, and allow users to "opt-in" or "opt-out" participation. For example, if a power transmitter is configured to poll sensitive information from a power receiver, such information may be presented to the user when the user places the device on the power transmitter.

[0056] Risks can be minimized by limiting the collection of data and deleting data once it is no longer needed. In addition, and when applicable, data de-identification can be used to protect the privacy of users. For example, a device identifier can be partially masked to convey the power characteristics of a device without uniquely identifying the device. De-identification can be facilitated by removing identifiers, controlling the amount or specificity of stored data (e.g., collecting location data at a city level rather than an address level), controlling how data is stored (e.g., aggregating data across users), and / or other methods such as differential privacy, where appropriate. Robust encryption can also be used to reduce the likelihood that communications between inductively coupled devices can be spoofed.

Claims

1. A clock recovery system for recovering an in-band communication clock in a wireless power transmission system, the clock recovery system comprising: A phase-locked loop, the phase-locked loop comprising: a phase detector that calculates an error signal based on a difference between an instantaneous peak position and an estimated peak position associated with a symbol in an in-band communication bit stream; a loop filter that selectively receives the error signal; and a voltage controlled oscillator that adjusts an output frequency of the voltage controlled oscillator in response to an output of the loop filter; and A bit decision block and a multiplexer cooperate to selectively provide the error signal to the loop filter in response to a detected bit in the in-band communication bit stream.

2. The clock recovery system according to claim 1, wherein: The multiplexer receives the error signal at a first input and receives a zero signal at a second input; The bit decision block is responsive to known bits in the in-band communication bit stream; and The bit decision block and the multiplexer cooperate to provide the error signal to the loop filter in response to the known bit and to provide the zero signal to the loop filter in response to a bit other than the known bit.

3. The clock recovery system of claim 2, wherein the known bit is a stop bit. The clock recovery system of claim 2 , wherein the known bit is 1 bit. The clock recovery system of claim 2 , wherein the known bit is a 0 bit.

6. The clock recovery system according to claim 1, wherein: The multiplexer receives the error signal at a first input and receives the error signal plus an offset signal at a second input; The bit decision block is responsive to known bits in the in-band communication bit stream; and The bit decision block and the multiplexer cooperate to provide the error signal to the loop filter in response to the known bit, and to provide the error signal plus the offset signal to the loop filter in response to a bit other than the known bit. 7 . The clock recovery system of claim 6 , wherein the known bit is a 1 bit, and bits other than the known bit are 0 bits.

8. The clock recovery system of claim 6, wherein the known bit is a 0 bit, and bits other than the known bit are a 1 bit.

9. The clock recovery system of claim 1, wherein the phase-locked loop and the bit decision block are implemented using digital circuits.

10. The clock recovery system of claim 1, wherein the phase-locked loop and the bit decision block are implemented using programmable circuits.

11. A clock recovery system for recovering an in-band communication clock in a wireless power transmission system, the clock recovery system comprising: A phase-locked loop, the phase-locked loop further comprising: a phase detector that calculates an error signal based on a difference between an instantaneous peak position and an estimated peak position associated with a symbol in an in-band communication bit stream; a loop filter that selectively receives the error signal; and a voltage controlled oscillator that adjusts its output frequency in response to an output of the loop filter; and An interpolation block applies interpolation to a plurality of samples of the in-band communication bitstream to improve timing accuracy at low sampling rates.

12. The clock recovery system of claim 11, wherein the interpolation is a quadratic interpolation.

13. The clock recovery system according to claim 11, further comprising: A bit decision block and a multiplexer cooperate to selectively provide the error signal to the loop filter in response to a detected bit in the in-band communication bit stream.

14. The clock recovery system of claim 13, wherein the bit decision block is responsive to a known bit in the in-band communication bit stream, and the known bit is a 1 bit.

15. The clock recovery system of claim 13, wherein: The multiplexer receives the error signal at a first input and receives the error signal plus an offset signal at a second input; The bit decision block is responsive to known bits in the in-band communication bit stream; and The bit decision block and the multiplexer cooperate to provide the error signal to the loop filter in response to the known bit, and to provide the error signal plus the offset signal to the loop filter in response to a bit other than the known bit.

16. The clock recovery system of claim 15, wherein the known bit is a 1 bit, and bits other than the known bit are 0 bits.

17. The clock recovery system of claim 15, wherein the known bit is a 0 bit, and bits other than the known bit are a 1 bit.

18. A method for recovering a clock from an in-band communication signal in a wireless power transmission system, the method being performed by a communication module of a wireless power transmission device and comprising selectively applying an error signal representing a difference between an instantaneous peak position and an estimated peak position associated with symbol samples of a bit stream of the in-band communication signal to a phase-locked loop.

19. The method of claim 18, wherein selectively applying the error signal to the phase locked loop comprises providing the error signal in response to a known bit in the bit stream.

20. The method of claim 18, further comprising performing secondary interpolation on a plurality of samples of the bitstream to improve timing accuracy at low sampling rates.

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