Solar cell, photovoltaic module and manufacturing method of solar cell

Abstract

The invention discloses a solar cell, a photovoltaic module and a manufacturing method of the solar cell, relates to the technical field of solar cells, and aims to solve the problem of poor passivation effect of the solar cell. The solar cell includes a semiconductor substrate. A plurality of polygonal structures are arranged on at least one surface of the semiconductor substrate, and the orthographic projection of each polygonal structure on the semiconductor substrate comprises at least two sides which are relatively distributed in parallel. At least part of the polygonal structures are arranged along a first straight line, an included angle A is formed between the extension direction of the first straight line and the extension direction of two relatively parallel sides included by the orthographic projection of any polygonal structure on the semiconductor substrate, and 0 degree < = A < = 90 degrees. In the surfaces with the polygonal structures, the planes where the surfaces except the polygonal structures are located are horizontal planes, and the polygonal structures are sunken relative to the horizontal planes.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell, a photovoltaic module and a method for manufacturing a solar cell. Background Art

[0002] A solar cell is a device that utilizes solar energy and directly converts light energy into electrical energy through the photoelectric effect.

[0003] Current solar cells mainly include IBC cells (Interdigitated Back Contact), TOPCON (Tunnel Oxide Passivated Contact), PERC cells (Passivated emitter and real cell), heterojunction cells and bifacial solar cells.

[0004] At present, how to improve the passivation effect of solar cells is a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0005] The object of the present invention is to provide a solar cell, a photovoltaic module and a method for manufacturing a solar cell, so as to improve the passivation effect of the solar cell.

[0006] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a solar cell. The solar cell comprises: a semiconductor substrate. A plurality of polygonal structures are provided on at least one surface of the semiconductor substrate, and the orthographic projection of the polygonal structure on the semiconductor substrate comprises at least two relatively parallel edges. At least some of the polygonal structures are arranged along a first straight line, and an angle A is formed between an extension direction of the first straight line and an extension direction of two relatively parallel edges included in the orthographic projection of any polygonal structure on the semiconductor substrate, and 0°≤A≤90°. Among the surfaces having polygonal structures, the plane on which the surface other than the polygonal structures is located is a horizontal plane, and the polygonal structures are recessed relative to the horizontal plane.

[0007] In the solar cell provided by the present invention, compared with the surface with polygonal structures being a horizontal plane, the surface with multiple polygonal structures recessed relative to the horizontal plane in the present invention has a larger specific surface area. At this time, not only can the adhesion of the passivation layer formed on the surface later be enhanced, and the passivation effect of the solar cell be improved; at the same time, the refraction of light can be improved, so that more light is transmitted to the semiconductor substrate of the solar cell, and the light trapping effect is improved, thereby improving the photoelectric conversion efficiency of the solar cell. Further, since at least part of the polygonal structures are arranged along the first straight line, there is an angle A between the extension direction of the first straight line and the extension direction of the two relatively parallel sides included in the positive projection of any polygonal structure on the semiconductor substrate, 0°≤A≤90°. Compared with at least part of the polygonal structures being arranged along the extension direction of the diagonal lines of the polygonal structures, at least part of the polygonal structures arranged along the first straight line in the present application have more uniform undulations, and at this time, the passivation layer subsequently formed on the surface with multiple polygonal structures has better compactness, which can further improve the passivation effect of the solar cell.

[0008] In one implementation, the orthographic projection of the polygonal structure on the semiconductor substrate is a quadrilateral, and the angle between any two adjacent sides of the quadrilateral is a right angle.

[0009] When the above technical solution is adopted, the specific surface area of ​​the surface with multiple polygonal structures can be further increased. At this time, not only can the adhesion of the passivation layer formed on the surface later be further enhanced, so as to further improve the passivation effect of the solar cell, but also the refraction of light can be further improved, so that more light can be transmitted to the semiconductor substrate of the solar cell, so as to further improve the light trapping effect, improve the utilization rate of light by the semiconductor substrate, and thus improve the photoelectric conversion efficiency of the solar cell.

[0010] In one implementation, the surface with the polygonal structure is a side surface of the semiconductor substrate; and / or the surface with the polygonal structure is a light-facing surface or a backlight surface of the semiconductor substrate.

[0011] In one implementation, at least two adjacent polygonal structures have overlapping portions.

[0012] When the above technical solution is adopted, the passivation layer formed on the surface with the polygonal structure later is more uniform, the film formation quality of the passivation layer is better, and the density of the passivation layer is better, thereby improving the passivation effect of the solar cell.

[0013] In one implementation, at least two adjacent polygonal structures are spaced apart from each other.

[0014] When the above technical solution is adopted, since at least two adjacent polygonal structures are spaced apart, there are undulations between the two adjacent polygonal structures. This can improve the light trapping effect of the surface, improve the utilization rate of light by the semiconductor substrate, and thus improve the photoelectric conversion efficiency of the solar cell.

[0015] In one implementation, at least two adjacent polygonal structures have an overlapping portion, and at least two adjacent polygonal structures are spaced apart.

[0016] When the above technical solution is adopted, combined with the above description, compared with the prior art, not only the passivation effect of the solar cell can be improved, but also the photoelectric conversion efficiency of the solar cell can be improved. In other words, the passivation effect and the photoelectric conversion efficiency of the solar cell can be taken into account. Moreover, it can be set according to actual needs to expand the scope of application of the solar cell and meet different needs.

[0017] In one implementation, along a direction going deeper into the interior of the semiconductor substrate, the polygonal structure has a top opening and a bottom surface that are relatively arranged, and a side wall located between the bottom surface and the top opening, and the orthographic projection area of ​​the top opening on the semiconductor substrate is larger than the orthographic projection area of ​​the bottom surface on the semiconductor substrate.

[0018] In the case of adopting the above technical solution, the orthographic projection area of ​​the top opening on the semiconductor substrate is larger than the orthographic projection area of ​​the bottom surface on the semiconductor substrate, which is conducive to the film layer being uniformly filled with the polygonal structure when the film layer is formed on the semiconductor substrate later, avoiding the formation of gaps between the film layer and the polygonal structure, while reducing the number of defects of the solar cell, improving the uniformity of the film layer and the film forming quality. Exemplarily, when the film layer formed on the semiconductor substrate later is a passivation layer, the formed passivation layer can be made more uniform, the film forming quality of the passivation layer is better, and the density of the passivation layer is better, thereby improving the passivation effect of the solar cell. Further, when the orthographic projection area of ​​the top opening on the semiconductor substrate is larger than the orthographic projection area of ​​the bottom surface on the semiconductor substrate, it is conducive to further increasing the specific surface area of ​​the surface having multiple polygonal structures that are concave relative to the horizontal plane. At this time, not only can the adhesion of the passivation layer formed on the surface later be further enhanced, thereby further improving the passivation effect of the solar cell; at the same time, the refraction of light can be further improved, so that more light is transmitted to the semiconductor substrate of the solar cell, so as to further improve the light trapping effect, improve the utilization rate of the semiconductor substrate for light, thereby improving the photoelectric conversion efficiency of the solar cell.

[0019] In one implementation, the solar cell further includes: a doped conductive layer and a passivation layer sequentially stacked on the surface of the semiconductor substrate.

[0020] When the above technical solution is adopted, the doped conductive layer plays a field passivation effect. Specifically, an electrostatic field pointing to the inside of the semiconductor substrate is formed on the surface of the semiconductor substrate, so that minority carriers escape from the interface, thereby reducing the minority carrier concentration, so that the carrier recombination rate at the interface of the semiconductor substrate is reduced, thereby increasing the open circuit voltage, short circuit current and fill factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0021] In one implementation, the solar cell further includes: a texture structure formed on the polygonal structure, the doped conductive layer has a first hole penetrating the doped conductive layer, at least part of the first hole corresponds to the texture structure, and the passivation layer fills the first hole and covers the texture structure.

[0022] When the above technical solution is adopted, the above texture structure and the first hole are both conducive to light trapping, so that more light is transmitted to the semiconductor substrate of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0023] In one implementation, the texture structure is a pyramid-shaped texture structure; and / or a one-dimensional size of the first hole is greater than or equal to 1 nm and less than or equal to 10 μm.

[0024] When the above technical solution is adopted, the pyramid-shaped texture structure has a large specific surface area and has a light trapping effect. Therefore, when the texture structure is a pyramid-shaped texture structure, more light can be transmitted to the semiconductor substrate through the pyramid-shaped texture structure, so that the solar cell has a higher photoelectric conversion efficiency.

[0025] In one implementation, the doped conductive layer includes any one or more stacked combinations of a doped polysilicon layer, a doped amorphous silicon layer, and a doped microcrystalline silicon layer. The passivation layer includes any one or more stacked combinations of a silicon oxide passivation layer, an aluminum oxide passivation layer, a silicon oxynitride passivation layer, and a silicon nitride passivation layer.

[0026] In one implementation, the length of the orthographic projection of the polygonal structure on the semiconductor substrate is greater than or equal to 10 μm and less than or equal to 100 μm; the length direction of the polygonal structure is consistent with the extension direction of two relatively parallel sides included in the orthographic projection of the polygonal structure on the semiconductor substrate;

[0027] And / or, the width of the orthographic projection of the polygonal structure on the semiconductor substrate is greater than or equal to 10 μm and less than or equal to 100 μm; the width direction of the polygonal structure is perpendicular to the extension direction of two relatively parallel sides included in the orthographic projection of the polygonal structure on the semiconductor substrate;

[0028] And / or, the depth of the polygonal structure is greater than or equal to 0.5 μm and less than or equal to 5 μm; and the depth direction of the polygonal structure is consistent with the direction vertically penetrating into the interior of the semiconductor substrate.

[0029] In one implementation, the solar cell further includes: a first doped semiconductor layer and a second doped semiconductor layer disposed on the first surface of the semiconductor substrate; the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. And a first dielectric layer located between the semiconductor substrate and the first doped semiconductor layer, and a second dielectric layer located between the semiconductor substrate and the second doped semiconductor layer. The first dielectric layer is a first tunneling layer, and the first doped semiconductor layer includes a doped polycrystalline silicon layer. The second dielectric layer is an intrinsic amorphous silicon layer, and the second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer.

[0030] When the above technical solution is adopted, the above solar cell is a hybrid back contact cell.

[0031] In one implementation, the solar cell further includes: a first doped semiconductor layer and a second doped semiconductor layer disposed on the first surface of the semiconductor substrate; the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. And a third dielectric layer located between the semiconductor substrate and the first doped semiconductor layer, and a fourth dielectric layer located between the semiconductor substrate and the second doped semiconductor layer. The third dielectric layer is a second tunneling layer, the first doped semiconductor layer includes an N-type doped polysilicon layer; the fourth dielectric layer is a third tunneling layer, and the second doped semiconductor layer includes a P-type doped polysilicon layer.

[0032] When the above technical solution is adopted, the above solar cell is a tunneling oxidation passivation back contact cell.

[0033] In summary, different materials can be selected to make the dielectric layer and the doped semiconductor layer according to the type of solar cell actually required, so as to expand the application scope and application scenarios of the solar cell.

[0034] In a second aspect, the present invention further provides a photovoltaic module, which includes a battery string and a packaging layer, wherein the battery string is formed by connecting a plurality of solar cells described in the above technical solution, and the packaging layer is used to cover the surface of the battery string.

[0035] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the present invention are the same as the beneficial effects of the solar cell described in the above technical solution, which will not be described in detail here.

[0036] In a third aspect, the present invention further provides a method for manufacturing a solar cell. The method for manufacturing a solar cell comprises:

[0037] First, a semiconductor substrate is provided;

[0038] Next, the semiconductor substrate is processed so that at least one surface of the semiconductor substrate has a plurality of polygonal structures;

[0039] The orthographic projection of the polygonal structure on the semiconductor substrate includes at least two relatively parallel sides; at least part of the polygonal structures are arranged along a first straight line, and an angle A is formed between the extension direction of the first straight line and the extension direction of two relatively parallel sides included in the orthographic projection of any polygonal structure on the semiconductor substrate; 0°≤A≤90°. In the surface with polygonal structures, the plane where the surface other than the polygonal structures is located is a horizontal plane, and the polygonal structures are recessed relative to the horizontal plane.

[0040] Compared with the prior art, the beneficial effects of the method for manufacturing a solar cell provided by the present invention are the same as the beneficial effects of the solar cell described in the above technical solution, and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0042] Figure 1 This is a SEM image of a surface with a polygonal structure in an embodiment of the present invention. Figure 1 ;

[0043] Figure 2 This is a SEM image of a surface with a polygonal structure in an embodiment of the present invention. Figure 2 ;

[0044] Figure 3 is a SEM cross-sectional view of a polygonal structure in an embodiment of the present invention;

[0045] Figure 4 A schematic cross-sectional view of a polygonal structure in an embodiment of the present invention;

[0046] Figure 5 A schematic diagram of a combination of a texture structure, a first hole and a polygonal structure in an embodiment of the present invention;

[0047] Figure 6 A cross-sectional view of a solar cell during the manufacturing process provided by an embodiment of the present invention Figure 1 ;

[0048] Figure 7 A cross-sectional view of a solar cell during the manufacturing process provided by an embodiment of the present invention Figure 2 ;

[0049] Figure 8 A cross-sectional view of a solar cell during the manufacturing process provided by an embodiment of the present invention Figure 3 ;

[0050] Fig. 9 A cross-sectional view of a solar cell during the manufacturing process provided by an embodiment of the present invention Figure 4 ;

[0051] Fig.10 A cross-sectional view of a solar cell during the manufacturing process provided by an embodiment of the present invention Figure 5 ;

[0052] Fig.11 A cross-sectional view of a solar cell during the manufacturing process provided by an embodiment of the present invention Figure 6 .

[0053] Reference numerals:

[0054] 1-semiconductor substrate, 10-first surface, 11-second surface, 12-side surface, 13-edge area, 14-middle area, 15-first area, 16-second area; 2-polygonal structure, 20-top opening, 21-bottom surface, 22-side wall, 23-polygonal structure group; 3-texture structure, 4-first hole, 5-first doped semiconductor layer, 50-first doped semiconductor material layer, 6-mask layer, 60-mask material layer, 7-first dielectric layer, 8-second doped semiconductor layer, 9-second dielectric layer. DETAILED DESCRIPTION

[0055] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0056] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0057] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0058] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0059] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] In order to solve the above technical problems, in the first aspect, the present invention provides a solar cell. The above solar cell can be a back contact solar cell, a bifacial solar cell, a hybrid HBC (Hybrid Back Contact) cell, a hybrid back contact cell or a tunneling oxide passivation back contact cell, etc. HBC is translated as a back contact heterojunction solar cell, wherein one pole of the hybrid HBC cell is a heterojunction passivation structure and the other pole is a tunneling oxide passivation structure.

[0061] See also Figures 1 to 4 The solar cell comprises: a semiconductor substrate 1. A plurality of polygonal structures 2 are provided on at least one surface of the semiconductor substrate 1, and the orthographic projection of the polygonal structures 2 on the semiconductor substrate 1 comprises at least two relatively parallel edges. It should be noted that the semiconductor substrate 1 comprises a light-facing surface and a backlight surface opposite to each other, and a side surface connecting the light-facing surface and the backlight surface.

[0062] See also Figure 1 and Figure 2 , at least part of the polygonal structures 2 are arranged along the first straight line L1, and an angle A is formed between the extension direction of the first straight line L1 and the extension direction of two relatively parallel sides L2 included in the orthographic projection of any polygonal structure 2 on the semiconductor substrate 1, 0°≤A≤90°. Exemplarily, the angle A can be 0°, 5°, 10°, 15°, 20°, 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85° or 90°, etc. When the angle A is 0°, the extension direction of the first straight line L1 is consistent with the extension direction of two relatively parallel sides L2 included in the orthographic projection of any polygonal structure 2 on the semiconductor substrate 1.

[0063] See also Figure 3 and Figure 4 , in the surface with polygonal structure 2, the plane where the surface other than polygonal structure 2 is located is a horizontal plane, and polygonal structure 2 is recessed relative to the horizontal plane. It should be noted that the "horizontal plane" in the above "the plane where the surface other than polygonal structure 2 is located is a horizontal plane" refers to the plane where the surface other than polygonal structure 2 is located on the entire surface of the semiconductor substrate 1 as a whole.

[0064] See also Figures 1 to 4 In the solar cell provided by the embodiment of the present invention, compared with the surface with polygonal structures 2 being a horizontal plane, the surface with multiple polygonal structures 2 recessed relative to the horizontal plane in the embodiment of the present invention has a larger specific surface area. At this time, not only can the adhesion of the passivation layer formed on the surface later be enhanced, and the passivation effect of the solar cell be improved; at the same time, the refraction of light can be improved, so that more light is transmitted to the semiconductor substrate 1 of the solar cell, and the light trapping effect is improved, thereby improving the photoelectric conversion efficiency of the solar cell. Further, since at least part of the polygonal structures 2 are arranged along the first straight line L1, there is an angle A between the extension direction of the first straight line L1 and the extension direction of the two relatively parallel sides L2 included in the positive projection of any polygonal structure 2 on the semiconductor substrate 1, 0°≤A≤90°. Compared with at least part of the polygonal structures 2 being arranged along the extension direction of the diagonal lines of the polygonal structures 2, at least part of the polygonal structures 2 arranged along the first straight line L1 in the present application have more uniform undulations, and at this time, the passivation layer subsequently formed on the surface with multiple polygonal structures 2 has better compactness, which can further improve the passivation effect of the solar cell.

[0065] Furthermore, when the angle A is in the range of A≤30°, the undulation of at least part of the polygonal structures 2 arranged along the first straight line L1 is further uniform, and the density of the passivation layer subsequently formed on the surface of the multiple polygonal structures 2 is better, further improving the passivation effect of the solar cell.

[0066] In actual application, the embodiment of the present invention does not specifically limit the material of the semiconductor substrate. For example, the semiconductor substrate can be a substrate made of any semiconductor material such as a silicon substrate, a silicon germanium substrate, a germanium substrate, or a gallium arsenide substrate.

[0067] In some embodiments, the semiconductor substrate may be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, which may be any one of the V-group elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type element, which may be any one of the III-group elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0068] The polygonal structure is distributed in the indentation, and the extension direction of the indentation is substantially consistent with or consistent with the extension direction of the first straight line. The indentation may refer to a line mark left when a diamond wire cuts a semiconductor substrate, or may refer to a grinding mark left when a grinding wheel grinds a semiconductor substrate.

[0069] See also Figure 1 and Figure 2 When the plurality of polygonal structures 2 form at least two polygonal structure groups 23 , the plurality of polygonal structures 2 in each polygonal structure group 23 are arranged along a first straight line L1 , and the solar cell includes at least two first straight lines L1 .

[0070] As a possible implementation manner, all first straight lines are parallel to each other.

[0071] As a possible implementation, see Figure 1 , an angle C is formed between the first straight line L1 and the edge of the surface where the first straight line L1 is located, and C is greater than or equal to 0° and less than or equal to 90°. Exemplarily, the angle C can be 0°, 5°, 10°, 15°, 20°, 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85° or 90°, etc. Preferably, the angle C is 30°, 35°, 40°, 45° or 50°, etc.

[0072] As a possible implementation manner, the length of the first straight line is greater than the thickness of the semiconductor substrate.

[0073] As a possible implementation manner, the surface with the polygonal structure is a side surface of the semiconductor substrate; and / or the surface with the polygonal structure is a light-facing surface or a backlight surface of the semiconductor substrate.

[0074] As a possible implementation, see Figure 3 and Figure 4 , along the direction going deep into the interior of the semiconductor substrate 1, the polygonal structure 2 has a top opening 20 and a bottom surface 21 which are arranged opposite to each other, and a side wall 22 located between the bottom surface 21 and the top opening 20, and the orthographic projection area of ​​the top opening 20 on the semiconductor substrate 1 is larger than the orthographic projection area of ​​the bottom surface 21 on the semiconductor substrate 1.

[0075] When the above technical solution is adopted, the orthographic projection area of ​​the top opening 20 on the semiconductor substrate 1 is larger than the orthographic projection area of ​​the bottom surface 21 on the semiconductor substrate 1, which is beneficial to the film layer uniformly filling the polygonal structure 2 when the film layer is formed on the semiconductor substrate 1 later, avoiding the formation of gaps between the film layer and the polygonal structure 2, while reducing the number of defects of the solar cell, improving the uniformity of the film layer and the film forming quality. Exemplarily, when the film layer formed on the semiconductor substrate 1 later is a passivation layer, the formed passivation layer can be made more uniform, the film forming quality of the passivation layer is better, and the density of the passivation layer is better, thereby improving the passivation effect of the solar cell. Furthermore, when the orthographic projection area of ​​the top opening 20 on the semiconductor substrate 1 is larger than the orthographic projection area of ​​the bottom surface 21 on the semiconductor substrate 1, it is beneficial to further increase the specific surface area of ​​the surface of the polygonal structure 2 having multiple depressions relative to the horizontal plane. At this time, not only can the adhesion of the passivation layer formed on the surface later be further enhanced, thereby further improving the passivation effect of the solar cell; at the same time, the refraction of light can be further improved, so that more light can be transmitted to the semiconductor substrate 1 of the solar cell, so as to further improve the light trapping effect and improve the utilization rate of light by the semiconductor substrate 1, thereby improving the photoelectric conversion efficiency of the solar cell.

[0076] The shape of the positive projection of the above polygonal structure on the semiconductor substrate can be a triangle, a quadrilateral (for example, a rectangle, a square, a rhombus, a parallelogram or a trapezoid, etc.), a pentagon or other polygons. As a possible implementation, see Figure 1 , the orthographic projection of the polygonal structure 2 on the semiconductor substrate 1 is a quadrilateral, and the angle between any two adjacent sides of the quadrilateral is a right angle. Exemplarily, the above quadrilateral can be a rectangle, a square, etc. It should be noted that the above “orthographic projection of the polygonal structure 2 on the semiconductor substrate 1” includes the orthographic projection of the top opening 20 of the polygonal structure 2 on the semiconductor substrate 1, and / or, the orthographic projection of the bottom surface 21 of the polygonal structure 2 on the semiconductor substrate 1.

[0077] When the above technical solution is adopted, the specific surface area of ​​the surface with multiple polygonal structures can be further increased. At this time, not only can the adhesion of the passivation layer formed on the surface later be further enhanced, so as to further improve the passivation effect of the solar cell, but also the refraction of light can be further improved, so that more light can be transmitted to the semiconductor substrate of the solar cell, so as to further improve the light trapping effect, improve the utilization rate of light by the semiconductor substrate, and thus improve the photoelectric conversion efficiency of the solar cell.

[0078] As a possible implementation, the length of the orthographic projection of the polygonal structure on the semiconductor substrate is greater than or equal to 10 μm and less than or equal to 100 μm; the length direction of the orthographic projection of the polygonal structure on the semiconductor substrate is consistent with the extension direction of two relatively parallel sides included in the polygonal structure; illustratively, the length of the orthographic projection of the polygonal structure on the semiconductor substrate can be 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm or 100 μm, etc. For example, see Figure 1 , the length of the positive projection of the polygonal structure on the semiconductor substrate is 16.7 μm.

[0079] As a possible implementation, the width of the orthographic projection of the polygonal structure on the semiconductor substrate is greater than or equal to 10 μm and less than or equal to 100 μm; the width direction of the orthographic projection of the polygonal structure on the semiconductor substrate is perpendicular to the extension direction of the two relatively parallel sides included in the polygonal structure; illustratively, the width of the orthographic projection of the polygonal structure on the semiconductor substrate can be 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm or 100 μm, etc. For example, see Figure 2 , the width of the polygonal structure's orthographic projection on the semiconductor substrate is 12.9 μm. Figure 5 The width of the orthographic projection of the polygonal structure on the semiconductor substrate is 14.5 μm.

[0080] Combined with the above description, along the direction going deep into the interior of the semiconductor substrate, the polygonal structure has a top opening and a bottom surface that are relatively arranged, and a side wall located between the bottom surface and the top opening. Therefore, the above-mentioned "length of the orthographic projection of the polygonal structure on the semiconductor substrate" may refer to the length of the top opening, or the length of the bottom surface, or include both the length of the top opening and the length of the bottom surface. The above-mentioned "width of the orthographic projection of the polygonal structure on the semiconductor substrate" may refer to the width of the top opening, or the width of the bottom surface, or include both the width of the top opening and the width of the bottom surface.

[0081] It should be noted that when the orthographic projection area of ​​the top opening on the semiconductor substrate is larger than the orthographic projection area of ​​the bottom surface on the semiconductor substrate, the length of the top opening and the length of the bottom surface may be different values, and the width of the top opening and the width of the bottom surface may be different values.

[0082] When the orthographic projection of the top opening on the semiconductor substrate is completely consistent with and overlaps with the orthographic projection of the bottom surface on the semiconductor substrate, the length of the top opening and the length of the bottom surface are the same value, and the width of the top opening and the width of the bottom surface are the same value.

[0083] As a possible implementation, the depth of the polygonal structure is greater than or equal to 0.5 μm and less than or equal to 5 μm; the depth direction of the polygonal structure is consistent with the direction of vertical penetration into the semiconductor substrate. Exemplarily, the depth of the polygonal structure can be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, 3.5 μm, 3.8 μm, 4 μm, 4.3 μm, 4.5 μm, 4.8 μm or 5 μm, etc.

[0084] The following uses three possible situations as examples to describe the relative positional relationship between at least two adjacent polygonal structures. It should be understood that the following description is only for understanding and is not intended to be a specific limitation.

[0085] The first one: See Figure 1 In the E region, at least two adjacent polygonal structures 2 have overlapping portions.

[0086] When the above technical solution is adopted, the passivation layer formed on the surface with the polygonal structure 2 later is more uniform, the film quality of the passivation layer is better, and the density of the passivation layer is better, thereby improving the passivation effect of the solar cell.

[0087] The second type: at least two adjacent polygonal structures are distributed at intervals.

[0088] When the above technical solution is adopted, since at least two adjacent polygonal structures are spaced apart, there are undulations between the two adjacent polygonal structures. This can improve the light trapping effect of the surface, improve the utilization rate of light by the semiconductor substrate, and thus improve the photoelectric conversion efficiency of the solar cell.

[0089] The third type: at least two adjacent polygonal structures have an overlapping portion, and at least two adjacent polygonal structures are distributed at intervals.

[0090] When the above technical solution is adopted, combined with the above description, compared with the prior art, not only the passivation effect of the solar cell can be improved, but also the photoelectric conversion efficiency of the solar cell can be improved. In other words, the passivation effect and the photoelectric conversion efficiency of the solar cell can be taken into account. Moreover, it can be set according to actual needs to expand the scope of application of the solar cell and meet different needs.

[0091] It should be noted that the above-mentioned "two adjacent polygonal structures" include two adjacent polygonal structures along the extension direction of the first straight line, and / or two adjacent polygonal structures along the extension direction perpendicular to the first straight line. Of course, it can also be two adjacent polygonal structures along other directions.

[0092] As a possible implementation manner, the solar cell further includes: a doped conductive layer and a passivation layer sequentially stacked on the surface of the semiconductor substrate.

[0093] When the above technical solution is adopted, the doped conductive layer plays a field passivation effect. Specifically, an electrostatic field pointing to the inside of the semiconductor substrate is formed on the surface of the semiconductor substrate, so that minority carriers escape from the interface, thereby reducing the minority carrier concentration, so that the carrier recombination rate at the interface of the semiconductor substrate is reduced, thereby increasing the open circuit voltage, short circuit current and fill factor of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.

[0094] In an alternative approach, see Figure 5 The solar cell further comprises: a texture structure 3 formed on the polygonal structure 2. The doped conductive layer has a first hole 4 penetrating the doped conductive layer, at least part of the first hole 4 corresponds to the texture structure 3, and the passivation layer fills the first hole 4 and covers the texture structure 3.

[0095] The distribution trend of the multiple texture structures 3 is consistent or approximately consistent with the extension direction of the first straight line. In addition, the distribution trend of the first holes 4 on the multiple texture structures 3 is also consistent or approximately consistent with the extension direction of the first straight line. This arrangement allows the multiple texture structures 3 and / or the multiple first holes 4 to be formed in the plane within the polygonal structure, avoiding distribution on the inclined surface or defective surface between the multiple polygonal structures, which can further improve the passivation quality of the passivation film layer and enhance the photoelectric conversion efficiency of the solar cell.

[0096] When the above technical solution is adopted, the texture structure 3 and the first hole 4 are both conducive to light trapping, so that more light is transmitted to the semiconductor substrate 1 of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0097] In an alternative approach, see Figure 5, the texture structure 3 is a pyramid-shaped texture structure; and / or, the one-dimensional size of the first hole 4 is greater than or equal to 1nm and less than or equal to 10μm. Exemplarily, the one-dimensional size of the first hole 4 can be 1nm, 5nm, 10nm, 15nm, 20nm, 50nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm or 10μm, etc. When the cross section of the first hole is a regular quadrilateral, the one-dimensional size can refer to the length or width of the first hole or the size of the diagonal, etc. When the cross section of the first hole is circular, the one-dimensional size can refer to the diameter of the first hole. When the cross section of the first hole is elliptical, the one-dimensional size can refer to the major axis or minor axis of the first hole, etc.

[0098] When the above technical solution is adopted, the pyramid-shaped texture structure has a large specific surface area and has a light trapping effect. Therefore, when the texture structure is a pyramid-shaped texture structure, more light can be transmitted to the semiconductor substrate through the pyramid-shaped texture structure, so that the solar cell has a higher photoelectric conversion efficiency.

[0099] In an optional manner, the doped conductive layer includes any one or more stacked combinations of a doped polysilicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, a doped silicon carbide layer, and a doped crystalline silicon layer.

[0100] In an optional manner, the passivation layer includes any one or more stacked combinations of a silicon oxide passivation layer, an aluminum oxide passivation layer, a silicon oxynitride passivation layer, a silicon nitride passivation layer, and an aluminum oxynitride passivation layer.

[0101] As a possible implementation, the solar cell further includes: a dielectric layer. The dielectric layer is located between the semiconductor substrate and the doped conductive layer.

[0102] When the above technical solution is adopted, the above dielectric layer can play a chemical passivation effect. Specifically, due to the presence of interface state defects at the interface between the semiconductor substrate and the dielectric layer, the interface state density on the front side of the semiconductor substrate is relatively large. The increase in the interface state density will promote the recombination of photogenerated carriers, increase the fill factor, short-circuit current and open-circuit voltage of the solar cell, so as to improve the photoelectric conversion efficiency of the solar cell. The dielectric layer is arranged on the surface of the semiconductor substrate so that the dielectric layer has a chemical passivation effect on the surface of the semiconductor substrate. Specifically, by saturating the dangling bonds of the semiconductor substrate, reducing the defect state density of the semiconductor substrate, and reducing the recombination center of the semiconductor substrate, the carrier recombination rate is reduced.

[0103] Furthermore, a passivation contact structure is formed between the dielectric layer and the doped conductive layer. The doped conductive layer can form an energy band bending on the surface of the semiconductor substrate. The dielectric layer causes an asymmetric shift in the energy band on the surface of the semiconductor substrate, so that the potential barrier to the majority carriers (also called majority carriers) among the carriers is lower than the potential barrier to the minority carriers (also called minority carriers) among the carriers. Therefore, the majority carriers can more easily perform quantum tunneling through the dielectric layer, while the minority carriers find it difficult to pass through the dielectric layer, so as to realize the selective transmission of carriers.

[0104] Furthermore, in combination with the previous description, since the polygonal structure is recessed relative to the horizontal plane, the specific surface area of ​​the surface having multiple polygonal structures recessed relative to the horizontal plane is larger. At this time, the specific surface area of ​​the dielectric layer and the doped conductive layer can be increased, thereby increasing the contact area between the electrode and the doped conductive layer and the dielectric layer, and reducing the contact resistance between the electrode and the doped conductive layer and the dielectric layer, thereby increasing the electrode's carrier collection efficiency, thereby improving the photoelectric conversion efficiency of the solar cell.

[0105] In an optional manner, the dielectric layer has a second hole corresponding to the first hole, and the bottom of the second hole exposes the texture structure.

[0106] In an optional manner, the dielectric layer includes any one or more stacked combinations of a silicon oxide dielectric layer, an aluminum oxide dielectric layer, a silicon oxynitride dielectric layer, and a silicon nitride dielectric layer.

[0107] The thickness of the dielectric layer can be set according to actual conditions and is not specifically limited here.

[0108] As a possible implementation, the solar cell further includes: a first doped semiconductor layer and a second doped semiconductor layer disposed on the first surface of the semiconductor substrate; the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. And a first dielectric layer located between the semiconductor substrate and the first doped semiconductor layer, and a second dielectric layer located between the semiconductor substrate and the second doped semiconductor layer. The first dielectric layer is a first tunneling layer, and the first doped semiconductor layer includes a doped polycrystalline silicon layer. The second dielectric layer is an intrinsic amorphous silicon layer, and the second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer. In this case, the solar cell is a hybrid back contact cell.

[0109] As a possible implementation, the solar cell further includes: a first doped semiconductor layer and a second doped semiconductor layer disposed on the first surface of the semiconductor substrate; the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. And a third dielectric layer located between the semiconductor substrate and the first doped semiconductor layer, and a fourth dielectric layer located between the semiconductor substrate and the second doped semiconductor layer. The third dielectric layer is a second tunneling layer, and the first doped semiconductor layer includes an N-type doped polysilicon layer; the fourth dielectric layer is a third tunneling layer, and the second doped semiconductor layer includes a P-type doped polysilicon layer. At this time, the solar cell is a tunneling oxide passivated back contact cell.

[0110] In summary, different materials can be selected to make dielectric layers and doped semiconductor layers according to the type of solar cells actually required, so as to expand the scope of application and application scenarios of solar cells. It should be noted that for the sake of convenience of description, the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are collectively referred to as dielectric layers, and the first doped semiconductor layer and the second doped semiconductor layer are collectively referred to as doped semiconductor layers.

[0111] For the convenience of description, the first tunnel layer, the second tunnel layer and the third tunnel layer are collectively referred to as tunnel layers, and the tunnel layers include any one or more stacked combinations of a silicon oxide tunnel layer, an aluminum oxide tunnel layer, a silicon oxynitride tunnel layer and a silicon nitride tunnel layer.

[0112] For the first doped semiconductor layer and the second doped semiconductor layer, in terms of doping type, the doping type of the first doped semiconductor layer can be N-type, in which case the doping type of the second doped semiconductor layer is P-type; or, the doping type of the first doped semiconductor layer can also be P-type, in which case the doping type of the second doped semiconductor layer is N-type. The embodiment of the present invention does not specifically limit the doping types of the first doped semiconductor layer and the second doped semiconductor layer, as long as the doping types of the two are opposite. When the doping type is P-type, it is generally doped with group III elements. When the doping type is N-type, it is generally doped with group V elements or group VI elements. In terms of materials, the material of the first doped semiconductor layer and / or the second doped semiconductor layer may include any semiconductor material such as silicon, silicon germanium or germanium.

[0113] In a second aspect, an embodiment of the present invention further provides a photovoltaic module, which includes a battery string and a packaging layer, wherein the battery string is formed by connecting a plurality of solar cells described in the above technical solution, and the packaging layer is used to cover the surface of the battery string.

[0114] The beneficial effects of the photovoltaic module provided by the embodiment of the present invention are the same as the beneficial effects of the solar cell described in the above technical solution, and will not be described in detail here.

[0115] In a third aspect, an embodiment of the present invention further provides a method for manufacturing a solar cell. The method for manufacturing a solar cell comprises:

[0116] First, a semiconductor substrate is provided;

[0117] Next, the semiconductor substrate is processed so that at least one surface of the semiconductor substrate has a plurality of polygonal structures. Exemplarily, the semiconductor substrate may be wet processed to form the polygonal structures.

[0118] The orthographic projection of the above-mentioned polygonal structure on the semiconductor substrate includes at least two relatively parallel sides, at least part of the polygonal structures are arranged along a first straight line, and an angle A is formed between the extension direction of the first straight line and the extension direction of the two relatively parallel sides included in the orthographic projection of any polygonal structure on the semiconductor substrate; 0°≤A≤90°. In the surface with polygonal structures, the plane where the surface other than the polygonal structure is located is a horizontal plane, and the polygonal structure is concave relative to the horizontal plane. Exemplarily, the above-mentioned angle A can be 0°, 5°, 10°, 15°, 20°, 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85° or 90°, etc.

[0119] The beneficial effects of the method for manufacturing a solar cell provided by the embodiment of the present invention are the same as the beneficial effects of the solar cell described in the above technical solution, and will not be described in detail here.

[0120] The following describes a method for manufacturing a solar cell by taking the formation of multiple polygonal structures on the side surface as an example. It should be noted that the following description is only for understanding and is not intended to be a specific limitation.

[0121] First, a semiconductor substrate is provided; the semiconductor substrate comprises a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface; the first surface comprises an edge region and a middle region, and the edge region surrounds the middle region.

[0122] Before actual use, the semiconductor substrate is first polished and cleaned. Specifically, the semiconductor substrate is placed in a slot polishing machine, and the semiconductor substrate is pre-cleaned to remove the organic matter and other pollutants generated by the cutting damage of the semiconductor substrate and the transportation process. The steps of polishing and cleaning the semiconductor substrate include: using SC-1 in the RCA (Resist Cleaning) cleaning process for cleaning. SC-1 is composed of NH4OH / KOH-H2O2-H2O, the ratio of the three is (1:1:5), and the temperature during cleaning is 65°C. Then, the chemicals remaining in the SC-1 cleaning are neutralized by deionized water washing. Then, alkaline polishing treatment is performed. The alkaline polishing formula is: 5.00%wt KOH, the concentration of KOH stock solution is (45%), the temperature is 80°C, and the time is 300s. The surface damage layer caused by cutting is removed, and the surface of the semiconductor substrate is polished. Next, high-efficiency SC-1 cleaning is performed, with the ratio of NH4OH / KOH-H2O2-H2O being (1:1:5), the temperature being 65°C, and the time being 300s. Next, SC-2 is used to remove the residual metal ions. SC-2 is a solution of HCl:H2O2:H2O, with a ratio of 1:1:5, a temperature of 65°C, and a cleaning time of 200s. Finally, after cleaning with 5%wt hydrofluoric acid and drying, the surface of the semiconductor substrate is polished. After polishing and cleaning, dents are formed on the surface of the semiconductor substrate, and the above dents have the same distribution as the wear marks produced by diamond wire cutting of the original silicon wafer.

[0123] Next, a first doped semiconductor layer and a mask layer are sequentially deposited on the second surface, and the first doped semiconductor layer and the mask layer are plated around the side surface and the edge area of ​​the first surface;

[0124] For example, see Figure 6 , firstly form a first doped semiconductor material layer 50 on the second surface 11 in an entire layer. For example, a process such as chemical vapor deposition can be used to form a semiconductor material layer on the second surface 11 in an entire layer. Next, the semiconductor material layer is doped to form a first doped semiconductor material layer 50 on the second surface 11 in an entire layer. In this process, the first doped semiconductor material layer 50 is plated around the side surface 12 and the first surface 10. The thickness of the first doped semiconductor material layer 50 is greater than or equal to 30nm and less than or equal to 120nm. For example, the thickness of the first doped semiconductor material layer 50 can be 30nm, 40nm, 50nm, 60nm, 80nm, 100nm or 120nm, etc.

[0125] Next, see Figure 6 and Figure 7, a mask material layer 60 is formed on the first doped semiconductor material layer 50 as a whole layer, and the mask material layer 60 finally formed is not only located on the second surface 11, but also plated around the side surface 12 and the edge area 13 of the first surface 10. The material of the mask material layer 60 can be one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbide or intrinsic silicon. The thickness of the mask material layer 60 is greater than or equal to 10nm and less than or equal to 120nm. For example, the thickness of the mask material layer 60 can be 10nm, 30nm, 40nm, 60nm, 80nm, 100nm or 120nm, etc. The formation method of the above-mentioned mask material layer 60 includes one or more of plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD) or atomic layer deposition (ALD).

[0126] Next, see Figure 7 and Figure 8 , process the mask material layer 60, and form a mask layer 6 on the portion of the first doped semiconductor material layer 50 corresponding to the first region 15; and retain the mask material layer 60 plated around the side 12 and the edge region 13 of the first surface 10 as the mask layer 6. Exemplarily, a laser film opening is used to vaporize and ablate part of the mask material layer. The laser can be one of a green nanosecond laser, a green picosecond laser, an ultraviolet nanosecond laser, or an ultraviolet picosecond laser. The first region can be a region used to form an N region later.

[0127] Next, see Figure 8 and Fig. 9 , removing the mask layer 6 located in the edge region 13;

[0128] As a possible implementation, the mask layer located in the edge area is removed by wet removal; wherein the concentration of HF is greater than or equal to 5% and less than or equal to 10%, the belt speed is greater than or equal to 1m / s and less than or equal to 2m / s; and the circulation amount is greater than or equal to 80% and less than or equal to 95%. For example, the concentration of HF may be 5%, 6%, 7%, 8%, 9% or 10%, etc. The belt speed may be 1m / s, 1.3m / s, 1.5m / s, 1.8m / s, 1.9m / s or 2m / s, etc. The circulation amount may be 80%, 82%, 85%, 88%, 90%, 92% or 95%, etc.

[0129] Next, see Fig. 9 and Fig.10, under the protection of the mask layer 6, the portion of the first doped semiconductor material layer 50 located on the second region 16 is removed to form at least the first doped semiconductor layer 5 on the first region 15. Exemplarily, an etching method such as laser etching or a wet process is used to remove the portion of the first doped semiconductor material layer 50 located on the second region 16 under the protection of the mask layer 6. The second surface 11 of the semiconductor substrate 1 has first regions 15 and second regions 16 alternately distributed along a first direction. Preferably, the first direction is orthogonal to the direction from the first surface 10 to the second surface 11. It should be noted that in this process, the first doped semiconductor material layer 50 located on the first surface 10 is removed to expose the semiconductor substrate 1.

[0130] As a possible implementation, see Figures 6 to 10 In the case where the solar cell further includes a first dielectric layer 7, after providing a semiconductor substrate 1 and before forming the first doped semiconductor layer 5 on the first region 15, the manufacturing method of the solar cell includes: forming the first dielectric layer 7 on the first region 15, the first dielectric layer 7 being located between the semiconductor substrate 1 and the first doped semiconductor layer 5. Alternatively, the first dielectric layer 7 is located between the first doped semiconductor layer 5 and the first region 15 and is formed on the side 12. The material of the first dielectric layer 7 can be determined according to the material of the first doped semiconductor layer 5. For example, in the case where the first doped semiconductor layer 5 includes a doped crystalline silicon layer, the first dielectric layer 7 is a tunneling layer. Preferably, the material of the first dielectric layer 7 can be silicon oxide, and the thickness of the first dielectric layer 7 can be greater than or equal to 1 nm and less than or equal to 2 nm. For example, the thickness of the first dielectric layer 7 can be 1 nm, 1.3 nm, 1.5 nm, 1.8 nm or 2 nm, etc.

[0131] For example, before forming the first doped semiconductor layer 5, the first dielectric layer 7 may be formed only on the first region 15 by using processes such as deposition and etching. Alternatively, before forming the first doped semiconductor layer 5, a deposition process is used to form the first dielectric layer 7 disposed entirely on the semiconductor substrate 1, and then after removing the portion of the first doped semiconductor layer 5 located above the second region 16 under the protection of the mask layer 6, a corresponding etching process is used to remove the portion of the first dielectric layer 7 located above the second region 16 under the protection of the mask layer 6. It should be noted that the above-mentioned method for forming the first dielectric layer 7 includes one or more of plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD) or atomic layer deposition (ALD). It should be noted that if the first dielectric layer 7 is plated around the side 12 and the first face 10 of the semiconductor substrate 1, the first dielectric layer 7 is removed while removing the first doped semiconductor material layer 50 located on the first face 10 to expose the semiconductor substrate 1.

[0132] Next, the semiconductor substrate is subjected to a texturing process, so that the semiconductor substrate located in the second region and the semiconductor substrate on the first surface form a pyramid structure, and the relevant dimensions thereof are not specifically limited herein.

[0133] Exemplarily, the semiconductor substrate is first cleaned by SC-1, SC-1 is composed of KOH-H2O2-H2O, the ratio of KOH-H2O2-H2O is (1:2:5), the cleaning temperature is 65°C, and the cleaning time is 360s. Then, the second area and the first surface of the semiconductor substrate are textured using a TS53V01:KOH:DIW system, wherein the TS53V01wt% concentration is 0.2-1.5%, the KOHwt concentration is 0.2-3%, the temperature is 75-85°C, and the time is 300-720s. Then, the semiconductor substrate is cleaned by high-efficiency SC-1, SC-1 is composed of KOH-H2O2-H2O, the ratio of KOH-H2O2-H2O is (1:2:5), the cleaning temperature is 65°C, and the cleaning time is 360s.

[0134] Next, 5% wt-10% wt hydrofluoric acid is used for 600 s to remove the mask layer.

[0135] After the semiconductor substrate is processed, a plurality of polygonal structures are formed on the side of the semiconductor substrate. The orthographic projection of the polygonal structure on the semiconductor substrate includes at least two relatively parallel sides, at least part of the polygonal structure is arranged along a first straight line, and an angle A is formed between the extension direction of the first straight line and the extension direction of the two relatively parallel sides included in the orthographic projection of any polygonal structure on the semiconductor substrate; 0°≤A≤90°. In the surface with polygonal structures, the plane where the surface other than the polygonal structures is located is a horizontal plane, and the polygonal structures are recessed relative to the horizontal plane.

[0136] Next, see Fig.11 , forming a second doped semiconductor layer 8 covering the second region 16 and extending to cover part of the first doped semiconductor layer 5; the second doped semiconductor layer 8 and the first doped semiconductor layer 5 have opposite conductivity types. It should be noted that the relative position relationship between the first doped semiconductor layer 5 and the second doped semiconductor layer 8 can be set according to actual needs, and the description here is only for understanding and is not used for specific limitation.

[0137] For example, see Fig.11, a process such as chemical vapor deposition (for example, one or more of plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD) or atomic layer deposition (ALD)) can be used to form a semiconductor material layer on the second surface 11 in an entire layer. Then, the semiconductor material layer is doped to form a second doped semiconductor material layer on the second surface 11 in an entire layer. Then, a laser film opening vaporization ablation is used to ablate the portion of the second doped semiconductor material layer located above at least part of the first doped semiconductor layer 5 to form a second doped semiconductor layer 8 covering the second region 16 and extending to cover part of the first doped semiconductor layer 5. Furthermore, the above-mentioned laser can be one of a green nanosecond laser, a green picosecond laser, an ultraviolet nanosecond laser or an ultraviolet picosecond laser. The thickness of the second doped semiconductor layer 8 is greater than or equal to 3 nm and less than or equal to 50 nm. Exemplarily, the thickness of the second doped semiconductor layer 8 may be 3 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc.

[0138] As a possible implementation, the solar cell further includes a second dielectric layer 9 (see Fig.11 ), before forming the second doped semiconductor layer covering the second region and extending to cover part of the first doped semiconductor layer, the manufacturing method of the solar cell includes: forming a second dielectric layer covering the second region and extending to cover part of the first region. The second dielectric layer is located between the second doped semiconductor layer and the second region and extends to cover part of the first region, and the portion of the second doped semiconductor layer corresponding to the first region is located on the portion of the second dielectric layer corresponding to the first region. It should be noted that the relative positional relationship between the second dielectric layer and the first doped semiconductor layer and the second doped semiconductor layer can be set according to actual conditions. Fig.11 This is just one example.

[0139] Exemplarily, before forming the second doped semiconductor layer, a deposition and etching process is used to form a second dielectric layer that only covers the second region and extends above a portion of the first region. Alternatively, after forming the first doped semiconductor layer, a deposition process is used to form a second dielectric layer that is disposed entirely on the second surface, and then a laser process is used to remove the portion of the second doped semiconductor layer that is located above at least a portion of the first doped semiconductor layer, and then a corresponding laser process is used to remove the portion of the second dielectric layer that is located above at least a portion of the first doped semiconductor layer. The material of the second dielectric layer can be determined according to the material of the second doped semiconductor layer. For example, when the second doped semiconductor layer includes a doped amorphous silicon layer, the second dielectric layer includes an intrinsic amorphous silicon layer. Preferably, the thickness of the second dielectric layer is greater than or equal to 1 nm and less than or equal to 50 nm. For example, the thickness of the second dielectric layer can be 1 nm, 5 nm, 10 nm, 12 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc.

[0140] In addition, in the case where a second passivation layer and an anti-reflection layer are formed on the first surface of the solar cell, before or after forming a second doped semiconductor layer covering the second region and extending to cover part of the first doped semiconductor layer, the manufacturing method of the solar cell includes: forming a second passivation layer on the first surface, and then forming an anti-reflection layer on the second passivation layer. Exemplarily, the material of the second passivation layer may include Al2O3, ia-Si:H, SiOx, SiNx:H, SiOxNy:H. The total thickness of the second passivation layer and the anti-reflection layer is greater than or equal to 5nm and less than or equal to 200nm. For example, the total thickness may be 5nm, 30nm, 40nm, 60nm, 80nm, 100nm, 120nm, 140nm, 180nm or 200nm, etc. Among them, the thickness of the second passivation layer is greater than or equal to 2nm and less than or equal to 100nm. For example, the thickness of the second passivation layer may be 2nm, 30nm, 40nm, 60nm, 80nm or 100nm, etc. The thickness of the anti-reflection layer is greater than or equal to 3 nm and less than or equal to 100 nm. For example, the thickness of the anti-reflection layer may be 3 nm, 30 nm, 40 nm, 60 nm, 80 nm or 100 nm.

[0141] Next, forming a transparent conductive layer covering the first doped semiconductor layer and the second doped semiconductor layer;

[0142] Next, an insulating groove is opened in the transparent conductive layer to physically insulate the portion of the transparent conductive layer corresponding to the first area from the portion of the transparent conductive layer corresponding to the second area.

[0143] Exemplarily, an etching paste is used to etch away a portion of the transparent conductive layer to form an insulating groove to prevent the first doped semiconductor layer and the second doped semiconductor layer from being interconnected and causing leakage. The insulation resistance of the insulating groove is tested to be greater than 2MΩ, and the etching width is greater than or equal to 40μm and less than or equal to 150μm. For example, the etching width can be 40μm, 60μm, 80μm, 100μm, 120μm, 140μm or 150μm, etc.

[0144] The transparent conductive layer may be composed of one or more stacked layers of an ITO (indium tin oxide) layer, an ITiO (titanium tin oxide) layer, an IWO (tungsten tin oxide) layer, and an ICO (cerium tin oxide) layer. The thickness of the transparent conductive layer is greater than or equal to 10 nm and less than or equal to 500 nm. For example, the thickness of the transparent conductive layer may be 10 nm, 30 nm, 40 nm, 60 nm, 80 nm, 100 nm, 180 nm, 200 nm, 230 nm, 300 nm, 400 nm or 500 nm. Preferably, the thickness of the transparent conductive layer is greater than or equal to 50 nm and less than or equal to 200 nm. The thickness direction of the transparent conductive layer is consistent with the direction from the first surface to the second surface.

[0145] By adopting the above technical solution, the transparent conductive layer covering the first doped semiconductor layer and the second doped semiconductor layer has a high conductivity, and the carriers collected by the first doped semiconductor layer and the second doped semiconductor layer can be timely led out to reduce the carrier recombination rate. Further, the above transparent conductive layer can not only improve the current collection capacity of the solar cell, but also can be used as an anti-reflection film to improve the light absorption rate of the solar cell. In addition, the above transparent conductive layer also has a passivation performance. In addition, as for the insulating groove provided in the transparent conductive layer, the insulating groove is used to physically insulate the part of the transparent conductive layer corresponding to the first area from the part of the transparent conductive layer corresponding to the second area. Specifically, because the part of the transparent conductive layer corresponding to the first area is ohmically connected to the first electrode, and the part of the transparent conductive layer corresponding to the second area is ohmically connected to the second electrode, the transparent conductive layers of these two parts cannot be directly electrically connected, that is, the transparent conductive layers of these two parts must be physically insulated, that is, not in contact. Based on this, it can be understood that in order to prevent short circuits, the positions of the two ends of the insulating groove are not restricted, as long as the transparent conductive layer with the first electrode and the second electrode can be insulated.

[0146] Next, an electrode paste is printed on the transparent conductive layer located on the first doped semiconductor layer and the second doped semiconductor layer to form a first electrode electrically connected to the first doped semiconductor layer and a second electrode electrically connected to the second doped semiconductor layer.

[0147] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0148] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: Semiconductor substrate; At least one surface of the semiconductor substrate has a plurality of polygonal structures; the orthographic projection of the polygonal structures on the semiconductor substrate includes at least two relatively parallel sides; At least part of the polygonal structures are arranged along a first straight line, and an angle A is formed between an extension direction of the first straight line and an extension direction of two relatively parallel sides included in an orthographic projection of any polygonal structure on the semiconductor substrate; 0°≤A≤90°; In the surface having the polygonal structure, the plane on which the surface other than the polygonal structure is located is a horizontal plane, and the polygonal structure is recessed relative to the horizontal plane.

2. The solar cell according to claim 1, characterized in that The orthographic projection of the polygonal structure on the semiconductor substrate is a quadrilateral, and the angle between any two adjacent sides of the quadrilateral is a right angle.

3. The solar cell according to claim 1, characterized in that The surface with the polygonal structure is a side surface of the semiconductor substrate; and / or the surface with the polygonal structure is a light-facing surface or a backlight surface of the semiconductor substrate.

4. The solar cell according to claim 1, characterized in that At least two adjacent polygonal structures have overlapping parts; and / or at least two adjacent polygonal structures are distributed at intervals.

5. The solar cell according to claim 1, characterized in that: Along the direction going deep into the semiconductor substrate, the polygonal structure has a top opening and a bottom surface which are arranged opposite to each other, and a side wall between the bottom surface and the top opening; An orthographic projection area of ​​the top opening on the semiconductor substrate is larger than an orthographic projection area of ​​the bottom surface on the semiconductor substrate.

6. The solar cell according to claim 1, characterized in that The solar cell further comprises: a doped conductive layer and a passivation layer sequentially stacked on the surface of the semiconductor substrate.

7. The solar cell according to claim 6, characterized in that: The solar cell further comprises: a texture structure formed on the polygonal structure; The doped conductive layer has a first hole penetrating the doped conductive layer; at least a portion of the first hole corresponds to the texture structure; The passivation layer fills the first hole and covers the texture structure.

8. The solar cell according to claim 7, characterized in that: The texture structure is a pyramid-shaped texture structure; And / or, a one-dimensional size of the first hole is greater than or equal to 1 nm and less than or equal to 10 μm.

9. The solar cell according to claim 6, characterized in that: The doped conductive layer includes any one or more stacked combinations of a doped polycrystalline silicon layer, a doped amorphous silicon layer, and a doped microcrystalline silicon layer; The passivation layer includes any one or more stacked combinations of a silicon oxide passivation layer, an aluminum oxide passivation layer, a silicon oxynitride passivation layer, and a silicon nitride passivation layer.

10. The solar cell according to claim 1, characterized in that: The length of the orthographic projection of the polygonal structure on the semiconductor substrate is greater than or equal to 10 μm and less than or equal to 100 μm; the length direction of the polygonal structure is consistent with the extension direction of two relatively parallel sides included in the orthographic projection of the polygonal structure on the semiconductor substrate; And / or, the width of the orthographic projection of the polygonal structure on the semiconductor substrate is greater than or equal to 10 μm and less than or equal to 100 μm; the width direction of the polygonal structure is perpendicular to the extension direction of two relatively parallel sides included in the orthographic projection of the polygonal structure on the semiconductor substrate; And / or, the depth of the polygonal structure is greater than or equal to 0.5 μm and less than or equal to 5 μm; and the depth direction of the polygonal structure is consistent with the direction vertically penetrating into the interior of the semiconductor substrate.

11. The solar cell according to claim 1, characterized in that: The solar cell further comprises: a first doped semiconductor layer and a second doped semiconductor layer disposed on the first surface of the semiconductor substrate; the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; and a first dielectric layer located between the semiconductor substrate and the first doped semiconductor layer, and a second dielectric layer located between the semiconductor substrate and the second doped semiconductor layer; The first dielectric layer is a first tunneling layer, and the first doped semiconductor layer includes a doped polysilicon layer; the second dielectric layer is an intrinsic amorphous silicon layer, and the second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer.

12. The solar cell according to claim 1, characterized in that The solar cell further comprises: a first doped semiconductor layer and a second doped semiconductor layer disposed on the first surface of the semiconductor substrate; the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; and a third dielectric layer located between the semiconductor substrate and the first doped semiconductor layer, and a fourth dielectric layer located between the semiconductor substrate and the second doped semiconductor layer; The third dielectric layer is a second tunneling layer, and the first doped semiconductor layer includes an N-type doped polysilicon layer; the fourth dielectric layer is a third tunneling layer, and the second doped semiconductor layer includes a P-type doped polysilicon layer.

13. A photovoltaic module, characterized in that: The photovoltaic module comprises: A battery string, wherein the battery string is formed by connecting a plurality of solar cells according to any one of claims 1 to 12; The encapsulation layer is used to cover the surface of the battery string.

14. A method for manufacturing a solar cell, characterized in that: include: Providing a semiconductor substrate; Processing the semiconductor substrate so that at least one surface of the semiconductor substrate has a plurality of polygonal structures; The orthographic projection of the polygonal structure on the semiconductor substrate includes at least two relatively parallel sides; At least part of the polygonal structures are arranged along a first straight line, and an angle A is formed between an extension direction of the first straight line and an extension direction of two relatively parallel sides included in an orthographic projection of any polygonal structure on the semiconductor substrate; 0°≤A≤90°; In the surface having the polygonal structure, the plane on which the surface other than the polygonal structure is located is a horizontal plane, and the polygonal structure is recessed relative to the horizontal plane.

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