Signal generation circuit

Abstract

The N-tap resistance network circuit (11) is provided with a plurality of first resistors and a plurality of first taps, and generates a control voltage having one of a plurality of predetermined voltage values by selecting one of the plurality of first taps in accordance with an input digital control signal. The M-tap resistance network circuit (12) is provided with a plurality of second resistors and a plurality of second taps, and generates a plurality of predetermined reference voltages from the plurality of second taps. The folding circuits (13, 14) generate an output signal having a signal level corresponding to a given phase of a sine wave or a cosine wave on the basis of a difference between the control voltage and a plurality of reference voltages.

Description

Technical Field

[0001] The present disclosure relates to a signal generating circuit, a phase shifter, an array antenna device, and a wireless communication device. Background Art

[0002] In wireless communication systems beyond the fifth generation mobile communication system (Beyond 5G), the use of high frequency bands such as millimeter waves and terahertz waves is being studied to increase the communication capacity. Furthermore, in order to increase the communication capacity, the use of phased array antenna devices to focus the beam of radio waves on the communication object is being studied. By using phased array antenna devices, for example, beam forming (directing the beam in a specific direction), beam steering (directing the beam toward the communication object), and beam tracking (continuously directing the beam toward the communication object moving at high speed) can be performed.

[0003] In order to realize a phased array antenna device, a phase shifter capable of freely controlling the phase of a local signal is required. For example, Patent Document 1 discloses a vector synthesis type analog phase shifter used in a communication device and a radar device.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2003-133906 Summary of the invention

[0007] -Problems to be solved by the invention-

[0008] Patent document 1 discloses that gain setting values ​​and bias voltage values ​​for four differential variable gain amplifiers are read out from a storage device and set, and the output signals of the four differential variable gain amplifiers are synthesized. However, in order to store such gain setting values ​​and bias voltage values, and in order to process signals based on the gain setting values ​​and bias voltage values, the circuit scale and power consumption increase. Therefore, it is required to shift the phase of a signal with a smaller circuit scale and power consumption than before.

[0009] In addition, the phase shifter is required to have a predetermined tolerance to process, voltage, and temperature fluctuations (PVT fluctuations). In addition, the phase shifter is sometimes required to be digitally controllable. In addition, the phase shifter is sometimes required to have a linear control characteristic with respect to a control signal.

[0010] The object of the present disclosure is to provide a signal generating circuit that generates a signal that can be used to control a phase shifter, has a smaller circuit scale and power consumption than before, has tolerance to PVT fluctuations, can be digitally controlled, and has linear control characteristics for the control signal. In addition, the object of the present invention is to provide a phase shifter, an array antenna device, and a wireless communication device having such a signal generating circuit.

[0011] -Methods for solving problems-

[0012] The signal generating circuit involved in the first mode of the present disclosure comprises: a first resistor network circuit, comprising a plurality of first resistors and a plurality of first taps, and generating a control voltage having one of a plurality of predetermined voltage values ​​by selecting one of the plurality of first taps according to an input digital control signal; a second resistor network circuit, comprising a plurality of second resistors and a plurality of second taps, and generating a plurality of predetermined reference voltages from the plurality of second taps; and at least one folding circuit, generating an output signal having a signal level corresponding to a given phase of a sine wave or a cosine wave based on a difference between the control voltage and the plurality of reference voltages.

[0013] According to the signal generating circuit involved in the second embodiment of the present disclosure, in the signal generating circuit involved in the first embodiment, the signal generating circuit comprises: a first folding circuit, which generates a first output signal having a signal level corresponding to a given phase of a sine wave; and a second folding circuit, which generates a second output signal having a signal level corresponding to a given phase of a cosine wave.

[0014] According to the signal generating circuit involved in the third aspect of the present disclosure, in the signal generating circuit involved in the second aspect, the first folding circuit comprises: a first differential amplifier, which compares the control voltage with a first reference voltage to generate a first differential output signal; a second differential amplifier, which compares the control voltage with a second reference voltage higher than the first reference voltage to generate a second differential output signal; and a third differential amplifier, which compares the control voltage with a third reference voltage higher than the second reference voltage to generate a third differential output signal, and the second folding circuit comprises: a fourth differential amplifier, which compares the control voltage with a fourth reference voltage a fifth differential amplifier that compares the control voltage with a fifth reference voltage that is higher than the fourth reference voltage to generate a fifth differential output signal; and a sixth differential amplifier that compares the control voltage with a sixth reference voltage that is higher than the fifth reference voltage to generate a sixth differential output signal, the first output signal being a sum of the first differential output signal and the third differential output signal and an inverted signal of the second differential output signal, and the second output signal being a sum of the fourth differential output signal and the sixth differential output signal and an inverted signal of the fifth differential output signal.

[0015] According to a signal generation circuit according to a fourth aspect of the present disclosure, in the signal generation circuit according to the third aspect, each of the first to sixth differential amplifiers includes a pair of bipolar transistors or a pair of field effect transistors.

[0016] According to a fifth aspect of the present disclosure, in the signal generating circuit according to any one of the first to fourth aspects, the first resistor network circuit further includes a first constant current source connected to the plurality of first resistors.

[0017] According to a sixth aspect of the present disclosure, in the signal generating circuit according to any one of the first to fifth aspects, the first resistor network circuit further includes a voltage dividing resistor connected to an output terminal of the first resistor network circuit.

[0018] According to a seventh aspect of the present disclosure, in the signal generating circuit according to the third aspect, the second resistor network circuit includes voltage dividing resistors that generate the first to sixth reference voltages from a power supply voltage.

[0019] According to the signal generating circuit involved in the eighth embodiment of the present disclosure, in the signal generating circuit involved in the third embodiment, the second resistor network circuit further comprises: a first voltage dividing resistor, which generates the first to third reference voltages from the power supply voltage; and a second voltage dividing resistor, which generates the fourth to sixth reference voltages from the power supply voltage.

[0020] According to the signal generating circuit involved in the ninth embodiment of the present disclosure, in the signal generating circuit involved in the third embodiment, the second resistor network circuit further comprises: a first voltage dividing resistor, which generates the first reference voltage to the third reference voltage from the first power supply voltage; and a second voltage dividing resistor, which generates the fourth reference voltage to the sixth reference voltage from the second power supply voltage.

[0021] According to a signal generating circuit according to a tenth aspect of the present disclosure, in the signal generating circuit according to any one of the first to ninth aspects, the second resistor network circuit further includes: a second constant current source connected to the plurality of second resistors.

[0022] According to the signal generating circuit involved in the eleventh aspect of the present disclosure, in the signal generating circuit involved in the first aspect, the first resistor network circuit and the second resistor network circuit are connected to a common voltage source.

[0023] According to a twelfth aspect of the present disclosure, in the signal generating circuit according to any one of the first to eleventh aspects, the first resistor and the second resistor have the same temperature coefficient.

[0024] According to the signal generating circuit involved in the thirteenth aspect of the present disclosure, in the signal generating circuit involved in any one of the first to twelfth aspects, the first resistor network circuit and the second resistor network circuit are implemented on one integrated circuit.

[0025] The phase shifter involved in the fourteenth embodiment of the present disclosure comprises: a signal generating circuit involved in any one of the second to fourth and seventh to ninth embodiments; an orthogonal distributor, which separates an input signal into an in-phase signal and an orthogonal phase signal; a first multiplier, which multiplies a second output signal of the signal generating circuit by the in-phase signal to generate a first multiplied signal; a second multiplier, which multiplies the first output signal of the signal generating circuit by the orthogonal phase signal to generate a second multiplied signal; and a synthesizer, which synthesizes the first multiplied signal and the second multiplied signal with each other.

[0026] A phase shifter according to a fifteenth aspect of the present disclosure is the phase shifter according to the fourteenth aspect, further comprising a low-pass filter that reduces a signal component having a frequency higher than a predetermined frequency in the first output signal and the second output signal of the signal generating circuit.

[0027] An array antenna device according to a sixteenth aspect of the present disclosure includes: a plurality of antenna elements; a plurality of third mixers; and a plurality of phase shifters according to the fourteenth or fifteenth aspect.

[0028] A wireless communication device according to a seventeenth aspect of the present disclosure includes: the array antenna device according to the sixteenth aspect; and a communication circuit.

[0029] The signal generating circuit involved in the eighteenth mode of the present disclosure comprises: a first resistor network circuit, which has a plurality of first resistors and a plurality of first taps, and generates a control voltage having one of a plurality of predetermined voltage values ​​by selecting one of the plurality of first taps according to an input digital control signal; a second resistor network circuit, which has a plurality of second resistors and a plurality of second taps, and generates a plurality of predetermined reference voltages from the plurality of second taps; at least one folding circuit, which generates an output signal having a signal level corresponding to a given phase of a sine wave or a cosine wave based on a difference between the control voltage and the plurality of reference voltages; and a first impedance conversion circuit, which is arranged between the first resistor network circuit and the folding circuit, the first impedance conversion circuit having an input impedance higher than an impedance from the first resistor network circuit to the folding circuit, and having an output impedance lower than an impedance from the folding circuit to the first resistor network circuit.

[0030] According to the signal generating circuit involved in the nineteenth aspect of the present disclosure, in the signal generating circuit involved in the eighteenth aspect, the first impedance conversion circuit includes an emitter follower circuit, a source follower circuit, or a voltage follower circuit.

[0031] According to the signal generating circuit pertaining to the twentieth aspect of the present disclosure, in the signal generating circuit pertaining to the eighteenth aspect, the first impedance conversion circuit includes a first buffer circuit and a second buffer circuit connected in parallel to each other.

[0032] According to the signal generating circuit involved in the twenty-first aspect of the present disclosure, in the signal generating circuit involved in the eighteenth aspect, the first impedance conversion circuit includes: a first buffer circuit; and a second buffer circuit cascade-connected at a subsequent stage of the first buffer circuit.

[0033] According to the signal generating circuit pertaining to the twenty-second aspect of the present disclosure, in the signal generating circuit pertaining to the twenty-first aspect, the first impedance conversion circuit further includes a third buffer circuit connected in parallel to the second buffer circuit.

[0034] According to the signal generating circuit involved in the twenty-third embodiment of the present disclosure, in the signal generating circuit involved in the eighteenth embodiment, the signal generating circuit further includes: a second impedance conversion circuit, arranged between the second resistor network circuit and the folding circuit, and the second impedance conversion circuit has characteristics same as those of the first impedance conversion circuit with respect to changes in at least one of the manufacturing process, the power supply voltage and the temperature.

[0035] According to the signal generating circuit involved in the twenty-fourth embodiment of the present disclosure, in the signal generating circuit involved in any one of the eighteenth to twenty-third embodiments, the signal generating circuit comprises: a first folding circuit that generates a first output signal having a signal level corresponding to a given phase of a sine wave; and a second folding circuit that generates a second output signal having a signal level corresponding to a given phase of a cosine wave.

[0036] According to the signal generation circuit pertaining to the twenty-fifth aspect of the present disclosure, in the signal generation circuit pertaining to any one of the eighteenth to twenty-fourth aspects, the first resistor and the second resistor have the same temperature coefficient as each other.

[0037] According to the signal generating circuit involved in the twenty-sixth aspect of the present disclosure, in the signal generating circuit involved in any one of the eighteenth to twenty-fifth aspects, the first resistor network circuit and the second resistor network circuit are implemented on one integrated circuit.

[0038] The phase shifter involved in the twenty-seventh embodiment of the present disclosure comprises: the signal generating circuit involved in the twenty-fourth embodiment; an orthogonal distributor, which separates the input signal into an in-phase signal and an orthogonal phase signal; a first multiplier, which multiplies the second output signal of the signal generating circuit by the in-phase signal to generate a first multiplied signal; a second multiplier, which multiplies the first output signal of the signal generating circuit by the orthogonal phase signal to generate a second multiplied signal; and a synthesizer, which synthesizes the first multiplied signal and the second multiplied signal with each other.

[0039] An array antenna device according to a twenty-eighth aspect of the present disclosure includes: a plurality of antenna elements; a plurality of mixers; and a plurality of phase shifters according to the twenty-seventh aspect.

[0040] A wireless communication device according to a twenty-ninth aspect of the present disclosure includes: the array antenna device according to the twenty-eighth aspect; and a communication circuit.

[0041] -Effects of the Invention-

[0042] According to one embodiment of the present disclosure, it is possible to provide a signal generating circuit that has a smaller circuit scale and power consumption than conventional circuits, has tolerance to PVT fluctuations, is digitally controllable, and has linear control characteristics with respect to a control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 1 is a block diagram showing a configuration of a phase shifter 1 including a signal generating circuit 10 according to the first embodiment.

[0044] Figure 2 Yes means Figure 1 2 is a circuit diagram of the structure of the signal generating circuit 10.

[0045] Figure 3 Yes means Figure 2 A circuit diagram showing an example of the structure of the differential amplifiers 31 to 33 and 41 to 43.

[0046] Figure 4 Yes means Figure 2 A circuit diagram of another example of the structure of the differential amplifiers 31 to 33 and 41 to 43.

[0047] Figure 5 It is a rough representation Figure 2 A graph showing the operating characteristics of each of the differential amplifiers 31 to 33 and 41 to 43.

[0048] Figure 6 It is a general statement of Figure 2 Graph showing changes in operating characteristics when the pair of differential amplifiers 31 and 32 are set with different reference voltages Vr2 and Vr4.

[0049] Figure 7 This means that Figure 2 A pair of differential amplifiers 31, 32 generates a signal having a waveform similar to a sine wave.

[0050] Figure 8 Yes Description Figure 1 Graph showing the relationship between the control voltage Vc(k), the reference voltage Vr, and the output signals Vsin(k) and Vcos(k).

[0051] Fig. 9 1 is a circuit diagram showing a configuration of an M-tap resistor network circuit 12A of a signal generating circuit according to a first modification of the first embodiment.

[0052] Fig.10 1 is a circuit diagram showing a configuration of an M-tap resistor network circuit 12B of a signal generating circuit according to a second modification of the first embodiment.

[0053] Fig.11 : is a circuit diagram showing the configuration of an N-tap resistor network circuit 11C of a signal generating circuit according to a third modification of the first embodiment.

[0054] Fig.12 1 is a circuit diagram showing a configuration of an M-tap resistor network circuit 12C of a signal generating circuit according to a third modification of the first embodiment.

[0055] Fig.13 1 is a circuit diagram showing the configuration of an N-tap resistor network circuit 11D and an M-tap resistor network circuit 12D of a signal generating circuit according to a fourth modification of the first embodiment.

[0056] Fig.14 : is a circuit diagram showing the configuration of an N-tap resistor network circuit 11E of a signal generating circuit according to a fifth modification of the first embodiment.

[0057] Fig.15 It is a block diagram showing the configuration of a phase shifter 1F according to a sixth modification of the first embodiment.

[0058] Fig.16 1 is a block diagram showing a configuration of a phase shifter 1G including a signal generating circuit 10G according to the second embodiment.

[0059] Fig.17 Yes means Fig.16 10G is a circuit diagram showing a structure of a signal generating circuit 10G.

[0060] Fig.18 It is a diagram for explaining delay generated in the signal generating circuit 10 according to the first embodiment.

[0061] Fig.19 Yes means Fig.16 A circuit diagram of the structure of the impedance conversion circuit 15.

[0062] Fig. 20 1 is a circuit diagram showing a configuration of an impedance conversion circuit 15A of a signal generating circuit according to a first modification of the second embodiment.

[0063] Fig.21 : is a circuit diagram showing the configuration of an impedance conversion circuit 15B of a signal generating circuit according to a second modification of the second embodiment.

[0064] Fig. 22 : is a circuit diagram showing the configuration of an impedance conversion circuit 15C of a signal generating circuit according to a third modification example of the second embodiment.

[0065] Fig.23 : is a circuit diagram showing a configuration of an impedance conversion circuit 15D of a signal generating circuit according to a fourth modification of the second embodiment.

[0066] Fig.24 : is a circuit diagram showing the configuration of an impedance conversion circuit 15E of a signal generating circuit according to a fifth modification of the second embodiment.

[0067] Fig.25 1 is a block diagram showing a configuration of a phase shifter 1H including a signal generating circuit 10H according to a sixth modification of the second embodiment.

[0068] Fig.26 Yes means Fig.25 10H is a circuit diagram showing a structure of a signal generating circuit 10H.

[0069] Fig. 27 It is a block diagram showing the configuration of a wireless communication device 100 according to the third embodiment. DETAILED DESCRIPTION

[0070] Hereinafter, a signal generation circuit, a phase shifter, an array antenna device, and a wireless communication device according to each embodiment of the present disclosure will be described with reference to the accompanying drawings. In each of the drawings, the same reference numerals represent the same components.

[0071] [First embodiment]

[0072] Figure 1 1 is a block diagram showing a configuration of a phase shifter 1 including a signal generating circuit 10 according to the first embodiment. The phase shifter 1 includes the signal generating circuit 10 and a quadrature modulation circuit 20 .

[0073] The signal generating circuit 10 includes an N-tap resistor network circuit 11, an M-tap resistor network circuit 12, and folding circuits 13 and 14. The N-tap resistor network circuit 11 includes a plurality of resistors and a plurality of N taps, and generates a control voltage Vc(k) having one of N predetermined voltage values ​​by selecting one of the N taps according to an input digital control signal k. The digital control signal k takes any value from 1 to N. The digital control signal k has a size of log2N bits. The M-tap resistor network circuit 12 includes a plurality of resistors and a plurality of M taps, and generates predetermined M reference voltages Vr1, ..., VrM from the M taps. The folding circuit 13 generates an output signal Vsin(k) having a signal level corresponding to a given phase of a sine wave based on the difference between the control voltage Vc(k) and the plurality of reference voltages Vr1, ..., VrM. The folding circuit 14 generates an output signal Vcos(k) having a signal level corresponding to a given phase of a cosine wave based on a control voltage Vc(k) and a difference between a plurality of reference voltages Vr1 , . . . , VrM.

[0074] The orthogonal modulation circuit 20 includes an orthogonal distributor 21, multipliers 22, 23, and a synthesizer 24. The orthogonal distributor 21 distributes the input original frequency signal Vin into a signal VinI of an I component and a signal VinQ of a Q component. The multiplier 22 multiplies the signal VinI of the I component by a signal Vcos(k) output from the folding circuit 14. The multiplier 23 multiplies the signal VinQ of the Q component by a signal Vsin(k) output from the folding circuit 13. When two analog signals are input, the multipliers 22 and 23 output their products. The multipliers 22 and 23 may be, for example, four-quadrant multipliers or variable gain amplifiers. The synthesizer 24 synthesizes the output signals of the multipliers 22 and 23 with each other, and outputs a frequency signal Vout after phase shifting.

[0075] Here, the operation principle of the orthogonal modulation circuit 20 is described. The original frequency signal Vin is a sine wave having an angular frequency ω, which is represented by Vin=sin(ωt). In addition, the following signals Vsin(k) and Vcos(k) are input from the signal generation circuit 10 .

[0076] [Mathematical formula 1]

[0077]

[0078] [Mathematical formula 2]

[0079]

[0080] The orthogonal distributor 21 generates two signals VinI=sin(ωt) and VinQ=cos(ωt) with phases shifted by 90 degrees. Then, the multipliers 22 and 23 multiply the signals Vcos(k) and Vsin(k) input from the signal generation circuit 10 by the signals VinI and VinQ, respectively. The synthesizer 24 synthesizes the output signals of the multipliers 22 and 23 and outputs the frequency signal Vout after phase shift. Therefore, the frequency signal Vout after phase shift is expressed as follows.

[0081] [Mathematical formula 3]

[0082]

[0083] Comparing the original frequency signal Vin and the phase-shifted frequency signal Vout, it can be seen that the phase shifter 1 generates an output signal having a phase shift amount proportional to the value of the digital control signal k.

[0084] The signal generation circuit 10 operates as a control circuit of the quadrature modulation circuit 20 , and controls the phase shift amount of the signal Vin of the quadrature modulation circuit 20 .

[0085] Figure 2 Yes means Figure 1 2 is a circuit diagram of the structure of the signal generating circuit 10.

[0086] The N-tap resistor network circuit 11 includes a plurality of resistors R10, R11, and R12, a plurality of N taps, and a switch SW. The plurality of resistors R10, R11, and R12 are connected in series between a terminal of a positive power supply voltage Vcc and a terminal of a negative power supply voltage Vee. Figure 2 Indicates the case of N = 128. In the N taps between the resistors R10, R11, and R12, different given voltage values ​​Vc1, ..., Vc128 are generated. The multiple resistors R10 have the same resistance value. In this case, the potential difference of the voltage values ​​Vc1, ..., Vc128 is equal to each other. The switch SW selects one of the plurality of N taps according to the digital control signal k, and outputs the corresponding voltage value Vck as the control voltage Vc (k).

[0087] In the present disclosure, for simplicity, the control voltage Vc(k) may also be simply referred to as control voltage Vc.

[0088] The M-tap resistor network circuit 12 includes resistors R21 to R28 and a plurality of M taps. Figure 2Indicates the case of M=6. Resistors R21, R25 to R28 are connected in series between the terminal of the positive power supply voltage Vcc and the terminal of the negative power supply voltage Vee, and are the first voltage-dividing resistors that generate reference voltages Vr2, Vr4, and Vr6 from the power supply voltage. Reference voltages Vr2, Vr4, and Vr6 are generated in the M / 2 taps between resistors R25 to R28. Resistors R21 to R24 and R28 are connected in series between the terminal of the positive power supply voltage Vcc and the terminal of the negative power supply voltage Vee, and are the second voltage-dividing resistors that generate reference voltages Vr1, Vr3, and Vr5 from the power supply voltage. Reference voltages Vr1, Vr3, and Vr5 are generated in the M / 2 taps between resistors R21 to R24. The resistance values ​​of resistors R24 and R25 are set to be equal to each other. The resistance values ​​of resistors R22, R23, R26, and R27 are equal to each other and are set to twice the resistance values ​​of resistors R24 and R25. By setting the resistance values ​​of resistors R22 to R27 in this way, reference voltages Vr1 to Vr6 for simultaneously generating sine waves and cosine waves can be generated.

[0089] In the present disclosure, for simplicity, the reference voltages Vr1 to Vr6 may be simply referred to as reference voltages Vr.

[0090] The resistors R10 , R11 , and R12 of the N-tap resistor network circuit 11 and the resistors R21 to R28 of the M-tap resistor network circuit 12 may also have the same temperature coefficient.

[0091] The folding circuit 13 includes differential amplifiers 31 to 33 and resistors R31 and R32. The differential amplifier 31 compares the control voltage Vc with the reference voltage Vr2 to generate a first differential output signal. The differential amplifier 32 compares the control voltage Vc with a reference voltage Vr4 higher than the reference voltage Vr2 to generate a second differential output signal. The differential amplifier 33 compares the control voltage Vc with a reference voltage Vr6 higher than the reference voltage Vr4 to generate a third differential output signal. The output terminals of the differential amplifiers 31 to 33 are connected to the terminals of the power supply voltage Vcc via the resistors R31 and R32. The first output signal Vsin (k) is the sum of the differential output signals of the differential amplifiers 31 and 33 and the inverted signals of the differential output signal of the differential amplifier 32.

[0092] The folding circuit 14 includes differential amplifiers 41 to 43 and resistors R41 and R42. The differential amplifier 41 compares the control voltage Vc with the reference voltage Vr1 to generate a fourth differential output signal. The differential amplifier 42 compares the control voltage Vc with a reference voltage Vr3 higher than the reference voltage Vr1 to generate a fifth differential output signal. The differential amplifier 43 compares the control voltage Vc with a reference voltage Vr5 higher than the reference voltage Vr3 to generate a sixth differential output signal. The output terminals of the differential amplifiers 41 to 43 are connected to the terminals of the power supply voltage Vcc via the resistors R41 and R42. The second output signal Vcos (k) is the sum of the differential output signals of the differential amplifiers 41 and 43 and the inverted signals of the differential output signal of the differential amplifier 42.

[0093] The signal generating circuit 10 may be implemented by a plurality of discrete components or by one or more integrated circuits. In addition, at least the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 among the components of the signal generating circuit 10 may be implemented on one integrated circuit.

[0094] Figure 3 Yes means Figure 2 A circuit diagram of an example of the structure of differential amplifiers 31 to 33, 41 to 43. Differential amplifiers 31 to 33, 41 to 43 respectively include a pair of bipolar transistors Q1, Q2, a constant current source 51, and resistors Ra to Rd. A control voltage Vc is applied to the base of the bipolar transistor Q1, and a reference voltage Vr (any one of the reference voltages Vr1 to Vr6) is applied to the base of the bipolar transistor Q2. According to the potential difference between the control voltage Vc and the reference voltage Vr, the output current Ix flows through the output terminals dout1 and dout2.

[0095] Figure 4 Yes means Figure 2 The folding circuits 13 and 14 may also include: Figure 4 The differential amplifiers 31A to 33A, 41A to 43A are used instead. Figure 3 Differential amplifiers 31A to 33A, 41A to 43A are provided with a pair of field effect transistors Q1A and Q2A, respectively, instead of Figure 3 Bipolar transistors Q1 and Q2.

[0096] The differential amplifier may include an emitter feedback resistor, or may include a Darlington connection. In addition, the folding circuits 13 and 14 may include a differential amplifier with a cascode connection, or may include a differential amplifier with a two-stage cascode connection.

[0097] Figure 5 It is schematically shown Figure 2 The following is a graph of the operating characteristics of the differential amplifiers 31 to 33, 41 to 43. The output current Ix of each differential amplifier 31 to 33, 41 to 43 varies approximately with the transmission characteristics (solid line) of the hyperbolic sine function tanh (Vc) related to the control voltage Vc or the transmission characteristics (dashed line) of its inverted signal. When the control voltage Vc is within a given voltage range Vtran centered on the reference voltage Vr, the output current Ix varies according to the control voltage Vc, but when the control voltage Vc is outside the voltage range Vtran, the output current Ix does not substantially vary even if the control voltage Vc changes.

[0098] Figure 6 It is a schematic representation of Figure 2 Graph showing changes in operating characteristics when the pair of differential amplifiers 31 and 32 are set with different reference voltages Vr2 and Vr4. Figure 6 The upper, middle and lower layers of φ represent the sum of the output currents of the differential amplifiers 31 and 32, that is, the current Isum′, with respect to the change in the control voltage Vc. Figure 6 The upper layer of shows the case where reference voltages Vr2 and Vr4 (represented as reference voltages Vr2a and Vr4a) having a large difference are set. Figure 6 The lower layer of shows the case where reference voltages Vr2 and Vr4 (expressed as reference voltages Vr2c and Vr4c) having a small difference are set. Figure 6 The middle layer shows the case where reference voltages Vr2 and Vr4 (represented as reference voltages Vr2b and Vr4b) are set to have a difference between them. By combining differential amplifiers 31 and 32 each having a hyperbolic sine function characteristic, the current Isum' varies with respect to the control voltage Vc having a characteristic of connecting two hyperbolic sine functions. Figure 6 In the upper and lower layers, the current Isum' deviates greatly from the sine wave waveform. Figure 6 In the case of the middle layer, it can be seen that by appropriately setting the difference between the reference voltages Vr2 and Vr4, the current Isum' can be well approximated to a sine wave waveform.

[0099] Figure 7 This means that Figure 2 The graph shows that a pair of differential amplifiers 31 and 32 generate a signal having a waveform similar to a sine wave. Formula f1 represents the transmission characteristic of the differential amplifier 31, and formula f2 represents the transmission characteristic of the differential amplifier 32. Formula f3 represents the combined transmission characteristic of the differential amplifiers 31 and 32 adjacent to each other. Formula f4 represents an ideal sine wave. Brepresents the Boltzmann constant, T represents temperature, and q represents elementary charge. According to the curves of equations f1 to f4, within the range of control voltage Vc=2.1 to 2.5, the combined transmission characteristics of the differential amplifiers 31 and 32 can be well approximated to a sine wave waveform.

[0100] Similarly, by appropriately setting the difference between the reference voltages Vr4 and Vr6, the sum of the output currents of the differential amplifiers 32 and 33 can be well approximated to a sine wave waveform. In addition, by appropriately setting the difference between the reference voltages Vr1 and Vr3, the sum of the output currents of the differential amplifiers 41 and 42 can be well approximated to a sine wave waveform. In addition, by appropriately setting the difference between the reference voltages Vr3 and Vr5, the sum of the output currents of the differential amplifiers 42 and 43 can be well approximated to a sine wave waveform.

[0101] The folding circuits 13 and 14 are analog circuits that repeatedly increase and decrease the output voltage in accordance with the increase or decrease of the input voltage.

[0102] Figure 8 Yes Description Figure 1 Graph showing the relationship between the control voltage Vc(k), the reference voltage Vr, and the output signals Vsin(k) and Vcos(k). Figure 8 The upper layer represents the voltage values ​​that the control voltage Vc can take, Vc1, ..., Vc128. Figure 8 The middle layer represents the voltage values ​​Vr1 to Vr6 that the reference voltage Vr can take. Figure 8 The lower layer shows that the magnitudes of the output signals Vsin(k) and Vcos(k) vary according to the control voltage Vc(k).

[0103] The total phase shift amount of the phase shifter 1 is ((M−1) / 4)2π radians. For example, when the control voltage Vc varies over the potential difference of Vr5 - Vr1 (or the potential difference of Vr6 - Vr2 ), a phase shift amount of 2π occurs in the orthogonal modulation circuit 20 .

[0104] The upper and lower limits of the control voltage Vc(k) may be made consistent with the upper and lower limits of the reference voltage Vr (Vc1=Vr1, Vc128=Vr6). In this case, when the kth voltage value is selected in the N-tap resistor network circuit 11, the phase shift amount of the phase shifter 1 is expressed by the following equation.

[0105] [Formula 4]

[0106]

[0107] As described above, the parameter M determines the total phase shift amount of the phase shifter 1. When a large phase shift amount is required, a large M is set when designing the phase shifter 1. In addition, the parameter N determines the resolution at which the digital control signal k can be set. When fine resolution is required, a large N is set when designing the phase shifter 1.

[0108] [Effects of the First Embodiment]

[0109] As described above, the signal generation circuit 10 includes two folding circuits 13 and 14, and an N-tap resistor network circuit 11 and an M-tap resistor network circuit 12 that generate a control voltage Vc and a reference voltage Vr used in the folding circuits 13 and 14, respectively. The folding circuits 13 and 14 generate output signals Vsin(k) and Vcos(k), which have signal levels corresponding to a phase that is a given phase of a sine wave or a cosine wave and changes in proportion to the value of the digital control signal k. The output signals Vsin(k) and Vcos(k) are applied as DC coefficients to two multipliers 22 and 23 of the orthogonal modulation circuit 20. As a result, the phase of the original frequency signal input to the orthogonal modulation circuit 20 is shifted by a phase proportional to the digital control signal k, and is output as a phase-shifted frequency signal. According to the present embodiment, it is possible to provide a signal generating circuit 10 and a phase shifter 1 that have a smaller circuit scale and power consumption than conventional ones, have tolerance to PVT fluctuations, are digitally controllable, and have linear control characteristics with respect to a control signal.

[0110] The phase shifter 1 including the signal generating circuit 10 according to the embodiment has the following advantages compared to the case of referring to data stored in advance in a storage device as in Patent Document 1 (for example, the case of using a lookup table).

[0111] ・The control system circuit can be realized with a much smaller number of components than before, making it easy to design the circuit at a low cost. In addition, the chip size can be reduced, making it possible to realize a low-cost phase shifter.

[0112] When the phase shifter 1 is arranged in the front-end circuit of a wireless terminal device, the signal generation circuit 10 and the orthogonal modulation circuit 20 are both manufactured as high-frequency integrated circuits, so that an analog circuit with high matching can be realized with a small number of components. In addition, it is technically difficult to mount a digital circuit in a high-frequency integrated circuit.

[0113] ・In order to realize massive MIMO (Multiple-Input and Multiple-Output), it is necessary to increase the number of antenna elements in the array antenna device. However, when using high frequency bands such as millimeter waves, it is impossible to increase the number of antenna elements in the array antenna device from the perspective of power consumption, and a method of performing transmission and reception while changing the beam pattern at short time intervals (time division multiple access massive MIMO or virtual massive MIMO) is being studied. When such a method is adopted, the phase shifter needs to be controlled at high speed, and the signal generation circuit needs to be operated at high speed. Therefore, the signal generation circuit 10 can be realized by an analog circuit with a small number of components, which is particularly useful for power consumption.

[0114] The N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 can be implemented by multiple resistors having the same resistance value or multiple resistors having a certain resistance value or a resistance value twice thereof, so in the case of integration, manufacturing deviations can be reduced. In addition, when the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 are implemented using the same type of resistors (for example, resistors having the same temperature coefficient), the control voltage Vc and the reference voltage Vr shift in the same direction and to the same degree according to the changes in the power supply voltage and temperature. The control voltage Vc and the reference voltage Vr are input to the differential amplifiers 31 to 33, 41 to 43, so the voltage shift in the same direction is eliminated by the high common-mode signal elimination ratio (CMRR) of the differential amplifier.

[0115] By installing the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 with resistors having the same temperature coefficient, high resistance to temperature fluctuations can be achieved. In addition, by installing the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 on one integrated circuit, high resistance to manufacturing process fluctuations can be achieved.

[0116] As described above, this circuit has high tolerance to variations in manufacturing process (P), power supply voltage (V), and temperature (T). By having tolerance to PVT variations, it is possible to maintain the same performance in various environments.

[0117] As in the present embodiment, when the control voltage Vc is generated by using an analog control voltage inputted from the outside instead of the N-tap resistor network circuit 11, the control voltage is generated by a mechanism different from the M-tap resistor network circuit 12 inside the phase shifter, so there is a problem of low resistance to PVT changes. On the other hand, according to the present embodiment, the control voltage Vc and the reference voltage Vr are generated respectively by using the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12, that is, the same type of resistor network circuits, so there is a high resistance to PVT changes. In addition, according to the present embodiment, for example, by using the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 that are integrated with each other, the resistance to PVT changes can be further improved.

[0118] The N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 can also be regarded as a digital / analog converter or a potentiometer. In addition, the N-tap resistor network circuit 11 and the M-tap resistor network circuit 12 bring about an arbitrary phase shift by freely designing and setting the voltage step, so they are also collectively referred to as "fine-tuning resistor networks".

[0119] In conventional phase shifters, generally, if the phase is to be changed, the amplitude may also change. In order to reduce such amplitude changes, it is necessary to use a variable gain amplifier provided in the front or rear stage of the phase shifter to digitally correct the amplitude. However, delays are generated due to digital correction. In addition, by providing an operation circuit for digital correction and / or a ROM for storing digital correction values, the circuit scale increases, and as a result, power consumption increases. In contrast, the signal generating circuit 10 involved in the embodiment has a linear control characteristic with respect to the control signal, so the amplitude of the output signal is constant regardless of the phase, and digital correction is not required. Therefore, according to the signal generating circuit 10 involved in the embodiment, it is possible to operate at high speed without delays caused by digital correction, and in addition, it is possible to operate with a smaller circuit scale and power consumption than when digital correction is performed.

[0120] Conventional phase shifters that perform digital correction are typically implemented by circuits including thousands of transistors, have a power consumption of tens to tens of mW, and have a transmission loss of less than 3 dB in a temperature range of ~40°C to 85°C. In contrast, the signal generation circuit 10 according to the embodiment is implemented by a circuit including, for example, about 30 transistors, has a power consumption of about 3 mW, and has a transmission loss of less than 1 dB in a temperature range of ~40°C to 85°C. Therefore, the signal generation circuit 10 according to the embodiment has a smaller circuit scale and power consumption than before, and has a higher tolerance to temperature fluctuations than before.

[0121] [Modification of the first embodiment]

[0122] Fig. 9 1 is a circuit diagram showing the structure of an M-tap resistor network circuit 12A of a signal generating circuit according to a first variant of the first embodiment. The M-tap resistor network circuit 12A includes resistors R21A to R27A. The resistors R21A to R27A are voltage-dividing resistors connected in series between a terminal for a positive power supply voltage Vcc and a terminal for a negative power supply voltage Vee. Reference voltages Vr1 to Vr6 are generated in the M taps between the resistors R21A to R27A. Fig. 9 The M-tap resistor network circuit 12A can use resistors R22A to R26A having the same resistance value, thereby reducing relative manufacturing errors and making the circuit easier to manufacture.

[0123] Fig.10 1 is a circuit diagram showing the structure of an M-tap resistor network circuit 12B of a signal generating circuit according to a second variant of the first embodiment. Resistors R21Ba, R22 to R24, and R28Ba are connected in series between the terminal of the positive power supply voltage Vcc1 and the terminal of the negative power supply voltage Vee1, and are voltage-dividing resistors for generating reference voltages Vr1, Vr3, and Vr5 from the power supply voltage. Resistors R21Bb, R25 to R27, and R28Bb are connected in series between the terminal of the positive power supply voltage Vcc2 and the terminal of the negative power supply voltage Vee2, and are voltage-dividing resistors for generating reference voltages Vr2, Vr4, and Vr6 from the power supply voltage. The power supply voltages Vcc1 and Vcc2 are set to be equal to each other, and the power supply voltages Vee1 and Vee2 are set to be equal to each other. By improving the mutual isolation between the voltage-dividing resistors R21Ba, R22 to R24, and R28Ba and the voltage-dividing resistors R21Bb, R25 to R27, and R28Bb, it is possible to reduce interference caused by signals from the input terminals of the folding circuits 13 and 14. Fig.10 The circuit is effective when the input impedance of the folding circuits 13 and 14 is not high enough.

[0124] Fig.11 : is a circuit diagram showing the configuration of an N-tap resistor network circuit 11C of a signal generating circuit according to a third modification of the first embodiment. Fig.12 The circuit diagram shows the configuration of an M-tap resistor network circuit 12C of a signal generating circuit according to a third modification of the first embodiment. The N-tap resistor network circuit 11C includes a constant current source 61 instead of Figure 2 The tap resistor network circuit 12C has a constant current source 62 instead of Figure 2 When the N-tap resistor network circuit 11C and the M-tap resistor network circuit 12C are integrated into one chip, the constant current sources 61 and 62 can be manufactured with a smaller manufacturing deviation. Fig.11 as well as Fig.12 The structure is suitable for integration.

[0125] Fig.13 1 is a circuit diagram showing the configuration of an N-tap resistor network circuit 11D and an M-tap resistor network circuit 12D of a signal generating circuit according to a fourth modification of the first embodiment. Figure 2 The resistors R21 and R28 are connected to the positive power supply voltage Vcc terminal and the negative power supply voltage Vee terminal via the resistors R11 and R12 of the N-tap resistor network circuit 11D. In other words, the N-tap resistor network circuit 11D and the M-tap resistor network circuit 12D are connected to a common voltage source. This has the effect of preventing the power supply voltage of the N-tap resistor network circuit 11D and the power supply voltage of the M-tap resistor network circuit 12D from deviating.

[0126] Fig.14 1 is a circuit diagram showing a configuration of an N-tap resistor network circuit 11E of a signal generating circuit according to a fifth modification of the first embodiment. Figure 2 In addition to the components of the N-tap resistor network circuit 11, the N-tap resistor network circuit 11E further includes resistors R13 and R14. The resistors R13 and R14 are connected in series with the terminal of the positive power supply voltage Vcc and the terminal of the negative power supply voltage Vee, and the node between the resistors R13 and R14 is connected to the output terminal of the N-tap resistor network circuit 11E. The N-tap resistor network circuit 11E can reduce the impedance of the entire circuit by including the voltage-dividing resistors R13 and R14, and can perform high-speed operation.

[0127] Fig.15 1 is a block diagram showing a configuration of a phase shifter 1F according to a sixth modification of the first embodiment. Figure 1 In addition to the various structural elements of the phase shifter 1, there are also low-pass filters (LPF) 71 and 72 inserted between the signal generating circuit 10 and the orthogonal modulation circuit 20. The low-pass filters 71 and 72 reduce the signal components with a frequency higher than a given frequency in the output signals Vsin (k) and Vcos (k) of the signal generating circuit 10. In a phased array antenna device using a phase shifter, when the phase shifter is controlled at high speed, there is a problem of generating spurious frequencies (unwanted waves) in the output signal of the phased array antenna device. By inserting the low-pass filters 71 and 72 between the signal generating circuit 10 and the orthogonal modulation circuit 20, the phase switching of the phase shifter 1F can be smoothly performed, and the generation of spurious can be prevented.

[0128] [Second embodiment]

[0129] In the second embodiment, a signal generating circuit and a phase shifter which can operate at a higher speed than that in the first embodiment will be described.

[0130] Fig.16 1 is a block diagram showing a configuration of a phase shifter 1G including a signal generating circuit 10G according to the second embodiment. Fig.17 Yes means Fig.16 The phase shifter 1G includes the signal generating circuit 10G instead of Figure 1 The signal generating circuit 10G includes a Figure 1 In addition to the components of the signal generating circuit 10, the present invention further includes an impedance conversion circuit 15 provided between the N-tap resistor network circuit 11 and the folding circuits 13 and 14. The impedance conversion circuit 15 has an input impedance higher than the impedance from the N-tap resistor network circuit 11 to the folding circuits 13 and 14, and has an output impedance lower than the impedance from the folding circuits 13 and 14 to the N-tap resistor network circuit 11.

[0131] Here, “impedance from the N-tap resistor network circuit 11 to the folding circuits 13 and 14” means the impedance when the folding circuits 13 and 14 are observed from the N-tap resistor network circuit 11 when the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are directly connected to each other without passing through the impedance conversion circuit 15. “Impedance from the folding circuits 13 and 14 to the N-tap resistor network circuit 11” means the impedance when the N-tap resistor network circuit 11 is observed from the folding circuits 13 and 14 when the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are directly connected to each other without passing through the impedance conversion circuit 15.

[0132] The impedance conversion circuit 15 outputs a control voltage Vc′(k) which is the same as or proportional to the control voltage Vc(k) input from the N-tap resistor network circuit 11 .

[0133] Fig.18 It is a diagram for explaining delay generated in the signal generating circuit 10 according to the first embodiment. Fig.18 1 shows an equivalent circuit of the N-tap resistor network circuit 11 when the switch SW is connected to a selected one of the plurality of N taps. R15 represents a combined resistance from the selected tap to the terminal of the positive power supply voltage Vcc, and R16 represents a combined resistance from the selected tap to the terminal of the negative power supply voltage Vee. In addition, the differential amplifiers 31 to 33 and the differential amplifiers 41 to 43 are connected to each other, for example. Figure 3 The same structure is used for the case. To simplify the diagram, Fig.18 Only show Figure 3 The bipolar transistors Q1 and Q2 are components of the differential amplifiers 31 to 33 and 41 to 43.

[0134] When each of the differential amplifiers 31 to 33 and 41 to 43 includes bipolar transistors Q1 and Q2, each transistor has a parasitic capacitance Cbc0 (for example, several tens of fF) between the base and the collector. Figure 2 In the example of , the folding circuits 13 and 14 have a total of 6 differential amplifiers 31 to 33, 41 to 43. In addition, one of the two input terminals of each differential amplifier 31 to 33 and differential amplifier 41 to 43 (i.e., the base of the bipolar transistor Q1) is connected in parallel with each other. Therefore, if the folding circuits 13 and 14 are observed from the N-tap resistor network circuit 11, it can be seen that the N-tap resistor network circuit 11 is connected to the parasitic capacitance 6×Cbc0.

[0135] The resistors R15 and R16 of the N-tap resistor network circuit 11 and the parasitic capacitance 6×Cbc0 of the folding circuits 13 and 14 constitute an RC circuit with a given time constant t0, that is, an integrating circuit. The larger the resistance R15×R16 / (R15+R16) when observing the N-tap resistor network circuit 11 from the folding circuits 13 and 14, the larger the time constant t0. In addition, the larger the parasitic capacitance of the folding circuits 13 and 14, the larger the time constant t0. Generally, when an input voltage Vin is applied to a circuit having a resistor R and a capacitor C, the output voltage Vout of the circuit changes according to Vout=Vin(1-exp(-t / RC)), and the circuit has a time constant RC (seconds). In the signal generating circuit 10 involved in the first embodiment, when the digital control signal k is changed to change the phase, the control voltage Vc(k) cannot change to the desired value instantly, but has a slope corresponding to the time constant t0 of the circuit and changes asymptotically to the desired value. The larger the time constant t0 of the circuit is, the longer the time from when the digital control signal k is changed until the control voltage Vc(k) reaches a desired value is.

[0136] When the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are directly connected as in the first embodiment, the time constant t0 of the circuit becomes large for the following reason. As a result, the signal generating circuit 10 may not be able to operate at a sufficiently high speed.

[0137] ・The parasitic capacitance when the folding circuits 13 and 14 are viewed from the N-tap resistor network circuit 11 is relatively large (for example, 6×several tens of fF).

[0138] ・The impedance when the N-tap resistor network circuit 11 is viewed from the folding circuits 13 and 14 is relatively high (for example, several kΩ).

[0139] Fig.16 The signal generating circuit 10G has the following characteristics by including the impedance conversion circuit 15 .

[0140] Since the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are not directly connected to each other, the resistors R15 and R16 of the N-tap resistor network circuit 11 and the parasitic capacitance 6×Cbc0 of the folding circuits 13 and 14 do not constitute an RC circuit.

[0141] Since the impedance conversion circuit 15 has a high input impedance, the N-tap resistor network circuit 11 has a time constant t1 that depends on the resistors R15 and R16 and the capacitance (parasitic capacitance, etc.) around them. The time constant t1 is substantially not affected by the parasitic capacitance 6×Cbc0 of the folding circuits 13 and 14. It is expected that the capacitance around the N-tap resistor network circuit 11 is smaller than the parasitic capacitance 6×Cbc0 of the folding circuits 13 and 14. Therefore, the time constant t1 of the N-tap resistor network circuit 11 is smaller than the time constant t0 in the case where the N-tap resistor network circuit 11 is directly connected to the folding circuits 13 and 14.

[0142] In addition, since the impedance conversion circuit 15 has a low output impedance, the folding circuits 13 and 14 have a time constant t2 that depends on the parasitic capacitance 6×Cbc0 and the resistance around it. The time constant t2 is substantially not affected by the resistors R15 and R16 of the N-tap resistor network circuit 11. It is expected that the resistance around the folding circuits 13 and 14 is smaller than the resistance of the resistors R15 and R16 of the N-tap resistor network circuit 11. Therefore, the time constant t2 of the folding circuits 13 and 14 is smaller than the time constant t0 in the case where the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are directly connected.

[0143] The time constant t1 of the N-tap resistor network circuit 11 and the time constant t2 of the folding circuits 13 and 14 are set to satisfy t1 + t2 < t0.

[0144] Fig.19 Yes means Fig.16A circuit diagram of the structure of the impedance conversion circuit 15. The impedance conversion circuit 15 can be an emitter follower circuit having a bipolar transistor Q101 and a resistor R101. The bipolar transistor Q101 has a parasitic capacitance Cbc1 between the base and the collector. The time constant t1 of the N-tap resistor network circuit 11 depends on the resistors R15, R16 and the parasitic capacitance Cbc1. For example, in the case of Cbc1≈Cbc0, the time constant t1 of the N-tap resistor network circuit 11 becomes approximately 1 / 6 of the time constant t0 in the case where the N-tap resistor network circuit 11 is directly connected to the folding circuits 13 and 14. In addition, the bipolar transistor Q101 has a small on-resistance. The time constant t2 of the folding circuits 13 and 14 depends on the parasitic capacitance 6×Cbc0 and the resistance of the impedance conversion circuit 15. When the on-resistance of the bipolar transistor Q101 is smaller than the resistors R15 and R16 of the N-tap resistor network circuit 11, the time constant t2 of the folding circuits 13 and 14 is smaller than the time constant t0 when the N-tap resistor network circuit 11 and the folding circuits 13 and 14 are directly connected.

[0145] As described above, the signal generating circuit 10G has a time constant smaller than the time constant t0 in the case where the N-tap resistor network circuit 11 is directly connected to the folding circuits 13 and 14. Therefore, the time from when the digital control signal k is changed to when the control voltage Vc (k) reaches the desired value is shortened. In this way, the signal generating circuit 10G involved in the second embodiment can operate at a higher speed than the signal generating circuit 10 involved in the first embodiment. In addition, the signal generating circuit 10G involved in the second embodiment, like the signal generating circuit 10 involved in the first embodiment, can provide a signal generating circuit 10G and a phase shifter 1G that have a smaller circuit scale and power consumption than before, have tolerance to PVT changes, can be digitally controlled, and have linear control characteristics for the control signal.

[0146] Fig. 20 1 is a circuit diagram showing a configuration of an impedance conversion circuit 15A of a signal generating circuit according to a first modification of the second embodiment. The impedance conversion circuit 15A may be a source follower circuit including a field effect transistor Q101A and a resistor R101 and having high input impedance and low output impedance.

[0147] Fig.21 : is a circuit diagram showing a configuration of an impedance conversion circuit 15B of a signal generating circuit according to a second modification of the second embodiment. The impedance conversion circuit 15B may be a voltage follower circuit including an operational amplifier and having high input impedance and low output impedance.

[0148] The signal generating circuit according to the second embodiment is not limited to the emitter follower circuit, the source follower circuit, and the voltage follower circuit, and may include other impedance conversion circuits having high input impedance and low output impedance.

[0149] Fig. 22 1 is a circuit diagram showing a configuration of an impedance conversion circuit 15C of a signal generating circuit according to a third modification of the second embodiment. Fig.19 In addition to the components of the impedance conversion circuit 15, the bipolar transistor Q101 and the resistor R101 constitute a "first buffer circuit", and the bipolar transistor Q102 and the resistor R102 constitute a "second buffer circuit", and these buffer circuits are connected in parallel. When driving the six bipolar transistors Q1 of the differential amplifiers 31 to 33 and 41 to 43, Fig.19 In the single-stage emitter follower circuit shown in FIG. 1 , sufficient base current may not be supplied. On the other hand, Fig. 22 As shown, by connecting two sets of buffer circuits in parallel with each other, sufficient base current can be supplied to the bipolar transistor Q1 of each differential amplifier 31 to 33 and 41 to 43.

[0150] Fig.23 1 is a circuit diagram showing a configuration of an impedance conversion circuit 15D of a signal generating circuit according to a fourth modification of the second embodiment. Fig.19 In addition to the components of the impedance conversion circuit 15, the bipolar transistor Q101 and the resistor R101 constitute a "first buffer circuit", the bipolar transistor Q111 and the resistor R111 constitute a "second buffer circuit", and these buffer circuits are connected in cascade. Fig. 22 When two groups of buffer circuits are connected in parallel as shown in FIG. 1 , it appears that an N-tap resistor network circuit 11 is connected. Fig.19 In the case of 2×Cbc1, the parasitic capacitance is twice that of 2×Cbc1. Fig.19 Compared with the case of , the time constant of the N-tap resistor network circuit 11 increases, and the time from changing the digital control signal k to the control voltage Vc (k) reaching the desired value becomes longer. Fig.23 As shown, by cascading two buffer circuits, the ratio can be reduced without increasing the time constant of the N-tap resistor network circuit 11. Fig.19 In the case of , a large base current is supplied to the bipolar transistor Q1 of each differential amplifier 31 to 33 and 41 to 43.

[0151] Fig.241 is a circuit diagram showing a configuration of an impedance conversion circuit 15E of a signal generating circuit according to a fifth modification of the second embodiment. Fig.23 In addition to the components of the impedance conversion circuit 15D, the bipolar transistor Q112 and the resistor R112 are also provided. The bipolar transistor Q112 and the resistor R112 constitute a "third buffer circuit", and the third buffer circuit is connected in parallel with the second buffer circuit (ie, the bipolar transistor Q111 and the resistor R111). Fig.23 In the example of FIG. 1 , only the emitter follower circuit of the second stage drives the six bipolar transistors Q1 of each differential amplifier 31 to 33, 41 to 43. In this case, it may not be possible to supply sufficient base current. On the other hand, if Fig.24 As shown, by connecting the second and third buffer circuits in parallel with each other, sufficient base current can be supplied to the bipolar transistors Q1 of the differential amplifiers 31 to 33 and 41 to 43 without increasing the time constant of the N-tap resistor network circuit 11 .

[0152] exist Figure 22 to Figure 24 In the example of FIG. 1 , the case where the impedance conversion circuit includes a plurality of emitter follower circuits is described, but the impedance conversion circuit may also include a plurality of source follower circuits.

[0153] Fig.25 1 is a block diagram showing a configuration of a phase shifter 1H including a signal generating circuit 10H according to a sixth modification of the second embodiment. Fig.26 Yes means Fig.25 The phase shifter 1H includes the signal generating circuit 10H instead of Figure 1 The signal generating circuit 10H includes a Figure 16-17 In addition to the components of the signal generating circuit 10G, the circuit further includes impedance conversion circuits 16-1 to 16-6 provided between the M-tap resistor network circuit 12 and the folding circuits 13 and 14. Fig.26 As shown, the impedance conversion circuits 16-1 to 16-6 are respectively provided between the taps of the reference voltages Vr2, Vr4, Vr6, Vr1, Vr3, and Vr5 and the corresponding differential amplifiers 31 to 33 and 41 to 43. Fig.25 In order to simplify the diagram, the impedance conversion circuits 16-1 to 16-6 are denoted by a common reference numeral "16". The impedance conversion circuits 16-1 to 16-6 have the same characteristics as those of the impedance conversion circuit 15 with respect to fluctuations in at least one of the manufacturing process, power supply voltage, and temperature.

[0154] The impedance conversion circuits 16 - 1 to 16 - 6 respectively output reference voltages Vr1 ′ to Vr6 ′ which are the same as or proportional to the reference voltages Vr1 to Vr6 input from the M-tap resistor network circuit 12 .

[0155] Due to the manufacturing process involved in the impedance conversion circuit 15, the power supply voltage or temperature fluctuation, sometimes an undesirable voltage shift occurs in the control voltage Vc'(k). In contrast, by providing the impedance conversion circuits 16-1 to 16-6 having the same characteristics as the impedance conversion circuit 15, the control voltage Vc'(k) and the reference voltages Vr1' to Vr6' shift in the same direction according to the power supply voltage and temperature fluctuations. The control voltage Vc'(k) and the reference voltages Vr1' to Vr6' are input to the differential amplifiers 31 to 33 and 41 to 43, so the voltage shift in the same direction is eliminated by the high common-mode signal cancellation ratio (CMRR) of the differential amplifiers. Even if the voltages generated by the impedance conversion circuits 15 and 16-1 to 16-6 respectively have absolute errors, the voltage shift can be reduced as long as the relative errors between the impedance conversion circuits 15 and 16-1 to 16-6 are small. As described above, the impedance conversion circuit 15H has high resistance to PVT fluctuations by including the impedance conversion circuits 16 - 1 to 16 - 6 .

[0156] In order to realize the simultaneous connection of multiple transmitters and multiple receivers, it is expected to apply the massive MIMO (mMIMO) method using a phased array antenna device including a large number of antenna elements. However, in the high frequency band, the increase in the number of antenna elements may lead to an increase in power consumption. Therefore, the following method is proposed: even when a phased array antenna device including a small number of antenna elements is used, the beam is steered to multiple directions in a short time (for example, a time period of less than 1 symbol), thereby achieving the same function as the mMIMO method. In order to realize such beam steering, it is necessary to control the phase shifter at high speed so that the phase of the signal transmitted and received by each antenna element changes at high speed. In the past, the phase shifter that can set an arbitrary phase, for example, has a digital operation circuit for correcting amplitude changes or a lookup table storing amplitude information, and the operation speed of the phase shifter is limited by the operation speed of the digital operation circuit or the lookup table. According to the second embodiment, the phase shifter can be controlled at high speed without the need for a digital operation circuit and a lookup table, so that the phase of the signal transmitted and received by each antenna element changes at high speed.

[0157] [Third Embodiment]

[0158] Fig. 271 is a block diagram showing a configuration of a wireless communication device 100 according to the third embodiment. The wireless communication device 100 includes a transmission circuit 101, mixers 102-1 to 102-4, amplifiers 103-1 to 103-4, antenna elements 104-1 to 104-4, a frequency synthesizer 105, a frequency multiplier 106, phase shifters 107-1 to 107-4, frequency multipliers 108-1 to 108-4, and a control circuit 109.

[0159] The transmission circuit 101 transmits a baseband signal including data to be transmitted to the mixers 102 - 1 to 102 - 4 .

[0160] The frequency synthesizer 105 generates a high frequency signal having a given frequency. The frequency multiplier 106 multiplies the frequency of the high frequency signal generated by the frequency synthesizer 105 and sends the multiplied frequency signal to the phase shifters 107-1 to 107-4.

[0161] The phase shifters 107-1 to 107-4 are respectively configured similarly to the phase shifter 1 according to the first embodiment or the phase shifters 1G and 1H according to the second embodiment. Digital control signals k1 to k4 are input to each of the phase shifters 107-1 to 107-4 from the control circuit 109. The phase shifters 107-1 to 107-4 change the phase of the high-frequency signal input from the frequency multiplier 106 according to the digital control signals k1 to k4. The control circuit 109 uses the digital control signals k1 to k4 to change the phase of the high-frequency signal independently and arbitrarily.

[0162] The frequency multipliers 108-1 to 108-4 double the frequencies of the high frequency signals output from the phase shifters 107-1 to 107-4 and send the doubled frequencies to the mixers 102-1 to 102-4.

[0163] Mixers 102-1 to 102-4 modulate high frequency signals (radio frequency signals) input from frequency multipliers 108-1 to 108-4 with baseband signals input from transmission circuit 101. Output signals of mixers 102-1 to 102-4 are amplified by amplifiers 103-1 to 103-4, respectively, and then radiated from antenna elements 104-1 to 104-4, respectively.

[0164] Antenna elements 104-1 to 104-4 operate as a phased array antenna device by changing the phase of the transmitted radio frequency signal using phase shifters 107-1 to 107-4. By using phase shifters 107-1 to 107-4 to change the phase of the radio frequency signal with high accuracy, the directivity of the antenna device can be further improved.

[0165] Fig. 27The wireless communication device 100 includes a transmission circuit 101, but the phase shifter 1 according to the first embodiment and the phase shifters 1G and 1H according to the second embodiment can also be applied to a wireless communication device including a reception circuit. When the wireless communication device includes a reception circuit, the direction of arrival of the received signal can be estimated based on the received signal, or a beam can be directed to the direction of arrival using a phase shifter.

[0166] According to the third embodiment, for example, a wireless communication device using a high frequency band such as a millimeter wave or a terahertz wave can be provided.

[0167] [Other embodiments]

[0168] The described embodiments and modifications may be arbitrarily combined.

[0169] exist Figure 2 In other examples, the reference voltages Vr1 to Vr6 for the differential amplifiers 31 to 33, 41 to 43 are set in the order of Vr1 < Vr2 < Vr3 < Vr4 < Vr5 < Vr6, but may also be set in other orders such as Vr2 < Vr1 < Vr4 < Vr3 < Vr6 < Vr5.

[0170] exist Figure 1 In the examples, the case where the signal generating circuit 10 generates both a sine wave and a cosine wave is described, but the technology described in the present disclosure can also be applied to the case where only one of the sine wave and the cosine wave is generated. In this case, the signal generating circuit only has one of the folding circuits 13 and 14. The output signal of the signal generating circuit can also be supplied to any circuit that uses a signal level corresponding to a given phase of the sine wave or the cosine wave, for example, a direct digital synthesizer that digitally generates a sine wave signal or a cosine wave signal.

[0171] [Summary of Implementation Methods]

[0172] The signal generating circuit, phase shifter, array antenna device, and wireless communication device according to each embodiment of the present disclosure can also be expressed as follows.

[0173] The signal generating circuit involved in the first mode of the present disclosure comprises: a first resistor network circuit, comprising a plurality of first resistors and a plurality of first taps, and generating a control voltage having one of a plurality of predetermined voltage values ​​by selecting one of the plurality of first taps according to an input digital control signal; a second resistor network circuit, comprising a plurality of second resistors and a plurality of second taps, and generating a plurality of predetermined reference voltages from the plurality of second taps; and at least one folding circuit, generating an output signal having a signal level corresponding to a given phase of a sine wave or a cosine wave based on a difference between the control voltage and the plurality of reference voltages.

[0174] According to the signal generating circuit involved in the second embodiment of the present disclosure, in the signal generating circuit involved in the first embodiment, the signal generating circuit comprises: a first folding circuit, which generates a first output signal having a signal level corresponding to a given phase of a sine wave; and a second folding circuit, which generates a second output signal having a signal level corresponding to a given phase of a cosine wave.

[0175] According to the signal generating circuit involved in the third aspect of the present disclosure, in the signal generating circuit involved in the second aspect, the first folding circuit comprises: a first differential amplifier, which compares the control voltage with a first reference voltage to generate a first differential output signal; a second differential amplifier, which compares the control voltage with a second reference voltage higher than the first reference voltage to generate a second differential output signal; and a third differential amplifier, which compares the control voltage with a third reference voltage higher than the second reference voltage to generate a third differential output signal, and the second folding circuit comprises: a fourth differential amplifier, which compares the control voltage with a fourth reference voltage a fifth differential amplifier that compares the control voltage with a fifth reference voltage that is higher than the fourth reference voltage to generate a fifth differential output signal; and a sixth differential amplifier that compares the control voltage with a sixth reference voltage that is higher than the fifth reference voltage to generate a sixth differential output signal, the first output signal being a sum of the first differential output signal and the third differential output signal and an inverted signal of the second differential output signal, and the second output signal being a sum of the fourth differential output signal and the sixth differential output signal and an inverted signal of the fifth differential output signal.

[0176] According to a signal generation circuit according to a fourth aspect of the present disclosure, in the signal generation circuit according to the third aspect, each of the first to sixth differential amplifiers includes a pair of bipolar transistors or a pair of field effect transistors.

[0177] According to a fifth aspect of the present disclosure, in the signal generating circuit according to any one of the first to fourth aspects, the first resistor network circuit further includes a first constant current source connected to the plurality of first resistors.

[0178] According to a sixth aspect of the present disclosure, in the signal generating circuit according to any one of the first to fifth aspects, the first resistor network circuit further includes a voltage dividing resistor connected to an output terminal of the first resistor network circuit.

[0179] According to a seventh aspect of the present disclosure, in the signal generating circuit according to the third aspect, the second resistor network circuit includes voltage dividing resistors that generate the first to sixth reference voltages from a power supply voltage.

[0180] According to the signal generating circuit involved in the eighth embodiment of the present disclosure, in the signal generating circuit involved in the third embodiment, the second resistor network circuit further comprises: a first voltage dividing resistor, which generates the first to third reference voltages from the power supply voltage; and a second voltage dividing resistor, which generates the fourth to sixth reference voltages from the power supply voltage.

[0181] According to the signal generating circuit involved in the ninth embodiment of the present disclosure, in the signal generating circuit involved in the third embodiment, the second resistor network circuit further comprises: a first voltage dividing resistor, which generates the first reference voltage to the third reference voltage from the first power supply voltage; and a second voltage dividing resistor, which generates the fourth reference voltage to the sixth reference voltage from the second power supply voltage.

[0182] According to a signal generating circuit according to a tenth aspect of the present disclosure, in the signal generating circuit according to any one of the first to ninth aspects, the second resistor network circuit further includes: a second constant current source connected to the plurality of second resistors.

[0183] According to the signal generating circuit involved in the eleventh aspect of the present disclosure, in the signal generating circuit involved in the first aspect, the first resistor network circuit and the second resistor network circuit are connected to a common voltage source.

[0184] According to the signal generating circuit involved in the twelfth embodiment of the present disclosure, in the signal generating circuit involved in any one of the first to eleventh embodiments, the signal generating circuit further comprises: a first impedance conversion circuit, arranged between the first resistor network circuit and the folding circuit, the first impedance conversion circuit having an input impedance higher than the impedance from the first resistor network circuit to the folding circuit, and having an output impedance lower than the impedance from the folding circuit to the first resistor network circuit.

[0185] According to the signal generating circuit involved in the thirteenth aspect of the present disclosure, in the signal generating circuit involved in the twelfth aspect, the first impedance conversion circuit includes an emitter follower circuit, a source follower circuit, or a voltage follower circuit.

[0186] According to the signal generating circuit of the fourteenth aspect of the present disclosure, in the signal generating circuit of the twelfth or thirteenth aspect, the first impedance conversion circuit includes a first buffer circuit and a second buffer circuit connected in parallel to each other.

[0187] According to the signal generating circuit involved in the fifteenth aspect of the present disclosure, in the signal generating circuit involved in the twelfth or thirteenth aspect, the first impedance conversion circuit includes: a first buffer circuit; and a second buffer circuit cascade-connected at a subsequent stage of the first buffer circuit.

[0188] According to the signal generating circuit pertaining to the sixteenth aspect of the present disclosure, in the signal generating circuit pertaining to the fifteenth aspect, the first impedance conversion circuit further includes a third buffer circuit connected in parallel to the second buffer circuit.

[0189] According to the signal generating circuit involved in the seventeenth embodiment of the present disclosure, in the signal generating circuit involved in any one of the twelfth to sixteenth embodiments, the signal generating circuit further comprises: a second impedance conversion circuit, arranged between the second resistor network circuit and the folding circuit, the second impedance conversion circuit having characteristics same as those of the first impedance conversion circuit with respect to changes in at least one of the manufacturing process, the power supply voltage and the temperature.

[0190] According to the signal generating circuit pertaining to the eighteenth aspect of the present disclosure, in the signal generating circuit pertaining to any one of the first to seventeenth aspects, the first resistor and the second resistor have the same temperature coefficient as each other.

[0191] According to the signal generating circuit involved in the nineteenth aspect of the present disclosure, in the signal generating circuit involved in any one of the first to eighteenth aspects, the first resistor network circuit and the second resistor network circuit are implemented on one integrated circuit.

[0192] The phase shifter involved in the twentieth embodiment of the present disclosure comprises: the signal generating circuit involved in the second embodiment or the signal generating circuit involved in any one of the third to nineteenth embodiments subordinate to the second embodiment; an orthogonal distributor, which separates the input signal into an in-phase signal and an orthogonal phase signal; a first multiplier, which multiplies the second output signal of the signal generating circuit by the in-phase signal to generate a first multiplied signal; a second multiplier, which multiplies the first output signal of the signal generating circuit by the orthogonal phase signal to generate a second multiplied signal; and a synthesizer, which synthesizes the first multiplied signal and the second multiplied signal with each other.

[0193] The phase shifter according to the twenty-first aspect of the present disclosure is the phase shifter according to the twentieth aspect, further comprising: a low-pass filter that reduces a signal component having a frequency higher than a predetermined frequency in the first output signal and the second output signal of the signal generating circuit.

[0194] An array antenna device according to a twenty-second aspect of the present disclosure includes: a plurality of antenna elements; a plurality of third mixers; and a plurality of phase shifters according to the twentieth or twenty-first aspect.

[0195] A wireless communication device according to a twenty-third aspect of the present disclosure includes: the array antenna device according to the twenty-second aspect; and a communication circuit.

[0196] Industrial Applicability

[0197] The signal generating circuit, phase shifter, array antenna device, and wireless communication device according to one embodiment of the present invention can be applied to, for example, a base station or a mobile station of a wireless communication system. The signal generating circuit, phase shifter, array antenna device, and wireless communication device according to one embodiment of the present invention can be applied to, for example, a phase shifter portion of a phased array antenna device for satellite communication and weather radar.

[0198] -Description of Reference Numerals-

[0199] 1. 1F~1H phase shifter

[0200] 10, 10G, 10H signal generation circuit

[0201] 11. 11C~11E N-tap resistor network circuit

[0202] 12, 12A ~ 12D M tap resistor network circuit

[0203] 13, 14 Folding Circuit

[0204] 15, 15A to 15E, 16, 16-1 to 16-6 Impedance conversion circuit

[0205] 20 Quadrature Modulation Circuit

[0206] 21. Orthogonal distributor

[0207] 22, 23 Multiplier

[0208] 24 Synthesizer

[0209] 31~33 Differential amplifier

[0210] 41~43 Differential amplifier

[0211] 51 Constant current source

[0212] 61, 62 Constant current source

[0213] 71, 72 Low-pass filter (LPF)

[0214] 100 Wireless communication device

[0215] 101 Transmitting Circuit

[0216] 102-1~102-4 Mixer

[0217] 103-1~103-4 Amplifier

[0218] 104-1~104-4 Antenna element

[0219] 105 Frequency Synthesizer

[0220] 106 Frequency Multiplier

[0221] 107-1~107-4 Phase Shifter

[0222] 108-1~108-4 Frequency Multiplier

[0223] 109 Control Circuit

[0224] R, R10~R14, R21~R28, R21A~R27A, R21Ba, R21Bb, R28Ba, R28Bb, R31, R32, R41, R42, R101, R102, R1111, R112, Ra~Rd resistor

[0225] Q1, Q2, Q101, Q102, Q111, Q112 Bipolar transistors

[0226] Q1A, Q2A, Q101A Field Effect Transistors

[0227] SW switch.

Claims

1. A signal generating circuit, characterized in that: have: A first resistor network circuit includes a plurality of first resistors and a plurality of first taps, wherein one of the plurality of first taps is selected according to an input digital control signal, thereby generating a control voltage having one of a plurality of predetermined voltage values; A second resistor network circuit includes a plurality of second resistors and a plurality of second taps, and generates a plurality of predetermined reference voltages from the plurality of second taps; as well as At least one folding circuit generates an output signal having a signal level corresponding to a given phase of a sine wave or a cosine wave based on a difference between the control voltage and the plurality of reference voltages.

2. The signal generating circuit according to claim 1, wherein: The signal generating circuit comprises: a first folding circuit for generating a first output signal having a signal level corresponding to a given phase of the sine wave; as well as The second folding circuit generates a second output signal having a signal level corresponding to a given phase of the cosine wave.

3. The signal generating circuit according to claim 2, wherein: The first folding circuit comprises: a first differential amplifier, comparing the control voltage with a first reference voltage to generate a first differential output signal; a second differential amplifier that compares the control voltage with a second reference voltage higher than the first reference voltage to generate a second differential output signal; as well as a third differential amplifier that compares the control voltage with a third reference voltage higher than the second reference voltage to generate a third differential output signal, The second folding circuit comprises: a fourth differential amplifier, comparing the control voltage with a fourth reference voltage to generate a fourth differential output signal; a fifth differential amplifier that compares the control voltage with a fifth reference voltage higher than the fourth reference voltage to generate a fifth differential output signal; as well as a sixth differential amplifier that compares the control voltage with a sixth reference voltage higher than the fifth reference voltage to generate a sixth differential output signal, The first output signal is the sum of the first differential output signal and the inverted signal of the third differential output signal and the second differential output signal. The second output signal is a sum of the fourth differential output signal and inverted signals of the sixth differential output signal and the fifth differential output signal.

4. The signal generating circuit according to claim 3, wherein: Each of the first to sixth differential amplifiers includes a pair of bipolar transistors or a pair of field effect transistors.

5. The signal generating circuit according to claim 1, wherein: The first resistor network circuit further includes: a first constant current source connected to the plurality of first resistors.

6. The signal generating circuit according to claim 1, wherein: The first resistor network circuit further includes a voltage dividing resistor connected to an output terminal of the first resistor network circuit.

7. The signal generating circuit according to claim 3, wherein: The second resistor network circuit includes voltage-dividing resistors that generate the first to sixth reference voltages from a power supply voltage.

8. The signal generating circuit according to claim 3, wherein: The second resistor network circuit further comprises: a first voltage-dividing resistor for generating the first to third reference voltages from a power supply voltage; and The second voltage dividing resistor generates the fourth to sixth reference voltages from the power supply voltage.

9. The signal generating circuit according to claim 3, wherein: The second resistor network circuit further comprises: a first voltage-dividing resistor for generating the first to third reference voltages from a first power supply voltage; and The second voltage dividing resistor generates the fourth to sixth reference voltages from the second power supply voltage.

10. The signal generating circuit according to claim 1, wherein: The second resistor network circuit further includes: a second constant current source connected to the plurality of second resistors.

11. The signal generating circuit according to claim 1, wherein: The first resistor network circuit and the second resistor network circuit are connected to a common voltage source.

12. The signal generating circuit according to claim 1, wherein: The first resistor and the second resistor have the same temperature coefficient as each other.

13. The signal generating circuit according to claim 1, wherein: The first resistor network circuit and the second resistor network circuit are mounted on an integrated circuit.

14. A phase shifter, characterized in that: have: The signal generating circuit according to claim 2; A quadrature splitter that separates the input signal into an in-phase signal and a quadrature-phase signal; a first multiplier, for multiplying the second output signal of the signal generating circuit by the in-phase signal to generate a first multiplied signal; a second multiplier, which multiplies the first output signal of the signal generating circuit by the quadrature phase signal to generate a second multiplied signal; and A synthesizer synthesizes the first multiplied signal and the second multiplied signal with each other.

15. The phase shifter according to claim 14, wherein: The phase shifter further includes a low-pass filter that reduces a signal component having a frequency higher than a predetermined frequency in the first output signal and the second output signal of the signal generating circuit.

16. An array antenna device, characterized in that: have: multiple antenna elements; a plurality of third mixers; and The plurality of phase shifters of claim 14.

17. A wireless communication device, characterized in that: have: The array antenna device according to claim 16; and Communication circuit.

18. A signal generating circuit, characterized in that: have: A first resistor network circuit includes a plurality of first resistors and a plurality of first taps, wherein one of the plurality of first taps is selected according to an input digital control signal, thereby generating a control voltage having one of a plurality of predetermined voltage values; A second resistor network circuit includes a plurality of second resistors and a plurality of second taps, and generates a plurality of predetermined reference voltages from the plurality of second taps; at least one folding circuit for generating an output signal having a signal level corresponding to a given phase of a sine wave or a cosine wave based on a difference between the control voltage and the plurality of reference voltages; as well as A first impedance conversion circuit is arranged between the first resistor network circuit and the folding circuit. The first impedance conversion circuit has an input impedance higher than an impedance from the first resistor network circuit to the folding circuit, and has an output impedance lower than an impedance from the folding circuit to the first resistor network circuit.

19. The signal generating circuit according to claim 18, wherein: The first impedance conversion circuit includes an emitter follower circuit, a source follower circuit or a voltage follower circuit.

20. The signal generating circuit according to claim 18, wherein: The first impedance conversion circuit includes a first buffer circuit and a second buffer circuit connected in parallel to each other.

21. The signal generating circuit according to claim 18, wherein: The first impedance conversion circuit comprises: a first buffer circuit; and A second buffer circuit is cascade-connected to a subsequent stage of the first buffer circuit.

22. The signal generating circuit according to claim 21, wherein: The first impedance conversion circuit further includes a third buffer circuit connected in parallel with the second buffer circuit.

23. The signal generating circuit according to claim 18, wherein: The signal generating circuit further comprises: a second impedance conversion circuit, which is arranged between the second resistor network circuit and the folding circuit. The second impedance conversion circuit has the same characteristics as those of the first impedance conversion circuit with respect to variations in at least one of a manufacturing process, a power supply voltage, and a temperature.

24. The signal generating circuit according to any one of claims 18 to 23, wherein: The signal generating circuit comprises: a first folding circuit for generating a first output signal having a signal level corresponding to a given phase of the sine wave; as well as The second folding circuit generates a second output signal having a signal level corresponding to a given phase of the cosine wave.

25. The signal generating circuit according to claim 18, wherein: The first resistor and the second resistor have the same temperature coefficient as each other.

26. The signal generating circuit according to claim 18, wherein: The first resistor network circuit and the second resistor network circuit are mounted on an integrated circuit.

27. A phase shifter, characterized in that: have: The signal generating circuit as claimed in claim 24; A quadrature splitter that separates the input signal into an in-phase signal and a quadrature-phase signal; a first multiplier, for multiplying the second output signal of the signal generating circuit by the in-phase signal to generate a first multiplied signal; a second multiplier, which multiplies the first output signal of the signal generating circuit by the quadrature phase signal to generate a second multiplied signal; and A synthesizer synthesizes the first multiplied signal and the second multiplied signal with each other.

28. An array antenna device, characterized in that: have: multiple antenna elements; a plurality of mixers; and The plurality of phase shifters of claim 27.

29. A wireless communication device, characterized in that: have: The array antenna device as claimed in claim 28; and Communication circuit.

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