Method of data access control, memory controller of memory device, memory device, and electronic device

Abstract

The present invention relates to a method for performing data access control of a memory device, a memory controller of a memory device, a memory device and an electronic device. The method comprises: receiving a plurality of host commands from a host device to perform data access on a non-volatile memory according to the plurality of host commands, wherein the data access comprises data read; and performing a read parameter optimization procedure to determine at least one optimized read parameter to maintain data read correctness, such as: initializing a reference of an original data indication, a temporary minimum read parameter and a temporary maximum read parameter; calculating a read parameter to be equal to an average of the temporary minimum read parameter and the temporary maximum read parameter; performing a read according to the read parameter to determine the original data indication; and comparing the original data indication with the reference of the original data indication to selectively adjust the temporary read parameter or determine the optimized read parameter.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to memory control, and more particularly, to a method for performing data access control of a memory device and related apparatus. BACKGROUND

[0002] A memory device can include a flash memory for storing data, and access management for the flash memory is quite complex. For example, the memory device can be a memory card, a solid state drive (SSD), or an embedded storage device (e.g., an embedded storage device compliant with the universal flash storage (UFS) specification). When a manufacturer attempts to implement certain features of a memory device according to existing specifications, certain problems can occur, especially in response to host requirements, the memory device can spend too much time performing certain internal operations of the memory device, which results in overall performance degradation. Prior art attempts to solve this problem, however, can introduce more problems (e.g., certain side effects), and thus, an innovative method and related architecture are needed to solve these problems without introducing side effects or by introducing side effects in a less likely manner. SUMMARY

[0003] Therefore, one of the purposes of the present disclosure is to provide a method for performing data access control of a memory device and related apparatus to solve the above problems.

[0004] At least one embodiment of the present disclosure provides a method for performing data access control of a memory device, wherein the method can be applied to a memory controller of the memory device, the memory device can include the memory controller and a non-volatile memory, and the non-volatile memory can include at least one non-volatile memory element (e.g., one or more non-volatile memory elements). The method can include receiving a plurality of host commands from a host device for data access of the non-volatile memory according to the plurality of host commands, wherein the data access includes data read; and performing a read parameter optimization procedure to determine at least one optimized read parameter for maintaining correctness of the data read. For example, the read parameter optimization procedure can include initializing an original data indication reference, a temporary minimum read parameter, and a temporary maximum read parameter, wherein the original data indication reference is determined according to a pre-set setting, and the temporary minimum read parameter and the temporary maximum read parameter are determined as a minimum value and a maximum value, respectively, of an adjustable read parameter range of a read parameter; in any iteration of at least one iteration of the read parameter optimization procedure, calculating the read parameter to be equal to an average of the temporary minimum read parameter and the temporary maximum read parameter; in any iteration, controlling the non-volatile memory to perform a read to obtain respective original data of a plurality of memory cells in a memory cell group according to the read parameter for determining an original data indication, wherein the original data indication represents a number of memory cells whose original data is equal to a predetermined logic value in a case that the memory cell group is read by the memory controller according to the read parameter; and in any iteration, comparing the original data indication with the original data indication reference to determine whether the original data indication is greater than or less than the original data indication reference for selectively adjusting the temporary maximum read parameter or the temporary minimum read parameter to be equal to the read parameter; wherein in a last iteration of the at least one iteration, the memory controller is configured to determine a first optimized read parameter of the at least one optimized read parameter to be equal to the read parameter in response to the original data indication being equal to the original data indication reference.

[0005] In addition to the above method, the present application also provides a memory controller of a memory device, wherein the memory device includes the memory controller and a non-volatile memory, which can include at least one non-volatile memory element (e.g., one or more non-volatile memory elements). Further, the memory controller includes a processing circuit and a transmission interface circuit, wherein the processing circuit is configured to control the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, and the transmission interface circuit is configured to communicate with the host device. Further, the memory controller receives the plurality of host commands from the host device through the transmission interface circuit of the memory controller for data access to the non-volatile memory according to the plurality of host commands, wherein the data access includes a data read. The memory controller performs a read parameter optimization procedure to determine at least one optimized read parameter for maintaining correctness of the data read, for example, the read parameter optimization procedure can include: initializing an original data indication reference, a temporary minimum read parameter, and a temporary maximum read parameter, wherein the original data indication reference is determined according to a preset setting, and the temporary minimum read parameter and the temporary maximum read parameter are respectively determined as a minimum value and a maximum value of an adjustable read parameter range of a read parameter; in any iteration of at least one iteration of the read parameter optimization procedure, calculating the read parameter to be equal to an average of the temporary minimum read parameter and the temporary maximum read parameter; in any iteration, controlling the non-volatile memory to perform a read to obtain respective original data of a plurality of memory cells in a memory cell group according to the read parameter for determining an original data indication, wherein the original data indication represents a number of memory cells whose original data is equal to a predetermined logical value in a case that the memory control reads the plurality of memory cells of the memory cell group according to the read parameter; and in any iteration, comparing the original data indication with the original data indication reference to determine whether the original data indication is greater than or less than the original data indication reference for selectively adjusting the temporary maximum read parameter or the temporary minimum read parameter to be equal to the read parameter; wherein in a last iteration of the at least one iteration, in response to the original data indication being equal to the original data indication reference, the memory controller is configured to determine a first optimized read parameter of the at least one optimized read parameter to be equal to the read parameter.

[0006] In addition to the above method, the present application also provides a memory device including the above memory controller, wherein the memory device includes: a non-volatile memory for storing information; and a memory controller coupled to the non-volatile memory and configured to control operation of the memory device.

[0007] In addition to the above method, the present application also provides an electronic device including the above memory device, wherein the electronic device further includes a host device coupled to the memory device. The host device can include at least one processor for controlling the operation of the host device, and a power supply circuit coupled to the at least one processor and for providing power to the at least one processor and the memory device. In addition, the memory device provides storage space to the host device.

[0008] The method and related devices of the present application can ensure that the memory device can operate properly in different situations, and in particular, can prevent the memory device from spending too much time on certain internal operations of the memory device in response to the request of the host. In addition, the method and related devices of the present application can solve the problems encountered in the prior art without introducing side effects or by means that are unlikely to introduce side effects. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A schematic diagram of an electronic device according to an embodiment of the present application.

[0010] Figure 2 A schematic diagram of a read voltage code control scheme according to an embodiment of the present application.

[0011] Figure 3 A schematic diagram of a program state monitoring control scheme according to an embodiment of the present application.

[0012] Figure 4 A schematic diagram of a read voltage scan control scheme according to an embodiment of the present application.

[0013] Figure 5 A schematic diagram of a read voltage search control scheme for performing data access control of a memory device according to an embodiment of the present application.

[0014] Figure 6 A schematic diagram of a read voltage search control scheme according to an embodiment of the present application. Figure 5 A schematic diagram of some implementation details of the read voltage search control scheme shown.

[0015] Figure 7 A schematic diagram of a read parameter optimization procedure of the method according to an embodiment of the present application.

[0016] Figure 8 A schematic diagram of a read parameter optimization procedure of the method according to another embodiment of the present application.

[0017] Figure 9 A schematic diagram of a workflow of the method according to an embodiment of the present application.

[0018] LIST OF ABBREVIATIONS

[0019] 10: electronic device

[0020] 50: host device

[0021] 52: processor

[0022] 54: power supply circuit

[0023] 58, 118: transmission interface circuit

[0024] 100: memory device

[0025] 110: memory controller

[0026] 112: microprocessor

[0027] 112C: program code

[0028] 112M: read only memory

[0029] 114: control logic circuit

[0030] 115: data access control engine circuit

[0031] 1151: randomization circuit

[0032] 1152: error correction code circuit

[0033] 116: random access memory

[0034] 116T: temporary logical to physical address mapping table

[0035] 120: non-volatile memory

[0036] 120T: global logical to physical address mapping table

[0037] 122-1 ~ 122-N E : non-volatile memory element

[0038] 120C: plurality of memory cells

[0039] Vth Code: read voltage code

[0040] Vth: read voltage

[0041] PS(1) ~ PS(16), PS(Y): candidate program state

[0042] CNT cell: memory cell count

[0043] Diff: cell count difference

[0044] Vth_Opt(y), Vth_Opt(yl), Vth_Opt(y2), Vth_Opt(y3): optimal read voltage

[0045] Vth_Code_Opt(y), Vth_Code_Opt(yl), Vth_Code_Opt(y2), Vth_Code_Opt(y3): optimal read voltage code

[0046] CNT_cell_Ref(y), CNT_cell_Ref(yl), CNT_cell_Ref(y2), CNT_cell_Ref(y3): reference memory cell count

[0047] Sll ~ S13, S14A, S14B, S15A, S15B, S15C, S16, S17, S21 ~ S23, S24A, S24B, S25A, S25B, S25C, S26, S27, S30 ~ S33, S34A, S34B, S35A, S35B, S35C, S36, S37: steps DETAILED DESCRIPTION

[0048] Figure 1Figure 1 shows a schematic diagram of an electronic device 10 according to an embodiment of the present application. The electronic device 10 can include a host device 50 and a memory device 100. The host device 50 can include at least one processor (e.g., one or more processors, which can be collectively referred to as a processor 52), a power supply circuit 54, and a transmission interface circuit 58. The processor 52 and the transmission interface circuit 58 can be coupled to each other through a bus, and can be coupled to the power supply circuit 54 to obtain power. The processor 52 can be configured to control the operation of the host device 50, and the power supply circuit 54 can be configured to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more driving voltages to the memory device 100. The memory device 100 can be configured to provide storage space for the host device 50, and can obtain one or more driving voltages from the host device 50 as power for the memory device 100. Examples of the host device 50 can include, but are not limited to, a multi-functional mobile phone, a tablet computer, a wearable device, and a personal computer, such as a desktop computer and a notebook computer. Examples of the memory device 100 can include, but are not limited to, a portable memory device (e.g., a memory card conforming to the SD / MMC, CF, MS, or XD specification, a solid state drive (SSD), and different types of embedded memory devices (e.g., an embedded memory device conforming to the universal flash storage (UFS) specification or the embedded multi media card (eMMC) specification). According to the present embodiment, the memory device 100 can include a controller, such as a memory controller 110, and can further include a non-volatile memory 120 (labeled as "NV memory" in Figure 1 Figure 1 for brevity), wherein the memory controller 110 is configured to access the non-volatile memory 120, and the non-volatile memory 120 is configured to store information. The non-volatile memory 120 can include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), such as a plurality of non-volatile memory elements 122-1, 122-2, …, and 122-N E (labeled as "NV memory elements" in Figure 1 Figure 1, respectively), wherein "N E " can represent a positive integer greater than 1. For example, the non-volatile memory 120 can be a flash memory, and the plurality of non-volatile memory elements 122-1, 122-2, …, and 122-N E may be a plurality of flash memory wafers or a plurality of flash memory dies, but the present application is not limited thereto.

[0049] As shown in Figure 1As shown, the memory controller 110 can include a processing circuit (e.g., a microprocessor 112), a storage unit (e.g., a read-only memory (ROM) 112M; labeled as "ROM" for brevity), a control logic circuit 114, a data access control (DAC) engine circuit 115, a random access memory 116 (RAM; labeled as "RAM" for brevity, which can be implemented by a static random access memory (SRAM), for example), and a transport interface circuit 118, at least a portion (e.g., one or more) of which can be coupled to each other by a bus. The random access memory 116 can be used to provide internal storage space for the memory controller 110 (e.g., to temporarily store information), although the present application is not limited thereto. In addition, the read-only memory 112M of the present embodiment is used to store program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the non-volatile memory 120, it is noted that the program code 112C can also be stored in the random access memory 116 or any type of memory. In addition, the control logic circuit 114 can be used to control the non-volatile memory 120, and the data access control engine circuit 115 can be used to perform data access control for the memory controller 110, in particular, can include a randomization circuit 1151 and an error correction code (ECC) circuit 1152, in which the randomization circuit 1151 can perform randomization operation on write data (e.g., data to be written into the non-volatile memory 120 during a write / program operation on the non-volatile memory 120 in response to a write command from the host device 50) and de-randomization operation on read data (e.g., data read from the non-volatile memory 120 during a read operation on the non-volatile memory 120 in response to a read command from the host device 50), and the error correction code circuit 1152 can perform error correction code encoding on the write data and error correction code decoding on the read data to protect data and / or perform error correction, although the present application is not limited thereto. According to certain embodiments, at least a portion (e.g., one or more) of the data access control engine circuit 115, such as the randomization circuit 1151 and the error correction code circuit 1152, can be integrated into the control logic circuit 114. For write data, the error correction code circuit 1152 can perform error correction code encoding on data to be written into the non-volatile memory 120 to generate encoded data, and the randomization circuit 1151 can perform randomization operation on the encoded data to generate randomized data for programming into the non-volatile memory 120.For reading data, the randomization circuit 1151 can de-randomize a readout version of the randomized data stored in the non-volatile memory 120 to generate a readout version of the encoded data, and the error correction code circuit 1152 can be used to perform error correction code decoding on the readout version of the encoded data to correct any error therein for returning an error-free version of the encoded data to the host device 50.

[0050] The transmission interface circuit 118 can comply with one or more communication specifications (e.g., Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIe) specification, Embedded Multi-Media Card specification, or Universal Flash Storage specification) and can communicate with the host device 50 (e.g., the transmission interface circuit 58) according to the one or more communication specifications for the memory device 100. Similarly, the transmission interface circuit 58 can comply with the one or more communication specifications and can communicate with the memory device 100 (e.g., the transmission interface circuit 118) according to the one or more communication specifications for the host device 50.

[0051] In the present embodiment, the host device 50 can indirectly access the non-volatile memory 120 in the memory device 100 by transmitting a plurality of host commands and corresponding logical addresses to the memory controller 110. The memory controller 110 receives the plurality of host commands and corresponding logical addresses, and respectively converts the plurality of host commands into a plurality of memory operation commands (which can be simply referred to as operation commands), and controls the non-volatile memory 120 using the plurality of operation commands to read or write / program memory cells or data pages at corresponding physical addresses in the non-volatile memory 120, where the physical addresses can be related to the logical addresses. For example, the memory controller 110 can generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between the physical addresses and the logical addresses, where the non-volatile memory 120 can store a global L2P address mapping table 120T for the memory controller 110 to control the memory device 100 to access data in the non-volatile memory 120, but the present application is not limited thereto.

[0052] For better understanding, the global logic-to-physical address mapping table 120T may be located in a predetermined region (e.g., a system region) within the non-volatile memory element 122-1, but the invention is not limited thereto. For example, the global logic-to-physical address mapping table 120T may be divided into multiple local logic-to-physical address mapping tables, and these multiple local logic-to-physical address mapping tables may be stored in non-volatile memory elements 122-1, 122-2, and 122-N. E In one or more non-volatile memory elements, in particular, they can be stored in non-volatile memory elements 122-1, 122-2 and 122-N, respectively. E When needed, the memory controller 110 may load at least a portion (e.g., part or all) of the global logic-to-physical address mapping table 120T into the random access memory 116 or other memory. For example, the memory controller 110 may load one of the plurality of regional logic-to-physical address mapping tables into the random access memory 116 as a temporary logic-to-physical address mapping table 116T for accessing data in the non-volatile memory 120 based on the regional logic-to-physical address mapping table stored as the temporary logic-to-physical address mapping table 116T. However, the invention is not limited thereto.

[0053] Furthermore, the aforementioned at least one non-volatile memory element (e.g., one or more non-volatile memory elements, such as {122-1, 122-2, ..., 122-N) E The memory controller 110 may contain multiple blocks, wherein the smallest unit for data erasure operations on the non-volatile memory 120 is a block, and the smallest unit for data write operations on the non-volatile memory 120 is a page; however, the invention is not limited thereto. For example, non-volatile memory elements 122-1, 122-2, ... and 122-N... E Any one of the non-volatile memory elements 122-n (the symbol "n" can represent a space in the interval [1, N]) E Any integer in ] can contain multiple blocks, and one of the multiple blocks can contain and record a specific number of pages, wherein the memory controller 110 can access a specific page of a certain block within the multiple blocks according to a block address and a page address.

[0054] According to certain embodiments, for non-volatile memory 120 (or non-volatile memory elements 122-1, 122-2, ... and 122-N therein) EIn some aspects, a read voltage drift phenomenon can occur, and thus the memory controller 110 can attempt to obtain an optimal read voltage Vth_Opt to perform a read operation on the non-volatile memory 120 to correctly read data, where the read voltage can be referred to as a threshold voltage according to some views, and thus the read voltage can be denoted by the symbol "Vth" for better understanding, but the present disclosure is not limited thereto.

[0055] Figure 2 A schematic diagram of a read voltage code control scheme according to an embodiment of the present disclosure. Figure 2 A plurality of memory cells 120C of a memory cell group of the non-volatile memory 120 shown can include a group of memory cells among a plurality of memory cells of any one of the non-volatile memory elements 122-n described above, and any one of the plurality of memory cells 120C can be in a programmed state PS(y) selected from a plurality of candidate programmed states {PS(1), …, PS(Y)}, where "Y" can represent a positive integer, and "y" can be an integer in the interval [1, Y]. For example, the plurality of memory cells 120C can be configured as quad-level cells (QLCs), the candidate programmed state count Y can be equal to 16, and thus the plurality of candidate programmed states {PS(1), …, PS(Y)} can be illustrated as Figure 2 the plurality of candidate programmed states {PS(1), …, PS(16)} shown, but the present disclosure is not limited thereto. The plurality of memory cells 120C can be configured as any one of a plurality of memory cell types, for example, the plurality of memory cells 120C can be configured as single-level cells (SLCs) to store 1 bit per cell of the non-volatile memory elements 122-n, where Y = 2 1 = 2; the plurality of memory cells 120C can be configured as multi-level cells (MLCs), such as double-level cells (DLCs) to store 2 bits per cell of the non-volatile memory elements 122-n, where Y = 2 2 = 4; the plurality of memory cells 120C can be configured as triple-level cells (TLCs) to store 3 bits per cell of the non-volatile memory elements 122-n, where Y = 2 3 = 8; the plurality of memory cells 120C can be configured as quad-level cells to store 4 bits per cell of the non-volatile memory elements 122-n, where Y = 2 4=16; Multiple memory cells 120C can be configured as five-level cells (PLCs) to store 5 bits of each cell in the non-volatile memory elements 122-n, where Y = 2 5 =32; and the rest can be deduced similarly.

[0056] like Figure 2 As shown, when needed, the memory controller 110 can transmit a read voltage code Vth_Code to the non-volatile memory 120 to configure a read voltage Vth corresponding to the read voltage code Vth_Code. For example, the read voltage Vth can be positively correlated with the read voltage code Vth_Code and / or have a linear relationship with the read voltage code Vth_Code, and the read voltage code Vth_Code can be regarded as a representative of the read voltage Vth, but the invention is not limited thereto. In addition, the memory controller 110 can dynamically adjust the read voltage code Vth_Code to dynamically adjust the read voltage Vth to accurately determine the respective programming states {PS(y)} of the plurality of memory cells 120C, and thus correctly determine the bit information corresponding to the programming state {PS(y)}. For example, any candidate programming state PS in the candidate programming states {PS(1),...,PS(16)} can be associated with a corresponding bit sequence in the bit sequence {0000,0001,...,1111} according to a Gray code, and any candidate programming state PS can represent the corresponding bit sequence, but the present invention is not limited thereto. According to some embodiments, the relationship between the bit sequence {0000,0001,...,1111} and the candidate programming states {PS(1),...,PS(16)} can vary.

[0057] Figure 3A schematic diagram of a program status monitoring control scheme according to an embodiment of the present application. The memory controller 110 can increase or decrease the read voltage code Vth Code to correspondingly increase or decrease the read voltage Vth, and monitor the number of memory cells having original data of bit 0 (e.g., original data obtained by reading the memory cells according to the read voltage Vth) as a memory cell count CNT cell to obtain a plurality of monitoring values indicative of a plurality of relationships between the memory cell count CNT cell and the read voltage code Vth Code (or the read voltage Vth) and / or a curve of the memory cell count CNT cell with respect to the read voltage code Vth Code (or the read voltage Vth). In addition, the memory controller 110 can determine a change in the memory cell count CNT cell with respect to the read voltage code Vth Code (or the read voltage Vth), and in particular, can calculate a difference between any two adjacent monitoring values of the memory cell count CNT cell along the Vth Code axis (or the Vth axis) as a change in the memory cell count CNT cell at a corresponding point on the Vth Code axis (or the Vth axis) to obtain a plurality of difference values indicative of a plurality of relationships between the cell count difference Diff and the read voltage code Vth Code (or the read voltage Vth) and / or a curve of the cell count difference Diff with respect to the read voltage code Vth Code (or the read voltage Vth). Thus, the curve of the cell count difference Diff with respect to the read voltage code Vth Code (or the read voltage Vth) can have portions of the curve respectively corresponding to the candidate program status {PS(1),..., PS(Y)}.

[0058] According to certain embodiments, when reading the plurality of memory cells 120C according to the read voltage Vth, the memory controller 110 can obtain original data (e.g., an original bit, such as "1" or "0", read according to the read voltage Vth) for a memory cell among the plurality of memory cells 120C from the non-volatile memory 120. For example, the memory cells in the non-volatile memory 120 can be implemented by floating-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), and whether a current can easily flow through a channel (e.g., an n-channel) of a memory cell depends on the amount of charge (e.g., electrons) stored in the memory cell, where original data (e.g., "0") can indicate that the read voltage Vth and a control gate voltage of the memory cell are high enough to allow the current to flow through the channel, and original data (e.g., "1") can indicate that the read voltage Vth and the control gate voltage are not enough to allow the current to flow through the channel, although the present disclosure is not limited thereto. According to certain embodiments, the architecture of the memory cells in the non-volatile memory 120 can vary.

[0059] Figure 4 A graph illustrating a read voltage scan control scheme according to an embodiment of the present disclosure is shown, where the horizontal axis can represent a read voltage code Vth Code corresponding to a read voltage Vth, and the vertical axis can represent a cell count difference Diff corresponding to a memory cell count CNT cell. For example, the memory cell group can include at least a portion (e.g., a portion or all) of the plurality of memory cells of any one of the non-volatile memory elements 122-1, 122-2, …, and 122-N described above, and the respective programming states {PS(y)} of the memory cells in the memory cell group can vary and have a certain distribution with respect to the read voltage code Vth Code (or the read voltage Vth). For the memory cell group, Figure 4 The curve shown can indicate a portion of the plurality of relationships between the cell count difference Diff and the read voltage code Vth Code (or the read voltage Vth), although the present disclosure is not limited thereto. According to certain embodiments, the range of the read voltage code Vth Code, the range of the cell count difference Diff, and / or the curve shown can vary. According to certain embodiments, the memory cell group can include the memory cells of the non-volatile memory elements 122-1, 122-2, …, and 122-N. Figure 4 The curve shown can indicate a portion of the plurality of relationships between the cell count difference Diff and the read voltage code Vth Code (or the read voltage Vth), although the present disclosure is not limited thereto. According to certain embodiments, the range of the read voltage code Vth Code, the range of the cell count difference Diff, and / or the curve shown can vary. According to certain embodiments, the memory cell group can include the memory cells of the non-volatile memory elements 122-1, 122-2, …, and 122-N. E

[0060] ​For example, assuming V_a ≥ V_min and V_b ≤ V_max, the memory controller 110 can select a predetermined read voltage range [V_a, V_b] (e.g., the range between read voltages V_a and V_b) from an adjustable read voltage range [V_min, V_max] (e.g., the range between the minimum read voltage V_min and the maximum read voltage V_max), and scan the predetermined read voltage range [V_a, V_b] using a fixed step size. In particular, it reads memory cells in the memory cell group according to the read voltages {V_a, (V_a + Vstep), (V_a + (2 * Vstep)), ..., V_b} to obtain relevant information. The memory controller 110 can determine at least one local minimum of the cell count difference Diff based on the relationship between the cell count difference Diff and the read voltage code Vth_Code (e.g., ...). Figure 4 The curve shown is a local minimum value, used to distinguish any two adjacent candidate programming states {PS} among multiple candidate programming states {PS(1),...,PS(Y)} for a group of memory cells. When the read voltage code Vth_Code is used as a representative of the read voltage Vth, the memory controller 110 may select a predetermined read voltage code range [V_a_Code, V_b_Code] (e.g., the range between the minimum read voltage code V_min_Code and the maximum read voltage code V_max_Code corresponding to the minimum read voltage V_min and the maximum read voltage V_max, respectively) from an adjustable read voltage code range [V_min_Code, V_max_Code] (e.g., the range between the read voltage codes V_a_Code and V_b_Code corresponding to the read voltages V_a and V_b, respectively), and scan the predetermined read voltage code range [V_a_Code, V_b_Code] using a fixed step size Vstep_Code (e.g., Vstep_Code = 1) corresponding to a fixed step size Vstep. Taking a series of four-layer memory cells 120C as an example, the memory controller 110 can perform a similar scan operation to determine 15 values ​​on the Vth_Code axis (or Vth axis) corresponding to 15 local minimum values ​​of the cell count difference Diff as 15 optimal read voltage codes {Vth_Code_Opt} (or 15 optimal read voltages {Vth_Opt}) to distinguish candidate programming states {PS(1),...,PS(16)}.

[0061] Because the amount of charge in a memory cell can change over time for some reason, the program state {PS(y)} in a group of memory cells can change correspondingly. When a read error occurs, the memory controller 110 can perform a read retry procedure to attempt to read the non-volatile memory 120 with one or more adjusted read voltages to correct the read error. For example, the memory controller 110 can perform read voltage adjustment according to a read voltage sweep control scheme to accurately determine the respective program states {PS(y)} of the memory cells in a group of memory cells, and thus can correctly determine the respective bit information of the memory cells in a group of memory cells, although the application is not limited thereto. According to some embodiments, the memory controller 110 can perform read voltage adjustment directly according to the memory cell count CNT cell without calculating the cell count difference Diff to increase overall performance.

[0062] Figure 5A schematic diagram of a read voltage search control scheme for a method of performing data access control of a memory device according to an embodiment of the present application. The memory controller 110 can set or adjust the read voltage code Vth Code to set or adjust the read voltage Vth, and monitor the memory cell count CNT cell to search for an optimal read voltage code Vth Code Opt(y) (e.g., an optimal value of the read voltage code Vth Code) corresponding to a reference memory cell count CNT cell Ref(y) (e.g., a reference value of the memory cell count CNT cell) and to search for an optimal read voltage Vth Opt(y) (e.g., an optimal value of the read voltage Vth) corresponding to the reference memory cell count CNT cell Ref(y), where the reference memory cell count CNT cell Ref(y) can be considered as a target memory cell count (e.g., a target value of the memory cell count CNT cell) of one or more search operations, and can be predetermined according to a pre-set setting as a predetermined target value corresponding to a local minimum of the cell count difference Diff. For example, at time point t0, the memory controller 110 can set the read voltage code Vth Code as Vth Code(t=t0) to set the read voltage Vth as Vth(t=t0), monitor the memory cell count CNT cell to determine that the memory cell count CNT cell does not reach the reference memory cell count CNT cell Ref(y), and thus decide to continue the search; at time point t1, the memory controller 110 can set the read voltage code Vth Code as Vth Code(t=t1) to set the read voltage Vth as Vth(t=t1), monitor the memory cell count CNT cell to determine that the memory cell count CNT cell does not reach the reference memory cell count CNT cell Ref(y), and thus decide to continue the search; at time point t2, the memory controller 110 can set the read voltage code Vth Code as Vth Code(t=t2) to set the read voltage Vth as Vth(t=t2), monitor the memory cell count CNT cell to determine that the memory cell count CNT cell reaches the reference memory cell count CNT cell Ref(y), and thus determine that the one or more search operations are completed; but the present application is not limited thereto. According to certain embodiments, the number of times of setting the read voltage code Vth Code (or the read voltage Vth) in the one or more search operations, the range of the read voltage code Vth Code, the range of the memory cell count CNT cell, and / or the like can be pre-determined according to a pre-set setting.Figure 5 The curve shown can vary.

[0063] Since the curve of the cell count difference Diff with respect to the read voltage code Vth Code (or the read voltage Vth) can have (Y-1) local minima (without considering the endpoints of the overall curve), the memory controller 110 can search for (Y-1) optimal read voltage codes {Vth Code Opt (y)} such as {Vth Code Opt (1), …, Vth Code Opt (Y-1)} and search for (Y-1) optimal read voltages {Vth Opt (y)} such as {Vth Opt (1), …, Vth Opt (Y-1)}. Taking the four-layer cell of the plurality of memory cells 120C as an example, the memory controller 110 can perform a similar search operation to determine 15 values on the Vth Code axis (or the Vth axis) as 15 optimal read voltage codes {Vth Code Opt (y)} (or 15 optimal read voltages {Vth Opt (y)}) for distinguishing the candidate programming states {PS (1), …, PS (16)}, where the 15 optimal read voltage codes {Vth Code Opt (y)} (or the 15 optimal read voltages {Vth Opt (y)}) can correspond to 15 local minima of the cell count difference Diff.

[0064] Figure 6 A flowchart of a read voltage search control scheme according to an embodiment of the present application. Figure 5 A schematic diagram of certain implementation details of the read voltage search control scheme shown, where the symbols "yl", "y2", and "y3" can represent three consecutive integers in the interval [1, Y], and yl < y2 < y3. For example, when y = yl, the memory controller 110 can search for the optimal read voltage code Vth Code Opt (yl) and the optimal read voltage Vth Opt (yl) for distinguishing the candidate programming states PS (yl) and PS (yl+1); when y = y2, the memory controller 110 can search for the optimal read voltage code Vth Code Opt (y2) and the optimal read voltage Vth Opt (y2) for distinguishing the candidate programming states PS (y2) and PS (y2+1); when y = y3, the memory controller 110 can search for the optimal read voltage code Vth Code Opt (y3) and the optimal read voltage Vth Opt (y3) for distinguishing the candidate programming states PS (y3) and PS (y3+1); and so on. For brevity, similar details for this embodiment are not repeated in detail here.

[0065] According to certain embodiments, the read voltage code Vth Code can be any integer in the interval [V_min Code, V_max Code], where V_min Code = -128 and V_max Code = +128 (e.g. V_min Code = -128 and V_max Code = +128), but the present application is not limited thereto. According to certain embodiments, the minimum read voltage code V_min Code and the maximum read voltage code V_max Code can vary. Figure 4 to Figure 6 The range of the read voltage code Vth Code shown in any of the figures), but the present application is not limited thereto. According to certain embodiments, the minimum read voltage code V_min Code and the maximum read voltage code V_max Code can vary.

[0066] Figure 7 A flowchart of a read parameter optimization procedure according to an embodiment of the present application, wherein the read parameter optimization procedure can include steps Sll-S13, S14A, S14B, S15A, S15B, S15C, S16 and S17 shown in the workflow Figure 7 The steps Sll-S13, S14A, S14B, S15A, S15B, S15C, S16 and S17 shown in the workflow), but the present application is not limited thereto. The memory controller 110 can perform the read parameter optimization procedure to determine at least one optimized read parameter (e.g. the optimized read voltage code Vth Code Opt(y) and / or the optimized read voltage Vth Opt(y)) corresponding to the reference memory cell count CNT cell Ref(y), and in particular, perform a binary search to search for the optimized read voltage Vth Opt(y) to accurately determine the respective program states {PS(y)} of the memory cells in the memory cell group, and thus can correctly determine the respective bit information of the memory cells in the memory cell group.

[0067] In step Sll, the memory controller can initialize the reference memory cell count CNT cell Ref(y), a temporary minimum memory cell count CNT cell TmpMin, a temporary minimum read voltage Vth TmpMin and a temporary maximum read voltage Vth TmpMax, and in particular, determine the reference memory cell count CNT cell Ref(y) according to a predetermined setting, determine the temporary minimum memory cell count CNT cell TmpMin as a predetermined value (e.g. a maximum obtainable value with all bits equal to a logical value 1, such as 0xFFFF in the case that the temporary minimum memory cell count CNT cell TmpMin has 16 bits), and set Vth TmpMin = V_min and Vth TmpMax = V_max, but the present application is not limited thereto. According to certain embodiments, the initial values of the temporary minimum read voltage Vth TmpMin and the temporary maximum read voltage Vth TmpMax can vary.

[0068] For example, the memory controller 110 can configure a group of memory cells as at least one page having CNT cell GRP memory cells, and the at least one page can be used to store 147456 bits or 18 kilobytes (KB) of data. In a case where no read voltage distribution drift occurs, an ideal value of the memory cell count CNT cell for the at least one optimized read parameter (e.g., the optimal read voltage Vth Opt (y)) can be equal to ((y / Y)*CNT cell GRP) after writing or programming randomized data into the at least one page, and thus the memory controller 110 can set the reference memory cell count CNT cell Ref (y) to ((y / Y)*CNT cell GRP). According to certain embodiments, when CNT cell GRP = 147456, Y = 2, and y = 1, CNT cell Ref (y) = ((y / Y)*CNT cell GRP) = 73728, but the application is not limited thereto. For example, the group memory cell count CNT cell GRP, the program state index y, and / or the candidate program state count Y can vary, and the reference memory cell count CNT cell Ref (y) can also correspondingly vary.

[0069] In step S12, the memory controller 110 can calculate a read voltage Vth to be equal to an average of the current minimum read voltage Vth TmpMin and the temporary maximum read voltage Vth TmpMax, where Vth = (Vth TmpMin + Vth TmpMax) / 2, but the application is not limited thereto. For example, the formula used to calculate the read voltage Vth can vary.

[0070] In step S13, the memory controller 110 can control the non-volatile memory 120 to perform a read operation according to the read voltage Vth to obtain a memory cell count CNT_cell corresponding to the read voltage Vth, particularly, set the read voltage Vth to the non-volatile memory 120 to read the memory cells of the memory cell group according to the read voltage Vth to obtain respective original data (e.g. original bits such as "1" or "0") of the memory cells for determining the memory cell count CNT_cell. The memory cell count CNT_cell can represent a number of memory cells whose original data (e.g. original bits) are equal to a predetermined logic value (e.g. "0") when the memory controller reads the memory cells of the memory cell group according to the read voltage Vth. Among all the original data (e.g. all the original bits) read from the memory cells of the memory cell group, the memory controller 110 can count a number of original bits equal to the logic value "0" as the memory cell count CNT_cell.

[0071] In step S14A, the memory controller 110 can determine whether the memory cell count CNT_cell is greater than the reference memory cell count CNT_cell_Ref(y), if yes (e.g. CNT_cell > CNT_cell_Ref(y)), proceed to step S15A; if no (e.g. CNT_cell ≤ CNT_cell_Ref(y)), proceed to step S14B.

[0072] In step S14B, the memory controller 110 can determine whether the memory cell count CNT_cell is less than the reference memory cell count CNT_cell_Ref(y), if yes (e.g. CNT_cell < CNT_cell_Ref(y)), proceed to step S15B; if no (e.g. CNT_cell = CNT_cell_Ref(y)), proceed to step S17.

[0073] In step S15A, the memory controller 110 can update the temporary maximum read voltage Vth_TmpMax to be equal to the read voltage Vth at this time (e.g. a time point when step S15A is performed).

[0074] In step S15B, the memory controller 110 can update the temporary minimum read voltage Vth_TmpMin to be equal to the read voltage Vth at this time (e.g. a time point when step S15B is performed).

[0075] In step S15C, the memory controller 110 can update the temporary minimum read voltage Vth_TmpMin to be equal to the difference (CNT_cell - CNT_cell_Ref(y)) between the memory cell count CNT_cell at this time (e.g., the time point when step S15C is performed) and the reference memory cell count CNT_cell_Ref(y).

[0076] In step S16, the memory controller 110 can determine whether the temporary minimum read voltage Vth_TmpMin is equal to the temporary maximum read voltage Vth_TmpMax, and if so, proceed to step S17; if not, proceed to step S12.

[0077] In step S17, the memory controller 110 can determine whether the optimal read voltage Vth_Opt(y) is equal to the read voltage Vth at this time (e.g., the time point when step S17 is performed).

[0078] For better understanding, the read parameter optimization procedure can be illustrated by the workflow shown in Figure 7 but the present application is not limited thereto. According to certain embodiments, one or more steps can be added, deleted, or modified in the workflow shown in Figure 7 For example, the memory controller 110 can search for the optimal read voltage code Vth_Code_Opt(y), and certain parameters in the related steps can be changed accordingly.

[0079] Figure 8 A schematic diagram of a read parameter optimization procedure for the method according to another embodiment of the present application, wherein the read parameter optimization procedure can include steps S21-S23, S24A, S24B, S25A, S25B, S25C, S26, and S27 in the workflow shown in Figure 8 but the present application is not limited thereto. The memory controller 110 can perform the read parameter optimization procedure to determine at least one optimized read parameter (e.g., the optimal read voltage code Vth_Code_Opt(y) and / or the optimal read voltage Vth_Opt(y)) corresponding to the reference memory cell count CNT_cell_Ref(y), especially, to search for the optimal read voltage code Vth_Code_Opt(y) in a binary search manner to accurately determine the respective program states {PS(y)} of the memory cells in the memory cell group, and thus can correctly determine the respective bit information of the memory cells in the memory cell group.

[0080] In step S21, the memory controller 110 can initialize the reference memory cell count CNT cell Ref(y), the temporary minimum memory cell count CNT cell TmpMin, a temporary minimum read voltage code Vth Code TmpMin, and a temporary maximum read voltage code Vth Code TmpMax, in particular, the reference memory cell count CNT cell Ref(y) is determined according to a pre-set setting, the temporary minimum memory cell count CNT cell TmpMin is determined as a pre-set value (e.g., a maximum obtainable value such as 0xFFFF), and Vth Code TmpMin = V min Code and Vth Code TmpMax = V max Code are set, but the present application is not limited thereto. According to certain embodiments, the initial values of the temporary minimum read voltage code Vth Code TmpMin and the temporary maximum read voltage code Vth Code TmpMax can vary.

[0081] For example, the memory controller 110 can configure the memory cell group as at least one page having CNT cell GRP memory cells as described above. In the case where no read voltage distribution drift occurs, after writing or programming the randomized data into the at least one page as described above, an ideal value of the memory cell count CNT cell for the at least one optimized read parameter (e.g., the optimal read voltage code Vth Code Opt(y)) can be equal to ((y / Y)*CNT cell GRP), and thus the memory controller 110 can set the reference memory cell count CNT cell Ref(y) as ((y / Y)*CNT cell GRP). According to certain embodiments, when CNT cell GRP = 147456, Y = 2, and y = 1, CNT cell Ref(y) = ((y / Y)*CNT cell GRP) = 73728, but the present application is not limited thereto. For example, the group memory cell count CNT cell GRP, the program state index y, and / or the candidate program state count Y can vary, and the reference memory cell count CNT cell Ref(y) can also correspondingly vary. Moreover, in the case where V min Code = -128 and V max Code = +128, at the time point (e.g., when step S21 is performed) Vth Code TmpMin = V min Code = -128 and Vth Code TmpMax = V max Code = +128.

[0082] In step S22, the memory controller 110 can calculate the read voltage code Vth Code to be equal to an average of the temporary minimum read voltage code Vth Code TmpMin and the temporary maximum read voltage code Vth Code TmpMax, where Vth Code = (Vth Code TmpMin + Vth Code TmpMax) / 2, but the present application is not limited thereto. For example, the formula used to calculate the read voltage code Vth Code described above can be varied.

[0083] In step S23, the memory controller 110 can control the non-volatile memory to perform a read operation to obtain a memory cell count CNT cell corresponding to the read voltage code Vth Code, in particular, the read voltage code Vth Code can be set to the non-volatile memory 120 to read memory cells of the memory cell group according to the read voltage code Vth Code to obtain respective original data (e.g., original bits such as "1" or "0") of the memory cells for determining the memory cell count CNT cell. The memory cell count CNT cell can represent a number of memory cells whose original data (e.g., original bits) are equal to a predetermined logic value (e.g., "0") when the memory controller reads memory cells of the memory cell group according to the read voltage Vth. Among all original data (e.g., all original bits) read from the memory cells of the memory cell group, the memory controller 110 can count a number of original bits equal to the logic value "0" as the memory cell count CNT cell.

[0084] In step S24A, the memory controller 110 can determine whether the memory cell count CNT cell is greater than the reference memory cell count CNT cell Ref(y), if yes (e.g., CNT cell > CNT cell Ref(y)), proceed to step S25A; if no (e.g., CNT cell ≤ CNT cell Ref(y)), proceed to step S24B.

[0085] In step S24B, the memory controller 110 can determine whether the memory cell count CNT cell is less than the reference memory cell count CNT cell Ref(y), if yes (e.g., CNT cell < CNT cell Ref(y)), proceed to step S25B; if no (e.g., CNT cell = CNT cell Ref(y)), proceed to step S27.

[0086] In step S25A, the memory controller 110 can update the temporary maximum read voltage code Vth_Code_TmpMax to be equal to the read voltage code Vth_Code at this time (e.g., the time point when step S25A is executed).

[0087] In step S25B, the memory controller 110 can update the temporary minimum read voltage code Vth_Code_TmpMin to be equal to the read voltage code Vth_Code at this time (e.g., the time point when step S25B is executed).

[0088] In step S25C, the memory controller 110 can update the temporary minimum read voltage code Vth_Code_TmpMin to be equal to the difference (CNT_cell - CNT_cell_Ref(y)) between the memory cell count CNT_cell at this time (e.g., the time point when step S25C is executed) and the reference memory cell count CNT_cell_Ref(y).

[0089] In step S26, the memory controller 110 can determine whether the temporary minimum read voltage code Vth_Code_TmpMin is equal to the temporary maximum read voltage code Vth_Code_TmpMax, if yes, proceed to step S27; if no, proceed to step S22.

[0090] In step S27, the memory controller 110 can decide the optimal read voltage code Vth_Code_Opt(y) to be equal to the read voltage code Vth_Code at this time (e.g., the time point when step S27 is executed).

[0091] For better understanding, the read parameter optimization procedure can be illustrated by the workflow shown in FIG. 2, but the present disclosure is not limited thereto. According to certain embodiments, one or more steps can be added, deleted, or modified in the workflow shown in FIG. 2. Figure 8 Figure 8

[0092] ​​According to certain embodiments, the memory controller 110 can adjust the read voltage Vth of step S12 and / or the read voltage code Vth_Code of step S22 according to the latest value of the temporary minimum memory cell count CNT_cell_TmpMin to increase overall performance. For example, the memory cell count CNT_cell can be positively correlated with the read voltage Vth, and the temporary minimum memory cell count CNT_cell_TmpMin can indicate a projection on the CNT_cell axis of a distance between a current point (Vth, CNT_cell) and a target point (Vth_Opt(y), CNT_cell_Ref(y)). When the temporary minimum memory cell count CNT_cell_TmpMin has been updated in step S15C of the workflow shown in FIG. 15, the memory controller 110 can update the weights of the temporary minimum read voltage Vth_TmpMin and the temporary maximum read voltage Vth_TmpMax in step S12 as follows: Vth = (fll*Vth_TmpMin) + (f12*Vth_TmpMax); Figure 7

[0093] where 0 < fll < 1, 0 < f12 < 1, and fll + f12 = 1. In particular, the weights fll and f12 can represent weight functions fll(CNT_cell_TmpMin) and f12(CNT_cell_TmpMin), respectively, and the above equation can be expressed as follows:

[0094] Vth = (fll(CNT_cell_TmpMin)*Vth_TmpMin) + (f12(CNT_cell_TmpMin)*Vth_TmpMax);

[0095] where the memory controller 110 can utilize the weight functions fll(CNT_cell_TmpMin) and f12(CNT_cell_TmpMin) to cause the temporary minimum memory cell count CNT_cell_TmpMin to converge or approach 0 rapidly. For another example, the memory cell count CNT_cell can be positively correlated with the read voltage code Vth_Code, and the temporary minimum memory cell count CNT_cell_TmpMin can indicate a projection on the CNT_cell axis of a distance between a current point (Vth_Code, CNT_cell) and a target point (Vth_Code_Opt(y), CNT_cell_Ref(y)). When the temporary minimum memory cell count CNT_cell_TmpMin has been updated in step S15C of the workflow shown in FIG. 15, the memory controller 110 can update the weights of the temporary minimum read voltage code Vth_Code_TmpMin and the temporary maximum read voltage code Vth_Code_TmpMax in step S22 as follows: Vth_Code = (fll*Vth_Code_TmpMin) + (f12*Vth_Code_TmpMax); Figure 8 ​When the step S25C is updated in the illustrated workflow, the memory controller 110 can update the weights of the temporary minimum read voltage code Vth_Code_TmpMin and the temporary maximum read voltage code Vth_Code_TmpMax in the step S22 as follows:

[0096] Vth_Code = (f21*Vth_Code_TmpMin) + (f22*Vth_Code_TmpMax);

[0097] where 0≤f21≤1, 0≤f22≤1, and f21+f22=1. In particular, the weights f21and f22may represent the weight functions f21(CNT_cell_TmpMin) and f22(CNT_cell_TmpMin), respectively, and the above equation can be expressed as follows:

[0098] Vth_Code = (f21(CNT_cell_TmpMin)*Vth_Code_TmpMin) + (f22(CNT_cell_TmpMin)*Vth_Code_TmpMax);

[0099] where the memory controller 110 can utilize the weight functions f21(CNT_cell_TmpMin) and f22(CNT_cell_TmpMin) to cause the temporary minimum memory cell count CNT_cell_TmpMin to converge or approach 0 rapidly. For brevity, similar details for these embodiments are not repeated in detail herein.

[0100]

[0101] Table I illustrates an example of certain parameters in one or more search operations described above, where the symbol "CNT_s" can represent a cumulative number of search operations, but the present application is not limited thereto. The reference memory cell count CNT_cell_Ref(y) can be equal to 72000, and the initial values of the temporary minimum read voltage code Vth_Code_TmpMin and the temporary maximum read voltage code Vth_Code_TmpMax can be equal to -128 and +128, respectively. When Vth_Code_TmpMin = -128 and Vth_Code_TmpMax = +128, the memory controller 110 can calculate the read voltage code Vth_Code to be equal to 0 in step S22, and determine CNT_cell = 72000 in step S23, where CNT_s = 1. Since the memory cell count CNT_cell has reached the reference memory cell count CNT_cell_Ref(y), the memory controller 110 can determine Vth_Code_Opt(y) = Vth_Code = 0 in step S27, and complete the operation of searching the optimal read voltage code Vth_Code_Opt(y).

[0102] Table II

[0103]

[0104] Table II illustrates another example of certain parameters in one or more searching operations described above, but the present application is not limited thereto. Referring to the memory cell count CNT_cell_Ref(y) can be equal to 72000, and the temporary minimum read voltage code Vth_Code_TmpMin and the temporary maximum read voltage code Vth_Code_TmpMax can be equal to -50 and +100, respectively. When Vth_Code_TmpMin = -50 and Vth_Code_TmpMax = +100, the memory controller 110 can calculate the read voltage code Vth_Code to be equal to +25 in step S22, and determine CNT_cell = 82000 in step S23, where CNT_s = 1. When Vth_Code_TmpMin = -50 and Vth_Code_TmpMax = +25, the memory controller 110 can calculate the read voltage code Vth_Code to be equal to -12 in step S22, and determine CNT_cell = 71000 in step S23, where CNT_s = 2. When Vth_Code_TmpMin = -12 and Vth_Code_TmpMax = +25, the read voltage code Vth_Code is calculated to be equal to +6 in step S22, and CNT_cell = 72000 is determined in step S23, where CNT_s = 3. Since the memory cell count CNT_cell has reached the reference memory cell count CNT_cell_Ref(y), the memory controller 110 can determine Vth_Code_Opt(y) = Vth_Code = +6 in step S27, and complete the operation of searching the optimal read voltage code Vth_Code_Opt(y).

[0105] According to certain embodiments, the memory controller 110 can adjust the fixed step size Vstep_Code for performing the related operations (e.g., scanning and / or searching operations) in the predetermined read voltage code range [V_a_Code, V_b_Code], and in particular, the fixed step size Vstep_Code can be set to any other value greater than 1. For brevity, similar contents for these embodiments are not repeated in detail herein.

[0106] Table III

[0107]

[0108] Table III illustrates yet another example of certain parameters in one or more search operations described above, wherein the symbol "..." can indicate that certain table contents are deleted, but the present application is not limited thereto. Referring to the memory cell count CNT_cell_Ref(y) can be equal to 72000, and the temporary minimum read voltage code Vth_Code_TmpMin and the temporary maximum read voltage code Vth_Code_TmpMax can be equal to -128 and +128, respectively. When Vth_Code_TmpMin = -128 and Vth_Code_TmpMax = +128, the memory controller 110 can calculate the read voltage code Vth_Code to be equal to 0 in step S22, and determine the memory cell count CNT_cell to be a first value in step S23, wherein CNT_s = 1. When Vth_Code_TmpMin = 0 and Vth_Code_TmpMax = +128, the memory controller 110 can calculate the read voltage code Vth_Code to be equal to +64 in step S22, and determine the memory cell count CNT_cell to be a second value in step S23, wherein CNT_s = 2. When Vth_Code_TmpMin = 0 and Vth_Code_TmpMax = +64, the memory controller 110 can calculate the read voltage code Vth_Code to be equal to +32 in step S22, and determine the memory cell count CNT_cell to be a third value in step S23, wherein CNT_s = 3. The rest can be similarly deduced, for example, when Vth_Code_TmpMin = 0 and Vth_Code_TmpMax = +2, the memory controller 110 can calculate the read voltage code Vth_Code to be equal to +1 in step S22, and determine the memory cell count CNT_cell to be 72000 in step S23, wherein CNT_s = 8. Since the memory cell count CNT_cell has reached the reference memory cell count CNT_cell_Ref(y), the memory controller 110 can determine Vth_Code_Opt(y) = Vth_Code = +1 in step S27, and complete the operation of searching the optimal read voltage code Vth_Code_Opt(y).

[0109] As illustrated by the example shown in Table III, even in the worst case (e.g., in the case where CNT_s = 8 and the entire range of read voltage codes Vth_Code equals the interval [-128, +128]), the memory controller 110 can still quickly complete the operation of searching for the optimal read voltage code Vth_Code_Opt(y). Moreover, the memory controller 110 can utilize the entire range of read voltage codes Vth_Code to cover any possible read voltage drift phenomenon and set the fixed step size Vstep_Code to the smallest achievable value (e.g., 1) to increase the searching accuracy. Therefore, the method and related apparatus of the present application can increase the overall performance.

[0110] Figure 9 A flowchart illustrating the workflow of the method according to an embodiment of the present application. The memory controller 110 can receive a plurality of host commands from the host device 50 via the transmission interface circuit 118 for performing data access (e.g., data read and data write / program) to the non-volatile memory 120 according to the plurality of host commands and can perform a read parameter optimization procedure to determine at least one optimized read parameter PARA_r(y) (e.g., optimized read parameters {PARA_r(1), …, PARA_r(Y-1)} corresponding to raw data indication references {IND_raw_Ref(1), …, IND_raw_Ref(Y-1)}) corresponding to at least one raw data indication reference IND_raw_Ref(y) for maintaining the correctness of data read, wherein the at least one optimized read parameter PARA_r(y) can include one or a combination of the optimal read voltage Vth_Opt(y) and the optimal read voltage code Vth_Code_Opt(y). For example, the read parameter optimization procedure can include Figure 9 The steps S31-S33, S34A, S34B, S35A, S35B, S35C, S36, and S37 in the workflow shown, but the present application is not limited thereto. The memory controller 110 can perform the read parameter optimization procedure to determine the at least one optimized read parameter PARA_r(y) (e.g., the optimal read voltage code Vth_Code_Opt(y) and / or the optimal read voltage Vth_Opt(y)), especially, to search for the optimized read parameter PARA_r(y) in a binary search manner to accurately determine the respective program states {PS(y)} of the memory cells in the memory cell group and thus determine the respective bit information of the memory cells in the memory cell group.

[0111] In step S30, the memory controller may determine whether to perform optimization operation on a read parameter PARA_r (e.g., read voltage Vth or read voltage code Vth_Code). If yes, proceed to step S31; if no, re-enter step S30.

[0112] In step S31, the memory controller 110 may specify the following parameters: raw data indication reference IND_raw_Ref(y) (e.g., the reference memory cell count CNT_cell_Ref(y) in steps S11 and S21), a temporary minimum raw data indication IND_raw_TmpMin (e.g., the temporary minimum memory cell count CNT_cell_TmpMin in steps S11 and S21), a temporary minimum read parameter PARA_r_TmpMin (e.g., the temporary minimum read voltage Vth_TmpMin in step S11 or the temporary minimum read voltage code Vth_Code_TmpMin in step S21), and a temporary maximum read parameter PARA_r_TmpMax. (For example, the temporary maximum read voltage Vth_TmpMax in step S11 or the temporary maximum read voltage code Vth_Code_TmpMax in step S21). In particular, the raw data indication reference IND_raw_Ref(y) can be determined according to a preset setting, the temporary minimum raw data indication IND_raw_TmpMin is determined to a preset value (e.g., the maximum obtainable value, such as 0xFFFF), and PARA_r_TmpMin = PARA_r_min (e.g., V_min or V_min_Code) and PARA_r_TmpMax = PARA_r_max (e.g., V_max or V_max_Code) are set, but the invention is not limited thereto. According to some embodiments, the initial values ​​of the temporary minimum read parameter PARA_r_TmpMin and the temporary maximum read parameter PARA_r_TmpMax can be varied.

[0113] In step S32, the memory controller 110 may calculate the read parameter PARA_r (e.g., the read voltage Vth in step S12 or the read voltage code Vth_Code in step S22) to be equal to the average of the temporary minimum read parameter PARA_r_TmpMin and the temporary maximum read parameter PARA_r_TmpMax, where PARA_r = (PARA_r_TmpMin + PARA_r_TmpMax) / 2. However, the present invention is not limited thereto. For example, the formula used to calculate the read parameter PARA_r described above can be varied.

[0114] In step S33, the memory controller 110 can control the non-volatile memory 120 to perform a read operation according to the read parameter PARA_r to obtain a raw data indicator IND_raw (e.g., memory cell count CNT_cell) corresponding to the read parameter PARA_r. In particular, the read parameter PARA_r can be set to the non-volatile memory 120 to read memory cells in the memory cell group according to the read parameter PARA_r to obtain the raw data of each memory cell to determine the raw data indicator IND_raw. The raw data of each memory cell in the memory cell group can represent multiple raw bits (e.g., "1" and "0"), wherein the raw data of any one of the memory cells is equal to a predetermined logical value (e.g., "0") or another predetermined logical value (e.g., "1").

[0115] For example, the raw data indicator IND_raw can be equal to the memory cell count CNT_cell. Therefore, the raw data indicator reference IND_raw_Ref(y) can be rewritten as the reference memory cell count CNT_cell_Ref(y), and the memory cell count CNT_cell can represent the number of memory cells whose raw bits are equal to a preset logic value (e.g., "0") when the memory controller 110 reads memory cells in the memory cell group according to the read parameter PARA_r. However, the present invention is not limited thereto. For example, when the memory controller 110 reads a memory cell from a memory cell group according to the read parameter PARA_r, the raw data indicator IND_raw can be equal to the bit count CNT_Bit0 of the raw bit that is equal to a preset logic value (e.g., "0"). Therefore, the raw data indicator reference IND_raw_Ref(y) can be rewritten to the reference bit count CNT_Bit0_Ref(y) (e.g., CNT_Bit0_Ref(y) = CNT_cell_Ref(y)), and the temporary minimum raw data indicator IND_raw_TmpMin can be rewritten to the temporary minimum bit count CNT_Bit0_TmpMin (e.g., CNT_Bit0_TmpMin = CNT_cell_TmpMin).

[0116] In step S34A, the memory controller 110 can determine whether the original data indicator IND_raw is greater than the original data indicator reference IND_raw_Ref(y). If yes (e.g., IND_raw>IND_raw_Ref(y)), proceed to step S35A; if no (e.g., IND_raw≤IND_raw_Ref(y)), proceed to step S34B.

[0117] In step S34B, the memory controller 110 may determine whether the original data indication IND_raw is less than the original data indication reference IND_raw_Ref(y). If so (e.g., IND_raw < IND_raw_Ref(y)), it proceeds to step S35B; if not (e.g., IND_raw = IND_raw_Ref(y)), it proceeds to step S37.

[0118] In step S35A, the memory controller 110 may update the temporary maximum read parameter PARA_r_TmpMax to be equal to the read parameter PARA_r at this time (e.g., the time point when step S35A is executed).

[0119] In step S35B, the memory controller 110 may update the temporary minimum read parameter PARA_r_TmpMin to be equal to the read parameter PARA_r at this time (e.g., the time point when step S35B is executed).

[0120] In step S35C, the memory controller 110 may update the temporary minimum original data indication IND_raw_TmpMin to be equal to the difference (IND_raw - IND_raw_Ref(y)) between the original data indication IND_raw and the original data indication reference IND_raw_Ref(y) at this time (e.g., the time point when step S35C is executed).

[0121] In step S36, the memory controller 110 may determine whether the temporary minimum read parameter PARA_r_TmpMin is equal to the temporary maximum read parameter PARA_r_TmpMax. If so, it proceeds to step S37; if not, it proceeds to step S32.

[0122] In step S37, the memory controller 110 may determine the optimized read parameter PARA_r(y) (e.g., the optimal read voltage Vth_Opt(y) in step S17 or the optimal read voltage code Vth_Code_Opt(y) in step S27) to be equal to the read parameter PARA_r (e.g., the read voltage Vth or the read voltage code Vth_Code) at this time (e.g., the time point when step S37 is executed).

[0123] In any of the at least one iteration of the read parameter optimization procedure, the memory controller 110 may calculate the read parameter PARA_r in step S32, control the non-volatile memory 120 to perform a read operation based on the read parameter PARA_r in step S33 to obtain the raw data indicator IND_raw, and compare the raw data indicator IND_raw with the raw data indicator reference IND_raw_Ref(y) in one or more steps S34A and S34B to determine whether the raw data indicator IND_raw is greater than or less than the raw data indicator reference IND_raw_Ref(y), so as to selectively adjust the temporary maximum read parameter in step S35A or adjust the temporary minimum read parameter in step S35B to be equal to the read parameter. In the last iteration of the above at least one iteration, since the original data indicator IND_raw and the original data indicator reference IND_raw_Ref(y) are equal, the memory controller 110 can determine the optimized read parameter PARA_r(y) to be equal to the read parameter PARA_r in step S37. For example, the memory controller can perform at least one binary search to determine the average of the temporary minimum read parameter PARA_r_TmpMin and the temporary maximum read parameter PARA_r_TmpMax in order to quickly complete the search operation of the optimized read parameter PARA_r(y).

[0124] To better understand this method, it can be achieved through... Figure 9 The workflow shown is intended to illustrate the invention, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 9 In the illustrated workflow, additions, deletions, or modifications may be made. For example, multiple host commands may include the aforementioned read command, and an uncorrectable error correction code (UECC) error may occur during the reading of non-volatile memory 120 according to the read command. The memory controller 110 may have already used the error correction code circuit 1152 to encode the read version of the encoded data using the error correction code, but the encoded data cannot be recovered. In response to the occurrence of the uncorrectable error correction code error, the memory controller 110 may perform a read retry procedure to attempt to read non-volatile memory 120 using at least one adjusted read voltage Vth, wherein at least one optimized read parameter PARA_r(y) may include the aforementioned at least one adjusted read voltage Vth (e.g., optimal read voltage Vth_Opt(y)). Furthermore, for example, during the lifetime of memory device 100, the memory controller 110 may perform the read parameter optimization procedure multiple times, particularly periodically or intermittently, to maintain the correctness of data reading. For the sake of brevity, similar details of these embodiments will not be described in detail here.

[0125] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A method for performing data access control of a memory device, the method being applied to a memory controller of the memory device, the memory device including the memory controller and a non-volatile memory, the non-volatile memory including at least one non-volatile memory element, the method comprising: A host device receives multiple host commands to perform data access on the non-volatile memory according to the multiple host commands, wherein the data access includes data reading; and A read parameter optimization procedure is performed to determine at least one optimized read parameter to maintain the correctness of the data read, wherein the read parameter optimization procedure includes: An original data indication reference, a temporary minimum read parameter, and a temporary maximum read parameter are initialized, wherein the original data indication reference is determined according to a preset setting, and the temporary minimum read parameter and the temporary maximum read parameter are respectively determined as a minimum value and a maximum value of an adjustable read parameter range. In any iteration of at least one iteration of the read parameter optimization procedure, the read parameter is calculated to be equal to an average of the temporary minimum read parameter and the temporary maximum read parameter; In any iteration, the non-volatile memory is controlled to perform a read according to the read parameter to obtain the original data of each of the multiple memory cells in a group of memory cells, so as to determine an original data indication, wherein the original data indication represents the number of memory cells in which the original data is equal to a predetermined logic value in the case that the memory controller reads the multiple memory cells of the group of memory cells according to the read parameter. as well as In any iteration, the original data indication is compared with the original data indication reference to determine whether the original data indication is greater than or less than the original data indication reference, so as to selectively adjust the temporary maximum read parameter or the temporary minimum read parameter to be equal to the read parameter; In the last iteration of the at least one iteration, since the original data indication is equal to the original data indication reference, the memory controller is used to determine a first optimized read parameter among the at least one optimized read parameters to be equal to the read parameter.

2. The method as described in claim 1, characterized in that, The at least one optimized read parameter includes one or a combination of an optimal read voltage and an optimal read voltage code.

3. The method as described in claim 1, characterized in that, The original data of each of the plurality of memory cells in the memory cell group represents a plurality of original bits, wherein an original bit of any of the plurality of memory cells is equal to the predetermined logical value or another predetermined logical value.

4. The method as described in claim 3, characterized in that, The original data indicates that it is equal to a memory cell count, and the memory cell count represents the number of memory cells in which the original data is equal to the predetermined logical value in the case where the memory controller reads the plurality of memory cells of the memory cell group according to the read parameter.

5. The method as described in claim 3, characterized in that, In the case where the memory controller reads the plurality of memory cells of the memory cell group according to the read parameters, the original data indication is equal to a one-bit count of the original bits equal to the predetermined logic value.

6. The method as described in claim 1, characterized in that, The plurality of host commands includes a read command, and an uncorrectable error correction code error occurs during the reading of the non-volatile memory according to the read command; The method also includes: In response to the occurrence of an uncorrectable error correction code error, a read retry procedure is performed to attempt to read the non-volatile memory using at least one adjusted read voltage, wherein the at least one optimized read parameter includes the at least one adjusted read voltage.

7. The method as described in claim 1, characterized in that, The memory controller is used to perform the read parameter optimization procedure multiple times during the lifetime of the memory device in order to maintain the correctness of the data read.

8. The method as described in claim 1, characterized in that, In at least one iteration, the memory controller is used to perform at least one binary search to determine the average of the temporary minimum read parameter and the temporary maximum read parameter.

9. A memory controller for a memory device, the memory device including the memory controller and a non-volatile memory, the non-volatile memory including at least one non-volatile memory element, the memory controller including: A processing circuit is used to control the memory controller according to a plurality of host commands from a host device, so as to allow the host device to access the non-volatile memory through the memory controller. as well as A transmission interface circuit for communicating with the host device; in: The memory controller receives multiple host commands from the host device through its transmission interface circuitry, for performing data access on the non-volatile memory according to the multiple host commands, wherein the data access includes data reading; and The memory controller performs a read parameter optimization procedure to determine at least one optimized read parameter to maintain the correctness of the data read, wherein the read parameter optimization procedure includes: An original data indication reference, a temporary minimum read parameter, and a temporary maximum read parameter are initialized, wherein the original data indication reference is determined according to a preset setting, and the temporary minimum read parameter and the temporary maximum read parameter are respectively determined as a minimum value and a maximum value of an adjustable read parameter range. In any iteration of at least one iteration of the read parameter optimization procedure, the read parameter is calculated to be equal to an average of the temporary minimum read parameter and the temporary maximum read parameter; In any iteration, the non-volatile memory is controlled to perform reads according to the read parameters to obtain the original data of each of a plurality of memory cells in a group of memory cells, in order to determine an original data indication, wherein the original data indication represents the number of memory cells in which the original data is equal to a predetermined logic value in a case where the memory controller reads the plurality of memory cells in the group of memory cells according to the read parameters; and In any iteration, the original data indication is compared with the original data indication reference to determine whether the original data indication is greater than or less than the original data indication reference, so as to selectively adjust the temporary maximum read parameter or the temporary minimum read parameter to be equal to the read parameter; In the last iteration of the at least one iteration, since the original data indication is equal to the original data indication reference, the memory controller is used to determine a first optimized read parameter among the at least one optimized read parameters to be equal to the read parameter.

10. A memory device comprising the memory controller of claim 9, wherein the memory device comprises: This non-volatile memory is used to store information; and The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

11. An electronic device comprising the memory device of claim 10, and further comprising: The host device is coupled to the memory device, wherein the host device includes: At least one processor is used to control the operation of the host device; as well as A power supply circuit is coupled to the at least one processor and is used to provide power to the at least one processor and the memory device; The memory device provides storage space to the host device.

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