Solar cell, preparation method thereof and photovoltaic module

Abstract

A solar cell includes: a cell substrate having a first surface and a second surface opposite to each other; the first surface is provided with first regions and second regions which are alternately distributed at intervals, and spacer regions located between the adjacent first regions and second regions; the first doping layer is at least located on the first region; the second doping layer is at least located on the second region, and the polarity of the first doping layer is opposite to that of the second doping layer; the first conductive layer is arranged on one side, deviating from the battery substrate, of the first doping layer; the second conductive layer is arranged on the side, away from the cell substrate, of the second doped layer. At least one extension contact of the first and second conductive layers connects the first and second doped layers, the second conductive layer being electrically isolated from the first conductive layer. The second doping layer and the first doping layer are locally connected through the conductive layer to form a micro short circuit, so that the temperature of the battery piece during working is reduced, and a hot spot phenomenon is prevented. The invention also provides a photovoltaic module comprising the solar cell and a preparation method of the solar cell.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and more specifically, to a solar cell and a preparation method thereof, including a photovoltaic module of the solar cell. Background Art

[0002] Solar energy has become one of the most promising energy sources due to its safety, reliability, wide distribution and low cost. Back contact (BC) solar cells include silicon wafers and P-type doped regions, N-type doped regions and electrodes arranged on the silicon wafers. Solar cells receive solar radiation to generate electrons and holes, and the electrons migrate to the N-type doped regions, and the holes migrate to the P-type doped regions. Electrodes coupled to the P-type doped regions and the N-type doped regions are respectively arranged, and the electrodes collect and conduct the holes and electrons.

[0003] The electrodes are usually interdigitated metal contact fingers. The metal contact fingers allow external circuits to be connected to the solar cell and powered by the solar cell. However, when the solar cell is reverse biased by shadows or dirt, it will usually heat up, which is easy to cause hot spots. As the power of the cell increases during operation, the temperature of the hot spot becomes higher and higher, causing the cell to dissolve easily, which is not conducive to the long-term use of the cell. Summary of the invention

[0004] In view of this, the present application provides a solar cell, which is designed to connect the first doped layer and the second doped layer through a conductive layer, so as to effectively control the risk of hot spots, reduce the leakage current of the battery cell, and thus control the heating power of the leakage point.

[0005] A solar cell, comprising: a battery substrate having a first side and a second side opposite to each other; The first surface has first areas and second areas that are alternately spaced and a spacing area between adjacent first areas and second areas; a first doped layer, at least located on the first region; A second doped layer, at least located on the second region, wherein the first doped layer and the second doped layer have opposite polarities; A first conductive layer, disposed on a side of the first doped layer away from the battery substrate; The second conductive layer is arranged on a side of the second doped layer away from the battery substrate, at least one of the first conductive layer and the second conductive layer extends to contact and connect the first doped layer and the second doped layer, and the second conductive layer is electrically isolated from the first conductive layer.

[0006] The solar cell of the present application is conducive to the input and output of current, so that the current has more paths and the local resistance is reduced; and it can balance the local heating of the cell, avoid the increase of local resistance when the cell generates hot spots, and then avoid the local dissolution and damage of the cell caused by heat accumulation, and prevent the occurrence of hot spot phenomenon. The solution of the present application does not need to redesign the pattern of the second doping layer and the first doping layer. The electrical coupling of the second doping layer and the first doping layer can be achieved only by designing the conductive layer pattern. The pattern design of the conductive layer is simpler and easier to implement than the second doping layer and the first doping layer, and will not affect the cell substrate. In this way, the cell preparation process is simplified and the cell preparation efficiency is improved.

[0007] As a possible implementation manner, the spacer has the first doping layer and the second doping layer stacked in layers; or, The spacer region has a groove region recessed relative to the surfaces of the first doping layer and the second doping layer.

[0008] As a possible implementation, the first conductive layer includes a main body portion and a docking portion, the main body portion contacts the first doped layer, the docking portion contacts the first doped layer and the second doped layer, and the main body portion is electrically isolated from the docking portion.

[0009] As a possible implementation manner, the total area of ​​the second sub-conductive layer accounts for 0.1 to 3 ten-thousandths of the area of ​​the first surface.

[0010] As a possible implementation, the solar cell further comprises a transparent conductive oxide layer, wherein the transparent conductive oxide layer is located between the cell substrate and the first conductive layer, and between the cell substrate and the second conductive layer; The transparent conductive oxide layer at least partially contacts the first doping layer and the second doping layer.

[0011] As a possible implementation, the solar cell further includes a dielectric layer, and the dielectric layer is located between the cell substrate and the first conductive layer, and between the cell substrate and the second conductive layer; The dielectric layer covers a portion of the first doping layer and the second doping layer.

[0012] As a possible implementation manner, the first conductive layer and the second conductive layer are formed integrally; and / or, The first conductive layer and the second conductive layer have the same thickness.

[0013] As a possible implementation manner, the first conductive layer and the second conductive layer both include a first sub-metal layer and a second sub-metal layer which are stacked, wherein the first sub-metal layer is located between the battery substrate and the second sub-metal layer; The standard conductive potential difference between the first sub-metal layer and the second sub-metal layer is 0.1-3.5V; and / or, The material of the first sub-metal layer includes one or more of Al, Zn, Fe, Co, Mg, Cu, Ag and alloys thereof; and / or, The material of the second sub-metal layer includes one or more of Cu, Ni, Cr, Ti, W, Mo, Ag, Sn and alloys thereof; and / or, The thickness of the second sub-metal layer is less than or equal to 10% of the thickness of the first sub-metal layer; and / or, The first sub-metal layer is composed of two or more sub-layers, and the material of each sub-layer is selected from one or more of Al, Zn, Fe, Co, Mg, Cu, Ag and alloys thereof.

[0014] As a possible implementation manner, a buffer layer is further provided between the first sub-metal layer and the battery substrate, and the buffer layer includes one or more combinations of metal oxides, metal nitrides, metal fluorides, metal silicides and metals; The metal oxides include AZO, TiO x 、Cu2O、MgO x 、TaO x , VO x CrO x 、SnO2、B:ZnO、CdO x and MoO x One or more combinations of; and / or, The metal nitride comprises one or more combinations of TiNx and TiOxNy; and / or, The metal fluoride comprises one or more combinations of MgF2, LiF, YF3 and CeF3; and / or, The metal silicide comprises one or more combinations of TiSi2, TaSi2, MoSi2, CoSi2, Ni2Si and WSi2; and / or, The metal includes one or more combinations of Ni, Ti, Cr, Cu, W, Mo and Ag.

[0015] As a possible implementation manner, the first doped layer is a doped polysilicon layer, and the second doped layer is a doped polysilicon layer or a doped microcrystalline silicon layer or a doped amorphous silicon layer; or, The first doped layer is a doped amorphous silicon layer or a doped microcrystalline silicon layer, and the second doped layer is a doped microcrystalline silicon layer or a doped amorphous silicon layer.

[0016] As a possible implementation manner, the conductivity type of the first doped layer is N-type, and the conductivity type of the second doped layer is P-type; or, The conductivity type of the first doping layer is P type, and the conductivity type of the second doping layer is N type.

[0017] In a second aspect, the present application provides a method for preparing a solar cell, comprising: Providing a battery substrate, the battery substrate having a first surface and a second surface opposite to each other, the first surface having first areas and second areas alternately distributed and a spacing area between adjacent first areas and second areas; forming a first doped layer at least on the first region, and forming a second doped layer at least on the second region, wherein the first doped layer and the second doped layer have opposite polarities; A first conductive layer is formed on a side of the first doped layer away from the battery substrate, and a second conductive layer is formed on a side of the second doped layer away from the battery substrate; at least one of the first conductive layer and the second conductive layer extends to contact and connect the first doped layer and the second doped layer; the first conductive layer and the second conductive layer are formed integrally; The first conductive layer and the second conductive layer are electrically isolated.

[0018] In a third aspect, the present application provides a photovoltaic module, comprising a glass cover plate, a film layer, a battery layer, a film layer and a transparent or opaque back plate stacked in sequence, wherein the battery layer comprises the solar cells described in the first aspect or the solar cells prepared by the preparation method described in the second aspect connected in series. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a cross-sectional schematic diagram of the solar cell according to the first embodiment of the present application.

[0020] Figure 2 for Figure 1 Schematic top view of a solar cell.

[0021] Figure 3 for Figure 1 A schematic top view of the docking portion of a solar cell.

[0022] Figure 4 This is a schematic top view of a solar cell according to the second embodiment of the present application.

[0023] Figure 5 This is a schematic top view of a solar cell according to the third embodiment of the present application.

[0024] Figure 6 This is a schematic top view of a solar cell according to the fourth embodiment of the present application.

[0025] Figure 7 FIG. 1 is a cross-sectional schematic diagram of a solar cell according to another embodiment of the present application.

[0026] Figure 8 FIG. 1 is a schematic diagram of a preparation process of a solar cell according to an embodiment of the present application.

[0027] Fig. 9 FIG. 1 is a schematic diagram of a preparation process of a solar cell according to another embodiment of the present application.

[0028] Description of main component symbols: Battery substrate 10, second surface 11, first surface 12, first doping layer 21, second doping layer 22, The first conductive layer 31, the main body parts 31a, 32a, the second conductive layer 32, the docking parts 40, 40a, 40b, Dielectric layer 50, through groove 51, TCO layer 60, initial electrode layer 80, first sub-metal layer 82, The second sub-metal layer 84 , the alloy intermediate 81 . DETAILED DESCRIPTION

[0029] At present, in order to effectively control the hot spot risk of solar cells, the existing technology usually adopts the design of bypass diodes, or the design of connecting the P-type and N-type doping layers to reduce the leakage current of the cell, thereby controlling the heating power of the leakage point. However, whether it is a bypass diode or connecting the P-type and N-type doping layers, the pattern of the doping area needs to be redesigned, and the preparation of the back contact battery doping area is usually cumbersome, including multiple steps of wet method and photolithography / laser to form two doping areas. If it is also necessary to design a bypass diode locally or connect the P-type and N-type doping layers, the preparation process will be more complicated, and more and more complicated steps are also likely to affect the battery substrate, thereby affecting the stability of the battery.

[0030] The present application provides a solar cell, which designs a conductive layer so that the second doped layer and the first doped layer are locally connected to form a micro short circuit, so that the current has more paths, which is beneficial to the input and output of the current, reduces the local resistance, balances the local heating of the battery cell, and prevents the occurrence of hot spot phenomenon; and the solution of the present application does not require redesign of the patterns of the second doped layer and the first doped layer.

[0031] Please refer to Figure 1 and Figure 2, the solar cell of the first embodiment of the present application includes a cell substrate 10, and the cell substrate 10 includes a first surface 12 and a second surface 11 opposite to each other. The solar cell is a back contact cell, and the first surface 12 is provided with first and second regions that are alternately spaced, and a spacing region between adjacent first and second regions. The first doping layer 21 is at least located on the first region. The second doping layer 22 is at least located on the second region. The first doping layer 21 and the second doping layer 22 have opposite polarities. The first doping layer 21 and the second doping layer 22 are P-type doping regions and N-type doping regions, respectively. In order to make the figure clear, Figure 1 Only one first region and one second region, one first doping layer 21 and one second doping layer 22 are shown. The battery substrate 10 can be an N-type substrate or a P-type substrate. The first doping layer 21 is a P-type doping layer, which is a hole generation and collection region, and the second doping layer 22 is an N-type doping layer, which is an electron generation and collection region. Alternatively, the first doping layer 21 is an N-type doping layer, and the second doping layer 22 is a P-type doping layer.

[0032] In the embodiment of the present application, the solar cell is a BC cell, and the spacing region has a groove region that is sunken relative to the surfaces of the first doping layer 21 and the second doping layer 22 .

[0033] In other embodiments, when the solar cell is another BC cell, the spacer region has a first doping layer 21 and a second doping layer 22 stacked in layers. That is, the first doping layer 21 and the second doping layer 22 also extend to cover the spacer region, wherein the first doping layer 21 of the spacer region may contact the first doping layer 21 on the first region, and the second doping layer 22 of the spacer region may contact the second doping layer 22 on the second region.

[0034] like Figure 1 and Figure 2 As shown, the solar cell further includes a first conductive layer 31 and a second conductive layer 32. The first conductive layer 31 is disposed on a side of the first doped layer 21 away from the battery substrate 10. The second conductive layer 32 is disposed on a side of the second doped layer 22 away from the battery substrate 10. The second conductive layer 32 is electrically isolated from the first conductive layer 31. In the embodiment of the present application, the second conductive layer 32 also extends onto the first doped layer 21 and directly or indirectly contacts the first doped layer 21.

[0035] When the first doping layer 21 is a P-type doping layer and the second doping layer 22 is an N-type doping layer, the first conductive layer 31 is used to collect and transport holes generated by the first doping layer 21, and the second conductive layer 32 is used to collect and transport electrons generated by the second doping layer 22. Alternatively, when the first doping layer 21 is an N-type doping layer and the second doping layer 22 is a P-type doping layer, the first conductive layer 31 is used to collect and transport electrons generated by the first doping layer 21; the second conductive layer 32 is used to collect and transport holes generated by the second doping layer 22.

[0036] In some embodiments, the first doped layer 21 is a doped polysilicon layer, and the second doped layer 22 is a doped polysilicon layer, a doped microcrystalline silicon layer, or a doped amorphous silicon layer.

[0037] In some other embodiments, the first doped layer 21 is a doped amorphous silicon layer or a doped microcrystalline silicon layer, and the second doped layer 22 is a doped microcrystalline silicon layer or a doped amorphous silicon layer.

[0038] In the embodiment of the present application, the second conductive layer 32 can be divided into two parts according to different connection positions, that is, the second conductive layer 32 includes a main body 32a and a docking portion 40. The main body 32a is in contact with and connected to the second doping layer 22, and covers most of the second doping layer 22. The docking portion 40 is in contact with and connected to both the first doping layer 21 and the second doping layer 22, and covers a small part of the first doping layer 21 and a small part of the second doping layer 22. In this way, the docking portion 40 is connected between an adjacent pair of first doping layers 21 and second doping layers 22, and electrically couples the first doping layer 21 and the second doping layer 22. The main body 32a covers a larger area of ​​the second doping layer 22, and the docking portion 40 covers a smaller area of ​​the first doping layer 21 and the second doping layer 22, which can ensure the power transmission area of ​​the conductive layer and reduce the impact on the power transmission efficiency.

[0039] The number of the butting portions 40 may be one or more, and each butting portion 40 spans the space between a pair of adjacent first doping layers 21 and second doping layers 22 and electrically couples the pair of first doping layers 21 and second doping layers 22 . In the present application embodiment, Figure 1 and Figure 2 As shown, the docking portion 40 is formed by an integral extension of the main body portion 32a of the second conductive layer 32. The docking portion 40 extends from the second doping layer 22 across the spacing region and then extends to the first doping layer 21, is electrically coupled to the first doping layer 21, and has no contact with the first conductive layer 31 (is electrically isolated).

[0040] Please refer to Figure 4 In the solar cell of the second embodiment of the present application, the first conductive layer 31 can be divided into two parts according to different connection positions, that is, the first conductive layer 31 includes a main body 31a and a docking portion 40. The main body 31a is in contact with and connected to the first doped layer 21, and covers most of the first doped layer 21. The docking portion 40 is in contact with and connected to both the first doped layer 21 and the second doped layer 22, and covers a small part of the first doped layer 21 and a small part of the second doped layer 22. The docking portion 40 is formed by an integral extension of the main body 31a of the first conductive layer 31, and the docking portion 40 extends from the first doped layer 21 across the spacing area, and then extends to the second doped layer 22, is electrically coupled with the second doped layer 22, and is not in contact with the second conductive layer 32 (electrically isolated).

[0041] Please refer to Figure 5 In the solar cell of the third embodiment of the present application, the docking portion 40 electrically coupling the first doped layer 21 and the second doped layer 22 includes two types. One docking portion 40a is formed by an integral extension of the main body portion 31a of the first conductive layer 31, the docking portion 40a extends from the first doped layer 21 across the spacing region, and then extends to the second doped layer 22, is electrically coupled with the second doped layer 22, and is not in contact with the second conductive layer 32 (electrically isolated). The other docking portion 40b is formed by an integral extension of the main body portion 32a of the second conductive layer 32, the docking portion 40b extends from the second doped layer 22 across the spacing region, and then extends to the first doped layer 21, is electrically coupled with the first doped layer 21, and is not in contact with the first conductive layer 31 (electrically isolated).

[0042] Please refer to Figure 6 In other embodiments, the butt joint 40 is independent of the main body 31a of the first conductive layer 31 and the main body 32a of the second conductive layer 32. In this case, the butt joint 40 extends from the first doped layer 21 across the spacer and then extends to the second doped layer 22. The butt joint 40 is not in contact with the main body 32a of the second conductive layer 32 and the main body 31a of the first conductive layer 31 (electrically isolated).

[0043] The main body 32a of the second conductive layer 32 or the main body 31a of the first conductive layer 31 may include a collector, or include a collector and a bus electrode. When the docking portion 40 is independent of the main body 32a of the second conductive layer 32 and the main body 31a of the first conductive layer 31, the arrangement of the docking portion 40 is divided into the following cases according to the situation of the conductive layer. When the conductive layer only includes a collector, the docking portion 40 is arranged in the collector region corresponding to the second doping layer 22, the collector region corresponding to the first doping layer 21, and the spacing area between the two. When the conductive layer includes a bus electrode and a collector, the docking portion 40 is arranged in the collector region corresponding to each of the two types of doping layers and the spacing area between the two, or in the bus electrode region corresponding to one type of doping region, the collector region corresponding to the other type of doping region, and the spacing area between the two, or in the bus electrode region corresponding to one type of doping region, the bus electrode region corresponding to the other type of doping region, and the spacing area between the two. Figure 6 It is exemplarily shown that when the main body 32a of the second conductive layer 32 or the main body 31a of the first conductive layer 31 respectively includes a bus electrode and a collector, the docking portion 40 is disposed in the collector regions corresponding to the first doping layer 21 and the second doping layer 22 and in the spacing region therebetween.

[0044] The solar cell provided in the present application is provided with a docking portion 40, which extends from a doping region of one conductive type across the spacing region to a doping region of another conductive type and does not contact the conductive layer of another conductive type, thereby achieving docking of the second doping layer 22 and the first doping layer 21. That is, by designing a tiny area of ​​the metal electrode (the docking portion 40), the first doping layer 21 and the second doping layer 22 are locally connected to form a micro short circuit, which is beneficial to the input and output of current, so that the current has more paths and the local resistance is reduced; and it can balance the local heating of the cell, avoid the increase of local resistance when the cell generates a hot spot, and then avoid the local dissolution and damage of the cell caused by heat accumulation, and prevent the occurrence of hot spot phenomenon. In addition, the solution of the present application does not need to set an anti-hot spot structure on the doping layer, and there is no need to redesign the patterns of the second doping layer 22 and the first doping layer 21. The electrical coupling of the second doping layer 22 and the first doping layer 21 can be achieved only by designing a conductive electrode layer pattern. The pattern design of the electrode layer is simpler and easier to implement than that of the second doping layer 22 and the first doping layer 21, and will not affect the battery substrate 10. In this way, the battery preparation process is simplified, the battery preparation efficiency is improved, and the battery preparation cost is reduced.

[0045] In some embodiments, the total area of ​​all the docking parts 40 on the first surface 12 accounts for 0.1 to 3 ten-thousandths of the area of ​​the first surface 12. By adjusting the area occupied by the docking part 40 on the first surface 12 of the solar cell, the docking part 40 can be controlled to reduce the reverse breakdown voltage when the battery is blocked, and at the same time, it will not cause leakage of the battery when the battery is in normal use. In addition, since the area occupied by the docking part 40 on the battery cell is very small, the impact on the power generation efficiency of the battery is relatively low. In this way, the micro-short-circuit structure formed by the docking part 40 has a smaller size and lighter weight, and is a structure built into the battery cell. Therefore, compared with the bypass diode installed additionally, it can improve the process preparation efficiency and reduce the process preparation cost. At the same time, the micro-short-circuit structure is smaller in size and can cover a small area that the bypass diode cannot cover, providing more precise protection. Furthermore, the micro-short-circuit structure built into the battery cell can respond more quickly when a hot spot is generated in the battery cell, and can more effectively protect the battery cell and improve the safety of the product.

[0046] like Figure 2 As shown, the length of the spacing region along the first direction (the direction in which the second doping layer 22 and the first doping layer 21 are alternately arranged) is D1, and the distance between the two collectors on both sides adjacent to the spacing region is D2. Then, the length L1 of the docking portion 40 along the first direction is greater than D1 and less than D2. Figure 3As shown, the length of a single docking portion 40 along the first direction is L1, and the length along the second direction (perpendicular to the first direction) is L2. Thus, for a specific solar cell, its D1, D2 and the area of ​​the first surface 12 of the entire cell are known, and based on these values, the range of the length L1 of the single docking portion 40 along the first direction can be obtained, and the total area of ​​the docking portion 40 and the range of the length L2 of the single docking portion 40 along the second direction can be calculated.

[0047] For example, the length D1 of the spacer along the first direction is 0.13 mm, the distance D2 between two collectors adjacent to the spacer is 0.3 mm, and the area S2 of the first surface 12 of the battery cell (192 mm*182 mm) is 34944 mm 2 , then the total area S1 of the docking portion 40 is 0.34944 mm 2 ~10.4832mm 2 .

[0048] When the total area of ​​all the butt joints 40 is the minimum value of 0.34944 mm 2 When the length L2 of a single docking portion 40 along the second direction is less than 2.688 / N mm and greater than 1.1648 / N mm, where N is the number of docking portions 40 and N is an integer greater than or equal to 1; thus, based on the minimum total area of ​​the docking portions 40, the lower limit of the length L2 of the docking portions 40 along the second direction can be obtained to be 1.1648 / N mm. Similarly, when the total area of ​​all docking portions 40 is the maximum value of 10.4832 mm 2 , it can also be calculated that the length L2 of a single docking portion 40 along the second direction is less than 80.64 / N mm and greater than 34.944 / N mm. Based on the maximum value of the total area of ​​the docking portion 40, it can be obtained that the upper limit of the length L2 of the docking portion 40 along the second direction is 80.64 / N mm. In summary, the length L2 of the docking portion 40 along the second direction is greater than 1.1648 / N mm and less than 80.64 / N mm. The number N of docking portions 40 can be designed according to actual conditions to adjust the size of a single docking portion 40. In addition, the distribution of multiple docking portions 40 on the battery cell can also be designed according to actual conditions. For example, when the number N of docking portions 40 is an even number, the docking portions 40 can be evenly and symmetrically distributed on the battery cell.

[0049] In some embodiments, the docking portion 40 is integrally formed with the main body of the first conductive layer and / or the second conductive layer, and the thickness of the docking portion 40 is the same as the thickness of the main body of the first conductive layer and / or the second conductive layer. When the thickness of the docking portion 40 is the same as the thickness of the main body of the first conductive layer and / or the second conductive layer, there is no need to adjust the height of the conductive glue and the height of the welding strip specifically for the docking portion 40 during the subsequent welding process, thereby avoiding affecting the welding efficiency.

[0050] In some embodiments, when the number of docking parts 40 is greater than or equal to 2, the docking parts 40 can be evenly and symmetrically distributed on the battery cell, and one or more docking parts 40 can be set in the same spacing area. When multiple docking parts 40 are set in the same spacing area, the resistivity of each docking part 40 in the spacing area can be made to meet the requirements by adjusting the ratio between the width of each docking part 40 along the long side direction of the spacing area and the length of the long side direction of the spacing area.

[0051] The docking portion 40 and the main portion 31a of the first conductive layer 31 and / or the main portion 32a of the second conductive layer 32 can be prepared in the same process. For example, the docking portion 40 and the main portion 31a of the first conductive layer 31 and / or the main portion 32a of the second conductive layer 32 are all deposited in a PVD process. In this way, the thickness of the docking portion 40 can be controlled to be the same as the thickness of the conductive layer, thereby avoiding the influence of the different thicknesses of the docking portion 40 and the conductive layer on the subsequent welding process. In some embodiments, the first conductive layer 31 and the second conductive layer 32 are formed integrally. The first conductive layer 31 and the second conductive layer 32 have the same thickness.

[0052] The docking portion 40 and the conductive layer (the main body 32a of the second conductive layer 32 and the main body 31a of the first conductive layer 31) can be integrally formed by a coating process. The coating process can be physical vapor deposition (such as evaporation, magnetron sputtering), chemical vapor deposition, electroplating, screen printing, and the like.

[0053] The second conductive layer 32 and the first conductive layer 31 may include a first sub-metal layer (not shown) and a second sub-metal layer (not shown) stacked sequentially on the surface of the battery substrate 10, wherein the first sub-metal layer is located between the battery substrate 10 and the second sub-metal layer. The standard electrode potential difference between the first sub-metal layer and the second sub-metal layer is 0.1-3.5V.

[0054] It can be understood that the first sub-metal layer is not in direct contact with the battery substrate 10. For example, for a battery with a Topcon structure, a passivation layer or a passivation anti-reflection layer (for example, a silicon nitride layer and an aluminum oxide layer), a doped polysilicon layer and a tunneling oxide layer are further provided between the first sub-metal layer and the battery substrate 10, and the tunneling oxide layer is in contact with the battery substrate 10; or, a doped polysilicon layer and a tunneling oxide layer are further provided between the first sub-metal layer and the battery substrate 10, and the tunneling oxide layer is in contact with the battery substrate 10; or, a TCO layer 60, a doped polysilicon layer and a tunneling oxide layer are further provided between the first sub-metal layer and the battery substrate 10, and the tunneling oxide layer is in contact with the battery substrate 10. For example, for a battery with an HJT structure, a TCO layer 60, a doped amorphous silicon layer and an intrinsic amorphous silicon layer are further provided between the first sub-metal layer and the battery substrate 10, and the intrinsic amorphous silicon layer is in contact with the battery substrate 10.

[0055] In some embodiments, the material of the first sub-metal layer includes one or more of Al, Zn, Fe, Co, Mg, Cu, Ag and alloys thereof. The material of the second sub-metal layer includes one or more of Cu, Ni, Cr, Ti, W, Mo, Ag, Sn and alloys thereof.

[0056] In some embodiments, the thickness of the second sub-metal layer is less than or equal to 10% of the thickness of the first sub-metal layer. The second sub-metal layer is disposed on the first sub-metal layer to protect the first sub-metal layer, and the second sub-metal layer needs to be connected to other layers of the battery (such as the encapsulation layer) later, which can improve the bonding strength between the metal layer and other layers (such as the encapsulation layer). Therefore, the thickness of the second sub-metal layer does not need to be set too thick, and can be less than or equal to 10% of the thickness of the first sub-metal layer.

[0057] In some embodiments, the first sub-metal layer is composed of two or more sub-layers, and the material of each sub-layer is selected from one or more of Al, Zn, Fe, Co, Mg, Cu, Ag and alloys thereof.

[0058] In some embodiments, the second conductive layer 32 and the first conductive layer 31 further include a buffer layer disposed between the first sub-metal layer and the battery substrate 10. The buffer layer includes one or more combinations of metal oxides, metal nitrides, metal fluorides, metal silicides, and metals. The buffer layer serves to enhance the bonding strength between the first metal layer 33 / the second metal layer 53 and the battery substrate 10.

[0059] In some embodiments, the metal oxide includes AZO, TiO x 、Cu2O、MgO x 、TaO x , VO x CrO x 、SnO2、B:ZnO、CdO x and MoO x In some embodiments, the metal nitride includes TiN x and TiO x N y In some embodiments, the metal fluoride comprises one or more combinations of MgF2, LiF, YF3 and CeF3. In some embodiments, the metal silicide comprises one or more combinations of TiSi2, TaSi2, MoSi2, CoSi2, Ni2Si and WSi2. In some embodiments, the metal comprises one or more combinations of Ni, Ti, Cr, Cu, W, Mo and Ag.

[0060] The thickness of the buffer layer is less than or equal to 10% of the thickness of the first sub-metal layer 33 , and the projection width of the buffer layer on the battery substrate 10 is less than or equal to the width of the corresponding doping region.

[0061] In one embodiment, the thickness of the buffer layer is 5 nm to 300 nm, the thickness of the first sub-metal layer is 0.5 μm to 20 μm, and the thickness of the second sub-metal layer is 5 nm to 300 nm.

[0062] In some embodiments, the resistivity of the butt joint 40 is 2.6×10 -8 Ω·m~8×10 -6 Ω·m. In one example, when the conductive layer includes only the first sub-metal layer and the second sub-metal layer, the resistivity of the butting portion 40 is in the order of 10 -8 Ω·m. When the conductive layer includes the first sub-metal layer, the second sub-metal layer and the buffer layer, the resistivity of the butt joint 40 is in the order of 10 -6 Ω·m. Thus, it can be seen that the resistivity of the docking portion 40 can be regulated by controlling the composition of the conductive layer. In addition, for a conductive layer of a certain composition, by controlling the thickness of different layers thereof, the resistivity of the docking portion 40 can also be regulated. In addition to regulating the resistivity of the docking portion 40 by controlling the composition and thickness of the conductive layer, the resistivity of the docking portion 40 can also be regulated by controlling the size of the docking portion 40. For example, when the shape of the docking portion 40 is a rectangle, the length or width of the docking portion 40 can be controlled to regulate the resistivity of the docking portion 40.

[0063] In some embodiments, the conductive layer includes a bus electrode and a collector. The collector is used to collect carriers generated by the corresponding doping region, and the bus electrode is used to collect carriers from the collector. When the conductive layer includes a collector and a bus electrode, the docking portion 40 may be a portion extending from the collector and the docking region is a doping region where another type of collector is located or a doping region where another type of bus electrode is located. For example, the docking portion 40 is a portion extending from an N-type collector and the docking region is the first doping layer 21 where a P-type bus electrode is located. Alternatively, the docking portion 40 is a portion extending from a bus electrode and the docking region is a doping region where another type of collector is located or a doping region where another type of bus electrode is located. For example, the docking portion 40 is a portion extending from an N-type bus electrode and the docking region is the first doping layer 21 where a P-type collector is located, for example, the docking portion 40 is a portion extending from an N-type bus electrode and the docking region is the doping region where a P-type bus electrode is located.

[0064] As a possible implementation scheme, when the solar cell has a tunnel oxide passivated contact (Tunnel Oxide Passivated Contact, Topcon) structure, the doping region (both the first doping layer 21 and the second doping layer 22) includes a tunnel oxide layer and a doped polysilicon layer, wherein the doped polysilicon layer of the first doping layer 21 is doped with a P-type element, wherein the P-type element may specifically be a trivalent element such as boron, indium or gallium. The doped polysilicon layer of the second doping layer 22 is doped with an N-type element, wherein the N-type element may specifically be a pentavalent element such as phosphorus, arsenic or antimony. The conductive layer (the first conductive layer 31 and the second conductive layer 32) is arranged on the doped polysilicon layer; or, a transparent conductive oxide (TCO) layer is further arranged between the conductive layer and the doped polysilicon layer, and the conductive layer is arranged on the side of the TCO layer 60 away from the battery substrate 10; or, an insulating passivation layer or a passivation anti-reflection layer is further arranged between the conductive layer and the doped polysilicon layer, and the conductive layer is arranged on the side of the passivation layer or the passivation anti-reflection layer away from the battery substrate 10.

[0065] As a possible implementation scheme, when the solar cell has a heterojunction structure (HJT), the doping region (the first doping layer 21 and the second doping layer 22) includes an intrinsic amorphous silicon layer and a doped amorphous silicon layer, and a TCO layer 60 is further provided between the conductive layer and the doped polysilicon layer, that is, the conductive layer (the first conductive layer 31 and the second conductive layer 32) is provided on the side of the TCO layer 60 away from the cell substrate 10. The TCO layer 60 is in contact with at least part of the first doping layer 21 and the second doping layer 22.

[0066] In some embodiments, such as Figure 1 As shown, the solar cell further includes a dielectric layer 50. The dielectric layer 50 is located on the surface of the first doped layer 21 away from the silicon substrate, the surface of the second doped layer 22 away from the silicon substrate and the spacer, and the dielectric layer 50 is located between the first conductive layer 31 and the first doped layer 21, and between the second conductive layer 32 and the second doped layer 22. The dielectric layer 50 is an insulating passivation layer or a passivation anti-reflection layer.

[0067] like Figure 1As shown, when a dielectric layer 50 is provided between the conductive layer and the doped layer, the dielectric layer 50 needs to be grooved so that the conductive layer can contact and couple with the doped layer. The dielectric layer 50 is provided with a plurality of through grooves 51 that run through its thickness direction, and through grooves 51 are provided corresponding to the first conductive layer 31, the second conductive layer 32 and the docking portion 40, respectively. In this way, the first conductive layer 31 extends into the corresponding through grooves 51 to connect to the first doped layer 21, the second conductive layer 32 extends into the corresponding through grooves 51 to connect to the second doped layer 22, and the docking portion 40 extends into the corresponding through grooves 51 to connect to the second doped layer 22 and / or the first doped layer 21. In the present application, there is no restriction on the number, shape, etc. of the through grooves 51.

[0068] In other embodiments, Figure 7 As shown, the solar cell further includes a TCO layer 60 . The TCO layer 60 is disposed between the first conductive layer 31 and the first doped layer 21 , and between the second conductive layer 32 and the second doped layer 22 .

[0069] like Figure 7 As shown, the docking portion 40 is formed by integrally extending the main body portion 32a of the second conductive layer 32, and the docking portion 40 needs to extend from the second doping layer 22 to the first doping layer 21. The TCO layer 60 located below the docking portion 40 also needs to extend from the second doping layer 22 to the first doping layer 21, and does not contact the TCO layer 60 below the first conductive layer 31. In addition, for this battery structure, the TCO layer 60 and the conductive layer are prepared together in the same process step of the same process, for example, the TCO layer 60 and the conductive layer are prepared together in the same process step of a physical vapor deposition process (such as evaporation or sputtering, etc.).

[0070] The second aspect of the present application provides a method for preparing the above-mentioned solar cell, and when the conductive layer is disposed on the dielectric layer 50, the method comprises the following steps: S1: providing a battery substrate 10, the battery substrate 10 comprising a second surface 11 and a first surface 12 opposite to each other, the first surface having first areas and second areas alternately distributed, and a spacing area between the first area and the second area adjacent thereto; S2: forming a first doping layer 21 at least on the first region, and forming a second doping layer 22 at least on the second region, wherein the first doping layer 21 and the second doping layer 22 have opposite polarities; S3: forming a first conductive layer 31 on a surface of the first doping layer 21 away from the battery substrate 10, and forming a second conductive layer 32 on a surface of the second doping layer 22 away from the battery substrate 10, wherein at least one of the first conductive layer 31 and the second conductive layer 32 extends to contact and connect the first doping layer 21 and the second doping layer 22; and S4: electrically isolating the first conductive layer 31 and the second conductive layer 32.

[0071] In S3 , the first conductive layer 31 and the second conductive layer 32 may be formed integrally.

[0072] refer to Figure 8 In one embodiment, when the conductive layer is disposed on the dielectric layer 50, the method for preparing the solar cell specifically includes: Step 1: Provide a battery substrate 10, and form alternating first doping layers 21 and second doping layers 22 on the first surface 12 of the battery substrate 10, the spacing area between two adjacent first doping layers 21 and second doping layers 22 is a spacing area, and a dielectric layer 50 is covered on the first doping layer 21, the second doping layer 22 and the spacing area.

[0073] Step 2: A through groove 51 is opened in the dielectric layer 50. The dielectric layer 50 is respectively provided with a through groove 51 corresponding to the first conductive layer 31, the second conductive layer 32 and the docking portion 40 to expose a portion of the first doped layer 21 and the second doped layer 22. The exposed portion of the first doped layer 21 and the second doped layer 22 relative to the dielectric layer 50 is the area that will be subsequently connected to the first conductive layer 31, the second conductive layer 32 and the docking portion 40.

[0074] Step 3: An initial electrode layer 80 is formed on the first surface 12 of the battery substrate 10, which completely covers the first surface 12, wherein the initial electrode layer 80 includes a first sub-metal layer 82 (non-corrosion-resistant metal layer) and a second sub-metal layer 84 (corrosion-resistant metal layer) stacked sequentially from the inside to the outside, or the initial electrode layer 80 includes a buffer layer, a first sub-metal layer (non-corrosion-resistant metal layer) and a second sub-metal layer (corrosion-resistant metal layer) stacked sequentially from the inside to the outside.

[0075] Step 4: According to the position and shape of the first conductive layer 31 and the second conductive layer 32 on the battery substrate 10, a laser is used to scan a part of the initial electrode layer 80, so that the multi-metal alloy in the area other than the first conductive layer 31 and the second conductive layer 32 in the initial electrode layer 80 is alloyed to obtain an alloy intermediate 81. In this step, the laser power is 10-80W, the laser wavelength is 300-1200nm, the spot diameter or width is maintained at 10-150um, and the scanning speed is 5-50m / s; optionally, an inert gas, such as argon, can be blown during the laser beam scanning process to protect the molten metal and the laser lens barrel. It should be noted that in this step, the laser will not hit the battery substrate 10.

[0076] Step 5: Use a corrosive solution to clean the battery substrate 10 to remove the alloy intermediate 81, and the retained initial electrode layer 80 is correspondingly formed into a first conductive layer 31 and a second conductive layer 32 (including a docking portion 40). When the electrode layer also includes a buffer layer, the corrosive solution can also remove the buffer layer. Among them, the corrosive solution can include one of NaOH, KOH, HCl, H2SO4, HNO3, H3PO4, tetramethylammonium hydroxide, and ammonia water. The mass concentration of the corrosive solution is 0.1-10%, the cleaning temperature is 10-50°C, and the cleaning time is 30s-600s. The intermediate substrate can be cleaned by immersion and / or ultrasound. Specifically, the battery substrate 10 can be immersed in the corrosive solution for 200-600s, or placed in an ultrasonic device containing the corrosive solution for ultrasonic assisted cleaning for 30-200s.

[0077] Step 6: Clean the battery substrate 10 with deionized water 3 to 5 times to remove the residual corrosive liquid, and each cleaning time is 30 seconds to 2 minutes; after cleaning, put the intermediate substrate into an oven at 50°C to 100°C for 10 minutes to 2 minutes to obtain the final first conductive layer 31 and the second conductive layer 32.

[0078] In one embodiment, reference Fig. 9 When the conductive layer is disposed on the TCO layer 60, the method for preparing the solar cell specifically includes: Step 1: Provide a battery substrate 10, and form alternately arranged first doping layers 21 and second doping layers 22 on the first surface 12 of the battery substrate 10, wherein the spacing region between two adjacent first doping layers 21 and second doping layers 22 is a spacing region.

[0079] Step 2: On the first surface 12 of the battery substrate 10, a TCO layer 60 and an initial electrode layer 80 are sequentially prepared to completely cover the first surface 12, wherein the initial electrode layer 80 includes a first metal layer 82 (non-corrosion-resistant metal layer) and a second metal layer 84 (corrosion-resistant metal layer) stacked from the inside to the outside, or the initial electrode layer 80 includes a buffer layer, a first metal layer (non-corrosion-resistant metal layer) and a second metal layer (corrosion-resistant metal layer).

[0080] Step 4: According to the position and shape of the first conductive layer 31 and the second conductive layer 32 on the battery substrate 10, the initial electrode layer 80 is scanned with a laser to alloy the multi-metal in the region other than the first conductive layer 31 and the second conductive layer 32 in the initial electrode layer 80 to obtain an alloy intermediate 81. In this step, the laser power is 10-80W, the laser wavelength is 300-1200nm, the spot diameter or width is maintained at 10-150um, and the scanning speed is 5-50m / s; optionally, an inert gas, such as argon, can be blown during the laser beam scanning process to protect the molten metal and the laser lens barrel. It should be noted that in this step, the laser will not hit the battery substrate 10.

[0081] Step 5: Use a corrosive liquid to clean the battery substrate 10 to remove the alloy intermediate 81 and the TCO layer 60 below the alloy intermediate 81, and the remaining conductive layer is correspondingly formed into a first conductive layer 31 and a second conductive layer 32 (including the docking portion 40). When the conductive layer also includes a buffer layer, the corrosive liquid can also remove the buffer layer. Among them, the corrosive liquid may include one of NaOH, KOH, HCl, H2SO4, HNO3, H3PO4, tetramethylammonium hydroxide, and ammonia water. The mass concentration of the corrosive liquid is 0.1-10%, the cleaning temperature is 10-50°C, and the cleaning time is 30s-600s. The intermediate substrate can be cleaned by immersion and / or ultrasound. Specifically, the battery substrate 10 can be immersed in the corrosive liquid for 200-600s, or placed in an ultrasonic device containing the corrosive liquid for ultrasonic assisted cleaning for 30-200s.

[0082] Step 6: Clean the battery substrate 10 with deionized water 3 to 5 times to remove the residual corrosive liquid, and each cleaning time is 30 seconds to 2 minutes; after cleaning, put the intermediate substrate into an oven at 50°C to 100°C for 10 minutes to 2 minutes to obtain the final first conductive layer 31 and the second conductive layer 32 (including the docking portion 40).

[0083] The present application also provides a photovoltaic module comprising the above solar cell.

[0084] In some embodiments, the photovoltaic module includes a glass cover plate, a film layer, a battery layer, a film layer and a transparent or opaque back plate stacked in sequence, wherein when the back plate is transparent, a glass cover plate can be selected for the back plate. The battery layer includes a plurality of the above-mentioned solar cells connected in series. The number of solar cells connected in series can be, for example, 4 to 20. These solar cells form a plurality of battery modules, each of which has the same number of solar cells. The solar cells in the battery modules are connected in series, and the battery modules can be connected in series or in parallel. The spacing between two adjacent battery modules is 0.5 to 10 mm, and the spacing between two adjacent battery cells in each battery module is 0.5 to 10 mm.

[0085] The solar cell of the present application realizes electrical coupling between the second doping layer 22 and the first doping layer 21 by designing the docking portion 40 (part of the conductive layer) to extend from a doping layer of one conductive type across the interval area to a doping layer of another conductive type and not contacting the conductive layer of the other conductive type. The docking portion 40 is equivalent to forming a diode with a relatively low reverse breakdown voltage. The docking portion 40 locally connects the second doping layer 22 and the first doping layer 21 to form a micro short circuit, which is beneficial to the input and output of current, so that the current has more paths and reduces the local resistance; and can balance the local heating of the battery cell, avoid the increase of local resistance when the battery cell generates hot spots, and then avoid the local dissolution and damage of the battery cell caused by heat accumulation, and prevent the occurrence of hot spot phenomenon; the solution of the present application does not need to redesign the patterns of the second doping layer 22 and the first doping layer 21, and the docking of the second doping layer 22 and the first doping layer 21 can be achieved only by designing the conductive layer pattern, and the pattern design of the conductive layer is simpler and easier to implement than that of the second doping layer 22 and the first doping layer 21, and will not affect the battery substrate 10, thus simplifying the battery preparation process and improving the battery preparation efficiency. In addition, the docking portion 40 occupies a very small area on the battery cell, so the impact on the power generation efficiency of the battery is very low.

[0086] The above implementation modes are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the above preferred implementation modes, a person skilled in the art should understand that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A solar cell, characterized in that: include: a battery substrate having a first side and a second side opposite to each other; The first surface has first areas and second areas that are alternately spaced and a spacing area between adjacent first areas and second areas; a first doped layer, at least located on the first region; A second doped layer, at least located on the second region, wherein the first doped layer and the second doped layer have opposite polarities; A first conductive layer, disposed on a side of the first doped layer away from the battery substrate; The second conductive layer is arranged on a side of the second doped layer away from the battery substrate, at least one of the first conductive layer and the second conductive layer extends to contact and connect the first doped layer and the second doped layer, and the second conductive layer is electrically isolated from the first conductive layer.

2. The solar cell according to claim 1, characterized in that The first doping layer and the second doping layer are stacked on the spacer; or, The spacer region has a groove region recessed relative to the surfaces of the first doping layer and the second doping layer.

3. The solar cell according to claim 1, characterized in that The first conductive layer includes a main body portion and a butt joint portion, the main body portion contacts the first doped layer, the butt joint portion contacts the first doped layer and the second doped layer, and the main body portion is electrically isolated from the butt joint portion.

4. The solar cell according to claim 3, characterized in that: The total area of ​​the docking portion accounts for 0.1 to 3 ten-thousandths of the area of ​​the first surface.

5. The solar cell according to any one of claims 1 to 3, characterized in that The solar cell further comprises a transparent conductive oxide layer, wherein the transparent conductive oxide layer is located between the cell substrate and the first conductive layer, and between the cell substrate and the second conductive layer; The transparent conductive oxide layer at least partially contacts the first doping layer and the second doping layer.

6. The solar cell according to any one of claims 1 to 3, characterized in that: The solar cell further comprises a dielectric layer, wherein the dielectric layer is located between the cell substrate and the first conductive layer, and between the cell substrate and the second conductive layer; The dielectric layer covers a portion of the first doping layer and the second doping layer.

7. The solar cell according to any one of claims 1 to 3, characterized in that The first conductive layer and the second conductive layer are formed integrally; and / or, The first conductive layer and the second conductive layer have the same thickness.

8. The solar cell according to any one of claims 1 to 3, characterized in that: The first conductive layer and the second conductive layer each include a first sub-metal layer and a second sub-metal layer stacked in layers, wherein the first sub-metal layer is located between the battery substrate and the second sub-metal layer; The standard conductive potential difference between the first sub-metal layer and the second sub-metal layer is 0.1-3.5V; and / or, The material of the first sub-metal layer includes one or more of Al, Zn, Fe, Co, Mg, Cu, Ag and alloys thereof; and / or, The material of the second sub-metal layer includes one or more of Cu, Ni, Cr, Ti, W, Mo, Ag, Sn and alloys thereof; and / or, The thickness of the second sub-metal layer is less than or equal to 10% of the thickness of the first sub-metal layer; and / or, The first sub-metal layer is composed of two or more sub-layers, and the material of each sub-layer is selected from one or more of Al, Zn, Fe, Co, Mg, Cu, Ag and alloys thereof.

9. The solar cell according to claim 8, characterized in that A buffer layer is further provided between the first sub-metal layer and the battery substrate, wherein the buffer layer comprises one or more combinations of metal oxides, metal nitrides, metal fluorides, metal silicides and metals; The metal oxides include AZO, TiO x 、Cu2O、MgO x 、TaO x , VO x CrO x 、SnO2、B:ZnO、CdO x and MoO x One or more combinations of; and / or, The metal nitride includes TiN x and TiO x N y One or more combinations of; and / or, The metal fluoride comprises one or more combinations of MgF2, LiF, YF3 and CeF3; and / or, The metal silicide comprises one or more combinations of TiSi2, TaSi2, MoSi2, CoSi2, Ni2Si and WSi2; and / or, The metal includes one or more combinations of Ni, Ti, Cr, Cu, W, Mo and Ag.

10. The solar cell according to any one of claims 1 to 3, characterized in that The first doped layer is a doped polysilicon layer, and the second doped layer is a doped polysilicon layer, a doped microcrystalline silicon layer, or a doped amorphous silicon layer; or, The first doped layer is a doped amorphous silicon layer or a doped microcrystalline silicon layer, and the second doped layer is a doped microcrystalline silicon layer or a doped amorphous silicon layer.

11. The solar cell according to any one of claims 1 to 3, characterized in that: The conductivity type of the first doped layer is N-type, and the conductivity type of the second doped layer is P-type; or, The conductivity type of the first doping layer is P type, and the conductivity type of the second doping layer is N type.

12. A method for preparing a solar cell, characterized in that: include: Providing a battery substrate, the battery substrate having a first surface and a second surface opposite to each other, the first surface having first areas and second areas alternately distributed and a spacing area between adjacent first areas and second areas; forming a first doped layer at least on the first region, and forming a second doped layer at least on the second region, wherein the first doped layer and the second doped layer have opposite polarities; A first conductive layer is formed on a side of the first doped layer away from the battery substrate, and a second conductive layer is formed on a side of the second doped layer away from the battery substrate, at least one of the first conductive layer and the second conductive layer extends to contact and connect the first doped layer and the second doped layer, and the first conductive layer and the second conductive layer are formed integrally; as well as The first conductive layer and the second conductive layer are electrically isolated.

13. A photovoltaic module, comprising a glass cover plate, a film layer, a battery layer, a film layer and a transparent or opaque back plate stacked in sequence, characterized in that: The cell layer includes a plurality of solar cells according to any one of claims 1 to 11 or solar cells prepared by the preparation method according to claim 12 connected in series.

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