Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a solar cell, a manufacturing method thereof and a photovoltaic module. The solar cell includes a semiconductor substrate, a first semiconductor layer, a first electrode, and a dielectric layer. The first surface of the semiconductor substrate comprises a first region and a second region which are adjacently arranged along a first direction; the first semiconductor layer covers the first region; the first electrode covers the first semiconductor layer; the dielectric layer covers the second region; a first gap is arranged between the dielectric layer and the edge of the first semiconductor layer along the first direction. Since the dielectric layer does not cover the first region, that is, the surface of the first semiconductor layer is not covered by the dielectric layer, laser grooving on the dielectric layer is not needed before the electrode is formed, and damage of laser to the semiconductor substrate is avoided. In the process of forming the first electrode, the contact area of the first electrode and the first semiconductor layer is not limited by the laser slotting area, so that the contact area of the first electrode and the first semiconductor layer is larger, the parasitic absorption is further reduced, and the photoelectric conversion efficiency of the cell is improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic power generation technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] At present, crystalline silicon solar cells still occupy the main market of photovoltaic cells, and TOPCon technology has become one of the most promising new high-efficiency cell technologies due to its process route, which is highly compatible with the traditional PERC cell production line and has obvious efficiency gains. The use of full-surface N-poly on the back of TOPCon cells is the current mainstream technology, but there is a large parasitic absorption, which limits JSC, so the formation of poly fingers on the back is one of the main directions for improving efficiency.

[0003] In the prior art, some solar cells have poly-finger and passivation layer covering the poly-finger formed on the front side, through-holes are opened in the passivation layer in the area corresponding to the poly-finger, and electrodes in contact with the poly-finger are formed in the through-holes. The prior art solution makes it impossible to make the width of the poly-finger area very small, and the technology of opening the through-hole will damage the poly layer at the position of the through-hole. The contact area between the electrode and the poly-finger is small, and the poly-finger that is not in contact with the electrode has serious parasitic absorption, which limits JSC and affects the battery efficiency. Summary of the invention

[0004] The purpose of the present application is to provide a solar cell and a manufacturing method thereof, and a photovoltaic module, so that the width of the poly-finger area is not limited by the opening area and can be made smaller, thereby improving the photoelectric conversion efficiency.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A solar cell, comprising:

[0007] A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, wherein the first surface includes a first region and a second region adjacently arranged along a first direction;

[0008] A first semiconductor layer, the first semiconductor layer covers the first region;

[0009] a first electrode, the first electrode covering the first semiconductor layer;

[0010] The dielectric layer covers the second region, and a first gap is formed between the dielectric layer and an edge of the first semiconductor layer along a first direction.

[0011] In the process of manufacturing the solar cell provided by the present application, since the dielectric layer does not cover the first area, that is, the surface of the first semiconductor layer is not covered by the dielectric layer, it is not necessary to laser groove the dielectric layer before forming the electrode, thereby avoiding damage to the semiconductor substrate by the laser. In addition, in the process of forming the first electrode, the contact area between the first electrode and the first semiconductor layer is no longer limited by the laser groove area, thereby making the contact area between the first electrode and the first semiconductor layer larger, thereby reducing parasitic absorption and improving the photoelectric conversion efficiency of the battery.

[0012] In one implementation, the width of the first gap along the first direction is 1 μm-10 μm to ensure that the recombination rate in the first gap is small while not affecting the first electrode covering more area of ​​the first semiconductor layer, thereby reducing contact resistance and current loss.

[0013] In one implementation, along the first direction, there is a second gap between the dielectric layer and the edge of the first electrode. In this way, along the first direction, the two side edges of the first electrode can appropriately exceed the two side edges of the first semiconductor layer, increasing the width of the first electrode, thereby reducing the transmission resistance, the series resistance is also lower, and then the fill factor FF is increased to improve the efficiency of the solar cell.

[0014] In one implementation, along the first direction, the width of the first gap is greater than the width of the second gap. With this technical solution, the two side edges of the first electrode are arranged beyond the two side edges of the first semiconductor layer, so that the first electrode can extend to the side of the first semiconductor layer, further increasing the contact area between the first electrode and the first semiconductor layer.

[0015] In one implementation, the first region is convex in a direction away from the first surface compared to the second region. In the case where the solar cell is a back contact cell, the second semiconductor layer is disposed in the groove structure, which is beneficial to increase the distance between the first semiconductor layer and the second semiconductor layer in the direction of the semiconductor thickness, thereby reducing recombination and preventing leakage.

[0016] The first region has an inclined side surface at a position close to the second region, and the first electrode extends from the top surface of the first semiconductor layer to cover at least a portion of the inclined side surface.

[0017] In one implementation, the first semiconductor layer extends to near the inclined side surface, and the first semiconductor layer is completely covered by the first electrode. In this configuration, the first electrode covers the top surface and at least part of the side surface of the first semiconductor layer, further increasing the contact area between the first electrode and the first semiconductor layer, and reducing the contact resistance between the first electrode and the first semiconductor layer.

[0018] In one implementation, the first electrode includes a first metal layer and a second metal layer stacked in sequence in a direction away from the first surface; and, along the thickness direction of the semiconductor substrate, a region of the inclined side surface covered by the first metal layer is closer to the first semiconductor layer than a region of the inclined side surface covered by the second metal layer; or,

[0019] The first electrode includes a first metal layer, a second metal layer, and a third metal layer which are sequentially stacked in a direction away from the first surface; and along the thickness direction of the semiconductor substrate, the region of the inclined side surface covered by the first metal layer, the region of the inclined side surface covered by the second metal layer, and the region of the inclined side surface covered by the third metal layer are sequentially away from the first semiconductor layer. With this technical solution, a relatively low-priced material can be selected according to the required functions of the first metal layer, the second metal layer, and the third metal layer, thereby reducing costs.

[0020] In one implementation, the first electrode covers the first semiconductor layer and the first gap, and extends onto the dielectric layer to prevent electrical performance loss caused by direct exposure of the semiconductor substrate.

[0021] In one implementation, the first electrode includes a first metal layer and a second metal layer stacked in sequence in a direction away from the first surface, and the first metal layer completely covers the top surface and side surfaces of the first semiconductor layer; the second metal layer contacts the semiconductor substrate at the first gap and extends onto the dielectric layer. Since the metal elements in the second metal layer can easily enter the first semiconductor layer, the blocking effect of the first metal layer is required. The first metal layer is used as a blocking layer and needs to completely cover the first semiconductor layer, that is, the top surface and side surfaces of the first semiconductor layer are covered by the first metal layer to prevent the metal elements in the second metal layer from entering the first semiconductor layer.

[0022] In one implementation, the first region is a first pyramid velvet surface, a pyramid base structure surface or a polished surface; when the first region of the first surface of the semiconductor substrate is a first pyramid velvet surface or a pyramid base structure surface, the surface area of ​​the first semiconductor layer formed in the first region can be increased, thereby facilitating increasing the contact area between the first semiconductor layer and the first electrode, reducing the contact resistance between the first semiconductor layer and the first electrode, and further improving the operating performance of the solar cell.

[0023] And / or, the second region is a second pyramid velvet surface, a pyramid base structure surface or a polished surface. In the case where the second region is a second pyramid velvet surface or a pyramid base structure surface, the second pyramid velvet surface or the pyramid base structure surface has an uneven feature, which is beneficial to increase the surface area of ​​the second region, improve the light trapping effect of the second region, and facilitate more light to be refracted into the semiconductor substrate through the concave-convex structure of the second region and utilized by the semiconductor substrate.

[0024] In one implementation, along the first direction, the width of the first semiconductor layer is 1 μm-100 μm; and / or, along the first direction, the width of the first electrode is 1 μm-150 μm. In this technical solution, since there is no need to groove the dielectric layer and then form the first electrode, the width of the first semiconductor layer is not limited by the groove area (for example, the width of the laser spot), and the width of the first semiconductor layer can be narrower, so that the area of ​​the dielectric layer covering the first surface can be larger, thereby further reducing parasitic absorption and improving JSC.

[0025] In one implementation, the solar cell further includes a second semiconductor layer, the conductivity type of the second semiconductor layer being opposite to that of the first semiconductor layer;

[0026] The second semiconductor layer covers at least a portion of the second surface of the semiconductor substrate; or, the second semiconductor layer covers at least a portion of the second region.

[0027] In one implementation, the first semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell further includes a first interface layer located on a side of the first semiconductor layer close to the semiconductor substrate;

[0028] The second semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell also includes a second interface layer located on the side of the second semiconductor layer close to the semiconductor substrate. The passivation contact structure composed of the interface layer and the semiconductor layer has an excellent interface passivation effect, and can achieve selective collection of carriers, reduce the carrier recombination rate in the area of ​​the semiconductor substrate surface where the semiconductor layer is formed, and further improve the photoelectric conversion efficiency of the solar cell.

[0029] A method for manufacturing a solar cell, comprising:

[0030] A semiconductor layer substrate is provided, wherein the semiconductor substrate has a first surface and a second surface opposite to each other; the first surface includes first regions and second regions alternately distributed along a first direction;

[0031] forming a first semiconductor layer and a sacrificial layer in sequence on the first surface;

[0032] removing the first semiconductor layer and the sacrificial layer in the second region;

[0033] Depositing a dielectric layer on the first surface, wherein a portion of the dielectric layer located in the first area and a portion of the dielectric layer located in the second area have a gap;

[0034] removing the sacrificial layer and simultaneously removing the dielectric layer located in the first region, so that the first semiconductor layer located in the first region is exposed;

[0035] A first electrode is formed on the first semiconductor layer.

[0036] In the above-mentioned method for manufacturing a solar cell, since a sacrificial layer is formed on the side of the first semiconductor layer away from the semiconductor substrate, and there is a gap between the portion of the deposited dielectric layer located in the first region and the portion located in the second region. In this way, the sacrificial layer in the first region can be removed together with the dielectric layer in the first region, so that the first semiconductor layer is finally exposed, and a first electrode is formed on the exposed first semiconductor layer. In the process of forming the first electrode, the contact area between the first electrode and the first semiconductor layer is no longer limited by the laser groove area, so that the contact area between the first electrode and the first semiconductor layer is larger, thereby reducing parasitic absorption and improving the photoelectric conversion efficiency of the battery. In addition, there is no need to laser groove the dielectric layer before forming the electrode, thereby avoiding damage to the semiconductor substrate by the laser.

[0037] In one implementation, forming a first semiconductor layer and a sacrificial layer in sequence on a first surface includes:

[0038] A deposition process is performed on the first surface of the semiconductor substrate to form a first semiconductor layer, and a doped silicon glass layer is formed on the side of the first semiconductor layer away from the semiconductor substrate. The doped silicon glass layer is a sacrificial layer, which simplifies the processing technology and improves the processing efficiency. Or,

[0039] After a first semiconductor layer is formed by a deposition process on the first surface of the semiconductor substrate, a sacrificial layer is deposited on the side of the first semiconductor layer away from the semiconductor substrate. The above technical solution makes it easier to control the thickness of the sacrificial layer and ensure that the thickness of the sacrificial layer is thick enough so that after the sacrificial layer is side-etched, a gap is formed between the mask layer and the first semiconductor layer, thereby forming a gap between the dielectric layer in the first area and the dielectric layer in the second area during the deposition of the dielectric layer. Or,

[0040] A deposition process is performed on the first surface of the semiconductor substrate to form a first semiconductor layer, and a doped silicon glass layer is formed on the side of the first semiconductor layer away from the semiconductor substrate. An intermediate layer is deposited on the side of the doped silicon glass layer away from the semiconductor substrate, and the sacrificial layer includes the doped silicon glass layer and the intermediate layer.

[0041] In one implementation, the material of the sacrificial layer includes PSG, BSG or SiOx; and / or, the thickness of the sacrificial layer is 50nm-300nm, so as to form a gap of appropriate width between the dielectric layer of the first region and the dielectric layer of the second region while avoiding material waste. And / or, the thickness of the first semiconductor layer is 150nm-200nm.

[0042] In one implementation, removing the first semiconductor layer and the sacrificial layer in the second region includes:

[0043] forming a mask layer on a side of the sacrificial layer facing away from the semiconductor substrate;

[0044] The first semiconductor layer and the sacrificial layer in the second region are removed by selective etching through the mask layer.

[0045] In one implementation, after removing the first semiconductor layer and the sacrificial layer in the second region by selectively etching the mask layer and before depositing the dielectric layer on the first surface, the method for manufacturing a solar cell further includes:

[0046] Etching the second area of ​​the first surface so that the second area is concave toward the second surface and a pyramid velvet surface or a polished surface is formed in the second area;

[0047] A portion of the sacrificial layer in the first region is selectively etched away and the mask layer in the first region is retained, so that a gap exists between a portion of the mask layer and the first semiconductor layer.

[0048] In one implementation, selectively etching away a portion of the sacrificial layer in the first region and retaining the mask layer in the first region includes: using an acid solution to side-etch the sacrificial layer, and the side-etching width of the sacrificial layer on both sides along the first direction is 6 μm-9 μm, so as to prevent the mask layer from collapsing and deforming, and ensure that there is a gap between the dielectric layer in the first region and the dielectric layer in the second region during the deposition of the dielectric layer.

[0049] In one implementation, forming a first electrode on a surface of a first semiconductor layer comprises:

[0050] The formed first electrode completely covers the first semiconductor layer; or,

[0051] The first region has an inclined side surface at a position close to the second region, and a first metal layer and a second metal layer are sequentially formed on a side of the first electrode facing away from the semiconductor substrate, and the first metal layer completely covers the first semiconductor layer and extends to cover part of the inclined side surface, and the second metal layer completely covers the first metal layer and extends to cover part of the inclined side surface; or,

[0052] The first region has an inclined side surface near the second region, and a first metal layer, a second metal layer, and a third metal layer are sequentially formed on the side of the first electrode away from the semiconductor substrate; and along the thickness direction of the semiconductor substrate, the area of ​​the inclined side surface covered by the first metal layer, the area of ​​the inclined side surface covered by the second metal layer, and the area of ​​the inclined side surface covered by the third metal layer are sequentially away from the first semiconductor layer. With this technical solution, a lower-priced material can be selected according to the required functions of the first metal layer, the second metal layer, and the third metal layer, thereby reducing costs.

[0053] In one implementation, after forming the first electrode on the surface of the first semiconductor layer, the method for manufacturing a solar cell further includes:

[0054] forming a second semiconductor layer on the second surface, the conductivity type of the second semiconductor layer being opposite to that of the first semiconductor layer, and forming a second electrode on the second semiconductor layer; or,

[0055] A second semiconductor layer is formed at least in the second region of the first surface, the conductivity type of the second semiconductor layer being opposite to that of the first semiconductor layer, and a second electrode is formed on the second semiconductor layer.

[0056] A photovoltaic module includes a plurality of solar cells as described above, or includes a plurality of solar cells formed by a manufacturing method as described above. Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell and the manufacturing method of the solar cell, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0058] Figure 1 A local SEM image of a solar cell provided in an embodiment of the present application;

[0059] Figure 2 A partial cross-sectional view of a solar cell provided in an embodiment of the present application;

[0060] Figure 3 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0061] Figure 4 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0062] Figure 5 A top view of a solar cell provided in an embodiment of the present application;

[0063] Figure 6 Schematic diagram of the solar cell manufacturing method provided in the embodiment of the present application Figure 1 ;

[0064] Figure 7 Schematic diagram of the solar cell manufacturing method provided in the embodiment of the present application Figure 2 ;

[0065] Figure 8 Schematic diagram of the solar cell manufacturing method provided in the embodiment of the present application Figure 3 ;

[0066] Fig. 9 Schematic diagram of the solar cell manufacturing method provided in the embodiment of the present application Figure 4 ;

[0067] Fig.10 Schematic diagram of the solar cell manufacturing method provided in the embodiment of the present application Figure 5 ;

[0068] Fig.11 Schematic diagram of the solar cell manufacturing method provided in the embodiment of the present application Figure 6 ;

[0069] Fig.12 Schematic diagram of the solar cell manufacturing method provided in the embodiment of the present application Figure 7 ;

[0070] Fig.13 A schematic diagram of a sacrificial layer after side etching in the solar cell manufacturing method provided in an embodiment of the present application;

[0071] Reference numerals:

[0072] 1-first semiconductor layer, 2-first electrode, 2a-first metal layer, 2b-second metal layer, 2c-third metal layer, 3-dielectric layer, 3a-passivation layer, 3b-anti-reflection layer, 4-semiconductor substrate, 4a-first region, 4b-second region, 5-doped silicon glass layer, 6-intermediate layer, 7-mask layer, a-side etched region, b-non-side etched region. DETAILED DESCRIPTION

[0073] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0074] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0075] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0076] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0077] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0078] As described in the background art, some solar cells have poly-finger (i.e., polycrystalline silicon finger-shaped portion) and dielectric layer 3 covering the poly-finger formed on the front side, through-holes are opened in the area corresponding to the poly-finger on the dielectric layer 3, and electrodes in contact with the poly-finger are formed in the through-holes. When laser is used to groove the dielectric layer 3 to form through-holes, there will be unavoidable laser damage, resulting in reduced cell efficiency; in addition, the laser groove area is limited, resulting in a small contact area between the electrode and the poly-finger, and a large area of ​​the poly-finger that is not in contact with the electrode, resulting in serious parasitic absorption, limiting JSC, and affecting cell efficiency.

[0079] In view of the above, please refer to Figure 1-Figure 5 The solar cell provided in the embodiment of the present application includes a semiconductor substrate 4, a first semiconductor layer 1, a first electrode 2 and a dielectric layer 3. The semiconductor substrate 4 has a first surface and a second surface opposite to each other, that is, the two surfaces opposite to each other along the thickness direction of the semiconductor substrate 4 are respectively the first surface and the second surface. The first surface includes a first region 4a and a second region 4b adjacently arranged along a first direction, and the first region 4a and the second region 4b are alternately distributed along the first direction, for example, the first region 4a and the second region 4b can be alternately distributed in strips, or can be alternately distributed in interdigitated shapes.

[0080] The first semiconductor layer 1 covers the first region 4a. The first semiconductor layer 1 can be additionally formed on the first region 4a by a deposition technique, or can be formed in the semiconductor substrate 4 by diffusion, ion implantation, etc. The first electrode 2 covers the first semiconductor layer 1, that is, the first electrode 2 covers at least a portion of the surface of the first semiconductor layer 1, so that the first electrode 2 is electrically connected to the first semiconductor layer 1, which is beneficial for the first electrode 2 to extract the carriers collected by the first semiconductor layer 1.

[0081] The dielectric layer 3 covers the second region 4b. On the one hand, the dielectric layer 3 can protect the surface of the cell and prevent water vapor or oxygen from penetrating into the interior of the cell, thereby avoiding the performance degradation of the cell due to oxidation or hydrolysis; on the other hand, the provision of the dielectric layer 3 can improve the utilization rate of light and reduce the surface recombination rate of the cell, thereby improving the photoelectric conversion efficiency of the cell. Along the first direction, there is a first gap between the dielectric layer 3 and the edge of the first semiconductor layer 1. That is, the dielectric layer 3 does not cover the first region 4a, the dielectric layer 3 is only located in the second region 4b, and along the first direction, the edge of the dielectric layer 3 does not contact the edge of the first semiconductor layer 1, but has a first gap.

[0082] In the process of manufacturing the solar cell provided by the present application, since the dielectric layer 3 does not cover the first area 4a, that is, the surface of the first semiconductor layer 1 is not covered by the dielectric layer 3, there is no need to laser groove the dielectric layer 3 before forming the electrode, thereby avoiding laser damage to the semiconductor substrate 4. In addition, in the process of forming the first electrode 2, the contact area between the first electrode 2 and the first semiconductor layer 1 is no longer limited by the laser groove area, so that the contact area between the first electrode 2 and the first semiconductor layer 1 is larger, and the width of the first semiconductor layer 1 can be made smaller, for example, the width of the first semiconductor layer 1 can be less than or equal to 5μm, thereby reducing parasitic absorption and improving the photoelectric conversion efficiency of the battery. Among them, the first surface can be the front side (i.e., the light-receiving side) of the solar cell, or it can be the back side (i.e., the backlight side) of the solar cell.

[0083] like Figure 5As shown, it is considered that if the first gap is too large, the area of ​​the semiconductor substrate 4 exposed in the first gap is large, which will lead to a large recombination rate in the first gap, and the semiconductor substrate 4 exposed in the first gap is easily oxidized or hydrolyzed, resulting in performance degradation; if the first gap is too small, the dielectric layer 3 may affect the formation of the first electrode 2 on the first semiconductor layer 1, reduce the area of ​​the first electrode 2 covering the first semiconductor layer 1, and increase the contact resistance between the first electrode 2 and the first semiconductor layer 1. In view of the above two situations, in this technical solution, the width L of the first gap along the first direction is set within a suitable range of 1μm-10μm to ensure that the recombination rate in the first gap is small, while not affecting the first electrode 2 covering more area of ​​the first semiconductor layer 1, reducing the contact resistance and reducing the current loss.

[0084] Exemplarily, the width L of the first gap along the first direction is 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, 9.5 μm or 10 μm.

[0085] In some embodiments, Figure 2 and Figure 3 As shown, along the first direction, there is a second gap between the dielectric layer 3 and the edge of the first electrode 2. In this way, along the first direction, the two side edges of the first electrode 2 can appropriately exceed the two side edges of the first semiconductor layer 1, increasing the width of the first electrode 2, thereby reducing the transmission resistance, the lower the series resistance, and thus improving the fill factor FF, so as to improve the efficiency of the solar cell.

[0086] In the above technical solution, along the first direction, the width of the first gap is greater than the width of the second gap. With this technical solution, the two side edges of the first electrode 2 are arranged beyond the two side edges of the first semiconductor layer 1, so that the first electrode 2 can extend to the side of the first semiconductor layer 1, further increasing the contact area between the first electrode 2 and the first semiconductor layer 1, thereby reducing the contact resistance between the first electrode 2 and the first semiconductor layer 1, and improving the efficiency of the solar cell.

[0087] In other embodiments, Figure 4As shown, the first electrode 2 covers the first semiconductor layer 1 and the first gap, and extends to the dielectric layer 3. At this time, the first electrode 2 is a structure of at least two layers, that is, it at least includes a first metal layer 2a and a second metal layer 2b stacked in sequence along a direction away from the first surface. The first metal layer 2a is an electroplating layer, for example, it can be an electroplating layer of nickel, titanium, copper, etc.; the thickness of the first metal layer 2a is relatively small, generally less than 5μm, for example, it can be 5μm, 4μm, 3μm, 2μm or 1μm. The second metal layer 2b is a printed metal layer, and the printed slurry can be a base metal slurry. The metal material in the second metal layer 2b is preferably copper, and can also be a mixture of aluminum and copper or a mixture of silver and copper. In this embodiment, the width of the second metal layer 2b can exceed the width of the first semiconductor layer 1, and can exceed a distance of more than 20μm on one side. For example, the width of the second metal layer 2b can exceed the edge of the first semiconductor layer 1 on the same side by 20μm, 21μm, 22μm, 23μm, 24μm, 25μm, etc., so that a part of the second metal layer 2b directly contacts the semiconductor substrate 4 at the first gap and extends onto the dielectric layer 3 to prevent the loss of electrical performance caused by direct exposure of the semiconductor substrate 4. In addition, the first metal layer 2a needs to completely cover the first semiconductor layer 1, and the first semiconductor layer 1 can be a polysilicon layer. This is because the metal elements in the second metal layer 2b can easily enter the first semiconductor layer 1, so the blocking effect of the first metal layer 2a is required. The first metal layer 2a is used as a blocking layer and needs to completely cover the first semiconductor layer 1, that is, the top surface and side surfaces of the first semiconductor layer 1 are covered by the first metal layer 2a.

[0088] In other embodiments, Figure 2 and Figure 3 As shown, the first region 4a is convex in the direction away from the first surface compared to the second region 4b, or in other words, the second region 4b is concave in the direction of the first surface relative to the first region 4a to form a groove structure. In this way, when the solar cell is a back-contact cell, the second semiconductor layer is arranged in the groove structure, which is conducive to increasing the distance between the first semiconductor layer 1 and the second semiconductor layer in the direction of the semiconductor thickness, thereby reducing recombination and preventing leakage. Among them, the first region 4a has an inclined side surface near the second region 4b, and the inclined side surface gradually moves away from the second region 4b in the direction away from the second surface. The first electrode 2 extends from the top surface of the first semiconductor layer 1 to cover at least part of the inclined side surface. In this way, the first electrode 2 covers the top surface and at least part of the side surface of the first semiconductor layer 1, further increasing the contact area between the first electrode 2 and the first semiconductor layer 1, reducing the contact resistance between the first electrode 2 and the first semiconductor layer 1, and improving the efficiency of the solar cell.

[0089] In the above technical solution, if Figure 2 and Figure 3As shown, the first semiconductor layer 1 extends to near the inclined side, and the first semiconductor layer 1 is completely covered by the first electrode 2. It can be understood that the side of the first semiconductor layer 1 and the top surface facing away from the semiconductor substrate 4 are completely covered by the first electrode 2, and the bottom surface of the first semiconductor layer 1 close to the semiconductor substrate 4 is in contact with the semiconductor substrate 4. In this technical solution, the edges of both sides of the first semiconductor layer 1 can extend to the top of the inclined side, so that the width of the first semiconductor layer 1 is wider, which improves the carrier collection efficiency of the first semiconductor layer 1; and the first semiconductor layer 1 is completely covered by the first electrode 2, so that the contact area between the first electrode 2 and the first semiconductor layer 1 is maximized, further reducing the contact resistance between the first electrode 2 and the first semiconductor layer 1, and improving the efficiency of the solar cell.

[0090] In some other embodiments, the first electrode 2 may include one or more metal layers. In the case where the first electrode 2 includes multiple metal layers, the multiple metal layers are stacked in sequence in a direction away from the first surface. Figure 2 As shown, the first electrode 2 may include a first metal layer 2a and a second metal layer 2b sequentially arranged in a direction away from the first surface. Moreover, along the thickness direction of the semiconductor substrate 4, the area of ​​the inclined side covered by the first metal layer 2a is closer to the first semiconductor layer 1 than the area of ​​the inclined side covered by the second metal layer 2b. In this technical solution, the first metal layer 2a can completely wrap the surface of the first electrode 2, and the second metal layer 2b can completely wrap the outer surface of the first metal layer 2a. By adopting the above technical solution, a lower-priced material can be selected according to the functions required by the first metal layer 2a and the second metal layer 2b, thereby reducing costs. Among them, the second metal layer 2b can be used as a welding layer, the second metal layer 2b can select a weldable metal material, and the first metal layer 2a can select a metal material with low cost and good conductivity. Compared with the prior art in which the electrode layer is an integrated structure, since the first metal layer 2a and the second metal layer 2b can select different materials as needed, different functions can be achieved. Exemplarily, the first metal layer 2a includes Ni and the second metal layer 2b includes Cu.

[0091] like Figure 3As shown, in another embodiment, the first electrode 2 includes a first metal layer 2a, a second metal layer 2b and a third metal layer 2c which are sequentially stacked in a direction away from the first surface, and along the thickness direction of the semiconductor substrate 4, the area of ​​the inclined side surface covered by the first metal layer 2a, the area of ​​the inclined side surface covered by the second metal layer 2b and the area of ​​the inclined side surface covered by the third metal layer 2c are sequentially away from the first semiconductor layer 1. In this technical solution, the first metal layer 2a can completely wrap the surface of the first electrode 2, the second metal layer 2b can completely wrap the outer surface of the first metal layer 2a, and the third metal layer 2c can completely wrap the outer surface of the second metal layer 2b. With this technical solution, a lower-priced material can be selected according to the required functions of the first metal layer 2a, the second metal layer 2b and the third metal layer 2c to reduce costs. Among them, the third metal layer 2c can be used as a welding layer, and the third metal layer 2c can be made of a weldable metal material, and the first metal layer 2a and the second metal layer 2b can be made of a metal material with low cost and good conductivity. Compared with the prior art in which the electrode layer is an integrated structure, since the first metal layer 2a, the second metal layer 2b and the third metal layer 2c can be made of different materials as needed, different functions can be achieved. Exemplarily, the first metal layer 2a includes Ni, the second metal layer 2b includes Cu, and the third metal layer 2c includes Ni.

[0092] In other embodiments, the first region 4a of the first surface of the semiconductor substrate 4 may be a first pyramid velvet surface, a pyramid base structure surface or a polished surface. In the case where the first region 4a of the first surface of the semiconductor substrate 4 is a first pyramid velvet surface or a pyramid base structure surface, the first pyramid velvet surface or the pyramid base structure surface has an uneven feature, so that the side of the first semiconductor layer 1 formed in the first region 4a away from the semiconductor substrate 4 will also fluctuate with the fluctuations of the surface of the first region 4a, that is, the side of the partial first semiconductor layer 1 formed in the first region 4a away from the semiconductor substrate 4 also has substantially the same undulating morphology as the first region 4a, so the use of this technical solution can increase the surface area of ​​the first semiconductor layer 1 formed in the first region 4a, thereby facilitating an increase in the contact area between the first semiconductor layer 1 and the first electrode 2, reducing the contact resistance between the first semiconductor layer 1 and the first electrode 2, and further improving the working performance of the solar cell.

[0093] In addition, the second region 4b is a second pyramid velvet surface, a pyramid base structure surface or a polished surface. In the case where the second region 4b is a second pyramid velvet surface or a pyramid base structure surface, the second pyramid velvet surface or the pyramid base structure surface has an uneven feature, which is beneficial to increase the surface area of ​​the second region 4b, improve the light trapping effect of the second region 4b, and facilitate more light to be refracted into the semiconductor substrate 4 through the concave-convex structure of the second region 4b and utilized by the semiconductor substrate 4.

[0094] In terms of width range, the width of the first semiconductor layer 1 and the first electrode 2 is not limited in this application, as long as the width of the first semiconductor layer 1 and the first electrode 2 have their corresponding performance. Exemplarily, along the first direction, the width of the first semiconductor layer 1 is 1μm-100μm. It should be noted that in this technical solution, since there is no need to groove the dielectric layer and then form the first electrode 2, the width of the first semiconductor layer 1 is not limited by the groove area (such as the width of the laser spot), and the width of the first semiconductor layer 1 can be narrower, so that the area covered by the dielectric layer 3 on the first surface can be larger, thereby further reducing parasitic absorption and improving JSC. For example, the width of the first semiconductor layer 1 is 1 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm or 100 μm. Optionally, the width of the first semiconductor layer 1 is 1 μm-50 μm.

[0095] In addition, in the first direction, the width of the first electrode 2 is 1 μm-150 μm. For example, the width of the first electrode 2 is 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm or 150 μm.

[0096] In the actual application process, the material of the semiconductor substrate 4 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 4 can be an intrinsic conductive substrate, an n-type conductive substrate or a p-type conductive substrate. Optionally, the semiconductor substrate 4 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0097] Exemplarily, the semiconductor substrate 4 may be a p-type substrate or an n-type substrate. The n-type substrate has the advantages of long minority carrier lifetime, no light decay, and good weak light performance.

[0098] The solar cell may further include a second semiconductor layer and a second electrode, wherein the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer 1, so as to collect and extract electrons and holes respectively, thereby facilitating the formation of photocurrent. The second electrode is disposed on a side of the second semiconductor layer away from the semiconductor substrate 4, so as to utilize the second electrode layer to extract the carriers collected by the second semiconductor layer.

[0099] The solar cell may be a back contact cell or a bifacial cell. When the solar cell is a back contact cell, the back contact cell may be a TBC (Tunnel Oxide Passivated Contact Back Contact) or a HPBC (Hybrid Passivated Back Contact), etc.; when the solar cell is a bifacial solar cell, the bifacial solar cell may be a PREC (Passivated Emitter Rear Cell) solar cell or a TOPCon (Tunnel Oxide Passivated Contact) solar cell, etc. Of course, the solar cell may also be a single-sided hybrid cell or a bifacial hybrid cell.

[0100] In the case where the solar cell is a bifacial cell, the second semiconductor layer covers at least a portion of the second surface of the semiconductor substrate 4. In the case where the solar cell is a back contact cell, the second semiconductor layer covers at least a portion of the second region 4b, and the second semiconductor layer and the first semiconductor layer 1 are alternately arranged on the first surface. Specifically, the second semiconductor layer and the first semiconductor layer 1 can be alternately spaced in strips or in interdigitated shapes.

[0101] Specifically, the first semiconductor layer 1 includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon. In this case, the doped polycrystalline silicon layer has higher carrier transport characteristics. Therefore, when the first semiconductor layer 1 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which is conducive to improving the photoelectric conversion efficiency of the back contact battery. Of course, the first semiconductor layer 1 can also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The second semiconductor layer also includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon.

[0102] In some embodiments, a first interface layer is provided between the first semiconductor layer 1 and the semiconductor substrate 4, and a second interface layer is provided between the second semiconductor layer and the semiconductor substrate 4. The passivation contact structure composed of the interface layer and the semiconductor layer has an excellent interface passivation effect, and can realize the selective collection of carriers, reduce the carrier recombination rate in the area where the semiconductor layer is formed on the surface of the semiconductor substrate 4, and further improve the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer can be set according to the material of the first semiconductor layer 1 and actual needs, and the material and thickness of the second interface layer can be set according to the material of the second semiconductor layer and actual needs, and are not specifically limited here.

[0103] For example, the first semiconductor layer 1 may be a doped polysilicon layer, and the first interface layer may be a tunneling oxide layer. The second semiconductor layer may be a doped polysilicon layer, and the second interface layer may be a tunneling oxide layer.

[0104] Of course, when the first semiconductor layer 1 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the first interface layer includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon. When the second semiconductor layer includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface layer includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon.

[0105] The materials of the first semiconductor layer 1 and the second semiconductor layer may be silicon (Si), germanium (Ge), silicon carbide (SiCx) or gallium arsenide (GaAs), etc. In terms of conductivity type, the first semiconductor layer 1 may be an n-type doped layer, and the second semiconductor layer may be a p-type doped layer; or, the first semiconductor layer 1 may be a p-type doped layer, and the second semiconductor layer may be an n-type doped layer.

[0106] In addition, in the embodiment of the present application, the dielectric layer 3 may be a single-layer structure or a multi-layer structure. In the case where the dielectric layer 3 is a single-layer structure, the dielectric layer 3 may include one or more of aluminum oxide, silicon nitride and silicon dioxide. In the case where the dielectric layer 3 is a multi-layer structure, it may include a passivation layer 3a and an anti-reflection layer 3b stacked in sequence, wherein the passivation layer 3a is located on the side of the anti-reflection layer 3b close to the semiconductor substrate 4. The material of the passivation layer 3a may include one or more of silicon nitride and Al2O3. The material of the anti-reflection layer 3b may include one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0107] The present invention also provides a method for manufacturing a solar cell. Figures 6 to 12 The manufacturing process is described by referring to the cross-sectional view of the operation shown in FIG. 1 . Specifically, the manufacturing method of the solar cell includes the following steps:

[0108] S1: Provide a semiconductor layer substrate, wherein the semiconductor substrate 4 has a first surface and a second surface opposite to each other; the first surface includes first regions 4a and second regions 4b alternately distributed along a first direction.

[0109] The first region 4a is used to form the first semiconductor layer 1, and the second region 4b is used to form the dielectric layer 3. The first region 4a and the second region 4b may be arranged alternately at intervals in a strip shape, or may be arranged alternately at intervals in a finger shape.

[0110] Before this step, in some embodiments, the semiconductor substrate 4 can also be put into a polishing and cleaning machine to remove the cut damage layer of the semiconductor substrate 4 using a polishing liquid. In addition, in this step, the morphology of the first surface and the second surface of the semiconductor substrate 4 after polishing and cleaning can be adjusted by adjusting parameters such as temperature, time, cleaning liquid type, and cleaning liquid concentration. It should be noted that in some examples, the polishing and cleaning step can be omitted.

[0111] S2: forming a first semiconductor layer 1 and a sacrificial layer in sequence on the first surface.

[0112] In the actual manufacturing process, in some examples, such as Figure 6 As shown, a first semiconductor layer 1 and a sacrificial layer are first formed on the first surface in an integral manner.

[0113] It should be noted that, when the solar cell also includes a first interface layer, in this step, before forming the first semiconductor layer 1, deposition and etching processes can be used to form a first interface layer that only covers the first area 4a; or, a first interface layer that is set as a whole layer can be formed on the first surface first, and then a first interface layer that is set as a whole layer can be formed.

[0114] S3: removing the first semiconductor layer 1 and the sacrificial layer in the second region 4b;

[0115] Next, if Figure 7 As shown, in this step, a mask layer 7 can be first formed on the side of the sacrificial layer away from the semiconductor substrate 4, and the first semiconductor layer 1 and the sacrificial layer corresponding to the second region 4b are selectively etched and removed under the masking effect of the mask layer 7, and the first semiconductor layer 1 and the sacrificial layer corresponding to the first region 4a are retained. Of course, after the mask layer 7 is formed, the mask layer 7, the first semiconductor layer 1 and the sacrificial layer located in the second region 4b can be removed simultaneously by laser process. Among them, the first semiconductor layer 1 and the sacrificial layer corresponding to the second region 4b can be selectively etched and removed by laser process or wet chemical process. For example, a green nanosecond laser can be used to remove the first semiconductor layer 1 and the sacrificial layer in the second region 4b.

[0116] It can be understood that, in the case where the solar cell further includes a first interface layer, in this step, the first interface layer in the second region 4 b is removed together with the first semiconductor layer 1 and the sacrificial layer.

[0117] After step S3 and before step S3, the method for manufacturing a solar cell further includes:

[0118] S3a: etching the second region 4b of the first surface so that the second region 4b is recessed toward the second surface, and at the same time forming a pyramid velvet surface or a polished surface in the second region 4b.

[0119] like Figure 8 In step S3a, the second region 4b of the first surface is etched to form a groove structure in the second region 4b. The function of the groove structure is described above and will not be described here. At the same time, during the etching process, the damaged layer of the second region 4b is removed, and a second pyramid velvet surface, a pyramid base structure surface or a polished surface is formed in the second region 4b.

[0120] Furthermore, in this step, the first region 4a forms an inclined side surface near the second region 4b.

[0121] S3b: selectively etching away a portion of the sacrificial layer in the first region 4a and retaining the mask layer 7 in the first region 4a, so that a gap exists between a portion of the mask layer 7 and the first semiconductor layer 1.

[0122] like Fig. 9 As shown, the sacrificial layer may be side-etched to a certain width so that a certain gap is formed between the mask layer 7 and the first semiconductor layer 1, as shown in FIG. Fig.13 As shown, in the side-etched area a, there is a gap between the mask layer 7 and the first semiconductor layer 1, and in the non-side-etched area b, there is also a sacrificial layer. Specifically, the sacrificial layer can be side-etched with an acid solution, for example, a 0.5% concentration HF solution is selected to etch for 300s. The side-etching width of the sacrificial layer on both sides along the first direction is 6μm-9μm. For example, the side-etching width of the sacrificial layer on both sides is 6μm, 7μm, 8μm or 9μm, so as to prevent the mask layer 7 from collapsing and deforming, while ensuring that there is a gap between the dielectric layer 3 in the first area 4a and the dielectric layer 3 in the second area 4b during the deposition of the dielectric layer 3.

[0123] S4: depositing a dielectric layer 3 on the first surface, with a gap between a portion of the dielectric layer 3 located in the first region 4 a and a portion of the dielectric layer 3 located in the second region 4 b .

[0124] Next, if Fig.10 As shown, a dielectric layer 3 may be deposited on the first surface, and along the first direction, the dielectric layer 3 is not continuous, but the dielectric layer 3 located in the first area 4a and the dielectric layer 3 located in the second area 4b are discontinuous and unconnected.

[0125] S5: removing the sacrificial layer and simultaneously removing the dielectric layer 3 located in the first region 4 a, so that the first semiconductor layer 1 located in the first region 4 a is exposed.

[0126] Next, if Fig.11As shown, when the sacrificial layer is removed, the dielectric layer 3 on the side of the sacrificial layer facing away from the semiconductor substrate 4 is removed together. It can be understood that in the case where the sacrificial layer has a mask layer 7 on the side facing away from the semiconductor substrate 4, the sacrificial layer and the mask layer 7 and the dielectric layer 3 on the side facing away from the semiconductor substrate 4 are removed together. Afterwards, the first semiconductor layer 1 located in the first region 4a is not covered by any film layer, so that the first semiconductor layer 1 in the first region 4a is exposed.

[0127] S6 : forming a first electrode 2 on the first semiconductor layer 1 .

[0128] Next, if Fig.12 As shown, the first electrode 2 can be formed on the exposed first semiconductor by screen printing, electroplating or evaporation. The first electrode 2 formed in this step covers at least a portion of the surface of the first semiconductor layer 1, so that the first electrode 2 is electrically connected to the first semiconductor layer 1, which is beneficial for the first electrode 2 to extract the carriers collected by the first semiconductor layer 1.

[0129] In step S6, the formed first electrode 2 completely covers the first semiconductor layer 1, so that the contact area between the first electrode 2 and the first semiconductor layer 1 is maximized, further reducing the contact resistance between the first electrode 2 and the first semiconductor layer 1, and improving the efficiency of the solar cell.

[0130] The first region 4a has an inclined side surface near the second region 4b, and the first electrode 2 covers a portion of the inclined side surface. The first electrode 2 may include a first metal layer 2a and a second metal layer 2b stacked in sequence in a direction away from the semiconductor substrate 4, and the first metal layer 2a completely covers the first semiconductor layer 1 and extends to cover part of the inclined side surface, and the second metal layer 2b completely covers the first metal layer 2a and extends to cover part of the inclined side surface. The first metal layer 2a may be a seed layer for electroplating, and the second metal layer 2b may be a metal layer obtained by screen printing or electroplating.

[0131] Alternatively, the first electrode 2 includes a first metal layer 2a, a second metal layer 2b and a third metal layer 2c which are sequentially stacked in a direction away from the first surface, and along the thickness direction of the semiconductor substrate 4, the area of ​​the inclined side surface covered by the first metal layer 2a, the area of ​​the inclined side surface covered by the second metal layer 2b and the area of ​​the inclined side surface covered by the third metal layer 2c are sequentially away from the first semiconductor layer 1. In the above two technical solutions, a lower-priced material can be selected according to the required functions of the first metal layer 2a, the second metal layer 2b and the third metal layer 2c to reduce costs. Among them, the first metal layer 2a, the second metal layer 2b and the third metal layer 2c can all be electroplated layers, or the first metal layer 2a and the third metal layer 2c are electroplated layers, and the second metal layer 2b is a screen-printed metal layer.

[0132] In the above-mentioned method for manufacturing a solar cell, in step S2, a sacrificial layer is formed on the side of the first semiconductor layer 1 facing away from the semiconductor substrate 4, and there is a gap between the portion of the dielectric layer 3 deposited and formed in step S4 located in the first region 4a and the portion located in the second region 4b. In this way, the sacrificial layer in the first region 4a can be removed together with the dielectric layer 3 in the first region 4a, so that the first semiconductor layer 1 is finally exposed, and the first electrode 2 is formed on the exposed first semiconductor layer 1. In the process of forming the first electrode 2, the contact area between the first electrode 2 and the first semiconductor layer 1 is no longer limited by the laser groove area, so that the contact area between the first electrode 2 and the first semiconductor layer 1 is larger, thereby reducing parasitic absorption and improving the photoelectric conversion efficiency of the battery. In addition, there is no need to laser groove the dielectric layer 3 before forming the electrode, thereby avoiding damage to the semiconductor substrate 4 by the laser.

[0133] In some examples, step S2 sequentially forms a first semiconductor layer 1 and a sacrificial layer on the first surface, including: S21 performing a deposition process on the first surface of the semiconductor substrate 4 to form the first semiconductor layer 1, and forming a doped silicon glass layer 5 on the side of the first semiconductor layer 1 away from the semiconductor substrate 4, and the doped silicon glass layer 5 is a sacrificial layer. Specifically, a layer of epitaxial semiconductor layer is first deposited on the first surface, and then a doping diffusion process is performed on the epitaxial semiconductor layer to form the first semiconductor layer 1 having the doped silicon glass layer 5. Exemplarily, when the first semiconductor layer 1 is an N-type semiconductor layer, a layer of PSG (phospho silicate Glass) is simultaneously formed in the process of forming the first semiconductor layer 1; when the first semiconductor layer 1 is a P-type semiconductor layer, a layer of BSG (Boro-phospho-silicate Glass) is simultaneously formed in the process of forming the first semiconductor layer 1. In this step S21, the sacrificial layer is the doped silicon glass layer 5 formed on the side of the first semiconductor layer 1 away from the semiconductor substrate 4, which simplifies the processing technology and improves the processing efficiency.

[0134] In other examples, step S2 sequentially forms a first semiconductor layer 1 and a sacrificial layer on the first surface, including: S22 deposits a sacrificial layer on the side of the first semiconductor layer 1 away from the semiconductor substrate 4 after performing a deposition process on the first surface of the semiconductor substrate 4 to form the first semiconductor layer 1. Specifically, in this step, after the first semiconductor layer 1 is formed, a sacrificial layer is deposited on the side of the first semiconductor layer 1 away from the semiconductor substrate 4 to form the first semiconductor layer 1. In this step, the sacrificial layer is formed by deposition alone, the sacrificial layer may be SiOx, and the mask layer 7 may be SiNx. The etching rate of SiOx in low-concentration HF is much greater than that of the mask layer 7 and the first semiconductor layer 1, so the sacrificial layer can be corroded by the low-concentration HF side. Of course, the material of the sacrificial layer is not limited to SiOx, as long as it is different from the chemical properties of the film layer to be retained.

[0135] By adopting the above technical solution, it is easier to control the thickness of the sacrificial layer and ensure that the thickness of the sacrificial layer is thick enough so that after the sacrificial layer is side-etched, a gap is formed between the mask layer 7 and the first semiconductor layer 1, thereby forming a gap between the dielectric layer 3 of the first area 4a and the dielectric layer 3 of the second area 4b during the deposition of the dielectric layer 3.

[0136] In other examples, step S2 sequentially forms a first semiconductor layer 1 and a sacrificial layer on the first surface, including: S23 performing a deposition process on the first surface of the semiconductor substrate 4 to form the first semiconductor layer 1, and forming a doped silicon glass layer 5 on the side of the first semiconductor layer 1 away from the semiconductor substrate 4, and depositing an intermediate layer 6 on the side of the doped silicon glass layer 5 away from the semiconductor substrate 4, and the sacrificial layer includes the doped silicon glass layer 5 and the intermediate layer 6. In this step, the sacrificial layer includes the doped silicon glass layer 5 and the intermediate layer 6, the doped silicon glass layer 5 may include PSG or BSG, and the intermediate layer 6 may include SiOx. With this technical solution, the thickness of the sacrificial layer can also be ensured to be within a suitable range.

[0137] Considering that if the sacrificial layer is too thin, the gap formed between the dielectric layer 3 of the first region and the dielectric layer 3 of the second region 4b is narrow; if the sacrificial layer is too thick, raw materials are wasted and time-consuming. Therefore, in the present technical solution, the thickness of the sacrificial layer is set to 50nm-300nm, so as to form a gap of appropriate width between the dielectric layer 3 of the first region and the dielectric layer 3 of the second region 4b while avoiding waste of materials. Exemplarily, the thickness of the sacrificial layer is 50nm, 80nm, 100nm, 120nm, 150nm, 180nm, 200nm, 220nm, 250nm or 300nm.

[0138] As for the thickness of the first semiconductor layer 1, the thickness of the first semiconductor layer 1 is 150nm-200nm, which can be set according to the actual application scenario of the solar cell. Exemplarily, the thickness of the first semiconductor layer 1 is 150nm, 155nm, 160nm, 165nm, 170nm, 175nm, 180nm, 185nm, 190nm, 195nm or 200nm.

[0139] In the case where the solar cell is a bifacial cell, after forming the first electrode 2 on the surface of the first semiconductor layer 1, the method for manufacturing the solar cell further includes: forming a second semiconductor layer on the second surface, the second semiconductor layer and the first semiconductor layer 1 having opposite conductivity types, and forming a second electrode on the second semiconductor layer.

[0140] In the case where the solar cell is a back-contact cell, after forming the first electrode 2 on the surface of the first semiconductor layer 1, the method for manufacturing the solar cell further includes: forming a second semiconductor layer in at least a second area 4b of the first surface, the second semiconductor layer and the first semiconductor layer 1 having opposite conductivity types, and forming a second electrode on the second semiconductor layer.

[0141] The first electrode 2 and the second electrode can be made of silver, copper, aluminum, or alloys thereof. The first electrode 2 and the second electrode can be the same or different.

[0142] In addition, the present application also provides a photovoltaic assembly, which includes a plurality of solar cells provided in any of the above embodiments, or includes a plurality of solar cells formed by the method for manufacturing a solar cell provided in any of the above embodiments. Compared with the prior art, the beneficial effects of the photovoltaic assembly provided in the embodiment of the present application are the same as the beneficial effects of the above solar cell and the method for manufacturing a solar cell, and will not be described in detail here.

[0143] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0144] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, wherein the first surface includes a first region and a second region adjacently arranged along a first direction; a first semiconductor layer, wherein the first semiconductor layer covers the first region; a first electrode, the first electrode covering the first semiconductor layer; A dielectric layer covers the second region, and a first gap is formed between the dielectric layer and an edge of the first semiconductor layer along the first direction.

2. The solar cell according to claim 1, characterized in that The width of the first gap along the first direction is 1 μm-10 μm.

3. The solar cell according to claim 1, characterized in that Along the first direction, a second gap is formed between the dielectric layer and an edge of the first electrode.

4. The solar cell according to claim 3, characterized in that: Along the first direction, the width of the first gap is greater than the width of the second gap.

5. The solar cell according to claim 1, characterized in that: The first area is convex in a direction away from the first surface compared to the second area; The first region has an inclined side surface at a position close to the second region, and the first electrode extends from the top surface of the first semiconductor layer to cover at least a portion of the inclined side surface.

6. The solar cell according to claim 5, characterized in that: The first semiconductor layer extends to be close to the inclined side surface, and the first semiconductor layer is completely covered by the first electrode.

7. The solar cell according to claim 5, characterized in that: The first electrode comprises a first metal layer and a second metal layer stacked in sequence in a direction away from the first surface; and, along the thickness direction of the semiconductor substrate, the area of ​​the inclined side surface covered by the first metal layer is closer to the first semiconductor layer than the area of ​​the inclined side surface covered by the second metal layer; or, The first electrode includes a first metal layer, a second metal layer, and a third metal layer stacked in sequence along a direction away from the first surface; and along the thickness direction of the semiconductor substrate, the area of ​​the inclined side covered by the first metal layer, the area of ​​the inclined side covered by the second metal layer, and the area of ​​the inclined side covered by the third metal layer are successively away from the first semiconductor layer.

8. The solar cell according to claim 1, characterized in that The first electrode covers the first semiconductor layer and the first gap, and extends onto the dielectric layer.

9. The solar cell according to claim 8, characterized in that: The first electrode includes a first metal layer and a second metal layer stacked in sequence in a direction away from the first surface, and the first metal layer completely covers the top surface and side surfaces of the first semiconductor layer; the second metal layer contacts the semiconductor substrate at the first gap and extends onto the dielectric layer.

10. The solar cell according to claim 1, characterized in that: The first region is a first pyramid velvet surface, a pyramid base structure surface or a polished surface; and / or the second region is a second pyramid velvet surface, a pyramid base structure surface or a polished surface.

11. The solar cell according to claim 1, characterized in that: Along the first direction, the width of the first semiconductor layer is 1 μm-100 μm; and / or, along the first direction, the width of the first electrode is 1 μm-150 μm.

12. The solar cell according to claim 1, characterized in that The solar cell further comprises a second semiconductor layer, the conductivity type of the second semiconductor layer being opposite to that of the first semiconductor layer; The second semiconductor layer covers at least a portion of the second surface of the semiconductor substrate; or, the second semiconductor layer covers at least a portion of the second region.

13. The solar cell according to claim 12, characterized in that: The first semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell further includes a first interface layer located on a side of the first semiconductor layer close to the semiconductor substrate; The second semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell also includes a second interface layer located on a side of the second semiconductor layer close to the semiconductor substrate.

14. A method for manufacturing a solar cell, characterized in that: include: Providing a semiconductor layer substrate, the semiconductor substrate having a first surface and a second surface opposite to each other; the first surface includes first regions and second regions alternately distributed along a first direction; sequentially forming a first semiconductor layer and a sacrificial layer on the first surface; removing the first semiconductor layer and the sacrificial layer in the second region; Depositing a dielectric layer on the first surface, wherein a portion of the dielectric layer located in the first area and a portion of the dielectric layer located in the second area have a gap; removing the sacrificial layer and simultaneously removing the dielectric layer located in the first region, so that the first semiconductor layer located in the first region is exposed; A first electrode is formed on the first semiconductor layer.

15. The method for manufacturing a solar cell according to claim 14, characterized in that: Sequentially forming a first semiconductor layer and a sacrificial layer on the first surface includes: Performing a deposition process on the first surface of the semiconductor substrate to form the first semiconductor layer, and forming a doped silicon glass layer on a side of the first semiconductor layer away from the semiconductor substrate, wherein the doped silicon glass layer is the sacrificial layer; or, After forming the first semiconductor layer by a deposition process on the first surface of the semiconductor substrate, depositing the sacrificial layer on a side of the first semiconductor layer away from the semiconductor substrate; or, A deposition process is performed on the first surface of the semiconductor substrate to form the first semiconductor layer, and a doped silicon glass layer is formed on the side of the first semiconductor layer facing away from the semiconductor substrate, and an intermediate layer is deposited on the side of the doped silicon glass layer facing away from the semiconductor substrate, and the sacrificial layer includes the doped silicon glass layer and the intermediate layer.

16. The method for manufacturing a solar cell according to claim 14 or 15, characterized in that: The material of the sacrificial layer includes PSG, BSG or SiOx; and / or the thickness of the sacrificial layer is 50nm-300nm; and / or the thickness of the first semiconductor layer is 150nm-200nm.

17. The method for manufacturing a solar cell according to claim 14, characterized in that: Removing the first semiconductor layer and the sacrificial layer in the second region includes: forming a mask layer on a side of the sacrificial layer facing away from the semiconductor substrate; The first semiconductor layer and the sacrificial layer in the second region are selectively etched away through the mask layer.

18. The method for manufacturing a solar cell according to claim 17, characterized in that: After removing the first semiconductor layer and the sacrificial layer in the second region by selectively etching the mask layer and before depositing a dielectric layer on the first surface, the method for manufacturing a solar cell further includes: Etching the second area of ​​the first surface so that the second area is concave toward the second surface and the second area is formed into a pyramid velvet surface or a polished surface; The sacrificial layer in the first region is partially removed by selective etching and the mask layer in the first region is retained, so that a gap exists between a portion of the mask layer and the first semiconductor layer.

19. The method for manufacturing a solar cell according to claim 18, characterized in that: Selectively etching away a portion of the sacrificial layer in the first region and retaining the mask layer in the first region, comprises: using an acid solution to side-etch the sacrificial layer, wherein the side-etching width of both sides of the sacrificial layer along the first direction is 6 μm-9 μm.

20. The method for manufacturing a solar cell according to claim 14, characterized in that: Forming a first electrode on a surface of the first semiconductor layer; comprising: The first electrode is formed to completely cover the first semiconductor layer; or, The first region has an inclined side surface at a position close to the second region, and a first metal layer and a second metal layer are sequentially formed on a side of the first electrode away from the semiconductor substrate, and the first metal layer completely covers the first semiconductor layer and extends to cover part of the inclined side surface, and the second metal layer completely covers the first metal layer and extends to cover part of the inclined side surface; or, The first region has an inclined side surface at a position close to the second region, and a first metal layer, a second metal layer and a third metal layer are sequentially formed on the side of the first electrode facing away from the semiconductor substrate; and along the thickness direction of the semiconductor substrate, the area of ​​the inclined side surface covered by the first metal layer, the area of ​​the inclined side surface covered by the second metal layer, and the area of ​​the inclined side surface covered by the third metal layer are successively away from the first semiconductor layer.

21. The method for manufacturing a solar cell according to claim 14, characterized in that: After forming a first electrode on the surface of the first semiconductor layer, the method for manufacturing a solar cell further includes: forming a second semiconductor layer on the second surface, the conductivity type of the second semiconductor layer being opposite to that of the first semiconductor layer, and forming a second electrode on the second semiconductor layer; or, A second semiconductor layer is formed at least in a second region of the first surface, the second semiconductor layer and the first semiconductor layer have opposite conductivity types, and a second electrode is formed on the second semiconductor layer.

22. A photovoltaic module, characterized in that: The method comprises a plurality of solar cells according to any one of claims 1 to 13, or comprises a plurality of solar cells formed by the manufacturing method according to any one of claims 14 to 21.

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