High-precision timer driven by dual clocks and timing method thereof

Abstract

The invention relates to the field of timers, and discloses a high-precision timer driven by dual clocks and a timing method thereof, comprising: a slow clock test module tests the frequency ratio of a fast clock to a slow clock; an error statistics module accumulates the decimal part of the frequency ratio when the system switches to a sleep state, and when the accumulated value is greater than or equal to 1, outputs an error correction mark to a timing module; when the system is in a working state, the timing module counts by 1 at the rising edge of each fast clock; when the system is in a sleep state, if the timing module does not receive the error correction mark, the timing module increases the integer part of the frequency ratio of the fast and slow clocks at each rising edge of the slow clock; if the timing module receives the error correction mark, the timing module increases the integer part of the frequency ratio of the fast and slow clocks at the current rising edge of the slow clock by 1, thereby minimizing the error, greatly reducing the influence of the error on the timing accuracy, and improving the timing accuracy of the timer.

Description

Technical Field

[0001] The invention relates to the field of timers, and in particular to a high-precision timer driven by dual clocks and a timing method thereof. Background Art

[0002] Microcontroller Unit (MCU) generally integrates one or more timers to support various timing functions, such as sleep timer wake-up, timer interrupt, etc. The driving clock of the timer generally uses a clock, and its frequency can be set according to the needs. In this case, it is a homologous clock. In some scenarios, the timer needs to use two clocks, such as the system sleep timer. The clock usage is as follows: (1) When the system is in working state, the system fast clock is turned on, and the sleep timer uses the system fast clock, such as a frequency of 32MHz; (2) When the system is in sleep state, the system fast clock is turned off, and the sleep timer switches to use the slow clock, such as a frequency of 32KHz.

[0003] If the timer uses clocks from different sources, for example, a 32MHz fast clock is used in the system working state, and a 32KHz clock output by the on-chip low-frequency clock generation circuit is used in the sleep state, the clocks from different sources may cause the timer to count inaccurately, resulting in the system being unable to wake up on time. Summary of the invention

[0004] In view of this, the present invention provides a high-precision timer driven by dual clocks and a timing method thereof to solve the problem that clocks from different sources may cause inaccurate timer counting.

[0005] In the first aspect, the present invention provides a high-precision timer driven by dual clocks, including: a slow clock test module, an error statistics module, a clock switching module, and a timing module, wherein the first input terminal and the second input terminal of the slow clock test module respectively input a fast clock and a slow clock, and the first output terminal and the second output terminal of the slow clock test module are respectively connected to the input terminal of the error statistics module and the first input terminal of the timing module; the slow clock test module is used to test the frequency ratio of the fast clock and the slow clock within a preset time before the fast clock switches to the slow clock, and the frequency ratio includes an integer part and a decimal part; the output terminal of the error statistics module is connected to the second input terminal of the timing module; the error statistics module is used to accumulate the decimal part of the frequency ratio when the system switches to a sleep state, and when the accumulated value is greater than or equal to 1, output the error correction mark to the timing module; the first input end and the second input end of the clock switching module are respectively input with the fast clock and the slow clock, and the output end of the clock switching module is connected with the third input end of the timing module; the clock switching module is used to output the fast clock to the timing module when the system is in working state, and output the slow clock to the timing module when the system is in sleeping state; when the system is in working state, the timing module counts up by 1 at the rising edge of each fast clock; when the system is in sleeping state, if the timing module does not receive the error correction mark, the timing module increases the integer part of the frequency ratio at each rising edge of the slow clock; if the timing module receives the error correction mark, the timing module increases the integer part of the frequency ratio at the current rising edge of the slow clock by 1.

[0006] The present invention tests the frequency ratio of the fast clock to the slow clock before switching from the fast clock to the slow clock, wherein the decimal part of the frequency ratio is the error when the slow clock is counted; after switching to the slow clock, the error when the slow clock is counted is statistically accumulated, and when it reaches 1, the count value of the next slow clock count value is additionally increased by 1, thereby minimizing the error, greatly reducing the influence of the error on the accuracy, and improving the timing accuracy of the timer.

[0007] In an optional implementation, the preset time is:

[0008]

[0009] in, T is the preset time; Q is the bit width of the decimal part in binary format; 2^Q is the number of slow clock cycles within the preset time; T 1 is a slow clock cycle.

[0010] In an optional embodiment, the slow clock test module includes: a slow clock counter, a slow clock rising edge detection unit, and an accumulative counter, wherein the first input end of the slow clock counter inputs a slow clock, the second input end of the slow clock counter inputs a preset time, and the output end of the slow clock counter is connected to the first input end of the accumulative counter; the slow clock counter is used to start counting after the test starts, and when the count reaches 2^Q, a counting completion signal is sent to the accumulative counter; the first input end of the slow clock rising edge detection unit inputs a slow clock, the second input end of the slow clock rising edge detection unit inputs a fast clock, and the output end of the slow clock counter is connected to the first input end of the accumulative counter. The output end of the test unit is connected to the second input end of the accumulator; the slow clock rising edge detection unit is used to send a start counting signal to the accumulator when the rising edge of the first slow clock is detected after the test starts; the fast clock is input to the third input end of the accumulator, and the output end of the accumulator is connected to the input end of the error statistics module and the first input end of the timing module; when the accumulator receives the start counting signal, the accumulator adds 1 to each fast clock cycle; when the accumulator receives the count completion signal, the accumulator stops counting, and the ratio of the number of fast clock cycles to the number of slow clock cycles is used as the frequency ratio.

[0011] In an optional implementation, the error statistics module includes: an error accumulator, wherein an input end of the error accumulator is connected to a first output end of the slow clock test module, and an output end of the error accumulator is connected to a second input end of the timing module.

[0012] In an optional embodiment, the timing module includes: a first adder, a timer, and a counting switching module, wherein the second input end of the counting switching module is connected to the output end of the error statistics module, the first input end of the counting switching module is connected to the first output end of the slow clock test module, the third input end of the counting switching module inputs a clock selection signal, and the fourth input end of the counting switching module inputs a value 1; the first input end of the first adder is connected to the output end of the register, the second input end of the first adder is connected to the output end of the counting switching module, and the output end of the first adder is connected to the first input end of the register; the second input end of the register is connected to the output end of the clock switching module; when the system is in a sleep state, when the counting switching module does not receive an error correction flag, the clock selection signal controls the counting switching module to output the integer part of the frequency ratio to the first adder; when the system is in a sleep state, when the counting switching module receives an error correction flag, the clock selection signal controls the counting switching module to add 1 to the integer part of the frequency ratio and output it to the first adder.

[0013] In an optional embodiment, the counting switching module includes: a second adder and a multiplexer, wherein the first input end of the second adder is connected to the output end of the error statistics module, the second input end of the second adder is connected to the first output end of the slow clock test module, and the output end of the second adder is connected to the second input end of the multiplexer; the first input end of the multiplexer inputs a value of 1, the third input end of the multiplexer inputs a clock selection signal, and the output end of the multiplexer is connected to the second input end of the first adder; when the second adder does not receive an error correction flag, the second adder outputs an integer part of the frequency ratio to the multiplexer; when the second adder receives an error correction flag, the second adder adds 1 to the integer part of the frequency ratio and outputs it to the multiplexer; when the system is in a working state, the clock selection signal controls the multiplexer to output a value of 1 to the first adder; when the system is in a sleep state, the clock selection signal controls the multiplexer to output the output value of the second adder to the first adder.

[0014] In an optional embodiment, the dual-clock driven high-precision timer also includes: a configuration module, wherein the configuration module is connected to the slow clock test module and the timing module, and the configuration module is used to configure parameters of the slow clock test module and the timing module, and the parameters include preset time and timing time.

[0015] In a second aspect, the present invention provides a timing method for a high-precision timer driven by a dual clock. The high-precision timer driven by a dual clock is based on the first aspect and any optional implementation manner thereof, and the timing method comprises: testing the frequency ratio of a fast clock to a slow clock within a preset time, the frequency ratio comprising an integer part and a decimal part; when the system is in a working state, the timing module counts by 1 at each rising edge of the fast clock; when the system is in a sleep state, the decimal part of the frequency ratio is accumulated, and when the accumulated value is greater than or equal to 1, at the current rising edge of the slow clock, the timing increases the integer part of the frequency ratio by 1; when the accumulated value is not greater than 1, at the current rising edge of the slow clock, the timing increases the integer part of the frequency ratio.

[0016] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the timing method of the dual-clock driven high-precision timer of the second aspect mentioned above by executing the computer instructions.

[0017] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the timing method of a high-precision timer driven by a dual clock according to the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a composition diagram of a high-precision timer driven by dual clocks according to an embodiment of the present invention;

[0020] Figure 2 It is a schematic diagram of the internal structure of the system;

[0021] Figure 3 is a composition diagram of another high-precision timer driven by dual clocks according to an embodiment of the present invention;

[0022] Figure 4 is a composition diagram of another high-precision timer driven by dual clocks according to an embodiment of the present invention;

[0023] Figure 5 is a composition diagram of another high-precision timer driven by dual clocks according to an embodiment of the present invention;

[0024] Figure 6 is a clock switching error compensation waveform diagram according to an embodiment of the present invention;

[0025] Figure 7 is a composition diagram of another high-precision timer driven by dual clocks according to an embodiment of the present invention;

[0026] Figure 8 is a flow chart of a timing method of a high-precision timer driven by dual clocks according to an embodiment of the present invention;

[0027] Fig. 9 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0029] In this embodiment, a high-precision timer driven by dual clocks is provided, such as Figure 1As shown, it includes: a slow clock test module, an error statistics module, a clock switching module, and a timing module.

[0030] like Figure 1 As shown, the first input terminal and the second input terminal of the slow clock test module are respectively input with the fast clock and the slow clock, and the first output terminal and the second output terminal of the slow clock test module are respectively connected with the input terminal of the error statistics module and the first input terminal of the timing module; the slow clock test module is used to test the frequency ratio of the fast clock and the slow clock within a preset time before the fast clock switches to the slow clock, and the frequency ratio includes an integer part and a decimal part.

[0031] like Figure 1 As shown, the output end of the error statistics module is connected to the second input end of the timing module; the error statistics module is used to accumulate the decimal part of the frequency ratio when the system switches to the sleep state, and when the accumulated value is greater than or equal to 1, output the error correction flag to the timing module.

[0032] like Figure 1 As shown, the first input terminal and the second input terminal of the clock switching module input the fast clock and the slow clock respectively, and the output terminal of the clock switching module is connected to the third input terminal of the timing module; the clock switching module is used to output the fast clock to the timing module when the system is in the working state, and output the slow clock to the timing module when the system is in the sleeping state. The system can be an MCU chip or a SoC chip.

[0033] Specifically, Figure 2 As shown in the figure, MCU chips and SoC chips generally integrate a low-frequency clock generation circuit (RC OSC), a CPU module (i.e., COU Sub-System), and a sleep timer (SleepTimer). The typical frequency of the low-frequency clock generation circuit is 32KHz, which is mainly used for the working clock of the MCU system in the sleep state, such as the working clock of the Timer timing clock, the system wake-up (WakeUp), and other always-on modules (Always-On). Its frequency is affected by many factors such as chip manufacturing process, working environment temperature, and power supply voltage. The frequency deviation caused by the manufacturing process is generally calibrated and adjusted (Trim) before the chip is produced. In the application link, when the working environment temperature and power supply voltage of the MCU change, it will also affect the frequency of the RC OSC, increasing or decreasing, and the deviation will be large, up to more than 10%. This can only be calibrated or corrected in the application link. When the working environment and power supply voltage continue to change, such as when the power supply is powered by a battery, as the battery power continues to be consumed, the voltage will become lower and lower, and the frequency deviation will become larger and larger. The price of low-frequency crystal oscillator of 32KHz outside the chip is very high, so the general solution is to use on-chip RC OSC to output 32KHz.

[0034] like Figure 2 As shown, there is at least one high-speed precision clock inside the MCU chip. This clock is input from the external crystal oscillator (i.e. Crystal Osc) into the chip, and is used directly or through the on-chip PLL to generate a higher frequency precision clock. This type of clock has a very high precision, generally below 10ppm. This type of clock can be regarded as a precision clock, which is mainly used as the working clock when the MCU chip is in working state. For MCU chips, the frequency of high-speed precision clock is generally between 1MHz and 100MHz. The disadvantage is that an external crystal oscillator is required, which is costly; the high operating frequency leads to high power consumption.

[0035] Based on this, in order to ensure that the timer can still accurately time when the system is in sleep mode, in this embodiment, when the system is in sleep mode, the timing module uses the fast clock to time, for example: in a slow clock cycle, the number of fast clock cycles is calculated, that is, at each rising edge of the slow clock, the timing module accumulates M, where M is the number of fast clock cycles included in a slow clock cycle, and when the count reaches a preset threshold, the system is awakened. At the same time, when the system is in working mode, the timing module can count by 1 at each rising edge of the fast clock.

[0036] Therefore, in order for the timing module to accumulate M at each rising edge of the slow clock when the system is in sleep mode, the slow clock test module tests the frequency ratio of the fast clock to the slow clock within a preset time before the system switches to sleep mode (or sets the test time as needed). Under ideal conditions, the frequency ratio = M, where M is an integer.

[0037] However, if the timer uses the same source clock, the system timing accuracy is generally not affected by the change of clock frequency. For example, if a 32MHz clock is used for timing, or a clock divided by 32MHz, such as 32KHz, then:

[0038] (1) When the system is in operation, it is only timing at a frequency of 32 MHz, with each clock incremented by 1.

[0039] (2) When the system enters sleep mode, the frequency of this clock is set to 32KHz (32MHz divided by 1000 times), which is one thousandth of the frequency in the working state. At this time, each clock timing is added by 1000; this is equal to the timing length of 1000 clock cycles when the frequency is 32MHz.

[0040] (3) When the system returns to working state, the clock frequency is switched back to 32 MHz, and each clock timer is incremented by 1.

[0041] Because the same clock is used, only the frequency changes, and the increment of each clock count value is adjusted accordingly. In this way, the count value of the timer is accurate and there is no error in the entire work->sleep->work process.

[0042] However, if the timer's driving clock uses different clocks in different system states, the timer timing will have errors. For example, different source clocks can be measured to determine the basic frequency ratio relationship, but there are errors. For example, the frequency output by the low-frequency clock generation circuit may be within the range of 32KHz±100Hz, and the ratio of the frequency to the fast clock may not be an integer. For example: the fast clock frequency is 10.3 times the slow clock frequency. The original timing method should be: under the fast clock, the timer +1, under the slow clock, the timer +10. Therefore, when the slow clock drives the timer, the counter must accumulate 10 or 11 for each slow clock cycle, and there will be an error, 0.3 less or 0.7 more fast clock cycles. The more slow clock count cycles, the greater the error accumulation, resulting in a greater final timer timing deviation. For example, the slow clock counts 10,000 cycles, and the accumulated fast clock count cycles are 100,000 or 110,000, which is 3,000 less or 7,000 more than the cumulative count.

[0043] Because the frequency relationship between clocks cannot be determined accurately, there will be non-integer errors. When the errors accumulate to a certain amount, the counting accuracy of the timer will be significantly reduced, resulting in inaccurate timer timing. For application scenarios with strict time accuracy requirements, functional errors may occur due to the timing error exceeding the acceptable range caused by different clock sources, making the system unusable or causing serious problems.

[0044] Based on this, the frequency of the slow clock of the MCU chip is easily affected by the working environment temperature and power supply voltage of the MCU, resulting in deviations, which leads to inaccurate timing. Therefore, before the fast clock switches to the slow clock, that is, before the MCU chip switches from the working state to the sleep state, it is necessary to test the frequency deviation of the slow clock, that is, the slow clock test module tests the frequency ratio of the fast clock to the slow clock within a preset time, the frequency ratio = MN, M is the integer part of the frequency ratio, and N is the decimal part of the frequency ratio.

[0045] For the error correction part, when the system enters the sleep state, the error statistics module starts to accumulate, that is, N is accumulated in each slow clock cycle. When the error accumulation value is greater than or equal to 1, the error statistics module outputs an error correction flag. At this time, the timing module will no longer accumulate M at the rising edge of the current slow clock, but accumulate M+1, thereby achieving error correction to the greatest extent, greatly reducing the impact of the error on the accuracy, and improving the timing accuracy of the timer.

[0046] For example, if the fast-slow clock frequency ratio is 10.3, the count value and error statistics for each slow clock cycle are as follows:

[0047] In the first cycle, the count value increases by 10, the accumulated value of the counter is 10, and the accumulated error is 0.3.

[0048] In the second cycle, the count value increases by 10, the accumulated value of the counter is 20, and the accumulated error is 0.6.

[0049] In the third cycle, the count value increases by 10, the accumulated value of the counter is 30, and the accumulated error is 0.9.

[0050] In the fourth cycle, the count value increases by 10, the cumulative value of the counter is 40, and the cumulative error is 1.2. In this cycle, the count value increases by 1 additionally, that is, a total increase of 11, then the cumulative value of the counter is 41, and the cumulative error becomes 0.2.

[0051] In the fifth cycle, the count value increases by 10, the accumulated value of the counter is 51, and the accumulated error is 0.5.

[0052] By analogy, the counting error of the timer is finally limited to a range less than 1, that is, the timing duration error is ultimately smaller than the cycle of a fast clock, thereby greatly improving the timing accuracy of the timer.

[0053] In some optional implementations, the preset time is:

[0054]

[0055] in, T is the preset time; Q is the bit width of the decimal part in binary format; 2^Q is the number of slow clock cycles within the preset time; T 1 is a slow clock cycle.

[0056] Specifically, the slow clock test module is actually a fast and slow clock frequency ratio accumulator, and the frequency ratio bit width is set as follows:

[0057] (1) According to the fast-slow clock frequency ratio (ie, MN), set the bit width of M to P. For example, if the multiple is about 1000 times, the bit width of M can be set to 10 bits, that is, P=10, then M is approximately 2^10=1024. If the error is too large, the bit width can be set to 11 bits, and so on.

[0058] (2) Set the bit width of N, and set the number of slow test cycles to 2^Q according to the bit width Q of N. For example, if Q is 8, the number of slow test cycles is 2^8=256 cycles, that is, the preset time is 256 slow clock cycles.

[0059] By directly utilizing the characteristics of binary representation, the preset time is set to 2^Q slow clock cycles. After measuring the number of fast clock cycles, the ratio of the number of fast clock cycles to the number of slow clock cycles is used as the frequency ratio, thereby not using a general division module, improving timing and saving area.

[0060] In some optional embodiments, such as Figure 3 As shown, the slow clock test module includes: a slow clock counter, a slow clock rising edge detection unit, and an accumulation counter.

[0061] like Figure 3 As shown, the first input end of the slow clock counter inputs the slow clock, the second input end of the slow clock counter inputs the preset time, and the output end of the slow clock counter is connected to the first input end of the accumulative counter; the slow clock counter is used to start counting after the test starts, and when the count reaches 2^Q, a counting completion signal is sent to the accumulative counter.

[0062] like Figure 3 As shown, the slow clock is input into the first input end of the slow clock rising edge detection unit, the fast clock is input into the second input end of the slow clock rising edge detection unit, and the output end of the slow clock rising edge detection unit is connected to the second input end of the cumulative counter; the slow clock rising edge detection unit is used to send a start counting signal to the cumulative counter when the first rising edge of the slow clock is detected after the test starts.

[0063] like Figure 3 As shown, the third input terminal of the accumulative counter inputs the fast clock, and the output terminal of the accumulative counter is connected to the input terminal of the error statistics module and the first input terminal of the timing module.

[0064] Specifically, the whole process is:

[0065] (1) After the test starts, the slow clock counter starts counting. When the slow clock rising edge detection unit detects the rising edge of the first slow clock, it sends a start counting signal to the accumulative counter. The accumulative counter increases by 1 in each fast clock cycle.

[0066] (2) When the slow clock counter reaches 2^Q, a counting completion signal is sent to the accumulator counter, and the accumulator counter stops counting. The ratio of the number of fast clock cycles to the number of slow clock cycles is used as the frequency ratio, where the integer part of the frequency ratio, i.e. the high part, is output to the timing module, and the decimal part, i.e. the low part, is output to the error statistics module.

[0067] Optionally, set an accumulative counter with a sufficiently large bit width, and specify 2^Q as the number of slow clock test cycles, that is, the preset time. After the test is completed, the low Q bit is the decimal part N, and the other high bits are the integer part M. The more test cycles there are, the larger Q is, and the finer the error scale is, which is 1 / 2^Q, set according to system requirements.

[0068] In some optional implementations, the error statistics module includes: an error accumulator, wherein an input end of the error accumulator is connected to a first output end of the slow clock test module, and an output end of the error accumulator is connected to a second input end of the timing module.

[0069] Specifically, when the system switches to the sleep state, the error accumulator accumulates the fractional part of the frequency ratio, and when the accumulated value is greater than or equal to 1, the error accumulator outputs an error correction flag to the timing module.

[0070] Specifically, the error accumulator has the following functions:

[0071] (1) When the fast clock switches to the slow clock, that is, when the system enters the sleep state from the working state, the error accumulator is reset to zero. (2) When the slow clock is used, that is, when the system is in the sleep state, the error accumulator accumulates normally. (3) When the slow clock switches to the fast clock, that is, when the system enters the working state from the sleep state, the error accumulator is suspended. (4) When the fast clock is used, that is, when the system is in the working state, the error accumulator is suspended.

[0072] In some optional embodiments, such as Figure 4 As shown, the timing module includes: a first adder, a register, and a counting switching module.

[0073] like Figure 4 As shown, the second input end of the counting switching module is connected to the output end of the error statistics module, the first input end of the counting switching module is connected to the first output end of the slow clock test module, the third input end of the counting switching module inputs the clock selection signal, and the fourth input end of the counting switching module inputs the value 1.

[0074] like Figure 4 As shown, the first input end of the first adder is connected to the output end of the register, the second input end of the first adder is connected to the output end of the counting switching module, and the output end of the first adder is connected to the first input end of the register.

[0075] like Figure 4 As shown, the second input end of the timer is connected to the output end of the clock switching module; when the system is in working state, the clock switching module outputs a fast clock, and the register outputs the output value of the first adder to the first adder again at the rising edge of each fast clock; when the system is in sleep state, the clock switching module outputs a slow clock, and the register outputs the output value of the first adder to the first adder again at the rising edge of the slow clock.

[0076] Specifically, the entire timing process of the timing module is:

[0077] (1) When the system is in working state, the clock selection signal controls the counting switching module to output the value 1 to the first adder. At the rising edge of each fast clock, the register outputs the count value of the previous cycle to the first adder again. The first adder adds 1 to the output value of the register and outputs it to the register.

[0078] (2) When the system is in sleep mode, if the counting switching module does not receive the error correction flag, the clock selection signal controls the counting switching module to output the integer part of the frequency ratio to the first adder. At the rising edge of the slow clock, the register outputs the count value of the previous cycle to the first adder again. The first adder adds the integer part to the output value of the register and outputs it to the register.

[0079] (3) When the system is in sleep mode, when the counting switching module receives the error correction flag, the clock selection signal controls the counting switching module to add 1 to the integer part of the frequency ratio and output it to the first adder. At the rising edge of the slow clock, the register outputs the count value of the previous cycle to the first adder again. The first adder adds the integer part to the output value of the register and outputs it to the register.

[0080] In some optional embodiments, such as Figure 5 As shown, the counting switching module includes: a second adder and a multiplexer.

[0081] like Figure 5 As shown, the first input end of the second adder is connected to the output end of the error statistics module, the second input end of the second adder is connected to the first output end of the slow clock test module, and the output end of the second adder is connected to the second input end of the multiplexer.

[0082] like Figure 5 As shown, the first input terminal of the multiplexer inputs a value of 1, the third input terminal of the multiplexer inputs a clock selection signal, and the output terminal of the multiplexer is connected to the second input terminal of the first adder.

[0083] like Figure 5 As shown, when the second adder does not receive the error correction flag, the second adder outputs the integer part of the frequency ratio to the multiplexer; when the second adder receives the error correction flag, the second adder adds 1 to the integer part of the frequency ratio and outputs it to the multiplexer.

[0084] Specifically, the switching process in the counting switching module is as follows:

[0085] (1) When the system is in working state, the error accumulator is paused, the second adder does not output a value to the multiplexer, the clock selection signal controls the multiplexer to select the output value 1, and the first adder accumulates 1.

[0086] (2) When the system is in sleep mode, the error accumulator starts to accumulate the decimal part, that is, in one slow clock cycle, the error accumulator accumulates the value of a decimal part. When the accumulated value of the error accumulator is greater than or equal to 1, the error accumulator outputs an error correction flag, which is actually a value of 1. The second adder adds 1 to the integer part and outputs it to the first adder. The clock selection signal controls the multiplexer to output the value output by the second adder to the first adder. The first adder accumulates M+1.

[0087] (3) When the system is in sleep mode, the error accumulator starts to accumulate the decimal part, that is, in one slow clock cycle, the error accumulator accumulates the value of the decimal part. When the accumulated value of the error accumulator is less than 1, the error accumulator does not output the error correction flag, and the second adder outputs the integer part to the first adder. The clock selection signal controls the multiplexer to output the value output by the second adder to the first adder, and the first adder accumulates M.

[0088] Based on the above method, the clock switching error compensation waveform of this embodiment is as follows: Figure 6 As shown, Figure 6 The waveform in the middle is, from top to bottom, the fast clock, the slow clock, the clock selection signal, the driving clock of the timer, the error correction flag, and the timer. Figure 6 The timing process under multiple fast clocks is recorded in Figure 6 In the embodiment, when the error correction flag falls, the first adder accumulates M+1.

[0089] In some optional embodiments, such as Figure 7 As shown, the high-precision timer driven by dual clocks also includes: a configuration module, wherein the configuration module is connected to the slow clock test module and the timing module, and the configuration module is used to configure the parameters of the slow clock test module and the timing module, and the parameters include preset time and timing time.

[0090] In this embodiment, a timing method of a high-precision timer driven by a dual clock is provided. The high-precision timer driven by a dual clock is based on the above embodiment and any optional implementation manner thereof. Figure 8 As shown, the timing methods include:

[0091] Step S1: testing the frequency ratio of the fast clock to the slow clock within a preset time, where the frequency ratio includes an integer part and a decimal part;

[0092] Step S2: When the system is in working state, the timing module counts by 1 from the rising edge to the falling edge of each fast clock;

[0093] Step S3: When the system is in sleep mode, the decimal part of the frequency ratio is accumulated. When the accumulated value is greater than or equal to 1, at the rising edge of the current slow clock, the timing is increased by 1 based on the integer part; when the accumulated value is not greater than 1, at the rising edge of the current slow clock, the timing is increased by the integer part.

[0094] An embodiment of the present invention further provides a computer device having the above-mentioned high-precision timer driven by dual clocks.

[0095] See also Fig. 9 , Fig. 9 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig. 9 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig. 9 A processor 10 is taken as an example.

[0096] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0097] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0098] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the use of a computer device based on the presentation of a small program landing page, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0099] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0100] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0101] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0102] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A high-precision timer driven by dual clocks, characterized in that: include: Slow clock test module, error statistics module, clock switching module, timing module, among which, The first input terminal and the second input terminal of the slow clock test module are respectively input with the fast clock and the slow clock, and the first output terminal and the second output terminal of the slow clock test module are respectively connected with the input terminal of the error statistics module and the first input terminal of the timing module; the slow clock test module is used to test the frequency ratio of the fast clock and the slow clock within a preset time before the fast clock switches to the slow clock, and the frequency ratio includes an integer part and a decimal part; The output end of the error statistics module is connected to the second input end of the timing module; the error statistics module is used to accumulate the decimal part of the frequency ratio when the system switches to the sleep state, and when the accumulated value is greater than or equal to 1, output an error correction flag to the timing module; The first input terminal and the second input terminal of the clock switching module are respectively input with a fast clock and a slow clock, and the output terminal of the clock switching module is connected with the third input terminal of the timing module; the clock switching module is used to output a fast clock to the timing module when the system is in a working state, and output a slow clock to the timing module when the system is in a sleeping state; When the system is in working state, the timing module counts up by 1 at the rising edge of each fast clock; When the system is in sleep mode, if the timing module does not receive the error correction flag, the timing module increases the integer part of the frequency ratio at each rising edge of the slow clock; if the timing module receives the error correction flag, the timing module increases the integer part of the frequency ratio by 1 at the current rising edge of the slow clock.

2. The high-precision timer driven by dual clocks according to claim 1, characterized in that: The preset time is: in, T is the preset time; Q is the bit width of the decimal part in binary format; 2^Q is the number of slow clock cycles within a preset time; T 1 is a slow clock cycle.

3. The high-precision timer driven by dual clocks according to claim 1, characterized in that: The slow clock test module includes: a slow clock counter, a slow clock rising edge detection unit, and an accumulative counter, wherein: The slow clock is input into the first input end of the slow clock counter, the preset time is input into the second input end of the slow clock counter, and the output end of the slow clock counter is connected to the first input end of the accumulative counter; the slow clock counter is used to start counting after the test starts, and when the count reaches 2^Q, a counting completion signal is sent to the accumulative counter; The slow clock is input into the first input end of the slow clock rising edge detection unit, the fast clock is input into the second input end of the slow clock rising edge detection unit, and the output end of the slow clock rising edge detection unit is connected to the second input end of the accumulative counter; the slow clock rising edge detection unit is used to send a start counting signal to the accumulative counter when the first rising edge of the slow clock is detected after the test starts; The fast clock is input into the third input terminal of the accumulative counter, and the output terminal of the accumulative counter is connected to the input terminal of the error statistics module and the first input terminal of the timing module; When the accumulative counter receives the start counting signal, the accumulative counter increases by 1 in each fast clock cycle; When the accumulative counter receives the counting completion signal, the accumulative counter stops counting, and uses the ratio of the number of fast clock cycles to the number of slow clock cycles as the frequency ratio.

4. The high-precision timer driven by dual clocks according to claim 1, characterized in that: The error statistics module includes: an error accumulator, wherein: The input end of the error accumulator is connected to the first output end of the slow clock test module, and the output end of the error accumulator is connected to the second input end of the timing module.

5. The high-precision timer driven by dual clocks according to claim 1, characterized in that: The timing module includes: a first adder, a register, and a counting switching module, wherein: The second input end of the counting switching module is connected to the output end of the error statistics module, the first input end of the counting switching module is connected to the first output end of the slow clock test module, the third input end of the counting switching module inputs a clock selection signal, and the fourth input end of the counting switching module inputs a value 1; The first input end of the first adder is connected to the output end of the register, the second input end of the first adder is connected to the output end of the counting switching module, and the output end of the first adder is connected to the first input end of the register; A second input terminal of the register and an output terminal of the clock switching module; When the system is in a sleep state, when the counting switching module does not receive the error correction flag, the clock selection signal controls the counting switching module to output the integer part of the frequency ratio to the first adder; When the system is in a sleep state, when the counting switching module receives the error correction flag, the clock selection signal controls the counting switching module to add 1 to the integer part of the frequency ratio and output the result to the first adder.

6. The high-precision timer driven by dual clocks according to claim 5, characterized in that: The counting switching module includes: a second adder and a multiplexer, wherein: The first input end of the second adder is connected to the output end of the error statistics module, the second input end of the second adder is connected to the first output end of the slow clock test module, and the output end of the second adder is connected to the second input end of the multiplexer; The first input terminal of the multiplexer inputs a value of 1, the third input terminal of the multiplexer inputs the clock selection signal, and the output terminal of the multiplexer is connected to the second input terminal of the first adder; When the second adder does not receive the error correction flag, the second adder outputs the integer part of the frequency ratio to the multiplexer; when the second adder receives the error correction flag, the second adder adds 1 to the integer part of the frequency ratio and outputs it to the multiplexer; When the system is in working state, the clock selection signal controls the multiplexer to output the value 1 to the first adder; when the system is in sleeping state, the clock selection signal controls the multiplexer to output the output value of the second adder to the first adder.

7. The high-precision timer driven by dual clocks according to claim 1, characterized in that: Also includes: Configuration module, where The configuration module is connected to the slow clock test module and the timing module, and the configuration module is used to configure parameters of the slow clock test module and the timing module, and the parameters include the preset time and the timing time.

8. A timing method for a high-precision timer driven by dual clocks, characterized in that: Based on the high-precision timer driven by dual clocks according to any one of claims 1 to 7, the timing method comprises: Testing a frequency ratio of a fast clock to a slow clock within a preset time, wherein the frequency ratio includes an integer part and a decimal part; When the system is in working state, the timing module counts up by 1 at the rising edge of each fast clock; When the system is in sleep mode, the decimal part of the frequency ratio is accumulated. When the accumulated value is greater than or equal to 1, at the rising edge of the current slow clock, the integer part of the frequency ratio is increased by 1; when the accumulated value is not greater than 1, at the rising edge of the current slow clock, the integer part of the frequency ratio is increased by 1.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the timing method of the dual-clock driven high-precision timer as described in claim 8 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the timing method of a high-precision timer driven by a dual clock as claimed in claim 8.

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