Digital PUF circuit based on FPGA and use method thereof

Abstract

The invention belongs to the technical field of hardware and information security, and particularly relates to a digital PUF circuit based on an FPGA and a use method of the digital PUF circuit. In the PUF circuit, entropy source extraction and PUF response generation are separately processed, and the resistance value of a memristor in a high resistance state is collected through a memristor resistance value collection circuit; the resistance value distribution of each memristor in a high-resistance state has randomness, so that the high-resistance-state resistance value of the memristor can be used as an entropy source of the PUF circuit; a memristor-based entropy source is subjected to digital processing and is applied to a digital PUF circuit, resistance values of different memristors in a high-resistance state are randomly selected through digital chaotic signals, and finally PUF response is output by comparing the resistance values of the two memristors selected randomly in the high-resistance state. Compared with a traditional analog PUF circuit which is easily influenced by factors such as voltage fluctuation and device parameter drift, the digital PUF circuit based on the FPGA designed by the invention is higher in reliability and is not easily influenced by the factors such as the voltage fluctuation.

Description

Technical Field

[0001] The present invention belongs to the technical field of hardware and information security, and in particular relates to a digital PUF circuit based on FPGA and a use method thereof. Background Art

[0002] With the rapid development of the Internet of Things and communication technology, IoT devices have been widely used in smart homes, smart warehousing, smart cities and other fields, bringing great convenience to people's lives. However, as a large number of IoT devices are put on the market, the hardware security issues of the devices are becoming increasingly prominent. At present, the hardware security protection of devices mainly relies on traditional cryptographic methods, but the key storage of traditional encryption algorithms is difficult, and the hardware overhead is large, which makes it difficult to meet the requirements of high security and low complexity. Therefore, developing a new method to generate a unique identifier for hardware devices has become a research hotspot for technicians.

[0003] Since the concept of Physically Unclonable Function (PUF) was first proposed in 2002, PUF has attracted widespread attention in the field of hardware security as a new hardware security protection solution. The concept of PUF was proposed by researchers inspired by human fingerprints. Each person's fingerprint is unique, so it can be used as an individual's unique identifier. Similarly, PUF forms the "fingerprint" of hardware devices by extracting the inevitable process differences in the manufacturing process of hardware devices. Since this process difference is random and uncontrollable, PUF is unique and cannot be cloned, and can be used as a unique identifier for hardware devices. PUF has input and output signals. Its input signal is called a challenge, and its output signal is called a response. Applying a stimulus to PUF will produce an unpredictable response and each stimulus has its own unique corresponding response. This input and output relationship is called a challenge response pair (CRPs). PUF has the characteristics of uniformity, uniqueness, and randomness. Using these properties, PUF is mainly used in the field of hardware security, especially in security issues such as hardware device authentication and anti-cloning.

[0004] PUF can be divided into silicon PUF and non-silicon PUF according to the implementation technology. Non-silicon PUF usually requires additional more sophisticated external auxiliary circuits to complete the extraction of CRPs, with high production costs and difficult to use on a large scale. In contrast, silicon PUF is usually implemented based on CMOS technology and can be integrated with other digital circuits and analog circuits in the same chip without the need for additional auxiliary circuit design. This high degree of integration is particularly important for electronic devices because they need to integrate more functions in a limited space. Therefore, research on silicon PUF has become a hot topic at home and abroad, and designing a high-performance silicon PUF circuit has become the focus of researchers.

[0005] Jimson Mathew et al. (Mathew J, Chakraborty RS, Sahoo DP, et al. A novel memristor-based hardware security primitive [J]. ACM Transactions on Embedded Computing Systems (TECS), 2015, 14 (3): 1-20.) designed an arbitration PUF circuit based on memristors. The PUF uses the uneven distribution of the high-resistance resistance of the memristor as the entropy source, and the parasitic capacitance in the MOS tube and the memristor form an RC delay circuit, so that the time for the signal to pass through the two delay circuits is random, and finally the D flip-flop outputs the PUF response according to the order in which the signal arrives. Since the parasitic capacitance in the MOS tube is easily affected by environmental factors such as voltage fluctuations, the output of the PUF circuit generated by applying the same stimulus in different environments may also be different. Therefore, the reliability index of the PUF circuit is poor.

[0006] E.Camacho-Ruiz et al. (Camacho-Ruiz E, Castro-López R, Roca E, et al. A novel physical unclonable function using RTN [C] / / 2022 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2022: 160-164) designed a novel PUF circuit. The PUF circuit consists of N identical MOS tubes, a multiplexer, two maximum current fluctuation calculation circuits and a comparator. The PUF circuit uses the random fluctuation of the drain current of the MOS tube as the entropy source, and its working steps are as follows: First, two MOS tubes are selected from the N MOS tubes according to the applied excitation signal. Due to the slight difference in the parameters of the device, the fluctuation of the drain current of the MOS tube is random. The maximum deviation of the drain current of the two transistors within a given time interval is measured by the maximum current fluctuation calculation circuit. Finally, the response of the PUF is obtained by comparing the size of the two maximum deviation values. Due to the difference in the parameters of the MOS tube in different environments, the circuit is easily affected by the voltage fluctuation factor, and the reliability index of the circuit is poor.

[0007] The patented technology of "A Physical Unclonable Function Circuit and Its Operation Method" (CN113096709A) selects two memristor units in two adjacent columns of a row in a memristor array according to an externally applied excitation signal, applies a high-level signal and a low-level signal to the two memristor units respectively, and the remaining unselected memristor units are left suspended, so that the two memristor units form a series voltage divider circuit, and generate a response signal by comparing the voltage signal at the middle voltage divider point of the series circuit with the reference voltage. When the difference between the voltage at the middle voltage divider point of the series circuit and the reference voltage is small, the noise in the circuit will dominate and determine the response of the PUF circuit, making the circuit less reliable.

[0008] Therefore, the common problem of the above-mentioned public documents is that the designed PUF circuit is easily affected by voltage fluctuations and the circuit reliability is low. Therefore, a PUF circuit that is not easily affected by voltage fluctuations and has high reliability becomes the focus of research and protection of the present invention. Summary of the invention

[0009] In order to solve the above problems existing in the prior art, the present invention provides a digital PUF circuit based on FPGA and a method for using the same, aiming to solve the technical problems in the prior art that the PUF circuit is easily affected by voltage fluctuation factors and has low reliability.

[0010] To achieve the above object, the present invention provides the following technical solutions: a digital PUF circuit based on FPGA, the input signal of the circuit includes an excitation signal C[0…(N-1)], a clock signal and a reset signal, the output signal is R, and the circuit is pre-processed by a memristor resistance value acquisition circuit;

[0011] The memristor resistance value acquisition circuit comprises a memristor, an R1 resistor, an R2 resistor, a precision operational amplifier and an MCU. The voltage input terminal V C A negative DC voltage U is applied between GND C , wherein the M0 terminal of the memristor is connected to the voltage input terminal V C The M1 terminal of the memristor is connected to the R2 resistor and the F-terminal of the precision operational amplifier respectively, the R1 resistor is connected to GND, and the R1 resistor and the F-terminal of the precision operational amplifier are connected to the R2 resistor and the F-terminal of the precision operational amplifier respectively. + terminal connection, the precision operational amplifier F O The terminals are connected to the R2 resistor and the ADC pin of the MCU respectively;

[0012] The digital PUF circuit comprises a clock frequency division module, a digital chaos module, a storage module and a response generation module. The digital PUF circuit is connected to an external clock signal through a clock terminal CLK and an external reset signal through a reset terminal RST. The CLK0 terminal of the clock frequency division module is connected to the clock terminal CLK, the RST0 terminal of the clock frequency division module is connected to the reset terminal RST, and the CLK1 terminal of the clock frequency division module is connected to the CLK0 terminal of the storage module and the CLK0 terminal of the response generation module, respectively.

[0013] The CLK0 terminal of the digital chaos module is connected to the clock terminal CLK, the RST0 terminal of the digital chaos module is connected to the reset terminal RST, the X0[0...31] terminal of the digital chaos module is connected to the X1[0...31] terminal of the response generation module, and the Y0[0...31] terminal of the digital chaos module is connected to the Y1[0...31] terminal of the response generation module.

[0014] The RST0 terminal of the storage module is connected to the reset terminal RST, the D0[0...31] terminal of the storage module is connected to the D1[0...31] terminal of the response generation module,

[0015] The C0[0...(N-1)] terminal of the response generation module is connected to the excitation terminal C[0...(N-1)], the RST0 terminal of the response generation module is connected to the reset terminal RST, and the R0 terminal of the response generation module is connected to the response output terminal R,

[0016] Wherein, N represents the number of bits of the excitation, and N is a natural number greater than or equal to 1 and less than or equal to 32;

[0017] The resistance value of the memristor in the high-resistance state acquired by the memristor resistance acquisition circuit is stored in the storage module of the digital PUF circuit.

[0018] Among them, the precision operational amplifier is a general-purpose precision operational amplifier, or a low-power precision operational amplifier; the FPGA chip has a floating-point operation IP core.

[0019] The present invention also discloses a method for using a digital PUF circuit based on FPGA, and the method comprises the following steps:

[0020] Step 1: Extract the resistance value of the memristor:

[0021] At the voltage input terminal V of the memristor resistance acquisition circuit C A negative DC voltage U is applied between C After a period of time, the memristor is reset to a high impedance state, and the precision operational amplifier F is read through the ADC pin of the MCU. O The output voltage of the terminal is calculated by the formula Calculate the resistance of the memristor when it is in the high resistance state, where M R Represents the resistance of the memristor in high resistance state, V in Indicates DC voltage U C The size of V out Indicates the precision operational amplifier terminal F O The output voltage of R2 represents the resistance value of R2 resistor;

[0022] Replace the memristor, repeat step Sp1-1, obtain the resistance data of multiple memristors in a high-resistance state, and generate a binary file from these data and store it in the storage module of the digital PUF circuit;

[0023] Step 2: Generate PUF response:

[0024] A high level signal is applied to the reset terminal RST of the digital PUF circuit, the digital PUF circuit is reset, and the response output is zero;

[0025] The reset terminal RST of the digital PUF circuit applies a low-level signal, the clock terminal CLK applies a pulse signal with a period of T, and the excitation terminal C[0...(N-1)] applies an excitation signal C[0...(N-1)], and the digital chaos module generates a two-dimensional Henon chaotic signal. The X-dimensional and Y-dimensional components of the chaotic signal are respectively input to the X1[0...31] terminal and Y1[0...31] terminal of the response generation module through the X0[0...31] terminal and the Y0[0...31] terminal of the digital chaos module. The pulse signal with a period of T is divided by the clock division module and then input to the CLK0 terminal of the storage module and the CLK0 terminal of the response generation module through the CLK1 terminal of the clock division module. The storage module reads the memristor resistance data generated in step Sp1-2 and inputs it to the D1[0...31] terminal of the response generation module through the D0[0...31] terminal;

[0026] The response generation module selects the X-dimensional or Y-dimensional component of the chaotic signal to participate in the generation of the PUF response according to the lowest bit of the excitation signal C[0...(N-1)]; if the lowest bit of the excitation signal C[0...(N-1)] is 1, the X-dimensional component is selected to participate in the generation of the PUF response; if the lowest bit of the excitation signal is 0, the Y-dimensional component is selected to participate in the generation of the PUF response, and the selected X-dimensional or Y-dimensional component is converted into a binary sequence through a zero-crossing comparator, and then the binary value corresponding to the excitation signal C[0...(N-1)] is used as the number of iterations P of the two-dimensional Henon chaotic mapping equation, and from the binary sequence corresponding to the X-dimensional or Y-dimensional component, N consecutive binary numbers are selected from the Pth iteration, and then N binary numbers are continuously selected from the P+Nth iteration, respectively combined into two binary values, and the two values ​​are used as addresses, and the resistance data of the two memristors stored in the storage units corresponding to the two addresses are selected, and the response R is output by comparing the size of the two resistance data.

[0027] The two-dimensional Henon chaotic signal is generated by the Henon chaotic mapping equation, which is:

[0028]

[0029] Among them, x n and n are the state values ​​of the nth iteration of the Henon chaotic mapping equation, with initial values ​​x0=0, y0=0; x n+1 and n+1 is the state value of the n+1th iteration of the Henon chaotic mapping equation

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] In the prior art, the PUF circuit is easily affected by voltage fluctuations, and the circuit reliability is low. In the present invention, the extraction of the entropy source and the generation of the PUF response are processed separately. The resistance value of the memristor in the high-resistance state is collected by the memristor resistance collection circuit. Since the resistance distribution of each memristor in the high-resistance state is random, the high-resistance state resistance value of the memristor can be used as the entropy source of the PUF circuit; the entropy source based on the memristor is then digitized and applied to the digital PUF circuit, and the resistance values ​​of different memristors in the high-resistance state are randomly selected by digital chaotic signals. Finally, the PUF response is output by comparing the resistance values ​​of two randomly selected memristors in the high-resistance state. Compared with the traditional analog PUF circuit that is easily affected by factors such as voltage fluctuations and device parameter drift, the FPGA-based digital PUF circuit designed by the present invention has stronger reliability and is not easily affected by factors such as voltage fluctuations. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0033] Figure 1 A circuit diagram of a memristor resistance value acquisition circuit in the present invention;

[0034] Figure 2 is a circuit diagram of the digital PUF circuit in the present invention.

[0035] Legend:

[0036] 101, memristor; 102, R1 resistor; 103, R2 resistor; 104, precision operational amplifier; 105, MCU;

[0037] 201, clock frequency division module; 202, digital chaos module; 203, storage module; 204, response generation module. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Embodiment 1:

[0040] In this embodiment, see Figure 1 and Figure 2, discloses a digital PUF circuit based on FPGA, the input signal of the circuit includes an excitation signal C[0…(N-1)], a clock signal and a reset signal, the output signal is R, and the circuit is pre-processed by a memristor resistance acquisition circuit;

[0041] The memristor resistance value acquisition circuit includes a memristor 101, an R1 resistor 102, an R2 resistor 103, a precision operational amplifier 104 and an MCU 105. The voltage input terminal V C A negative DC voltage U is applied between GND C , wherein the M0 terminal of the memristor 101 is connected to the voltage input terminal V C The M1 terminal of the memristor 101 is connected to the R2 resistor 103 and the F of the precision operational amplifier 104. - terminal, R1 resistor 102 is connected to GND, R1 resistor 102 and the precision operational amplifier 104 are connected to the F + Terminal connection, precision operational amplifier 104 F O The terminals are connected to the R2 resistor 103 and the ADC pin of the MCU 105 respectively;

[0042] The digital PUF circuit includes a clock frequency division module 201, a digital chaos module 202, a storage module 203 and a response generation module 204. The digital PUF circuit is connected to an external clock signal through a clock terminal CLK and an external reset signal through a reset terminal RST. The CLK0 terminal of the clock frequency division module 201 is connected to the clock terminal CLK, the RST0 terminal of the clock frequency division module 201 is connected to the reset terminal RST, and the CLK1 terminal of the clock frequency division module 201 is connected to the CLK0 terminal of the storage module 203 and the CLK0 terminal of the response generation module 204, respectively.

[0043] The CLK0 terminal of the digital chaos module 202 is connected to the clock terminal CLK, the RST0 terminal of the digital chaos module 202 is connected to the reset terminal RST, the X0[0…31] terminal of the digital chaos module 202 is connected to the X1[0…31] terminal of the response generation module 204, the Y0[0…31] terminal of the digital chaos module 202 is connected to the Y1[0…31] terminal of the response generation module 204,

[0044] The RST0 terminal of the storage module 203 is connected to the reset terminal RST, and the D0[0...31] terminal of the storage module 203 is connected to the D1[0...31] terminal of the response generation module 204.

[0045] The C0[0...(N-1)] terminal of the response generation module 204 is connected to the excitation terminal C[0...(N-1)], the RST0 terminal of the response generation module 204 is connected to the reset terminal RST, and the R0 terminal of the response generation module 204 outputs the response output signal R.

[0046] Wherein, N represents the number of bits of the excitation, and N is a natural number greater than or equal to 1 and less than or equal to 32;

[0047] The resistance value of the memristor 101 in the high resistance state acquired by the memristor resistance acquisition circuit is stored in the storage module 203 of the digital PUF circuit.

[0048] The calculation formula of the resistance value of the memristor 101 when it is in the high-resistance state is:

[0049]

[0050] Among them, M R represents the resistance value of the memristor 101 when it is in a high-resistance state,

[0051] V in Indicates DC voltage U C The size of

[0052] V out Indicates the precision operational amplifier 104 terminal F O The output voltage size,

[0053] R2 represents the resistance value of the resistor 103 .

[0054] The precision operational amplifier 104 is a general-purpose precision operational amplifier 104 or a low-power precision operational amplifier 104; and the FPGA chip has a floating-point operation IP core.

[0055] The FPGA-based digital PUF circuit provided in this embodiment uses the high-resistance value of the memristor 101 as the entropy source of the PUF circuit, and then digitizes the entropy source based on the memristor 101 and applies it to the digital PUF circuit, which is not easily affected by factors such as voltage fluctuations and device parameter drifts.

[0056] Embodiment 2:

[0057] Based on the FPGA-based digital PUF circuit disclosed in Example 1, this embodiment provides a method for using the FPGA-based digital PUF circuit, which includes the following steps:

[0058] Step 1: Extract the resistance value of memristor 101:

[0059] At the voltage input terminal V of the memristor resistance acquisition circuit CA negative DC voltage U is applied between C After a period of time, the memristor 101 is reset to a high impedance state, and the precision operational amplifier 104F is read through the ADC pin of the MCU 105. O The output voltage of the terminal is calculated by the formula Calculate the resistance value of the memristor 101 when it is in a high resistance state, where M R represents the resistance value of the memristor 101 when it is in a high-resistance state, V in Indicates DC voltage U C The size of V out Indicates the precision operational amplifier 104 terminal F O The output voltage of R2 represents the resistance value of the resistor 103;

[0060] Replace the memristor 101, repeat step Sp1-1, obtain the resistance data of multiple memristors 101 in high resistance state, and generate a binary file with these data and store it in the storage module 203 of the digital PUF circuit generated in response;

[0061] Step 2: Generate PUF response:

[0062] A high-level signal is applied to the reset terminal RST of the digital PUF circuit, the digital PUF circuit is reset, and the response output is zero;

[0063] A low-level signal is applied to the reset terminal RST of the digital PUF circuit, a pulse signal with a period of T is applied to the clock terminal CLK, an excitation signal C[0…(N-1)] is applied to the excitation terminal C[0…(N-1)], and the digital chaos module 202 generates a two-dimensional Henon chaotic signal. The X-dimensional and Y-dimensional components of the chaotic signal are respectively input to the X1[0…31] terminal and Y1[0…31] terminal of the response generation module 204 through the X0[0…31] terminal and the Y0[0…31] terminal of the digital chaos module 202. The pulse signal with a period of T is divided by the clock division module 201 and then input to the CLK0 terminal of the storage module 203 and the CLK0 terminal of the response generation module 204 through the CLK1 terminal of the clock division module 201. The storage module 203 reads the resistance data of the memristor 101 generated in step Sp1-2, and inputs it to the D1[0…31] terminal of the response generation module 204 through the D0[0…31] terminal;

[0064] The response generation module 204 selects the X-dimensional or Y-dimensional component of the chaotic signal to participate in the generation of the PUF response according to the lowest bit of the excitation signal C[0…(N-1)]. If the lowest bit of the excitation signal C[0…(N-1)] is 1, the X-dimensional component is selected to participate in the generation of the PUF response; if the lowest bit of the excitation signal is 0, the Y-dimensional component is selected to participate in the generation of the PUF response, and the selected X-dimensional or Y-dimensional component is converted into a binary sequence through a zero-crossing comparator, and then the binary value corresponding to the excitation signal C[0…(N-1)] is used as the number of iterations P of the two-dimensional Henon chaotic mapping equation, and from the binary sequence corresponding to the X-dimensional or Y-dimensional component, N consecutive binary numbers are selected from the Pth iteration, and then N binary numbers are continuously selected from the P+Nth iteration, respectively combined into two binary values, and the two values ​​are used as addresses, and the resistance data of the two memristors 101 stored in the storage units corresponding to the two addresses are selected, and then the response R is output by comparing the sizes of the two resistance data.

[0065] The two-dimensional Henon chaotic signal is generated by the Henon chaotic mapping equation, which is:

[0066]

[0067] Among them, x n and n are the state values ​​of the nth iteration of the Henon chaotic mapping equation, with initial values ​​X0=0, y0=0; x n+1 and n+1 is the state value of the n+1th iteration of the Henon chaotic mapping equation.

[0068] The core of the method for using the FPGA-based digital PUF circuit provided in this embodiment is to output a PUF response by comparing the resistance values ​​of two randomly selected memristors 101 in a high-resistance state, thereby achieving the effect that the digital PUF circuit is not easily affected by factors such as voltage fluctuations and device parameter drifts, and the reliability of the digital PUF circuit is higher.

[0069] Embodiment 3:

[0070] This embodiment provides a reliability index evaluation method for a digital PUF circuit based on FPGA, which is used to verify the reliability of the digital PUF circuit, wherein the reliability index is:

[0071]

[0072] Wherein, S represents the total number of times the digital PUF circuit based on Example 1 is tested under voltage fluctuation conditions,

[0073] p represents the first test of the digital PUF circuit based on Example 1 under voltage fluctuation conditions, where p=1,

[0074] R represents the response of the digital PUF circuit based on Example 1 under standard voltage conditions,

[0075] Rp represents the p-th response of the digital PUF circuit based on Example 1 measured under voltage fluctuation conditions,

[0076] n represents the number of bits of the digital PUF circuit response output based on Example 1,

[0077] HD(R,R P ) represents the Hamming distance between the response R of the digital PUF circuit based on Example 1 measured under standard voltage conditions and the response Rp of the digital PUF circuit based on Example 1 measured under voltage fluctuation conditions, and its calculation formula is:

[0078]

[0079] Wherein, R represents the response of the digital PUF circuit based on Example 1 under standard voltage conditions,

[0080] Rp represents the p-th response of the digital PUF circuit based on Example 1 measured under voltage fluctuation conditions,

[0081] S represents the total number of tests on the digital PUF circuit based on Example 1 under voltage fluctuation conditions,

[0082] p represents the first test of the digital PUF circuit based on Example 1 under voltage fluctuation conditions, wherein p=1, R[p] represents the output response R of the digital PUF circuit based on Example 1 at position p under standard voltage,

[0083] Rp[p] represents the output response of the digital PUF circuit based on Example 1 at position p under different voltage conditions;

[0084] Mathematical operator representing exclusive OR.

[0085] In this embodiment, it can be used to verify the reliability of the FPGA-based digital PUF circuit in Embodiment 1. When the reliability index is greater than 90%, it indicates that the reliability index of the digital PUF circuit is good.

[0086] Embodiment 4:

[0087] This embodiment provides specific implementation data for verifying the reliability of the digital PUF circuit in Example 1 under the reliability verification method based on Example 3. In this embodiment, based on a 6-bit excitation digital PUF circuit;

[0088] In this embodiment, a supply voltage of 3.3V is used as a standard value; when the supply voltage fluctuates between 2.9V and 3.33V, the same stimulus is applied to the FPGA-based digital PUF circuit to obtain a response of the FPGA-based digital PUF circuit.

[0089] When the power supply voltage is 2.9V, 3.0V, 3.1V, 3.2V, 3.3V and 3.33V respectively, the 2 6 The output responses under different excitations are: each time an excitation is applied, one response is output. That is, n in formula (3) is 1, and a total of 64 tests are performed, so S in formula (3) = 64.

[0090] According to formula (4), the responses obtained when the power supply voltage is 2.9 V, 3.0 V, 3.1 V, 3.2 V and 3.33 V are XORed with the responses obtained when the power supply voltage is 3.3 V. Then, the reliability index of the FPGA-based digital PUF circuit is calculated according to formula (3), and the obtained reliability index is: 100%, 100%, 100%, 100%, 100%.

[0091] Therefore, based on the above data, it can be seen that when the power supply voltage varies between 2.9V and 3.33V, the reliability index of the digital PUF circuit based on FPGA is greater than 90%, indicating that in this embodiment, the reliability index of the digital PUF circuit based on 6-bit excitation is better.

[0092] Embodiment 5:

[0093] This embodiment provides specific implementation data for verifying the reliability of the digital PUF circuit in Example 1 under the reliability verification method based on Example 3. In this embodiment, based on an 8-bit excitation digital PUF circuit;

[0094] In this embodiment, a supply voltage of 3.3V is used as a standard value; when the supply voltage fluctuates between 2.9V and 3.33V, the same stimulus is applied to the FPGA-based digital PUF circuit to obtain a response of the FPGA-based digital PUF circuit.

[0095] When the power supply voltage is 2.9V, 3.0V, 3.1V, 3.2V, 3.3V and 3.33V respectively, the 2 8The output responses under different excitations are: each time an excitation is applied, one response is output. That is, n in formula (3) is 1, and a total of 256 tests are performed, then S in formula (3) = 256.

[0096] According to formula (4), the responses obtained when the power supply voltage is 2.9V, 3.0V, 3.1V, 3.2V and 3.33V are respectively XORed with the responses obtained when the power supply voltage is 3.3V. Then, the reliability index of the FPGA-based digital PUF circuit is calculated according to formula (3), and the obtained reliability index is: 100%, 100%, 100%, 100%, 100%. It can be seen that when the power supply voltage varies between 2.9V and 3.33V, the reliability index of the FPGA-based digital PUF circuit is greater than 90%, indicating that in this embodiment, the reliability index of the 8-bit excitation digital PUF circuit is better.

[0097] Therefore, based on Embodiment 4 and Embodiment 5, it can be concluded that in the digital PUF circuits based on 6-bit and 8-bit excitation, the reliability indexes of the digital PUF circuits are relatively good.

[0098] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A digital PUF circuit based on FPGA, the input signal of the circuit includes an excitation signal C[0...(N-1)], a clock signal and a reset signal, and the output signal is R, characterized in that: This circuit uses a memristor resistance value acquisition circuit for pre-processing; The memristor resistance value acquisition circuit comprises a memristor (101), an R1 resistor (102), an R2 resistor (103), a precision operational amplifier (104) and an MCU (105), wherein a voltage input terminal V C A negative DC voltage U is applied between GND C , wherein the M0 terminal of the memristor (101) is connected to the voltage input terminal V C The M1 terminal of the memristor (101) is connected to the R2 resistor (103) and the F-terminal of the precision operational amplifier (104), respectively; the R1 resistor (102) is connected to GND; the R1 resistor (102) and the F-terminal of the precision operational amplifier (104) are connected to each other. + terminal connection, the precision operational amplifier (104) F O The terminals are connected to the R2 resistor (103) and the ADC pin of the MCU (105) respectively; The digital PUF circuit comprises a clock frequency division module (201), a digital chaos module (202), a storage module (203) and a response generation module (204); the digital PUF circuit is connected to an external clock signal via a clock terminal CLK, and is connected to an external reset signal via a reset terminal RST; wherein the CLK0 terminal of the clock frequency division module (201) is connected to the clock terminal CLK, the RST0 terminal of the clock frequency division module (201) is connected to the reset terminal RST, and the CLK1 terminal of the clock frequency division module (201) is connected to the CLK0 terminal of the storage module (203) and the CLK0 terminal of the response generation module (204), respectively. The CLK0 terminal of the digital chaos module (202) is connected to the clock terminal CLK, the RST0 terminal of the digital chaos module (202) is connected to the reset terminal RST, the X0 [0 ... 31] terminal of the digital chaos module (202) is connected to the X1 [0 ... 31] terminal of the response generation module (204), the Y0 [0 ... 31] terminal of the digital chaos module (202) is connected to the Y1 [0 ... 31] terminal of the response generation module (204), The RST0 terminal of the storage module (203) is connected to the reset terminal RST, the D0[0...31] terminal of the storage module (203) is connected to the D1[0...31] terminal of the response generation module (204), The C0[0...(N-1)] terminal of the response generation module (204) is connected to the excitation terminal C[0...(N-1)], the RST0 terminal of the response generation module (204) is connected to the reset terminal RST, and the R0 terminal of the response generation module (204) is connected to the response output terminal R. Wherein, N represents the number of bits of the excitation, and N is a natural number greater than or equal to 1 and less than or equal to 32; The resistance value of the memristor (101) in a high-resistance state acquired by the memristor resistance acquisition circuit is stored in a storage module (203) of the digital PUF circuit.

2. The digital PUF circuit according to claim 1, characterized in that: The calculation formula of the resistance value of the memristor (101) when it is in a high resistance state is: Among them, M R represents the resistance value of the memristor (101) when it is in a high resistance state, V in Indicates DC voltage U C The size of V out Indicates the precision operational amplifier (104) terminal F O The output voltage size, R2 represents the resistance value of the R2 resistor (103).

3. A method for using a digital PUF circuit based on FPGA, the method for using the digital PUF circuit according to claim 1, characterized in that: The steps include: Sp1: memristor (101) resistance extraction; Sp1-1: At the voltage input terminal V of the memristor resistance acquisition circuit C A negative DC voltage U is applied between C After a period of time, the memristor (101) is reset to a high impedance state, and the precision operational amplifier (104) F is read through the ADC pin of the MCU (105). O The output voltage of the terminal is calculated by the formula Calculate the resistance value of the memristor (101) when it is in a high resistance state, where M R represents the resistance value of the memristor (101) when it is in a high resistance state, V in Indicates DC voltage U C The size of V out Indicates the precision operational amplifier (104) terminal F O The output voltage of R2 represents the resistance value of the resistor (103); Sp1-2: Replace the memristor (101), repeat step Sp1-1, obtain resistance data of multiple memristors (101) in a high-resistance state, and generate a binary file from these data and store it in a storage module (203) of the digital PUF circuit; Sp2: Generate PUF response; Sp2-1: A high-level signal is applied to the reset terminal RST of the digital PUF circuit, the digital PUF circuit is reset, and the response output is zero; Sp2-2: A low-level signal is applied to the reset terminal RST of the digital PUF circuit, a pulse signal with a period of T is applied to the clock terminal CLK, and an excitation signal C[0...(N-1)] is applied to the excitation terminal C[0...(N-1)], and the digital chaos module (202) generates a two-dimensional Henon chaotic signal, and the X-dimensional and Y-dimensional components of the chaotic signal are respectively input to the X1[0...(N-1)] terminal of the response generation module (204) through the X0[0...31] terminal and the Y0[0...31] terminal of the digital chaos module (202). …31] terminal and Y1[0…31] terminal, a pulse signal with a period of T is divided by a clock frequency division module (201), and then inputted from the CLK1 terminal of the clock frequency division module (201) to the CLK0 terminal of the storage module (203) and the CLK0 terminal of the response generation module (204), the storage module (203) reads the resistance data of the memristor (101) generated in step Sp1-2, and inputs the data to the D1[0…31] terminal of the response generation module (204) through the D0[0…31] terminal; Sp2-3: The response generation module (204) selects the X-dimensional or Y-dimensional component of the chaotic signal to participate in the generation of the PUF response according to the lowest bit of the excitation signal C[0...(N-1)], and converts the selected X-dimensional or Y-dimensional component into a binary sequence through a zero-crossing comparator, and then uses the binary value corresponding to the excitation signal C[0...(N-1)] as the number of iterations P of the two-dimensional Henon chaotic mapping equation, selects N consecutive binary numbers starting from the Pth iteration from the binary sequence corresponding to the X-dimensional or Y-dimensional component, and then selects N consecutive binary numbers starting from the P+Nth iteration, respectively, and combines them into two binary values, and uses the two values ​​as addresses, selects the resistance data of the two memristors (101) stored in the storage units corresponding to the two addresses, and outputs a response R by comparing the sizes of the two resistance data.

4. The method of use according to claim 3, characterized in that: In the step Sp2-3, if the lowest bit of the excitation signal C[0...(N-1)] is 1, the X-dimensional component is selected to participate in the generation of the PUF response; if the lowest bit of the excitation signal is 0, the Y-dimensional component is selected to participate in the generation of the PUF response.

5. The method of use according to claim 3, characterized in that: In the step Sp2-2, the two-dimensional Henon chaotic signal is generated by the Henon chaotic mapping equation, which is: Among them, x n and n are the state values ​​of the nth iteration of the Henon chaotic mapping equation, with initial values ​​x0=0, y0=0; x n+1 and n+1 is the state value of the n+1th iteration of the Henon chaotic mapping equation.

6. The method of use according to claim 3, characterized in that: The precision operational amplifier (104) is a general-purpose precision operational amplifier (104) or a low-power precision operational amplifier (104); in the step Sp2-2, the FPGA chip has a floating-point operation IP core.

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