Charge pump booster circuit

Abstract

The invention discloses a charge pump booster circuit, relates to the technical field of brush motors, and aims to solve the problem of low boosting efficiency of a built-in charge pump booster circuit in a brush motor in the prior art. The charge pump boost circuit comprises a logic control module, a current source module, a driving module and a boost module. The current source module is used for providing stable voltage for the driving module; the driving module at least comprises a pull-up PMOS tube; the logic control module is used for generating two non-overlapped clock signals based on an input clock source, and generating a first switching signal and a second switching signal based on the two non-overlapped clock signals; the two non-overlapped clock signals comprise a first clock signal and a second clock signal; and the logic control module is used for jointly controlling the switch of the driving module based on the two non-overlapped clock signals, the first switch signal and the second switch signal, so that the driving module drives the boosting module to output a target voltage by utilizing the pull-up PMOS tube. Therefore, the boosting efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of brushed motors, and in particular to a charge pump boost circuit. Background Art

[0002] At present, the built-in charge pump of brushed motors often has the problem of low boost efficiency. Brushed motor driver chips with H-bridges often need to consider the boost problem of the high-side switch gate voltage. Most practices use off-chip bootstrap boost capacitors and Schottky diodes to increase the gate voltage of the high-side switch to a level higher than the power supply voltage VCC.

[0003] In order to avoid using external devices and reduce chip output ports, most motor driver chips in eSOP8 package use built-in charge pumps to provide power supply voltage for high-side switch drivers, such as Figure 1 However, the boost efficiency of this charge pump is often easily affected by parasitic capacitance, dead time, switching speed of power devices, etc., resulting in a low boost. The output voltage of the charge pump determines the gate-source voltage and on-resistance of the high-side switch in the H-bridge. The lower the output voltage, the higher the on-resistance, which increases the thermal power consumption of the power tube. At the same time, its transient power consumption is large. If it shares the same ground line with other digital analog circuits, the transient current will cause greater interference on the ground line.

[0004] The structure diagram of the built-in charge pump of the current motor driver chip is as follows Figure 1 The detailed circuit structure diagram is shown in Figure 2 As shown, a high-frequency clock source (usually 10MHz) controls a push-pull mechanism to charge and discharge the capacitor after passing through a level converter. One end of the capacitor is connected to a reference voltage source, and the other end is connected to the output end of the push-pull mechanism. At the beginning, one end of the capacitor is charged to about 6.3V by the reference voltage source, while the voltage at the other end of the capacitor is 0V. After that, when the other end of the capacitor is charged to the power supply voltage by the push-pull structure, since the voltage at both ends of the capacitor cannot change suddenly, the voltage of the upper board will rise to the power supply voltage +6.3V. After the voltage drops through the diode, this voltage will eventually power the high-side drive, which is about the power supply voltage +5.5V.

[0005] For the above-mentioned push-pull mechanism in the prior art, the pull-up PMOS therein generally adopts a high-voltage power PMOS with a large size. Moreover, since the PMOS turns on slowly, the lower plate of the capacitor starts to discharge before the voltage of the lower plate reaches the power supply voltage, resulting in the external final voltage failing to meet the requirements and the boost efficiency being low. Summary of the invention

[0006] The object of the present invention is to provide a charge pump boost circuit for improving the charge pump boost efficiency.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] The present invention provides a charge pump boost circuit, comprising: a logic control module, a current source module, a driving module and a boost module;

[0009] The current source module and the logic control module are both connected to the driving module; the driving module is connected to the boost module; the current source module is used to provide a stable voltage for the driving module; the driving module at least includes a pull-up PMOS tube;

[0010] The logic control module is used to generate two non-overlapping clock signals based on an input clock source, and generate a first switching signal and a second switching signal based on the two non-overlapping clock signals; the two non-overlapping clock signals include a first clock signal and a second clock signal;

[0011] The logic control module is used to control the switch of the driving module based on the two non-overlapping clock signals, the first switch signal and the second switch signal, so that the driving module drives the boost module to output the target voltage by using the pull-up PMOS tube.

[0012] Compared with the prior art, the present invention provides a charge pump boost circuit, comprising a logic control module, a current source module, a driving module and a boost module; wherein the logic control module is used to generate two non-overlapping clock signals based on an input clock source, and to generate a first switch signal and a second switch signal based on the two non-overlapping clock signals; the two non-overlapping clock signals include a first clock signal and a second clock signal; the current source module is used to provide a stable voltage for the driving module; the logic control module is used to jointly control the switch of the driving module based on the two non-overlapping clock signals, the first switch signal and the second switch signal, so that the driving module drives the boost module to output a target voltage using the pull-up PMOS tube, wherein the logic control module cooperates with the driving module to provide more current to charge the gate end of the pull-up PMOS to accelerate the opening speed, and specifically accelerates the closing speed of the pull-up PMOS in the driving module through the joint action of the first clock signal, the second clock signal, the first switch signal and the second switch signal, thereby improving the boost speed and boost efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0014] Figure 1A schematic diagram of the structure of a charge pump boost circuit provided by the prior art;

[0015] Figure 2 for Figure 1 Specific circuit structure diagram of the charge pump boost circuit in FIG.

[0016] Figure 3 A schematic diagram of the circuit structure of a charge pump boost circuit provided by one embodiment of the present invention;

[0017] Figure 4 A schematic diagram of the circuit structure of a logic control module in a charge pump boost circuit provided by an embodiment of the present invention;

[0018] Figure 5 A schematic diagram of the circuit structure of a non-overlapping clock signal generating module in a logic control module provided in one embodiment of the present invention;

[0019] Figure 6 A schematic diagram of the circuit structure of a first switch signal generating module provided by an embodiment of the present invention;

[0020] Figure 7 A schematic diagram of the circuit structure of a second switch signal generating module provided by an embodiment of the present invention;

[0021] Figure 8 A schematic diagram of a specific circuit structure of a charge pump boost circuit provided by an embodiment of the present invention;

[0022] Fig. 9 A waveform diagram of two non-overlapping clock signals VN and VP provided for one embodiment of the present invention;

[0023] Fig.10 A waveform diagram of a first switching signal vb following a clock signal VN provided in one embodiment of the present invention;

[0024] Fig.11 A waveform diagram of a first switching signal, a first clock signal, and a second clock signal provided for one embodiment of the present invention;

[0025] Fig.12 is a diagram showing simulation results of output voltage of an embodiment of the present invention and the prior art;

[0026] Fig.13 A simulation result diagram provided for an embodiment of the present invention;

[0027] Fig.14 A power consumption simulation result diagram of an embodiment of the present invention and the prior art;

[0028] Fig.15A schematic diagram of the structure of a MIM capacitor provided by one embodiment of the present invention.

[0029] Reference numerals:

[0030] 10- logic control module; 20- current source module; 30- driving module; 40- boost module;

[0031] 11-non-overlapping clock signal generating module; 12-first switch signal generating module; 13-second switch signal generating module;

[0032] 101-first NOT gate; 102-second NOT gate; 103-third NOT gate; 104-fourth NOT gate; 105-fifth NOT gate; 106-sixth NOT gate; 107-seventh NOT gate; 108-first NAND gate; 109-second NAND gate;

[0033] 110-eighth NOT gate; 111-ninth NOT gate; 112-tenth NOT gate; 113-eleventh NOT gate; 114-twelfth NOT gate; 115-AND gate;

[0034] 116 - a first D flip-flop; 117 - a second D flip-flop; 118 - an XOR gate; 119 - a thirteenth NOT gate; 120 - a fourteenth NOT gate;

[0035] 50 - substrate; 60 - first metal layer; 70 - second metal layer; 71 - first region; 72 - second region; 80 - third metal layer; 90 - insulating layer; 91 - metal through hole. DETAILED DESCRIPTION

[0036] In order to facilitate the clear description of the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, the words "the first" and "the second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that the words "the first" and "the second" do not limit the quantity and execution order, and the words "the first" and "the second" do not necessarily limit them to be different.

[0037] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0038] In the present invention, "at least one" means one or more, "more than one" means two or more. "And / or" describes the association relationship of the associated objects, indicating that three types of relationships may exist.

[0039] like Figure 3 As shown, an embodiment of the present invention provides a charge pump boost circuit, which may include: a logic control module 10, a current source module 20, a driving module 30 and a boost module 40;

[0040] The current source module 20 and the logic control module 10 are both connected to the driving module 30; the driving module 30 is connected to the boost module 40; the current source module 20 is used to provide a stable voltage for the driving module 30; the driving module 30 at least includes a pull-up PMOS tube;

[0041] The logic control module 10 is used to generate two non-overlapping clock signals based on an input clock source, and to generate a first switching signal and a second switching signal based on the two non-overlapping clock signals; the two non-overlapping clock signals include a first clock signal and a second clock signal;

[0042] The logic control module 10 is used to control the switch of the driving module 30 based on two non-overlapping clock signals, a first switch signal and a second switch signal, so that the driving module 30 drives the boost module 40 to output a target voltage by using a pull-up PMOS tube.

[0043] like Figure 4 As shown, the logic control module 10 at least includes a non-overlapping clock signal generating module 11, a first switch signal generating module 12, and a second switch signal generating module 13. As mentioned above, the non-overlapping clock signal generating module 11 is used to generate a non-overlapping first clock signal (e.g., represented by VN) and a second clock signal (e.g., represented by VP). Figure 4 In the figure, the first switch signal generating module 12 is connected to the non-overlapping clock signal generating module 11, and the first switch signal generating module 12 is used to generate a first switch signal (for example, represented by vb) based on the first clock signal VN; the second switch signal generating module 13 is connected to the non-overlapping clock signal generating module 11, and the second switch signal generating module 13 is used to generate a second switch signal (for example, represented by sw) based on the first clock signal VN and the second clock signal VP.

[0044] In an optional embodiment, if Figure 5 As shown, the non-overlapping clock signal generating module includes a first NOT gate 101, a second NOT gate 102, a third NOT gate 103, a fourth NOT gate 104, a fifth NOT gate 105, a sixth NOT gate 106, a seventh NOT gate 107, a first NAND gate 108, a second NAND gate 109, a first capacitor C1 and a second capacitor C2;

[0045] Wherein, the input end of the first NOT gate 101 and the first input end of the first NAND gate 108 are both connected to the clock source input end, and the clock source input end is connected to the clock source;

[0046] The output end of the first NOT gate 101 is connected to the first input end of the second NAND gate 109; the input end of the second NOT gate 102 and the first end of the first capacitor C1 are both connected to the output end of the second NAND gate 109; the second end of the second capacitor C2 is grounded; the input end of the third NOT gate 103 is connected to the output end of the second NOT gate 102; the input end of the fourth NOT gate 104 and the second input end of the first NAND gate 108 are both connected to the output end of the third NOT gate 103; the output end of the fourth NOT gate 104 outputs the first clock signal VN;

[0047] The input end of the fifth NOT gate 105 and the first end of the second capacitor C2 are both connected to the output end of the first NAND gate 108; the second end of the second capacitor C2 is grounded; the output end of the fifth NOT gate 105 is connected to the input end of the sixth NOT gate 106; the input end of the seventh NOT gate 107 and the second input end of the first NAND gate 108 are both connected to the output end of the sixth NOT gate 106; the output end of the seventh NOT gate 107 outputs the second clock signal VP.

[0048] In an optional embodiment, if Figure 6 As shown, the first switch signal generating module includes:

[0049] an eighth NOT gate 110 , a ninth NOT gate 111 , a tenth NOT gate 112 , an eleventh NOT gate 113 , a twelfth NOT gate 114 , a third capacitor C3 , a fourth capacitor C4 and an AND gate 115 ;

[0050] The input end of the eighth NOT gate 110 is connected to the output end of the fourth NOT gate (connected to the first clock signal VN), the first end of the third capacitor C3 and the input end of the ninth NOT gate 111 are both connected to the output end of the eighth NOT gate 110; the second end of the third capacitor C3 is grounded; the input end of the tenth NOT gate 112 and the first end of the fourth capacitor C4 are both connected to the output end of the ninth NOT gate 111; the second end of the fourth capacitor C4 is grounded;

[0051] The output end of the tenth NOT gate 112 is connected to the first input end of the AND gate 115; the second input end of the AND gate 115 is connected to the input end of the eighth NOT gate 110; the output end of the AND gate 115 is connected to the input end of the eleventh NOT gate 113; the output end of the eleventh NOT gate 113 is connected to the input end of the twelfth NOT gate 114; the output end of the twelfth NOT gate 114 outputs the first switching signal vb.

[0052] In an optional embodiment, if Figure 7 As shown, the second switch signal generating module includes: a first D flip-flop 116, a second D flip-flop 117, an XOR gate 118 and a thirteenth NOT gate 119;

[0053] The clock input terminal of the first D flip-flop 116 is connected to the output terminal of the seventh NOT gate (connected to the VP signal), the first output terminal of the first D flip-flop 116 is connected to the data input terminal of the first D flip-flop 116; the second output terminal of the first D flip-flop 116 is connected to the first input terminal of the XOR gate 118;

[0054] The clock input terminal of the second D flip-flop 117 is connected to the output terminal of the fourth NOT gate (connected to the VN signal), the first output terminal of the second D flip-flop 117 is connected to the data input terminal of the second D flip-flop 117; the second output terminal of the second D flip-flop 117 is connected to the second input terminal of the XOR gate 118;

[0055] The output end of the XOR gate 118 is connected to the input end of the thirteenth NOT gate 119; the output end of the thirteenth NOT gate 119 outputs the second switch signal sw.

[0056] In an optional embodiment, if Figure 8 As shown, the boost module includes a fifth capacitor C5, a first diode D1, a second diode D2 and a third diode D3;

[0057] Among them, the lower board VCB of the fifth capacitor C5 is connected to the driving module, the first end of the first diode D1 and the first end of the second diode D2 are both connected to the upper board VCT of the fifth capacitor C5; the second end of the first diode D1 is connected to the power supply voltage (7V); the second end of the second diode D2 and the first end of the third diode D3 are both connected to the output end of the boost module; the second end of the third diode D3 is connected to the driving module.

[0058] like Figure 8 As shown, the current source module 20 includes:

[0059] A current source I1, a first low-voltage NMOS transistor MN1, a second low-voltage NMOS transistor MN2, a third low-voltage NMOS transistor MN3, a fourth low-voltage NMOS transistor MN4 and a fifth low-voltage NMOS transistor MN5;

[0060] The first end of the current source I1 is connected to the reference power supply; the drain of the first low-voltage NMOS transistor MN1, the gate of the first low-voltage NMOS transistor MN1, the gate of the second low-voltage NMOS transistor MN2, the gate of the third low-voltage NMOS transistor MN3, the gate of the fourth low-voltage NMOS transistor MN4 and the gate of the fifth low-voltage NMOS transistor MN5 are all connected to the second end of the current source I1;

[0061] The source of the first low-voltage NMOS transistor MN1, the source of the second low-voltage NMOS transistor MN2, the source of the third low-voltage NMOS transistor MN3, the source of the fourth low-voltage NMOS transistor MN4 and the source of the fifth low-voltage NMOS transistor MN5 are all grounded;

[0062] The drain of the second low-voltage NMOS tube MN2 , the drain of the third low-voltage NMOS tube MN3 , the drain of the fourth low-voltage NMOS tube MN4 , and the drain of the fifth low-voltage NMOS tube MN5 are all connected to the protected driving module 30 .

[0063] like Figure 8 As shown, the driving module 30 includes a first high-voltage PMOS tube MHP1, a second high-voltage PMOS tube MHP2, a third high-voltage PMOS tube MHP3, a fourth high-voltage PMOS tube MHP4, a fifth high-voltage PMOS tube MHP5, a first high-voltage NMOS tube MHN1, a second high-voltage NMOS tube MHN2, a third high-voltage NMOS tube MHN3, a fourth high-voltage NMOS tube MHN4, a fifth high-voltage NMOS tube MHN5, a sixth low-voltage NMOS tube MN6, a seventh low-voltage NMOS tube MN7, an eighth low-voltage NMOS tube MN8, a first resistor R1, a second resistor R2, a third resistor R3, a fourteenth NOT gate 120 and a voltage stabilizing diode D4;

[0064] Wherein, the third high-voltage PMOS tube MHP3 is a pull-up PMOS tube;

[0065] The source of the first high-voltage PMOS tube MHP1, the source of the second high-voltage PMOS tube MHP2, the source of the third high-voltage PMOS tube MHP3, the source of the fourth high-voltage PMOS tube MHP4, the source of the fifth high-voltage PMOS tube MHP5, the first end of the first resistor R1, the first end of the second resistor R2, the first end of the third resistor R3 and the first end of the voltage stabilizing diode D4 are all connected to the high-voltage power supply to access the high-voltage VM voltage;

[0066] The second end of the first resistor R1 and the gate (VR port) of the second high-voltage PMOS transistor MHP2 are both connected to the drain of the second high-voltage NMOS transistor MHN2; the source of the second high-voltage NMOS transistor MHN2 is connected to the drain of the second low-voltage NMOS transistor MN2; the gate of the second high-voltage NMOS transistor MHN2 is connected to the second switch signal sw;

[0067] The second end of the second resistor R2 and the gate (VH port) of the first high-voltage PMOS transistor MHP1 are both connected to the drain of the third high-voltage NMOS transistor MHN3; the source of the third high-voltage NMOS transistor MHN3 is connected to the drain of the third low-voltage NMOS transistor MN3; the gate of the third high-voltage NMOS transistor MHN3 is connected to the first end of the fourteenth NOT gate 120, and the second end of the fourteenth NOT gate 120 is connected to the second clock signal VP;

[0068] The gate of the fourth high-voltage PMOS tube MHP4, the drain of the fourth high-voltage PMOS tube MHP4 and the gate of the fifth high-voltage PMOS tube MHP5 are all connected to the drain of the first high-voltage PMOS tube MHP1;

[0069] The drain of the fourth high-voltage NMOS transistor MHN4 is connected to the drain of the fourth high-voltage PMOS transistor MHP4; the gate of the fourth high-voltage NMOS transistor MHN4 is connected to the enable signal EN; the source of the fourth high-voltage NMOS transistor MHN4 is connected to the drain of the sixth low-voltage NMOS transistor MN6;

[0070] The drain of the fifth high-voltage NMOS transistor MHN5 is connected to the drain of the fifth high-voltage PMOS transistor MHP5; the gate of the fifth high-voltage NMOS transistor MHN5 is connected to the enable signal EN; the source of the fifth high-voltage NMOS transistor MHN5 is connected to the drain of the seventh low-voltage NMOS transistor MN7;

[0071] The source of the sixth low-voltage NMOS transistor MN6 and the source of the seventh low-voltage NMOS transistor MN7 are both connected to the drain of the fourth low-voltage NMOS transistor MN4;

[0072] The source of the sixth low-voltage NMOS tube MN6 and the source of the seventh low-voltage NMOS tube MN7 are also connected to the drain of the eighth low-voltage NMOS tube MN8; the source of the eighth low-voltage NMOS tube MN8 is connected to the drain of the fifth low-voltage NMOS tube MN5; the gate of the eighth low-voltage NMOS tube MN8 is connected to the first switch signal vb;

[0073] The second end of the third resistor R3, the second end of the voltage stabilizing diode D4, the drain of the second high-voltage PMOS tube MHP2 and the gate of the third high-voltage PMOS tube MHP3 are all connected to the drain of the fifth high-voltage PMOS tube MHP5;

[0074] The drain of the third high-voltage PMOS tube MHP3 is connected to the drain of the first high-voltage NMOS tube MHN1; the source of the first high-voltage NMOS tube MHN1 is grounded;

[0075] The drain of the third high-voltage PMOS transistor MHP3 and the drain of the first high-voltage NMOS transistor MHN1 are both connected to the lower plate VCB of the fifth capacitor C5.

[0076] Regarding the working process of the charge pump boost circuit: when the second clock signal is at a high level and the first clock signal is at a low level, the gate voltage of the first high-voltage PMOS tube is a high voltage to turn off the first high-voltage PMOS tube; and when the second switch signal is at a high level, the second high-voltage PMOS tube is turned on to charge the gate of the third high-voltage PMOS tube to lock the third high-voltage PMOS tube and turn on the first high-voltage NMOS tube;

[0077] When the first clock signal switches to a high level and the second clock signal switches to a low level, the first high-voltage PMOS tube is turned on, and the gate voltages of the fourth high-voltage PMOS tube and the fifth high-voltage PMOS tube are pulled up to turn off the fourth high-voltage PMOS tube and the fifth high-voltage PMOS tube; the first switch signal turns on the eighth low-voltage NMOS tube; the fifth low-voltage NMOS tube amplifies the current source I1 as a mirror current source to turn on the third high-voltage PMOS tube; the second high-voltage PMOS tube is turned off before the third high-voltage PMOS tube is turned on; the voltage regulator diode is used to protect the third high-voltage PMOS tube;

[0078] When the first clock signal switches to a low level and the second clock signal switches to a high level, the second high-voltage PMOS tube is turned on, the third high-voltage PMOS tube is turned off, and the first high-voltage PMOS tube is turned off at the same time, and the current flows from the fourth high-voltage PMOS tube to the fourth low-voltage NMOS tube.

[0079] It should be noted that Figure 8 VH stands for the port named VH, VR stands for the port named VR, and neither of them represents voltage or signal. This is done to avoid too complicated circuit wiring. VM represents high voltage, and VSS represents 0V voltage.

[0080] In layman's terms, the working principle of the logic control module is:

[0081] The CLK signal (clock source) undergoes Figure 5 After the non-overlapping clock signal generation module shown in the figure, the following is generated: Fig. 9 The two non-overlapping clock signals VN and VP are shown, wherein the dead time of VP and VN is 5ns.

[0082] VN signal passing Figure 6 After the first switch signal generating module shown in FIG. 1 is connected, a first switch signal vb with a pulse width of 5 ns following the VN signal is generated, and the waveform is as follows: Fig.10 shown.

[0083] In addition, VN and VP signals are transmitted through Figure 7 After a switch signal generating module is shown, a second switch signal sw is generated, such as Fig.11 As shown, the rising edge of sw is before VP is at a high level, the falling edge is after VN is at a high level, and it does not overlap with VP and VN.

[0084] VP, VN, sw, and vb jointly control the on and off of the charge pump boost circuit.

[0085] In a specific implementation, CLK is an input clock source port with a frequency of 10 MHz. When the clock signal arrives and the EN terminal is high, the charge pump boost circuit starts to work.

[0086] When VP is high and VN is low, the VH port (i.e., the gate of MHP1) is at VM voltage, so MHP1 is turned off. At this time, the second switch signal sw is high, which turns on MHP2, charges the gate of MHP3 to VM voltage, and locks MHP3 (pull-up PMOS tube). MHN1 is turned on, discharging the lower board VCB of C5 to VSS (0V).

[0087] When VN switches to a high level and VP switches to a low level. At this time, the voltage at the VH port becomes low, MHP1 is turned on, and the gate voltage of MHP4 and MHP5 is instantly pulled up to VM, so MHP4 and MHP5 are turned off. The VN signal will generate a narrow pulse signal (that is, the first switch signal) vb through the delay chain. The pulse signal vb turns on MN8. MN5 acts as a mirror current source to copy the size of the current source I1 several dozen times. The copied current will be injected into the gate of MHP3, turning on MHP3 quickly. Before MHP3 is turned on, the voltage at the VR port will be pulled up to the VM voltage, turning off MHP2, thereby preventing the large current provided by MN5 from flowing away from MHP2. At the same time, a Zener diode D4 is added to the gate-source end of MHP3 for protection.

[0088] Next, when VN switches to a low level and VP switches to a high level, MHP2 is turned on, and the gate voltage of MHP3 is quickly pulled to the VM voltage level to quickly turn off MHP3. At the same time, MHP1 is turned off, and the current flows normally through MHP4 to MN4.

[0089] Through the above operation logic, the problem of simultaneous conduction of the pull-up MOS tube (ie, MHP3) and the pull-down MOS tube (ie, MHN1) in the charge pump boost circuit is solved, and the boost efficiency of the charge pump is greatly improved.

[0090] In the existing technology Figure 2 The circuit structure of the charge pump boost circuit in the embodiment of the present invention is compared and simulated to obtain the following Fig.12 The simulation comparison results in Fig.12 The output voltages of two charge pumps are shown, where the red one is the output voltage of the charge pump boost circuit in the embodiment of the present invention, and the blue one is the output voltage of the charge pump in the prior art. When the power supply voltage is 20V, the charge pump boost circuit in the embodiment of the present invention can increase the voltage from 20V to 26.7V, while the prior art can increase the voltage to 26.1V. According to the formula:

[0091]

[0092] Calculation shows that the boost efficiency of the embodiment of the present invention is improved by 10% compared with the prior art. δ is the boost efficiency.

[0093] In addition, in the embodiment of the present invention, after the driving module and the logic control module cooperate, the switching speed of MHP3 and MNH1 is improved, and a dead time of about 4-5ns is generated. Fig.13 As shown, combined with Fig.14 The simulation results show that under the premise of 10MHz frequency and 20V power supply voltage, the average power consumption of the charge pump boost circuit of this design (this design refers to the design of the embodiment of the present invention) is 22.4mW, while under the same conditions, the total average current of the charge pump boost circuit of the existing design (the existing design refers to the design of the prior art) is 2.46mA and the average power consumption is 49.2mW. The power consumption of the circuit of the embodiment of the present invention is reduced by 54%, which is quite significant.

[0094] In an optional embodiment, if Fig.15 As shown, the fifth capacitor is a MIM capacitor; the MIM capacitor at least includes a substrate 50 and a first metal layer 60, a second metal layer 70, and a third metal layer 80 on the substrate; the second metal layer 70 is on the first metal layer 60, the third metal layer 80 is on the second metal layer 70, and an insulating layer 90 is between the first metal layer 60 and the second metal layer 70; the insulating layer 90 is between the second metal layer 70 and the third metal layer 80; the first metal layer 60 is a lower plate;

[0095] The second metal layer 70 includes a first region 71, a second region 72 and a spacing region, the first region 71 and the second region 72 are separated by the spacing region, and the first region 71 surrounds the second region 72; the second region 72 is an upper plate; a plurality of metal through holes 91 are formed on the insulating layer 90 and the second metal layer 70, so that the third metal layer 80 can be connected to the first metal layer 60 through the metal through holes 91. In other words, the third metal layer 80 is also connected to the lower plate.

[0096] In the prior art, for example Figure 2 The boost capacitor c0 in the circuit is a MIM capacitor. The MIM capacitor in the prior art only includes two metal layers, one of which is used as a lower plate of the capacitor, and the other is used as an upper plate of the capacitor connected to two diodes. The place where the upper plate of the capacitor is connected to the two diodes is defined as a VCT node. There is a parasitic capacitor at this VCT node. The parasitic capacitor will cause voltage division during each charge pump boost process, thereby reducing the output voltage of the charge pump.

[0097] In detail, for the MIM capacitor with only two metal layers in the prior art, it can be understood that the parasitic capacitance mainly includes two types of capacitance. The first type of capacitance is the parasitic capacitance C11 between the metal traces near the boost capacitor, and the second type of capacitance is the parasitic capacitance CC from the upper plate of the boost capacitor to the substrate. The influence of these two types of capacitance on the output voltage of the charge pump is shown in expression (1), where Vo is the ideal output voltage of the charge pump when there is no parasitic capacitance influence, Vcp is the actual output voltage after the parasitic capacitance divider, and C11 is the capacitance value of the boost capacitor. According to formula (1), the larger the parasitic capacitance CC is, the smaller the charge pump output voltage Vcp is. At this time, it is necessary to increase the size of C11 to alleviate the problem. However, increasing C11 will increase the area cost of the circuit.

[0098]

[0099] In order to solve the above problems, the embodiment of the present invention improves and designs the structure of the MIM capacitor with only two metal layers in the prior art: a third metal layer is covered on the second metal layer, and the second metal layer is divided into an intermediate metal layer and a surrounding metal layer, and the intermediate metal layer is used as a lower plate, so that the boost capacitor ( Figure 8 The lower plate of the fifth capacitor C5) can be completely surrounded by the surrounding metal layer and the third metal layer, and isolated from other metal traces in the circuit layout of the entire charge pump boost circuit.

[0100] Combination Fig.15 It can be known that it is assumed that C21 is the parasitic capacitance from the upper plate to the third metal layer M3. In this structure, the third metal layer is connected to the first metal layer (capacitor lower plate) by metal vias, so the parasitic capacitance from the second metal layer to the third metal layer is actually equivalent to a part of C11. And because the first metal layer isolates the second metal layer and the substrate, the parasitic capacitance from the second metal layer to the substrate can be almost ignored. In addition, since the upper plate of the capacitor is also surrounded by the surrounding metal layer, the surrounding metal layer is connected to the third metal layer and the first metal layer, blocking the connection between the upper plate of the capacitor and other metal routings, and also greatly reducing the parasitic capacitance therein.

[0101] After the above improvements to the boost capacitor structure, the parasitic capacitance in the design of the embodiment of the present invention can reach about 60fF, while the parasitic capacitance of the existing design is about 200fF, which reduces the parasitic capacitance by 70%. Thanks to the very low parasitic capacitance in the embodiment of the present invention, the output voltage of the charge pump boost circuit in the embodiment of the present invention is improved. The calculation process is as follows:

[0102] V0=V M +6V(3)

[0103]

[0104] Among them, the total parasitic capacitance of this design is 60fF (C+CC)1, and the total parasitic capacitance of Del design in the prior art is 200fF (C+CC)2, V M is the power supply voltage of 30V, V0 is the output voltage of the charge pump, V CP1 is the output voltage after the parasitic capacitor voltage division in the prior art design, V CP2 The output voltage of this design after parasitic capacitance voltage division

[0105] From all the above, it can be seen that the charge pump boost circuit provided in the embodiment of the present invention has further improved the boost efficiency, power consumption and reference voltage utilization compared to the prior art, and also solves the problem that the charge pump is susceptible to interference from parasitic parameters.

[0106] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other device may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0107] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A charge pump boost circuit, characterized in that: include: Logic control module, current source module, drive module and boost module; The current source module and the logic control module are both connected to the driving module; the driving module is connected to the boost module; the current source module is used to provide a stable voltage for the driving module; the driving module at least includes a pull-up PMOS tube; The logic control module is used to generate two non-overlapping clock signals based on an input clock source, and generate a first switching signal and a second switching signal based on the two non-overlapping clock signals; the two non-overlapping clock signals include a first clock signal and a second clock signal; The logic control module is used to control the switch of the driving module based on the two non-overlapping clock signals, the first switch signal and the second switch signal, so that the driving module drives the boost module to output the target voltage by using the pull-up PMOS tube.

2. The charge pump boost circuit according to claim 1, characterized in that: The logic control module at least includes a non-overlapping clock signal generation module; The non-overlapping clock signal generating module includes a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, a first NAND gate, a second NAND gate, a first capacitor and a second capacitor; Wherein, the input end of the first NOT gate and the first input end of the first NAND gate are both connected to the clock source input end, and the clock source input end is connected to the clock source; The output end of the first NOT gate is connected to the first input end of the second NAND gate; the input end of the second NOT gate and the first end of the first capacitor are both connected to the output end of the second NAND gate; the second end of the second capacitor is grounded; the input end of the third NOT gate is connected to the output end of the second NOT gate; the input end of the fourth NOT gate and the second input end of the first NAND gate are both connected to the output end of the third NOT gate; the output end of the fourth NOT gate outputs the first clock signal; The input end of the fifth NOT gate and the first end of the second capacitor are both connected to the output end of the first NAND gate; the second end of the second capacitor is grounded; the output end of the fifth NOT gate is connected to the input end of the sixth NOT gate; the input end of the seventh NOT gate and the second input end of the first NAND gate are both connected to the output end of the sixth NOT gate; the output end of the seventh NOT gate outputs the second clock signal.

3. The charge pump boost circuit according to claim 2, characterized in that: The logic control module further includes a first switch signal generating module, the first switch signal generating module is connected to the non-overlapping clock signal generating module, and the first switch signal generating module is used to generate the first switch signal based on the first clock signal; The first switch signal generating module includes: an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, an eleventh NOT gate, a twelfth NOT gate, a third capacitor, a fourth capacitor and an AND gate; The input end of the eighth NOT gate is connected to the output end of the fourth NOT gate, the first end of the third capacitor and the input end of the ninth NOT gate are both connected to the output end of the eighth NOT gate; the second end of the third capacitor is grounded; the input end of the tenth NOT gate and the first end of the fourth capacitor are both connected to the output end of the ninth NOT gate; the second end of the fourth capacitor is grounded; The output end of the tenth NOT gate is connected to the first input end of the AND gate; the second input end of the AND gate is connected to the input end of the eighth NOT gate; the output end of the AND gate is connected to the input end of the eleventh NOT gate; the output end of the eleventh NOT gate is connected to the input end of the twelfth NOT gate; the output end of the twelfth NOT gate outputs the first switching signal.

4. The charge pump boost circuit according to claim 3, characterized in that: The logic control module further includes a second switch signal generating module, the second switch signal generating module is connected to the non-overlapping clock signal generating module, and the second switch signal generating module is used to generate the second switch signal based on the first clock signal and the second clock signal; The second switch signal generating module includes: a first D flip-flop, a second D flip-flop, an XOR gate and a thirteenth NOT gate; Wherein, the clock input terminal of the first D flip-flop is connected to the output terminal of the seventh NOT gate, the first output terminal of the first D flip-flop is connected to the data input terminal of the first D flip-flop; the second output terminal of the first D flip-flop is connected to the first input terminal of the XOR gate; The clock input terminal of the second D flip-flop is connected to the output terminal of the fourth NOT gate, the first output terminal of the second D flip-flop is connected to the data input terminal of the second D flip-flop; the second output terminal of the second D flip-flop is connected to the second input terminal of the XOR gate; The output end of the XOR gate is connected to the input end of the thirteenth NOT gate; the output end of the thirteenth NOT gate outputs the second switch signal.

5. The charge pump boost circuit according to claim 4, characterized in that: The boost module includes a fifth capacitor, a first diode, a second diode and a third diode; Among them, the lower board of the fifth capacitor is connected to the driving module, the first end of the first diode and the first end of the second diode are both connected to the upper board of the fifth capacitor; the second end of the first diode is connected to the power supply voltage; the second end of the second diode and the first end of the third diode are both connected to the output end of the boost module; the second end of the third diode is connected to the driving module.

6. The charge pump boost circuit according to claim 5, characterized in that: The current source module includes: a current source, a first low-voltage NMOS tube, a second low-voltage NMOS tube, a third low-voltage NMOS tube, a fourth low-voltage NMOS tube and a fifth low-voltage NMOS tube; Wherein, the first end of the current source is connected to a reference power supply; the drain of the first low-voltage NMOS tube, the gate of the first low-voltage NMOS tube, the gate of the second low-voltage NMOS tube, the gate of the third low-voltage NMOS tube, the gate of the fourth low-voltage NMOS tube and the gate of the fifth low-voltage NMOS tube are all connected to the second end of the current source; The source of the first low-voltage NMOS tube, the source of the second low-voltage NMOS tube, the source of the third low-voltage NMOS tube, the source of the fourth low-voltage NMOS tube and the source of the fifth low-voltage NMOS tube are all grounded.

7. The charge pump boost circuit according to claim 6, characterized in that: The driving module includes a first high-voltage PMOS tube, a second high-voltage PMOS tube, a third high-voltage PMOS tube, a fourth high-voltage PMOS tube, a fifth high-voltage PMOS tube, a first high-voltage NMOS tube, a second high-voltage NMOS tube, a third high-voltage NMOS tube, a fourth high-voltage NMOS tube, a fifth high-voltage NMOS tube, a sixth low-voltage NMOS tube, a seventh low-voltage NMOS tube, an eighth low-voltage NMOS tube, a first resistor, a second resistor, a third resistor, a fourteenth NOT gate and a voltage stabilizing diode; Wherein, the third high-voltage PMOS tube is the pull-up PMOS tube; The source of the first high-voltage PMOS tube, the source of the second high-voltage PMOS tube, the source of the third high-voltage PMOS tube, the source of the fourth high-voltage PMOS tube, the source of the fifth high-voltage PMOS tube, the first end of the first resistor, the first end of the second resistor, the first end of the third resistor and the first end of the voltage regulator diode are all connected to a high-voltage power supply to access the high-voltage voltage; The second end of the first resistor and the gate of the second high-voltage PMOS tube are both connected to the drain of the second high-voltage NMOS tube; the source of the second high-voltage NMOS tube is connected to the drain of the second low-voltage NMOS tube; the gate of the second high-voltage NMOS tube is connected to the second switch signal; The second end of the second resistor and the gate of the first high-voltage PMOS tube are both connected to the drain of the third high-voltage NMOS tube; the source of the third high-voltage NMOS tube is connected to the drain of the third low-voltage NMOS tube; the gate of the third high-voltage NMOS tube is connected to the first end of the fourteenth NOT gate, and the second end of the fourteenth NOT gate is connected to the second clock signal; The gate of the fourth high-voltage PMOS tube, the drain of the fourth high-voltage PMOS tube and the gate of the fifth high-voltage PMOS tube are all connected to the drain of the first high-voltage PMOS tube; The drain of the fourth high-voltage NMOS tube is connected to the drain of the fourth high-voltage PMOS tube; the gate of the fourth high-voltage NMOS tube is connected to the enable signal; the source of the fourth high-voltage NMOS tube is connected to the drain of the sixth low-voltage NMOS tube; The drain of the fifth high-voltage NMOS tube is connected to the drain of the fifth high-voltage PMOS tube; the gate of the fifth high-voltage NMOS tube is connected to the enable signal; the source of the fifth high-voltage NMOS tube is connected to the drain of the seventh low-voltage NMOS tube; The source of the sixth low-voltage NMOS tube and the source of the seventh low-voltage NMOS tube are both connected to the drain of the fourth low-voltage NMOS tube; The source of the sixth low-voltage NMOS tube and the source of the seventh low-voltage NMOS tube are also connected to the drain of the eighth low-voltage NMOS tube; the source of the eighth low-voltage NMOS tube is connected to the drain of the fifth low-voltage NMOS tube; the gate of the eighth low-voltage NMOS tube is connected to the first switch signal; The second end of the third resistor, the second end of the voltage stabilizing diode, the drain of the second high-voltage PMOS tube and the gate of the third high-voltage PMOS tube are all connected to the drain of the fifth high-voltage PMOS tube; The drain of the third high-voltage PMOS tube is connected to the drain of the first high-voltage NMOS tube; the source of the first high-voltage NMOS tube is grounded; The drain of the third high-voltage PMOS tube and the drain of the first high-voltage NMOS tube are both connected to the lower plate of the fifth capacitor.

8. The charge pump boost circuit according to claim 7, characterized in that: When the second clock signal is at a high level and the first clock signal is at a low level, the gate voltage of the first high-voltage PMOS tube is a high voltage to turn off the first high-voltage PMOS tube; and when the second switch signal is at a high level, the second high-voltage PMOS tube is turned on to charge the gate of the third high-voltage PMOS tube to lock the third high-voltage PMOS tube and turn on the first high-voltage NMOS tube; When the first clock signal switches to a high level and the second clock signal switches to a low level, the first high-voltage PMOS tube is turned on, and the gate voltages of the fourth high-voltage PMOS tube and the fifth high-voltage PMOS tube are pulled up to turn off the fourth high-voltage PMOS tube and the fifth high-voltage PMOS tube; the first switch signal turns on the eighth low-voltage NMOS tube; the fifth low-voltage NMOS tube amplifies the current source as a mirror current source to turn on the third high-voltage PMOS tube; the second high-voltage PMOS tube is turned off before the third high-voltage PMOS tube is turned on; the voltage regulator diode is used to protect the third high-voltage PMOS tube; When the first clock signal switches to a low level and the second clock signal switches to a high level, the second high-voltage PMOS tube is turned on, the third high-voltage PMOS tube is turned off, and the first high-voltage PMOS tube is turned off at the same time, and the current flows from the fourth high-voltage PMOS tube to the fourth low-voltage NMOS tube.

9. The charge pump boost circuit according to claim 5, characterized in that: The fifth capacitor is a MIM capacitor; The MIM capacitor at least includes a substrate and a first metal layer, a second metal layer, and a third metal layer on the substrate; the first metal layer is the lower plate of the fifth capacitor; The second metal layer includes a first region, a second region and a spacing region, the first region and the second region are separated by the spacing region, the first region surrounds the second region; the second region is the upper plate of the fifth capacitor; The third metal layer is also connected to the lower board.

10. The charge pump boost circuit according to claim 9, characterized in that: There is an insulating layer between the first metal layer and the second metal layer; there is an insulating layer between the second metal layer and the third metal layer; and the spacing area is also an insulating layer.

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