Data processing method and device

Abstract

The embodiment of the invention provides a data processing method and device, and relates to the technical field of data communication. A first physical PHY of a sending device receives first indication information of a first media access control MAC layer from the sending device, wherein the first indication information is used for indicating the sending device to send a service flow to a receiving device; the first PHY obtains a first indication code block according to the first indication information, and the first indication code block is used for indicating that a second PHY of the receiving equipment is switched from a dormant state to a working state and indicating that a second serializer / deserializer SerDes corresponding to the second PHY is switched from a keep-alive state to the working state; the first PHY transmits the first indication code block to the receiving device. Through the mode, the working state can be recovered more quickly under the condition of ensuring that the physical layer of the Ethernet saves power consumption, and the user experience can be further improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of data communication technology, and in particular, to a data processing method and device. Background Art

[0002] As the demand for Ethernet capacity increases, services are placing higher and higher demands on Ethernet link speeds. In addition, Ethernet service bandwidth is also developing at a high speed. With the increase in service bandwidth and the increase in physical link bit errors, the physical layer requires a more complex structure to support the development of service needs. For example, cascaded forward error correction (FEC) increases the power consumption of the physical layer.

[0003] In order to reduce the power consumption of PHY, the related art proposes to save the power consumption of the physical layer by sleeping the serializer / deserializer (SerDes). In the current processing mechanism, it takes a long recovery time for SerDes to switch from the sleep state to the working state. Specifically, the time required is more than tens of milliseconds (ms). This method not only requires caching of service data transmitted for tens of milliseconds or more, but also requires a delay of tens of milliseconds for the subsequent service data to be sent, which has a great impact on the delay experience of Ethernet users and poor user experience. Summary of the invention

[0004] The present application provides a data processing method and device to effectively shorten the time it takes for a SerDes to resume working status while saving power consumption at the Ethernet physical layer, reduce the cache of service data, and improve user experience.

[0005] In a first aspect, the present application provides a data processing method, which is applied to a sending device, the sending device includes a first medium access control (MAC) layer and a first physical layer (PHY), the sending device can be a device in Ethernet or Hyper Ethernet, such as a switch, a router, etc., which is not specifically limited here, and the method is performed as follows:

[0006] The first PHY receives first indication information from the first MAC layer, where the first indication information is used to instruct the sending device to send a service flow to the receiving device; the first PHY obtains a first indication code block according to the first indication information, where the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct the second SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the first PHY sends the first indication code block to the receiving device.

[0007] It should be noted that the first PHY obtains the first indication code block according to the first indication information, which can be understood as the first PHY generating the first indication code block according to the first indication information, or the first PHY selecting the indication code block from the pre-generated indication code blocks according to the first indication information as the first indication code block. This application does not specifically limit how to obtain the first indication code block. In addition, the sleep state in this application can be understood as a non-working state, a state of not processing business, and a state of not transmitting business flows; the working state can be understood as a state of transmitting business flows and processing business; the keep-alive state can be understood as a standby state, and once a business-related trigger message or instruction is received, it will immediately resume to a working state.

[0008] In the present application, after the PHY of the sending device receives the first indication information of the MAC layer, it determines that the transmission of the service flow needs to be restored based on the first indication information, and then obtains the first indication code block based on the first indication information, and indicates the first indication code block to the receiving device, so that the receiving device switches the state of the PHY according to the first indication code block, and the PHY of the receiving device switches from the sleep state to the working state, and the corresponding SerDes switches from the keep-alive state to the working state. In this way, when the Ethernet device is not working, the PHY is in the sleep state, and the corresponding SerDes is in the keep-alive state, which can save the power consumption of the physical layer. Once the service is restored, the Ethernet device can respond in time, the PHY switches from the sleep state to the working state, and the SerDes switches from the keep-alive state to the working state. The response is faster when the service is restored, and there is no need to cache a large amount of service data in the service recovery process to wait for the Ethernet device to resume work, which can improve the user experience, and further, it can improve the data processing efficiency.

[0009] In an optional manner, the first PHY switches the first PHY from a sleep state to a working state and switches a first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information.

[0010] It should be noted that the first PHY can directly refer to the first indication information to adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY, and can also obtain the first indication code block based on the first indication information, and adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY according to the first indication code block. This application does not specifically limit this.

[0011] In the present application, when resuming work, the first PHY switches the first PHY from a sleep state to a working state according to the first indication information and switches the first SerDes corresponding to the first PHY from a keep-alive state to a working state, which can ensure rapid response to service recovery and improve user experience.

[0012] In an optional manner, the first PHY includes a first physical coding sublayer (PCS) and a first physical medium attachment (PMA), wherein the first PHY switches from a sleep state to a working state including the first PCS switches from a sleep state to a working state and the first PMA switches from a sleep state to a working state.

[0013] In the present application, the first PHY switches from a sleep state to a working state including the first PCS switches from a sleep state to a working state and the first PMA switches from a sleep state to a working state, which can ensure rapid response to service recovery and improve user experience.

[0014] In an optional manner, the first PHY receives second indication information from the first MAC layer, the second indication information being used to instruct the sending device to stop sending service flows to the receiving device; the first PHY obtains a second indication code block based on the second indication information, the second indication code block being used to instruct the second PHY of the receiving device to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; the first PHY sends the second indication code block to the receiving device.

[0015] It should be noted that the first PHY obtains the second indication code block according to the second indication information, which can be understood as the first PHY generating the second indication code block according to the second indication information, or the first PHY selects an indication code block from the pre-generated indication code blocks as the second indication code block according to the second indication information. The present application does not specifically limit how to obtain the second indication code block.

[0016] In the present application, after the PHY of the sending device receives the second indication information of the MAC layer, it determines that the transmission of the service flow needs to be stopped based on the second indication information, and then obtains the second indication code block based on the second indication information, and indicates the second indication code block to the receiving device, so that the receiving device switches the state of the PHY according to the second indication code block, and the PHY of the receiving device switches from the working state to the sleeping state, and the corresponding SerDes switches from the working state to the keep-alive state. In this way, when the Ethernet device is not working, the PHY is in the sleeping state, and the corresponding SerDes is in the keep-alive state, which can save the power consumption of the physical layer.

[0017] In an optional manner, the first PHY switches the first PHY from a working state to a sleep state and switches the first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information.

[0018] It should be noted that the first PHY can directly refer to the second indication information to adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY, and can also obtain the second indication code block based on the second indication information, and adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY according to the second indication code block. This application is not specifically limited here.

[0019] In the present application, when the first PHY stops working, the first PHY is switched from the working state to the sleep state according to the second indication information, and the first SerDes corresponding to the first PHY is switched from the working state to the keep-alive state, which can ensure a quick response to service stop and save power consumption.

[0020] In an optional manner, the first PHY includes a first PCS and a first PMA, wherein the switching of the first PHY from a working state to a sleeping state includes the switching of the first PCS from a working state to a sleeping state and the switching of the first PMA from a working state to a sleeping state.

[0021] In the present application, the first PHY switches from a working state to a sleeping state, including the first PCS switches from a working state to a sleeping state and the first PMA switches from a working state to a sleeping state, which can ensure a quick response to service stoppage and save power consumption.

[0022] In an optional manner, the first PCS switches the first PCS from a sleep state to a working state according to the first indication information, and obtains a first indication code block; the first PCS sends the first indication code block to the first PMA; the first PMA switches the first PMA from a sleep state to a working state according to the received first indication code block.

[0023] In an optional manner, the first PCS switches the first PCS from a sleep state to a working state according to the first indication information, and sends the first indication information to the first PMA; the first PMA switches the first PMA from a sleep state to a working state according to the received first indication information, and obtains a first indication code block.

[0024] In the present application, the first PCS switches the first PCS from a sleep state to a working state according to the first indication information. The first indication information can be directly transmitted to the first PMA. The first indication code block can also be obtained and the first indication code block can be transmitted to the first PMA to enable the first PMA to switch the state. Regardless of which method is used, it can ensure that the first PCS and the first PMA are switched from a sleep state to a working state, which can ensure rapid business recovery and improve data processing efficiency.

[0025] In an optional manner, the first PCS switches the first PCS from a working state to a sleep state according to the second indication information, and obtains a second indication code block; the first PCS sends the second indication code block to the first PMA; the first PMA switches the first PMA from a working state to a sleep state according to the received second indication code block.

[0026] In an optional manner, the first PCS switches the first PCS from a working state to a sleep state according to the second indication information, and sends the second indication information to the first PMA; the first PMA switches the first PMA from a working state to a sleep state according to the received second indication information, and obtains a second indication code block.

[0027] In the present application, the first PCS switches the first PCS from a working state to a sleep state according to the second indication information. The second indication information can be directly transmitted to the first PMA. The second indication code block can also be obtained and the second indication code block can be transmitted to the first PMA to enable the first PMA to switch the state. Regardless of which method is used, it can ensure that the first PCS and the first PMA are switched from a working state to a sleep state, which can ensure that the business is quickly stopped and improve data processing efficiency.

[0028] In an optional manner, the first PCS includes multiple first PCS channels, and the first PCS switches the multiple first PCS channels from a sleep state to a working state; or, the first PCS switches some of the multiple first PCS channels from a sleep state to a working state according to a first service flow rate threshold.

[0029] In the present application, when the service is restored, part or all of the first PCS channels can be switched from the sleep state to the working state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring the normal transmission of the service.

[0030] In an optional manner, the first PCS includes multiple first PCS channels, and the first PCS switches the multiple first PCS channels from a working state to a sleep state; or, the first PCS switches some of the multiple first PCS channels from a working state to a sleep state according to a second service flow rate threshold.

[0031] In the present application, when the service is stopped, part or all of the first PCS channels can be switched from the working state to the sleeping state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring the normal transmission of the service.

[0032] In an optional manner, the first PCS includes multiple first PCS channels, and the first PCS sends the first indication code block via at least one first PCS channel among the multiple first PCS channels.

[0033] In the present application, when the service is restored, multiple first PCS channels of the first PCS may all send the first indication code block, or may partially send the first indication code block, which is not specifically limited here, as long as it is ensured that the receiving device can receive the first indication code block.

[0034] In an optional manner, the first PCS includes multiple first PCS channels, and the first PCS sends the second indication code block via at least one first PCS channel among the multiple first PCS channels.

[0035] In the present application, when the service is paused, multiple first PCS channels of the first PCS may all send the second indication code block, or may partially send the second indication code block, which is not specifically limited here, as long as it is ensured that the receiving device can receive the second indication code block.

[0036] In an optional manner, the first PHY includes a first physical media dependent (PMD), and the first PHY switches the first PMD from a keep-alive state to a working state according to first indication information; the first PHY switches a first SerDes corresponding to the first PMD from a keep-alive state to a working state.

[0037] In the present application, the first PMD is switched from a keep-alive state to a working state, and the first SerDes corresponding to the first PMD is switched from a keep-alive state to a working state, which can ensure rapid response to service recovery and improve user experience.

[0038] In an optional manner, the first PMD includes multiple first PMD channels, and the first PMD switches the multiple first PMD channels from a keep-alive state to a working state; or, the first PMD switches some of the multiple first PMD channels from a keep-alive state to a working state according to a first service flow rate threshold.

[0039] In the present application, when the service is restored, part or all of the first PMD channels can be switched from the keep-alive state to the working state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring the normal transmission of the service.

[0040] In an optional manner, when the first SerDes is in a keep-alive state, the first PHY periodically sends a keep-alive code block to the receiving device via the first SerDes.

[0041] This method can ensure that when the service is restored, the first SerDes can respond to the service demand in time and restore the service transmission.

[0042] In an optional manner, the length of the first indication code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0043] In a second aspect, the present application provides a data processing method, which is applied to a receiving device, the receiving device includes a second PHY, and the receiving device can be a device in Ethernet or a device in Hyper Ethernet, such as a switch, a router, etc., which is not specifically limited here. The method is performed as follows:

[0044] The second PHY receives a first indication code block sent by the first PHY in the transmitting device, where the first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct the second SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the second PHY switches the second PHY from a sleep state to a working state and switches the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block.

[0045] In the present application, the receiving device receives the first indication code block from the sending device, so that the receiving device switches the state of PHY according to the first indication code block, and the PHY of the receiving device switches from the sleep state to the working state, and the corresponding SerDes switches from the keep-alive state to the working state. In this way, when the Ethernet device is not working, the PHY is in the sleep state, and the corresponding SerDes is in the keep-alive state, which can save the power consumption of the physical layer. Once the service is restored, the Ethernet device can respond in time, the PHY switches from the sleep state to the working state, and the SerDes switches from the keep-alive state to the working state. The response is faster when the service is restored, and during the service recovery process, there is no need to cache a large amount of service data waiting for the Ethernet device to resume work, which can improve the user experience, and further, it can improve the data processing efficiency.

[0046] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the second PHY switching from a sleep state to an operating state includes the second PCS switching from a sleep state to an operating state and the second PMA switching from a sleep state to an operating state.

[0047] In the present application, the second PHY switches from a sleep state to a working state including the second PCS switches from a sleep state to a working state and the first PMA switches from a sleep state to a working state, which can ensure rapid response to service recovery and improve user experience.

[0048] In an optional manner, the second PHY receives a second indication code block sent by the first PHY in the sending device, and the second indication code block is used to indicate that the second PHY switches from a working state to a sleep state, and indicates that a second SerDes corresponding to the second PHY switches from a working state to a keep-alive state; the second PHY switches the second PHY from a working state to a sleep state and switches the second SerDes corresponding to the second PHY from a working state to a keep-alive state according to the second indication code block.

[0049] In the present application, the receiving device receives the second indication code block from the sending device, so that the receiving device switches the state of the PHY according to the second indication code block, and the PHY of the receiving device switches from the working state to the sleeping state, and the corresponding SerDes switches from the working state to the keep-alive state. In this way, when the Ethernet device is not working, the PHY is in the sleeping state, and the corresponding SerDes is in the keep-alive state, which can save the power consumption of the physical layer.

[0050] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the second PHY switching from a working state to a sleep state includes the second PCS switching from a working state to a sleep state and the second PMA switching from a working state to a sleep state.

[0051] In the present application, the second PHY switches from a working state to a sleep state including the second PCS switches from a working state to a sleep state and the second PMA switches from a working state to a sleep state, which can ensure a quick response to service stoppage and save power consumption.

[0052] In an optional manner, the second PMA switches the second PMA from a sleep state to a working state according to the first indication code block; the second PMA sends the first indication information to the second PCS; the second PCS receives the first indication information and switches the second PCS from a sleep state to a working state.

[0053] In the present application, the second PMA switches the second PMA from a sleep state to a working state according to the first indication code block. The first indication code block can be directly transmitted to the second PCS, and the first indication information can be obtained and the first indication information can be transmitted to the second PCS to enable the second PCS to switch the state. Regardless of which method is used, it can ensure that the second PCS and the second PMA are switched from a sleep state to a working state, which can ensure rapid business recovery and improve data processing efficiency.

[0054] In an optional manner, the second PMA switches the second PMA from a working state to a sleep state according to a second indication code block; the second PMA sends second indication information to the second PCS; the second PCS receives the second indication information and switches the second PCS from a working state to a sleep state.

[0055] In the present application, the second PMA switches the second PMA from a working state to a sleep state according to the second indication code block, and the second indication code block can be directly transmitted to the second PCS. The second indication information can also be obtained and the second indication information can be transmitted to the second PCS to enable the second PCS to switch the state. Regardless of which method is used, it can ensure that the second PCS and the second PMA are switched from the sleep state to the working state, which can ensure that the business is quickly stopped and the data processing efficiency is improved.

[0056] In an optional manner, the second PCS includes multiple second PCS channels, and the second PCS switches the multiple second PCS channels from a sleep state to a working state; or, the second PCS switches some of the multiple second PCS channels from a sleep state to a working state according to a first service flow rate threshold.

[0057] In the present application, when the service is restored, part or all of the second PCS channels can be switched from the sleep state to the working state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring the normal transmission of the service.

[0058] In an optional manner, the second PCS includes multiple second PCS channels, and the second PCS switches the multiple second PCS channels from a working state to a sleep state; or, the second PCS switches some of the multiple second PCS channels from a working state to a sleep state according to a second service flow rate threshold.

[0059] In the present application, when the service is stopped, part or all of the second PCS channels can be switched from the working state to the sleeping state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring the normal transmission of the service.

[0060] In an optional manner, the second PHY includes a second physical medium dependent PMD, and the second PHY switches the second PMD from a keep-alive state to a working state according to the first indication code block; the second PHY switches the second SerDes corresponding to the second PMD from a keep-alive state to a working state.

[0061] In the present application, the second PMD is switched from the keep-alive state to the working state, and the second SerDes corresponding to the second PMD is switched from the keep-alive state to the working state, which can ensure rapid response to service recovery and improve user experience.

[0062] In an optional manner, the second PMD includes multiple second PMD channels, and the second PMD switches the multiple second PMD channels from a keep-alive state to a working state; or, the second PMD switches some of the multiple second PMD channels from a keep-alive state to a working state according to a first service flow rate threshold.

[0063] In the present application, when the service is restored, part or all of the second PMD channels can be switched from the keep-alive state to the working state based on the actual service traffic demand. This method can further save the power consumption of the physical layer while ensuring the normal transmission of the service.

[0064] In an optional manner, the second PCS includes multiple second PCS channels, and the second PCS receives the second indication information via at least one second PCS channel among the multiple second PCS channels.

[0065] In an optional manner, when the second SerDes is in a keep-alive state, the second PHY periodically receives a keep-alive code block via the second SerDes.

[0066] In an optional manner, the length of the first indication code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0067] In a third aspect, an embodiment of the present application provides a data processing method, which is applied to a sending device, the sending device includes a first MAC layer and a first PHY, and the sending device can be a device in Ethernet or a device in Hyper Ethernet, such as a switch, a router, etc., which is not specifically limited here. The method is performed as follows:

[0068] The first PHY receives second indication information from the first MAC layer, where the second indication information is used to instruct the sending device to stop sending the service flow to the receiving device; the first PHY obtains a second indication code block according to the second indication information, where the second indication code block is used to instruct the second PHY of the receiving device to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; the first PHY sends the second indication code block to the receiving device.

[0069] In an optional manner, the first PHY switches the first PHY from a working state to a sleep state and switches the first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information.

[0070] In an optional manner, the first PHY includes a first PCS and a first PMA, and the first PHY obtains a second indication code block according to the second indication information, including:

[0071] The first PCS switches the first PCS from the working state to the sleeping state according to the second indication information, and obtains the second indication code block; the first PCS sends the second indication code block to the first PMA; the first PMA switches the first PMA from the working state to the sleeping state according to the received second indication code block.

[0072] In an optional manner, the first PHY obtains the second indication code block according to the second indication information, including:

[0073] The first PCS switches the first PCS from the working state to the sleeping state according to the second indication information, and sends the second indication information to the first PMA; the first PMA switches the first PMA from the working state to the sleeping state according to the received second indication information, and obtains the second indication code block.

[0074] In an optional manner, the first PCS includes a plurality of first PCS channels, wherein the first PCS switches the first PCS from a working state to a dormant state according to the second indication information, including:

[0075] The first PCS switches the multiple first PCS channels from a working state to a dormant state; or, the first PCS switches some of the multiple first PCS channels from a working state to a dormant state according to a second service flow rate threshold.

[0076] In an optional manner, the first PCS includes multiple first PCS channels, and the first PCS sends a second indication code block to the first PMA, including:

[0077] The first PCS sends a second indication code block via at least one first PCS channel among the plurality of first PCS channels.

[0078] In an optional manner, when the first SerDes is in a keep-alive state, the first PHY periodically sends a keep-alive code block to the receiving device via the first SerDes.

[0079] In an optional manner, the length of the second indication code block is 10 bits, 64 bits, 66 bits, 128 bits, or 130 bits.

[0080] In a fourth aspect, the present application provides a data processing method, which is applied to a receiving device, the receiving device includes a second physical layer PHY, and the receiving device can be a device in Ethernet or a device in Hyper Ethernet, such as a switch, a router, etc., which is not specifically limited here. The method is performed as follows:

[0081] The second PHY receives a second indication code block sent by the first PHY in the sending device, and the second indication code block is used to instruct the second PHY to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; the second PHY switches the second PHY from a working state to a sleep state and switches the second SerDes corresponding to the second PHY from a working state to a keep-alive state according to the second indication code block.

[0082] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the second PHY switching from a working state to a sleep state includes the second PCS switching from a working state to a sleep state and the second PMA switching from a working state to a sleep state.

[0083] In an optional manner, the second PHY switches the second PHY from a working state to a sleep state according to the second indication code block, including:

[0084] The second PMA switches the second PMA from the working state to the sleeping state according to the second indication code block; the second PMA sends the second indication information to the second PCS; the second PCS receives the second indication information and switches the second PCS from the working state to the sleeping state.

[0085] In an optional manner, the second PCS includes multiple second PCS channels, and the second PCS receives the second indication information, including:

[0086] The second PCS receives the second indication information via at least one second PCS channel among the plurality of second PCS channels.

[0087] In an optional manner, the second PCS includes a plurality of second PCS channels, wherein the second PCS receives the second indication information and switches the second PCS from a working state to a sleeping state, including:

[0088] The second PCS switches the plurality of second PCS channels from a working state to a dormant state; or, the second PCS switches some of the plurality of second PCS channels from a working state to a dormant state according to a second service flow rate threshold.

[0089] In an optional manner, when the second SerDes is in a keep-alive state, the second PHY periodically receives a keep-alive code block via the second SerDes.

[0090] In an optional manner, the length of the second indication code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0091] In a fifth aspect, an embodiment of the present application provides a data processing device, which may be a sending device (such as the sending device in the first aspect, the sending device in the second aspect, the sending device in the third aspect, or the sending device in the fourth aspect) or a chip disposed inside the sending device, or a receiving device (such as the receiving device in the first aspect, the receiving device in the second aspect, the receiving device in the third aspect, or the receiving device in the fourth aspect) or a chip disposed inside the receiving device. The communication device has the function of implementing any aspect of the first to fourth aspects above, for example, the data processing device includes a module or unit or means corresponding to the steps involved in executing any aspect of the first to fourth aspects above, and the function or unit or means may be implemented by software, or by hardware, or the corresponding software may be implemented by hardware.

[0092] In one possible design, the data processing device includes a processing unit and a transceiver unit, wherein the transceiver unit can be used to send and receive indication code blocks or indication information to realize communication between the data processing device and other devices; the processing unit can be used to perform some internal operations of the data processing device. The transceiver unit can be called an input-output unit, a communication unit, etc., and the transceiver unit can be a transceiver; the processing unit can be a processor. When the data processing device is a module (such as a chip) in a communication device, the transceiver unit can be an input-output interface, an input-output circuit or an input-output pin, etc., and can also be called an interface, a communication interface or an interface circuit, etc.; the processing unit can be a processor, a processing circuit or a logic circuit, etc.

[0093] In another possible design, the data processing device includes a processor and may also include a transceiver, the transceiver is used to send and receive signals, and the processor executes program instructions to complete the method in any possible design or implementation of the first to fourth aspects above. The data processing device may also include one or more memories, the memory is used to couple with the processor, and the memory can store the necessary computer programs or instructions for implementing the functions involved in any of the first to fourth aspects above. The processor can execute the computer program or instructions stored in the memory, and when the computer program or instructions are executed, the data processing device implements the method in any possible design or implementation of the first to fourth aspects above.

[0094] In another possible design, the data processing device includes a processor, which can be used to couple with a memory. The memory can store necessary computer programs or instructions for implementing the functions involved in any one of the first to fourth aspects. The processor can execute the computer program or instructions stored in the memory, and when the computer program or instructions are executed, the data processing device implements the method in any possible design or implementation of the first to fourth aspects.

[0095] In another possible design, the data processing device includes a processor and an interface circuit, wherein the processor is used to communicate with other devices through the interface circuit and execute the method in any possible design or implementation of the first to fourth aspects above.

[0096] It can be understood that in the fifth aspect above, the processor can be implemented by hardware or by software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc.; when implemented by software, the processor can be a general-purpose processor, which is implemented by reading the software code stored in the memory. In addition, the above processors can be one or more, and the memories can be one or more. The memory can be integrated with the processor, or the memory can be separately set from the processor. In the specific implementation process, the memory can be integrated with the processor on the same chip, or can be set on different chips respectively. The embodiment of the present application does not limit the type of memory and the setting method of the memory and the processor.

[0097] In a sixth aspect, an embodiment of the present application provides a data processing system, which includes a sending device and a receiving device in the above-mentioned first to fourth aspects.

[0098] In a seventh aspect, the present application provides a chip, which includes a processor and may also include a memory, for implementing the method described in any possible design in the first to fourth aspects above. The chip system may be composed of a chip, or may include a chip and other discrete devices.

[0099] In an eighth aspect, the present application provides an integrated circuit, comprising an interface circuit and a control circuit, wherein the interface circuit is coupled to the control circuit; the interface circuit is used to receive first indication information from a first MAC layer through a first PHY, the first indication information being used to instruct a sending device to send a service flow to a receiving device; the control circuit is used to obtain a first indication code block through the first PHY according to the first indication information, the first indication code block being used to instruct a second PHY of the receiving device to switch from a sleep state to a working state, and to instruct a second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the interface circuit is also used to send the first indication code block to the receiving device through the first PHY.

[0100] In a ninth aspect, the present application provides another integrated circuit, which includes an interface circuit and a control circuit, and the interface circuit is coupled to the control circuit; the interface circuit is used to receive a first indication code block sent by a first PHY in a sending device through a second PHY, and the first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct the second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the control circuit is used to switch the second PHY from a sleep state to a working state and switch the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block through the second PHY.

[0101] In the tenth aspect, the present application also provides a computer-readable storage medium, in which computer-readable instructions are stored. When the computer-readable instructions are executed on a computer, the computer executes a method in any possible design of the first to fourth aspects.

[0102] In an eleventh aspect, the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the methods of the embodiments of the first to fourth aspects described above.

[0103] For the technical effects that can be achieved by the above-mentioned second to eleventh aspects, please refer to the description of the technical effects that can be achieved by the corresponding possible design schemes in the above-mentioned first aspect, and this application will not repeat them here. BRIEF DESCRIPTION OF THE DRAWINGS

[0104] Figure 1 A schematic diagram of interface composition and communication is shown;

[0105] Figure 2A A schematic diagram of the composition and communication of an electrical chip interface is shown;

[0106] Figure 2B A schematic diagram of a PCS logic function is shown;

[0107] Figure 2C Another schematic diagram of PCS logic function is shown;

[0108] Figure 2D A schematic diagram of a PMD logic function is shown;

[0109] Figure 2E A schematic diagram of implementing PHY through an electrical chip and an optical module chip is shown;

[0110] Figure 2F A schematic diagram of a channel for implementing 100GE PHY through an electrical chip and an optical module chip is shown;

[0111] Figure 3 A schematic diagram of a data processing flow is shown;

[0112] Figure 4 A schematic diagram of the structure of SerDes and PHY is shown;

[0113] Figure 5 A schematic diagram of transmission of a keep-alive code block is shown;

[0114] Figure 6 A schematic diagram of a data processing flow is shown;

[0115] Figure 7 A schematic diagram of a data processing flow is shown;

[0116] Figure 8 A schematic diagram of a data processing flow is shown;

[0117] Fig. 9 A schematic diagram of the structure of a communication device provided in an embodiment of the present application is shown;

[0118] Fig.10 A schematic diagram showing the structure of another data processing device is shown;

[0119] Fig.11 A structural schematic diagram of another data processing device is shown. DETAILED DESCRIPTION

[0120] In this application, the media independent interface (MII) is referred to as MII at 10 Mb / s and 100 Mb / s, as GMII at 1000 Mb / s, and as XGMI at 10 Gb / s. The xMII in the present application may include RMII (reduced MII), serial MII (serial MII, SMII), serial synchronous MII (serial sync MII, SSMII), source synchronous SMII (source synchronous SMII, S3MII), Gigabit MII (Gigabit MII, GMII), RGMII (Reduced GMII), serial GMII (serial GMII, SGMII), 10 bit interface (ten bit interface, TBI), RTBI (Reduced TBI), 10 Gigabit MII (10Gigabit MII, XGMII), 25 Gigabit MII (25GigabitMII), 40 Gigabit MII, 50 Gigabit MII, 100 Gigabit MII (100Gb / s MII, CGMII), 200 Gigabit MII (200Gb / s MII, 200GMII), 400 Gigabit MII (400Gb / s MII, 400GMII), 800 Gigabit MII, 1.6 Terabit MII and other Ethernet interfaces.

[0121] The 200GbE / 400GbE rate standard realizes a new generation of Ethernet rate standards based on the single-channel electrical interface 50G four-level pulse amplitude modulation (PAM4) technology. In the research of the next-generation Ethernet 800G / 1.6TE standard, as the single-channel electrical interface rate increases to 100G PAM4 or 200G (using N-level pulse amplitude modulation PAM-N, N=4, 6 or 8), the next-generation rate may support the electrical interface rate and may need to be compatible with the old 50G electrical interface per channel. The optical interface rate has the possibility of multiple evolution routes such as 50Gbps / 100Gbps / 200Gbps / 400Gbps / 800Gbps per wavelength.

[0122] There are many Ethernet interface logic layer solutions at present. There are some common features and obvious differences between the interface logic layers of different rates. These differences make it difficult to share hardware resources between different rates, or to bind multiple low-rate Ethernet interfaces to a high-rate interface module for intercommunication. For example, on the 200GbE / 400GbE interface, Figure 1 The logical layer architecture. Figure 1 In the MAC layer, the device interface includes the medium access control (MAC) layer, the adaptation sublayer (RS), the physical coding sublayer (PCS), the cascaded forward error correction (FEC), the physical medium attachment (PMA) and the physical media dependent (PMD), among which PCS, FEC, PMA and PMD belong to the physical layer (PHY). The data of the transmitting device is sent from the PMD to the PMD of the receiving device after processing, and reaches the MAC layer after being processed by multiple submodules. The PCS sublayer is used to implement functions such as 64B / 66B encoding and decoding, transcoding, scrambling, alignment marker (AM) insertion, FEC encoding and decoding; the PMA sublayer is used to implement functions such as clock recovery, carrier detection, PAM4 modulation / demodulation; the PMD sublayer is used to convert the received data into parallel-to-serial / serial-to-parallel and modulate the digital signal to the line for transmission. Among them, in the FEC sublayer of PCS, the introduction of new interleaved FEC (such as Reed-Solomon RS (544, 514) FEC) makes its logical layer very different from the 100GbE solution, and the workload of redevelopment is large. For example, the logical layer defined by 400G-ZR adopts Figure 2A The architecture shown. Figure 2A A schematic diagram of the composition of an electrical chip interface is shown. Under this logical layer architecture, an optical module that supports 400G-ZR (80km) cannot support a 2*200GbE interface because the host side interface is fixed to 400GAUI (attachment unit interface, AUI).

[0123] Figure 1 as well as Figure 2A The data transmission scenario can be applicable to Ethernet, or Hyper Ethernet and other similar data communication systems such as unified bus (UB), infinite bandwidth (IB), peripheral component interconnect express (PCIE), etc., which are not specifically limited in this application. The sending device and the receiving device can be switches and routers, etc., which are not specifically limited in this application. In addition, it should be noted that Figure 1There is only one sending device and receiving device shown in the figure, but in actual application, the data processing scenario may include multiple sending devices and receiving devices, and the sending device can also be used as a receiving device, and the receiving device can also be used as a sending device. This application does not specifically limit this.

[0124] In order to more clearly illustrate the scheme of the present application, PHY is described in detail, and PHY includes PCS, PMA, and PMD. It should be noted that PCS, PMA, and PMD are sublayers of PHY. Among them, a channel (lane) is set between PCS and PMA, between the PMA of the electrical chip and the PMA of the optical module chip, between PMD and the medium (Medium), and between PMA and PMD. For example, there is a logical lane between PCS and PMA, which can also be called PCS lane; there may also be another logical lane between PCS and PMA, which can also be called FEC lane; there may be a physical lane between the PMA of the electrical chip and the PMA of the optical module chip, which can also be called PMA lane; in addition, there may also be a logical lane between the PMA layer and PMD; there may be a physical lane between PMD and the medium, which can also be called PMD lane. Among them, the logical lane is also called a virtual lane. The number of channels can be configured according to actual needs, and the specific number is not limited. For example, the number of PCS lanes is set to 8, 10, 12 or 16. This is only an example and does not specifically limit the number of logical channels.

[0125] Among them, PCS is usually connected to the MAC chip via MII. Specifically, PCS is connected to the RS in the MAC chip via MII. In PHY, the main function of PCS is to reduce overhead and have certain error detection and correction capabilities. For example, in the sending device, PCS includes a 64B / 66B encoding module, which converts the 72B code block into 66B, thereby reducing overhead. PCS can also include a 256B / 257B encoding module, which compresses every 4 66B code blocks into 1 257B code block, thereby further reducing overhead. PCS can also include an scrambling module, which is used to change the sequence content so that the number of 0s and 1s in the data sequence is balanced, and to ensure the frequency of 0 / 1 jumps to facilitate the operation of the phase-locked loop of the receiving device. Among them, a sufficiently long random number cycle period prevents malicious intrusion from causing the phase-locked loop to fail. PCS can also include a distribution and interleaving module, which is used to distribute the two RS codewords into PCS lanes after the encoding is completed, and the codewords A / B are interleaved on each PCS lane to achieve the interleaving effect. PCS can also include an AM insertion module, which is used to enable the receiving device to find the boundaries of the RS codewords. In addition, PCS can also include FEC, which is used to improve the error detection and correction capabilities of PHY.

[0126] Among them, the logical functions that PCS can perform are as follows: Figure 2B and 2C As shown, Figure 2B Indicates the logical functions of 40G BASE-R and 100G BASE-R, Figure 2C Indicates the logical functions of 200G BASE-R and 400G BASE-R, Figure 2C Relative to Figure 2B For the 40G BASE-R, FEC is added, and there are some adjustments to the execution logic. Among them, 40G BASE-R, 100G BASE-R, 200G BASE-R and 400GBASE-R represent the type of PHY. Take 40G BASE-R as an example: "40G" represents the rate, "BASE" represents the modulation type is Baseband (bandwidth modulation), and "R" represents the use of 64B / 66B encoding. Figure 2BLet's first introduce the logical functions of PCS. After the PCS of the sending device receives the data information from MAC, it encodes it through the encoding module (encode) to obtain a code block, scrambles the code block through the scramble module (scramble) to obtain a scrambled code block, distributes the scrambled code block through the distribution module (Block Distribution), inserts AM (alignment marker) into the scrambled code block through the AM insertion module, and then transmits the data to PMA through the logical channel. The data processing logic of PMA and the layers behind PMA will not be described in detail here. The PCS of the receiving device receives the code block from PMA, synchronizes the code blocks of each virtual channel through the block synchronization module (lane BLOCK SYNC), and then eliminates the SKEW between the PCS virtual channels through the SKEW elimination module (AlignmentLOCK lane DESKEW). After eliminating the SKEW between the PCS virtual channels, the sorting module (Lane Reorder) sorts the data stream based on the PCS virtual channel so that the data stream can enter the correct PCS lane. The AM in the code block is removed by the AM removal module (Alignment Removal), and then the code block is descrambled by the descrambler module (Descramble), and then the data information is decoded by the decoder module (decode). Among them, SKEW is a processing module used to eliminate the skew between PCS lanes. Specifically, after the AM operation is completed, the PCSlane will be skewed, so the SKEW module is used to eliminate the skew to ensure alignment with the physical lane in the subsequent processing.

[0127] Next reference Figure 2CLet's introduce the logical functions of PCS. Since 200G BASE-R and 400G BASE-R are larger, after the PCS of the sending device receives the data information from the MAC, it encodes and rate matches the encoding and rate matching module to obtain the encoding block, and converts the four 66-bit blocks in the encoding block into a 257-bit block through the encoding conversion module (256B / 257B Transcode). Then, the encoding block is scrambled by the scrambling module (Scramble) to obtain a scrambled encoding block, and the insertion module (Alignment Insertion) inserts AM into the scrambled encoding block. Then, the FEC distribution module (Pre-FEC Distribution) distributes it according to symbol splitting before FEC encoding, and then the FEC encoding module (FEC encoder) performs FEC encoding, and then the distribution and symbol interleaving processing is performed by the distribution and interleaver module (Distribution and Interleaver), and then the data is transmitted to the PMA through the logical lane. The data processing logic of PMA and the layers after PMA is not described in detail here. The PCS of the receiving device receives the code blocks from PMA, eliminates the SKEW between the PCS virtual lanes through the SKEW elimination module (Alignment LOCK lane DESKEW), and then sorts and deinterleaves the data stream through the sorting and deinterleaving module (Lane Reorderand de-Interleaver), then performs FEC decoding through the FEC decoding module (FEC decode), and then deinterleaves the symbols after FEC decoding through the symbol deinterleaving module (Post FEC de_interleaver), eliminates AM in the code blocks through the AM elimination module (Alignment Removal), and then descrambles the code blocks through the descrambling module (Descramble), and then converts 257-bitblocks to 66-bit blocks through the code block conversion module (Reverse transcode), and then performs encoding and decoding and rate matching through the decoding module and rate matching module (decode and ratematching) to obtain data information.

[0128] It should be noted that 200GBASE-R and 400GBASE-R PCS provide all services required for MII with a MAC layer rate of 200G and MII with a MAC layer rate of 400G (hereinafter referred to as 200GMI / 400GMII), including the following:

[0129] a) Encode (decode) 8 200GMI / 400GMII data bytes to (from) 66-bit blocks (64B / 66B).

[0130] b) Transcode from 66-bit blocks to 257-bit blocks, and then perform scrambling (descrambling) processing.

[0131] c) Reed-Solomon encoded (decoded) 257-bit blocks.

[0132] d) transmitting the encoded data to the PMA or transmitting the encoded data to the PMA after interleaving.

[0133] e) Compensate for any rate difference due to insertion or deletion of alignment marks or due to any rate difference between 200GMII / 400GMII and PMA by inserting or deleting idle control characters.

[0134] f) Determine when a functional link is established and notify the management entity via management data input / output (MDIO) when the PHY is ready for use.

[0135] It should also be noted that the main functions of the PMA in the transmit and receive directions include the following:

[0136] a) Adapt PCS lane formatted signals to the appropriate number of abstract or physical lanes.

[0137] b) Provide clock and data recovery for each input lane.

[0138] c) Provide bit-level multiplexing.

[0139] d) Provide clock generation.

[0140] e) Provide signal drive.

[0141] f) Optionally provide local loopback to or from the PMA service interface.

[0142] g) Optionally provide remote loopback to the PMD service interface or remote loopback from the PMA service interface.

[0143] h) Optionally provide test pattern generation and detection.

[0144] i) Allow SKEW variation.

[0145] j) Perform PAM4 encoding and decoding for 200GBASE-R PMA with 4 physical lanes and 400GBASE-R PMA with 4 or 8 physical lanes.

[0146] Among them, PMA is used for modulation and demodulation, and the commonly used channel transmission modulation formats include: non-return-to-zero (NRZ), PAM4, and 16-quadrature amplitude modulation (16-QAM). In addition, PMA is also used to implement clock and data recovery (CDR) and signal drive, among which CDR is used to extract the clock from the received signal and recover it to binary data to achieve analog to digital conversion; signal drive is used to provide power drive for attachment unit interface (AUI) signal transmission to achieve digital to analog conversion.

[0147] Among them, PMD implements the transmitter of electrical / optical signals and the connector with the transmission medium.

[0148] In addition, after the PMD service interface of the sending device receives data from the PMA, Figure 2D As shown, data can be transmitted to a receiving device after Gray coding (GRAY), precoding and other operations.

[0149] It should be noted that the embodiments of the present application Figure 1 The implementation method of PHY is explained by using an electrical chip. Figure 1 The PMD of the transmitting device is used to connect the electrical transmission medium.

[0150] In actual application scenarios, PHY can also be implemented through an electrical chip ( Figure 2E ) and the optical module chip ( Figure 2E (indicated by dotted lines in the figure) is realized by cooperation, such as Figure 2E shown.

[0151] For example, PHY includes an electrical chip and an optical module chip. The electrical chip includes a PCS and a PMA. The PCS of the electrical chip is connected to the RS of the MAC chip through the MII, and the PMA of the electrical chip is connected to the PMA in the optical module chip through the AUI. In addition, the optical module chip also includes a PMD, and the PMD of the optical module chip is connected to the optical transmission medium through a medium dependent interface (MDI).

[0152] For another example, PHY includes an electrical chip, a PMA module, and an optical module chip. The electrical chip includes a PCS and a PMA. The PCS of the electrical chip is connected to the RS of the MAC chip through the MII, and the PMA of the electrical chip is connected to the PMA module through the AUI, wherein the PMA module can be implemented by an independent chip. The PMA module is connected to the PMA in the optical module chip through the AUI. In addition, the optical module chip also includes a PMD, and the PMD of the optical module chip is connected to the optical transmission medium through the MDI.

[0153] Under the above architecture, for example, the 100GE PHY is implemented by using the architecture of electrical chips, PMA modules and optical module chips, such as Figure 2F As shown. Usually, the PCS lane included in the PCS is a logical lane, such as 4 25G PCS lanes; correspondingly, the PCS can also include 4 25G FEC lanes (logical lanes). The PMA in the electrical chip includes 4 25G PMA lanes (physical lanes), corresponding to 4 25G PCS lanes, and the PMA in the electrical chip includes 4 25G PMA lanes connected to the PMA module. Correspondingly, the PMA module can include 2 50G PMA lanes (physical lanes), and the 2 50G PMA lanes of the PMA module are used to connect the PMA in the optical module chip. The PMA in the optical module chip includes 1 100G PMA lane (logical lane), corresponding to 2 50G PMA lanes, and 1 100G PMA lane is used to connect the PMD in the optical module chip. The PMD in the optical module chip includes one 100G PMD lane (physical lane), which corresponds to one 100G PMA lane. The PMD in the optical module chip includes one 100G PMD lane for connecting the medium.

[0154] In the above architecture, AUI is the channel for chip interconnection. SerDes is usually used for serial-to-parallel conversion on both sides of AUI. Therefore, the serializer / deserializer (SerDes) implements some functions of PMA in PHY. In addition, PMD is the connector of the transmission medium, and the function of PMD is usually implemented by SerDes. Therefore, SerDes is mainly used to implement the functions of PMA and PMD in PHY. In other words, SerDes implements some functions of the PHY protocol layer in a physical form.

[0155] It should be noted that SerDes is a serial-to-parallel signal conversion device that converts parallel signals into parallel-to-serial (serialization) and serial-to-parallel (deserialization) conversion of serial signals. SerDes is part of PHY. Traditional parallel buses are generally single-ended signal transmissions, which can be multi-point connections or point-to-point connections, with clocks and data separated. When the data rate is further increased, the bandwidth can be increased by increasing the bus width and increasing the clock rate, but the clock must be coordinated (the data and clock need to meet strict setup and hold times, there is crosstalk between signals, the ability to resist common-mode interference is weak, the equipment has electromagnetic interference (EMI) problems, and it takes up too much printed circuit board (PCB) space, etc.), and its bus clock rate can only reach hundreds of megabits. The high-speed serial data bus overcomes the shortcomings of the parallel bus and increases the data transmission rate by several levels. SerDes has the following advantages:

[0156] 1) Use serial signals to reduce the difficulty of single-board wiring, reduce the impact of crosstalk between signals, and reduce the difficulty of timing design;

[0157] 2) Eliminate the skew problem of parallel signal transmission and increase data transmission rate;

[0158] 3) No special clock signal is required (the clock is directly recovered from the data), data and clock are transmitted on one chip pin, which greatly saves pins, reduces packaging costs and saves board space; there is no separate clock, and the clock signal is extracted from the data.

[0159] 4) Using serial differential data bus output can improve the ability to resist common mode interference;

[0160] 5) Through pre-processing on the sending side and filtering on the receiving side, the quality of the signal is improved and the impact of the external environment on the signal is greatly reduced;

[0161] 6) Through SerDes, chips can be connected across boards, which expands the scope of chip use and improves the scalability of the architecture.

[0162] In combination with the above, SerDes corresponds to physical lanes one by one. For example, the PMA in the electrical chip includes four 25G PMA lanes, which means that four SerDes are included in physical form. In the embodiment of the present application, the energy-saving control and state switching control implemented on the SerDes refers to the energy-saving control and state switching control implemented on at least one of the SerDes that implements the PMA function and the SerDes that implements the PMD function.

[0163] As the demand for Ethernet capacity expands, the service requires higher and higher rates for Ethernet links, and the power consumption of PHY is increasing. The relevant technology proposes to turn off SerDes when there is no service transmission to save power consumption. However, when the service is restored, the SerDes recovery work takes a long time. During the SerDes recovery period, a large amount of service data will be cached, and there will be delays in the service data. This method will reduce the user's service experience, and a large amount of service cache may require a chip with a higher rate, which will also increase the cost of equipment. Based on this, a new data processing method is urgently needed to reduce the cache of service data and improve the user experience while saving PHY power consumption. The data processing of this application mainly considers the situation of service suspension and service recovery during service flow transmission.

[0164] See also Figure 3 A flow chart of a data processing method provided in an embodiment of the present application, the method can be executed through data interaction between a sending device and a receiving device, wherein the sending device and the receiving device can be devices in Ethernet, and can also be devices in Hyper Ethernet, which is not specifically limited in the present application, wherein the sending device and the receiving device can be routers, switches, etc. Here, only the data interaction between the sending device MAC layer (also the first MAC layer), PHY (also the first PHY) and the receiving device MAC layer (also the second MAC layer), PHY (also the second PHY) is described, and the data interaction of other layers is not described in detail. Figure 3 Applicable to the scenario of resuming business after suspension. Execute as follows:

[0165] Step 301: The first MAC layer sends first indication information to the first PHY, where the first indication information is used to instruct a sending device to send a service flow to a receiving device.

[0166] Before executing step 301, the sending device has obtained the service flow, and based on the service flow, the first MAC layer of the sending device is triggered to send the first indication information to the first PHY, or the sending device receives an indication message sent by the upper layer device, and the indication message is used to indicate service recovery, so that the first MAC layer of the sending device sends the first indication information to the first PHY. The specific method used to trigger the sending of the first indication information is not specifically limited in this application.

[0167] Specifically, the first indication information may be a data block in a service flow, or may be signaling (or a notification message), etc. This is merely an example, and the present application does not specifically limit the form of the first indication information.

[0168] Refer to the above Figure 2AIt can be seen that the MAC layer includes RS, and the first MAC layer sending the first indication information to the first PHY can be understood as the RS of the MAC chip sending the first indication information to the PCS of the PHY electrical chip through the MII. This is only an exemplary explanation and does not specifically limit the transmission path of the first indication information.

[0169] Step 302: The first PHY obtains a first indication code block according to the first indication information, where the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct the second SerDes corresponding to the second PHY to switch from a keep-alive state to a working state.

[0170] It should be noted that acquisition can be understood as generation, selection, selection, etc. For example, the first PHY generates a first indication code block according to the first indication information, or the first PHY selects (or selects) an indication code block as the first indication code block from the pre-generated indication code blocks according to the first indication information, etc., and the present application does not specifically limit this. When the first indication information is used to generate the first indication code block, the first indication information may be encoded to obtain the first indication code block. When the first indication information is used to select the first indication code block, the first PHY may pre-select the corresponding relationship between the stored indication information and the indication code block, and determine the first indication code block based on the acquired first indication information and the corresponding relationship. This is only an exemplary description.

[0171] The sleep state in this application can be understood as a non-working state, a state of not processing business, and a state of not transmitting business flow; the working state can be understood as a state of transmitting business flow and processing business; the keep-alive state can be understood as a standby state, and once a business-related trigger message or instruction is received, it immediately returns to the working state. The following descriptions regarding the sleep state, working state, and keep-alive state can be understood by referring to this.

[0172] It should also be noted that the first PHY can switch the first PHY from a sleep state to a working state and switch the first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information. The first PHY can directly refer to the first indication information to adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY, and can also obtain the first indication code block based on the first indication information, and adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY according to the first indication code block, which is not specifically limited in this application. When the first PHY resumes work, the first PHY switches the first PHY from a sleep state to a working state and switches the first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information, which can ensure rapid response to service recovery and improve user experience.

[0173] In addition, the first SerDes corresponding to the first PHY (or the second SerDes corresponding to the second PHY) can be provided together with the PHY in one chip, or can be provided separately from the PHY in a different chip, which is not specifically limited in the present application. Figure 1 It can be seen that PHY also includes PCS, PMA and PMD, etc. In addition, as mentioned in the above introduction of SerDes, SerDes is mainly used to implement the functions of PMA and PMD in PHY, the AUI of PMA can be implemented through SerDes, and the PMD connection medium can also be implemented through SerDes. SerDes needs to be switched to a working state, and all SerDes can be switched in state, or some SerDes can be switched in state (such as switching the SerDes implemented by the AUI of PMA to a working state, and not switching the SerDes implemented by the PMD connection medium). This application is not specifically limited here. In actual applications, the SerDes implemented by the AUI of PMA and the SerDes implemented by the PMD connection medium can be implemented by two different chips, or by the same chip, see Figure 2F If the same chip is used, the SerDes implemented by the AUI of the PMA and the SerDes implemented by the PMD connection medium belong to two different hardware units, which are not specifically limited here. The following can refer to this to understand the working state switching of the SerDes, and will not be repeated elsewhere.

[0174] Here, the first PHY includes a first PCS, a first PMA, and a first PMD, and the second PHY includes a second PCS, a second PMA, and a second PMD. Figure 4 As shown, the first SerDes is set in the first PMD, and the second SerDes is not set in the second PMD. That is, the SerDes that implements the PMD function can be set in the PHY chip or not. Figure 4The chips of the transmitting device and the receiving device shown are electrical chips, the first SerDes can be arranged in the electrical chip PMD, the second SerDes can be arranged independently of the electrical chip PMD, and no matter how they are arranged, the SerDes are connected through an electrical interface. In addition, it should be noted that when the chips of the transmitting device and the receiving device are optical module chips, the first SerDes can be arranged in the optical module chip PMD, the second SerDes can be arranged independently of the optical module chip PMD, and no matter how they are arranged, the SerDes are connected through an optical interface. If the SerDes is not arranged in the PMD, the switching of the PHY from the dormant state to the working state includes the switching of the PCS from the dormant state to the working state, the switching of the PMA from the dormant state to the working state, and the switching of the PMD from the dormant state to the working state. If the SerDes is arranged in the PMD, the switching of the PHY from the dormant state to the working state means that the PCS is switched from the dormant state to the working state and the PMA is switched from the dormant state to the working state, and at this time, the PMD is switched from the keep-alive state to the working state.

[0175] In addition, when the first PHY includes a first PCS, a first PMA, and a first PMD, when executing step 302, the first PCS may switch the first PCS from a dormant state to a working state according to the first indication information, and obtain a first indication code block; the first PCS sends the first indication code block to the first PMA; the first PMA switches the first PMA from a dormant state to a working state according to the received first indication code block. Alternatively, the first PCS switches the first PCS from a dormant state to a working state according to the first indication information, and sends the first indication information to the first PMA; the first PMA switches the first PMA from a dormant state to a working state according to the received first indication information, and obtains the first indication code block. Of course, in actual application, the first PCS may switch the first PCS from a dormant state to a working state according to the first indication information, and send the first indication information to the first PMA; the first PMA switches the first PMA from a dormant state to a working state according to the received first indication information, and sends the first indication information to the first PMD, and the first PMD may switch from a dormant state (or a keep-alive state) to a working state according to the first indication information, and obtain the first indication code block. No matter which method is adopted, it can ensure that the first PHY is switched from the sleep state to the working state, which can ensure rapid service recovery and improve data processing efficiency.

[0176] In addition, when the first SerDes is set in the first PMD, the first PHY can switch the first PMD from the keep-alive state to the working state according to the first indication information, and switch the first SerDes corresponding to the first PMD from the keep-alive state to the working state.

[0177] It should also be noted that the first PCS and the first PMA of the first PHY transmit data through logical channels, and the number of the logical channels can be flexibly set according to business needs, such as 100GE PHY, including 4 25G PCS lanes. The first PMD transmits data through a physical channel, and the number of the physical channels is limited and cannot be expanded arbitrarily. However, in actual business transmission, the logical channel and the physical channel can correspond one-to-one, such as one logical channel corresponding to one physical channel, or it can be many-to-one for the logical channel and the physical channel, such as 4 logical channels corresponding to one physical channel. Usually during data transmission, the sending device and the receiving device can predefine in advance which channels are used to transmit data. Of course, when switching the data transmission channel, the sending device can also send an indication signaling to the receiving device in advance to notify the switched data transmission channel before transmitting data. This application does not specifically limit this. Regarding the logical channel, the PCS channel is taken as an example to illustrate that the first PCS includes multiple PCSlanes, and the first PCS switches multiple PCS lanes from a sleep state to a working state. For example, the first PCS sets 16 PCSlanes, and all 16 PCS lanes can be switched from a sleep state to a working state; or, the first PCS switches some of the multiple first PCS channels from a sleep state to a working state according to the first business flow rate threshold. For example, the business flow rate is W, the first business flow rate threshold is W1, and W is less than W1, then 10 PCS lanes can be switched from a sleep state to a working state. In addition, the first PCS can send the first indication code block via at least one first PCS channel among the multiple first PCS channels (if all the above PCS lanes are switched from the sleep state to the working state, all the PCS lanes are used to send the first indication code block, such as using 16 PCS lanes to send the first indication code block; if part of the above PCS lanes are switched from the sleep state to the working state, part of the PCS lanes are used to send the first indication code block, such as using 10 PCS lanes to send the first indication code block), as long as the first PMA is guaranteed to receive the first indication code block.

[0178] For the physical channel, the PMD channel is taken as an example to illustrate that the first PMD includes multiple first PMD channels, and the first PMD switches the multiple first PMD channels from the keep-alive state to the working state. For example, the first PMD sets 8 PMD lanes, and all 8 PMD lanes can be switched from the keep-alive state to the working state; or, the first PMD switches some of the multiple PMD lanes from the keep-alive state to the working state according to the first business flow rate threshold. For example, the business flow rate is W, the first business flow rate threshold is W1, and W is less than W1, then 3 PMD lanes can be switched from the keep-alive state to the working state.

[0179] In addition, it should be noted that in actual application, multiple service flow rate thresholds can be set according to demand, and the number of virtual channels and logical channels used to transmit service data can be determined according to different service flow rate thresholds. For example, PCS lanes include 20 lanes, PMD lanes include 16 lanes, and service flow rate thresholds are W1, W2, and W3 (W1>W2>W3). When the service flow rate is less than W1, 10 PCS lanes of the first PCS and 3 PMD lanes of the first PMD are used to transmit service data; when the service flow rate is greater than W1 and less than W2, 12 PCS lanes of the first PCS and 4 PMD lanes of the first PMD are used to transmit service data; when the service flow rate is greater than W2 and less than W3, 15 PCS lanes of the first PCS and 6 PMD lanes of the first PMD are used to transmit service data. This is only an example and is not specifically limited. The following description of service flow rate thresholds can be understood with reference to the description here.

[0180] Step 303: The first PHY sends a first indication code block to the second PHY of the receiving device.

[0181] The length of the first indicator code block may be 10 bits, 64 bits, 66 bits, 128 bits or 130 bits, such as 66-bit Blocks. The following Table 1 shows the data structure of 66-bit Blocks, where Hd represents the head of 66-bit Blocks, the default value is 0x1, and M0-M7 are the payloads of 66-bit Blocks.

[0182] Table 1

[0183]

[0184] Step 304: the second PHY switches the second PHY from the sleep state to the working state and switches the second SerDes corresponding to the second PHY from the keep-alive state to the working state according to the first indication code block.

[0185] In addition, when the second PHY includes a second PCS, a second PMA, and a second PMD, when executing step 304, the second PMA can switch the second PMA from a sleep state to a working state according to the first indication code block; the second PMA sends the first indication information to the second PCS (specifically, the second PMA can obtain the first indication information according to the first indication code block, such as determined according to the mapping relationship between the indication code block and the indication information, or directly generate the first indication information based on the first indication code block, which is not specifically limited here); the second PCS receives the first indication information and switches the second PCS from a sleep state to a working state. Alternatively, the second PMA can switch the second PMA from a sleep state to a working state according to the first indication code block; the second PMA sends the first indication code block to the second PCS; the second PCS receives the first indication code block, and switches the second PCS from a sleep state to a working state. Regardless of which method is used, it can be ensured that the second PHY is switched from a sleep state to a working state, which can ensure rapid service recovery and improve data processing efficiency.

[0186] In addition, when the second SerDes is set in the second PMD, the second PHY can switch the first PMD from the keep-alive state to the working state according to the first indication information or the first indication code block, and switch the second SerDes corresponding to the second PMD from the keep-alive state to the working state.

[0187] It should also be noted that the second PCS and the second PMA of the second PHY transmit data through a logical channel, and the number of the logical channels can be flexibly set according to business needs. The second PMD transmits data through a physical channel, and the number of the physical channels is limited and cannot be expanded arbitrarily. However, in actual business transmission, the logical channel and the physical channel can correspond one to one, such as one logical channel corresponding to one physical channel, or it can be many-to-one for the logical channel and the physical channel, such as 4 logical channels corresponding to one physical channel. Usually, during data transmission, the sending device and the receiving device can predefine in advance which channels are used to transmit data. Of course, when switching the data transmission channel, the sending device can also send an indication signaling to the receiving device in advance to notify the switched data transmission channel before transmitting data. This application does not specifically limit this. Regarding the logical channel, the PCS channel is taken as an example to illustrate that the second PCS includes multiple second PCS channels, and the second PCS switches the multiple second PCS channels from the sleep state to the working state. For example, the second PCS sets 16 PCS lanes, and all 16 PCS lanes can be switched from the sleep state to the working state; or, the second PCS switches some of the multiple second PCS channels from the sleep state to the working state according to the first business flow rate threshold. For example, the business flow rate is W, the first business flow rate threshold is W1, and W is less than W1, then 10 PCS lanes can be switched from the sleep state to the working state.

[0188] For the physical channel, the channel of PMA is used as an example to illustrate that the second PMD includes multiple second PMD channels, and the second PMD switches the multiple second PMD channels from the keep-alive state to the working state. For example, the second PMD sets 8 PMD lanes, and the 8 PMD lanes can be switched from the keep-alive state to the working state; or, the second PMD switches some of the second PMD channels in the multiple second PMD channels from the keep-alive state to the working state according to the first service flow rate threshold. For example, the service flow rate is W, the first service flow rate threshold is W1, and W is less than W1, then 3 PMD lanes can be switched from the keep-alive state to the working state. In addition, it should be noted that in actual application, multiple service flow rate thresholds can be set according to demand, and how many logical channels and physical channels are used to transmit service data according to different service flow rate thresholds can be determined. The description of the above step 303 can be referred to for understanding and will not be repeated here.

[0189] It should also be noted that when the first SerDes and the second SerDes are in the keep-alive state, the first PHY periodically sends a keep-alive code block to the receiving device via the first SerDes, and the second PHY periodically receives the keep-alive code block via the second SerDes, wherein the keep-alive code block does not include service information and may be a pseudo-random code block, for example, a keep-alive code block is sent every 5 microseconds, and 10 keep-alive code blocks may be sent. The data transmission of the keep-alive code block may refer to Figure 5 To understand, in case 1, when the first SerDes is set in the first PMD, the keep-alive code block enters the first SerDes in the first PMD through the first PCS and the first PMA of the first PHY, and is transmitted to the second SerDes. The keep-alive code block does not perform data processing through the first PCS and the first PMA, that is, the above-mentioned Figure 2A Or the encoding, interleaving and other processing operations in 2B, directly reach the first SerDes for data processing. In case 2, if the first SerDes is not set in the first PMD, the keep-alive code block enters the first SerDes through the first PCS, the first PMA, and the first PMD of the first PHY, and is transmitted to the second SerDes. The keep-alive code block does not perform data processing through the first PCS, the first PMA, and the first PMD, that is, the above-mentioned operation is not performed. Figure 2A Or the encoding, interleaving and other processing operations in 2B directly reach the first SerDes for data processing.

[0190] In the present application, after the PHY of the sending device receives the first indication information of the MAC layer, it determines that the transmission of the service flow needs to be restored based on the first indication information, and then obtains the first indication code block based on the first indication information, and indicates the first indication code block to the receiving device, so that the receiving device switches the state of the PHY according to the first indication code block, and the PHY of the receiving device switches from the sleep state to the working state, and the corresponding SerDes switches from the keep-alive state to the working state. In this way, when the Ethernet device is not working, the PHY is in the sleep state, and the corresponding SerDes is in the keep-alive state, which can save the power consumption of the physical layer. Once the service is restored, the Ethernet device can respond in time, the PHY switches from the sleep state to the working state, and the SerDes switches from the keep-alive state to the working state. The response is faster when the service is restored, and there is no need to cache a large amount of service data in the service recovery process to wait for the Ethernet device to resume work, which can improve the user experience, and further, it can improve the data processing efficiency.

[0191] See also Figure 6 A flow chart of a data processing method provided in an embodiment of the present application, the method can be executed through data interaction between a sending device and a receiving device, wherein the sending device and the receiving device can be devices in Ethernet, and can also be devices in Hyper Ethernet, which is not specifically limited in the present application, wherein the sending device and the receiving device can be routers, switches, etc. Here, only the data interaction between the sending device MAC layer (also the first MAC layer), PHY (also the first PHY) and the receiving device MAC layer (also the second MAC layer), PHY (also the second PHY) is described, and the data interaction of other layers is not described in detail. Figure 3 Applicable to the scenario where the service is suspended, execute as follows:

[0192] Step 601: The first MAC layer sends second indication information to the first PHY, where the second indication information is used to instruct a sending device to stop sending a service flow to a receiving device.

[0193] Before executing step 601, the sending device fails to obtain the service flow for a preset period of time, such as failing to obtain the service flow within 5 seconds, based on which the first MAC layer of the sending device is triggered to send the second indication information to the first PHY, or the sending device receives an indication message sent by an upper-layer device, which is used to indicate that the service is suspended, so that the first MAC layer of the sending device sends the second indication information to the first PHY. The specific method of triggering the sending of the second indication information is not specifically limited in this application.

[0194] Specifically, the second indication information may be signaling (or notification message), etc. This is only an example, and the present application does not specifically limit the form of the second indication information.

[0195] Refer to the above Figure 2A It can be seen that the MAC layer includes RS, and the first MAC layer sending the second indication information to the first PHY can be understood as the RS of the MAC chip sending the second indication information to the PCS of the PHY electrical chip through the MII. This is only an exemplary explanation and does not specifically limit the transmission path of the second indication information.

[0196] Step 602: The first PHY obtains a second indication code block according to the second indication information, where the second indication code block is used to instruct the second PHY of the receiving device to switch from a working state to a sleeping state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state.

[0197] It should be noted that acquisition can be understood as generation, selection, selection, etc. For example, the first PHY generates a second indication code block according to the second indication information, or the first PHY selects (or selects) an indication code block as the second indication code block from the pre-generated indication code blocks according to the second indication information, etc., and the present application does not specifically limit this. When the second indication information is used to generate the second indication code block, the second indication information can be encoded to obtain the second indication code block. When the second indication information is used to select the second indication code block, the first PHY can pre-select the corresponding relationship between the stored indication information and the indication code block, and determine the second indication code block based on the acquired second indication information and the corresponding relationship. This is only an exemplary description.

[0198] It should also be noted that the first PHY can switch the second PHY from a working state to a sleep state and switch the first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information. The first PHY can directly refer to the second indication information to adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY, and can also obtain a second indication code block based on the second indication information, and adjust the working state of the first PHY and the working state of the first SerDes corresponding to the first PHY according to the second indication code block, which is not specifically limited in this application. When the first PHY suspends work, the first PHY switches the first PHY from a working state to a sleep state and switches the first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information, which can ensure a quick response to service suspension.

[0199] In addition, the first SerDes corresponding to the first PHY (or the second SerDes corresponding to the second PHY) can be provided together with the PHY in one chip, or can be provided separately from the PHY in a different chip, which is not specifically limited in the present application.

[0200] Refer to the above Figure 1It can be seen that PHY also includes PCS, PMA and PMD, etc. Here, the first PHY includes the first PCS, the first PMA, the first PMD, and the second PHY includes the second PCS, the second PMA, and the second PMD. For example, if the SerDes is not set in the PMD, the switching of the PHY from the working state to the sleep state includes the switching of the PCS from the working state to the sleep state, the switching of the PMA from the working state to the sleep state, and the switching of the PMD from the working state to the sleep state. If the SerDes is set in the PMD, the switching of the PHY from the working state to the sleep state means that the PCS switches from the working state to the sleep state and the PMA switches from the working state to the sleep state, and at this time, the PMD switches from the working state to the keep-alive state.

[0201] In addition, when the first PHY includes a first PCS, a first PMA, and a first PMD, when executing step 602, the first PCS may switch the first PCS from a working state to a dormant state according to the second indication information, and obtain a second indication code block; the first PCS sends the second indication code block to the first PMA; the first PMA switches the first PMA from a working state to a dormant state according to the received second indication code block. Alternatively, the first PCS switches the first PCS from a working state to a dormant state according to the second indication information, and sends the second indication information to the first PMA; the first PMA switches the first PMA from a working state to a dormant state according to the received second indication information, and obtains the second indication code block. Of course, in actual application, the first PCS may switch the first PCS from a working state to a dormant state according to the second indication information, and send the second indication information to the first PMA; the first PMA switches the first PMA from a working state to a dormant state according to the received second indication information, and sends the second indication information to the first PMD, and the first PMD may switch from a working state to a dormant state (or a keep-alive state) according to the second indication information, and obtain the second indication code block. Regardless of which method is adopted, it can be ensured that the first PHY is switched from the working state to the sleeping state, and the service can be quickly suspended.

[0202] In addition, when the first SerDes is set in the first PMD, the first PHY can switch the first PMD from a working state to a keep-alive state according to the second indication information, and switch the first SerDes corresponding to the first PMD from a working state to a keep-alive state.

[0203] It should also be noted that the first PCS and the first PMA of the first PHY transmit data through logical channels, and the number of the logical channels can be flexibly set according to business needs, such as in the 100GE PHY, including 2 50G PMA lanes. The first PMD transmits data through a physical channel, and the number of the physical channels is limited and cannot be expanded arbitrarily. However, in actual business transmission, the logical channel and the physical channel can correspond one to one, such as one logical channel corresponds to one physical channel, and can also be many-to-one for the logical channel and the physical channel, such as 4 logical channels correspond to one physical channel. Usually during data transmission, the sending device and the receiving device can predefine in advance which channels are used to transmit data. Of course, when switching the data transmission channel, the sending device can also send an indication signaling to the receiving device in advance to notify the switched data transmission channel before transmitting data. This application does not specifically limit this. Regarding the logical channel, the PCS channel is taken as an example to illustrate that the first PCS includes multiple first PCS channels, and the first PCS switches the multiple first PCS channels from a working state to a sleep state. For example, the first PCS sets 16 PCS lanes, and all 16 PCS lanes can be switched from a working state to a sleep state; or, the first PCS switches some of the multiple first PCS channels from a working state to a sleep state according to a second business flow rate threshold. For example, the business flow rate is S, the second business flow rate threshold is S1, and S is less than S1, then 10 PCS lanes can be switched from a working state to a sleep state. In addition, the first PCS can send the second indication code block via at least one first PCS channel among the multiple first PCS channels (if all of the above-mentioned first PCS channels are switched from the working state to the sleep state, all of the first PCS channels are used to send the second indication code block, such as using 16 PCS lanes to send the second indication code block; if part of the above-mentioned PCS lanes are switched from the sleep state to the working state, part of the PCS lanes are used to send the second indication code block, such as using 10 PCS lanes to send the second indication code block), as long as the first PMA is guaranteed to receive the second indication code block.

[0204] For the physical channel, the PMD channel is taken as an example to illustrate that the first PMD includes multiple first PMD channels, and the first PMD switches the multiple first PMD channels from the working state to the keep-alive state. For example, the first PMD sets 8 PMD lanes, and all 8 PMD lanes can be switched from the working state to the keep-alive state; or, the first PMD switches some of the multiple PMD lanes from the working state to the keep-alive state according to the second business flow rate threshold. For example, the business flow rate is S, the second business flow rate threshold is S1, S is less than S1, then 3 PMD lanes can be switched from the working state to the keep-alive state.

[0205] Step 603: The first PHY sends a second indication code block to the receiving device.

[0206] Among them, the length of the second indication code block can be 10 bits, 64 bits, 66 bits, 128 bits or 130 bits, such as 66-bit Blocks, which can be understood by referring to the above Table 1 and will not be repeated here.

[0207] Step 604: The second PHY switches the second PHY from the working state to the sleep state and switches the second SerDes corresponding to the second PHY from the working state to the keep-alive state according to the second indication code block.

[0208] In addition, when the second PHY includes a second PCS, a second PMA, and a second PMD, when executing step 604, the second PMA can switch the second PMA from a working state to a dormant state according to the second indication code block; the second PMA sends a second indication message to the second PCS (specifically, the second PMA can obtain the second indication message according to the second indication code block, such as determined according to the mapping relationship between the indication code block and the indication information, or directly generate the second indication message based on the second indication code block, which is not specifically limited here); the second PCS receives the second indication message and switches the second PCS from a working state to a dormant state. Alternatively, the second PMA can switch the second PMA from a working state to a dormant state according to the second indication code block; the second PMA sends a second indication code block to the second PCS; the second PCS receives the second indication code block, and switches the second PCS from a working state to a dormant state. Regardless of which method is used, it can be ensured that the second PHY is switched from a working state to a dormant state, and the service can be quickly suspended.

[0209] In addition, when the second SerDes is set in the second PMD, the second PHY can switch the first PMD from the working state to the keep-alive state according to the second indication information or the second indication code block, and switch the second SerDes corresponding to the second PMD from the working state to the keep-alive state.

[0210] It should also be noted that the second PCS and the second PMA of the second PHY transmit data through a logical channel, and the number of the logical channels can be flexibly set according to business needs. The second PMD transmits data through a physical channel, and the number of the physical channels is limited and cannot be expanded arbitrarily. However, in actual business transmission, the logical channel and the physical channel can correspond one to one, such as one logical channel corresponding to one physical channel, or it can be many-to-one for the logical channel and the physical channel, such as 4 logical channels corresponding to one physical channel. Usually, during data transmission, the sending device and the receiving device can predefine in advance which channels are used to transmit data. Of course, when switching the data transmission channel, the sending device can also send an indication signaling to the receiving device in advance to notify the switched data transmission channel before transmitting data. This application does not specifically limit this. Regarding the logical channel, the PCS channel is used as an example to illustrate that the second PCS includes multiple second PCS channels, and the second PCS switches the multiple second PCS channels from the working state to the dormant state. For example, the second PCS sets 16 PCS lanes, and the 16 PCS lanes can be switched from the working state to the dormant state; or, the second PCS switches some of the second PCS channels in the multiple second PCS channels from the working state to the dormant state according to the second service flow rate threshold. For example, the service flow rate is S, the second service flow rate threshold is S1, and S is less than S1, then 10 PCS lanes can be switched from the dormant state to the working state. In addition, the second PCS receives the second indication information via at least one second PCS channel in the multiple second PCS channels. If the above 16 PCS lanes are switched from the working state to the dormant state, the second indication information is received through the 16 PCS lanes. If the above 10 PCS lanes are switched from the dormant state to the working state, the second indication information can be received through the 10 PCS lanes.

[0211] For the physical channel, the channel of PMD is used as an example to illustrate that the second PMD includes multiple second PMD channels, and the second PMD switches the multiple second PMD channels from the working state to the keep-alive state. For example, the second PMD sets 8 PMD lanes, and the 8 PMD lanes can be switched from the working state to the keep-alive state; or, the second PMD switches some of the second PMD channels in the multiple second PMD channels from the working state to the keep-alive state according to the second service flow rate threshold, for example, the service flow rate is S, the second service flow rate threshold is S1, S is less than S1, then 3 PMD lanes can be switched from the working state to the keep-alive state. In addition, it should be noted that in actual application, multiple service flow rate thresholds can be set according to demand, and how many logical channels and physical channels are used to transmit service data according to different service flow rate thresholds can be determined, which can be understood by referring to the description of the above step 303 and will not be repeated here.

[0212] In the present application, after the PHY of the sending device receives the second indication information of the MAC layer, it determines that the transmission of the service flow needs to be stopped based on the second indication information, and then obtains the second indication code block based on the second indication information, and indicates the second indication code block to the receiving device, so that the receiving device switches the state of the PHY according to the second indication code block, and the PHY of the receiving device switches from the working state to the sleeping state, and the corresponding SerDes switches from the working state to the keep-alive state. In this way, when the Ethernet device is not working, the PHY is in the sleeping state, and the corresponding SerDes is in the keep-alive state, which can save the power consumption of the physical layer.

[0213] In order to better illustrate the solution of the present application, the following two different situations of low bit error rate (NO FEC) and high bit error rate (with FEC) are used to illustrate the data processing logic when the service is resumed and the service is suspended, as follows:

[0214] Situation 1: For scenarios where the Ethernet physical link bit error rate is low (NO FEC) and the rate is less than or equal to 100G, such as NRZ physical link applications such as 10G / 25G / 40G (4*10G) / 50G (2*25G) / 100G (4*25G)

[0215] Figure 7 A schematic diagram of the business processing flow from data stop to data recovery is shown, taking 100GE PHY as an example. In the figure, the sending device (TX) and the receiving device (RX) are illustrated by setting SerDes in the PMD of the PHY as an example, wherein PKT indicates the time when business data is transmitted, and IDLE indicates the time when there is no business data transmission. The MAC layer of TX detects that there is no business message (that is, the cache is empty), and only transmits IDLE code stream (that is, empty business code stream), generates stop flow indication information (that is, the second indication information mentioned above), and transmits the stop flow indication information to the PCS (specifically, the MAC layer RS ​​transmits the stop flow indication information through the MII). The stop flow indication information can be a notification message, etc., which can be understood with reference to the second indication information mentioned above. The stop flow indication information can also be a low-power code stream, or a normal power consumption code stream, which is not specifically limited in this application. The PCS generates a stop flow code block (i.e., a second indication code block) according to the stop flow indication. The stop flow code block is illustrated by taking 66-bit blocks as an example. The time interval of the stop flow code block can be set according to the business requirements. For example, if the stop flow operation needs to be performed quickly, the time interval can be set to 5 milliseconds. If the stop flow operation does not need to be performed too quickly, the time interval can be set to 10 milliseconds. This is only an example and is not specifically limited. The number of stop flow code blocks can be multiple to ensure that RX can receive it. The specific setting is not specifically limited in this application. The PCS can be connected through the PCS lane ( Figure 7The dotted lines in the figure indicate the logical channels. Figure 7 The stop-flow code block is transmitted to the PMA through the PMA lane ( Figure 7 The stop-flow code block is transmitted to the PMD, and the PMD transmits the stop-flow code block through the PMD lane ( Figure 7 The 2 50G PMD lanes are used as an example to describe the physical channel (shown by solid lines) to the RX PMD, and the RX PMD transmits the stop-flow code block through the PMA lane ( Figure 7 The PMA uses fuzzy matching to identify the received stop-flow code blocks. If the number of received stop-flow code blocks exceeds the predefined stop-flow threshold, the detected code blocks are determined to be legal stop-flow indications. The PMA can convert the stop-flow code blocks into stop-flow indication information and transmit them to the PMA through the PCS lane ( Figure 7 The 2 50G PCS lanes are used as an example in the figure) to transmit to PCS, and PCS transmits to MAC layer through MII. After that, PCS and PMA of TX and PCS and PMA of RX are switched from working state to sleeping state, PMD of TX and PMD of RX are switched from working state to keep alive state, and SerDes of PMD is also switched from working state to keep alive state. In addition, PMA of TX can generate pseudo-random code blocks (i.e. keep alive code blocks, such as pseudo-random code blocks and scrambled IDLE code blocks) according to the stop flow indication code blocks, and transmit them between SerDes of TX and SerDes of RX to ensure that SerDes is in keep alive state. Once the service is restored, SerDes can respond to the transmission of the restored service in time.

[0216] In addition, once the service of the sending device is restored, the MAC layer of TX detects the service message, generates a flow indication information (that is, the first indication information mentioned above), and transmits the flow indication information to the PCS. The flow indication information can be a notification message, etc., which can be understood with reference to the first indication information mentioned above. The flow indication information can be a low-power code stream, or a normal power code stream, which is not specifically limited in this application. The PCS generates a flow code block (that is, the first indication code block) according to the flow indication. The flow code block is illustrated by taking 66-bit blocks as an example. The time interval of the flow code block can be set according to the service requirements. For example, if it is necessary to quickly execute the stop flow and resume service flow operation, the time interval can be set to 5 milliseconds. If it is not necessary to recover too quickly, the time interval can be set to 10 milliseconds. The number of flow code blocks can be multiple to ensure that RX can receive it. The specific setting is not specifically limited in this application. PCS can transmit the streaming code block to PMA through PCS lane, PMA transmits the streaming code block to PMD through PMA lane, PMD transmits the streaming code block to RX's PMD through PMD lane, RX's PMD transmits the streaming code block to PMA through PMA lane, PMA uses fuzzy matching to identify, if the number of received streaming code blocks exceeds the predefined service flow recovery threshold, it is determined that the detected code block is a legal streaming indication. PMA can convert the streaming code block into streaming indication information and transmit it to PCS through PCS lane, PCS transmits it to MAC layer through PCS lane. Afterwards, TX's PCS, PMA and RX's PCS, PMA switch from sleep state to working state, TX's PMD and RX's PMD switch from keep-alive state to working state, and PMD's SerDes also switches from keep-alive state to working state.

[0217] Situation 2: For Ethernet physical link PAM4 (bit error rate becomes high and with FEC error correction code) and the rate is greater than or equal to 50G, such as 50G (1*50G) / 100G (2*50G) / 200G (4*50G / 2*100G) / 400G (8*50G / 4*100G) and other PAM4 physical link applications

[0218] Figure 8A schematic diagram of the service processing flow from data stop flow to data recovery is shown, and the PHY of 200GE is used as an example to illustrate. In the figure, the transmitting device (TX) and the receiving device (RX) are illustrated by taking the case where the SerDes is not set in the PMD of the PHY as an example, wherein PKT indicates the time when service data transmission exists, and IDLE indicates the time when service data transmission does not exist. The MAC layer of TX detects that there is no service message, and only transmits the IDLE code stream (that is, the empty service code stream), generates the stop flow indication information (that is, the second indication information mentioned above), and transmits the stop flow indication information to the PCS (specifically, the MAC layer RS ​​transmits the stop flow indication information through the MII). The stop flow indication information can be a notification message, etc., which can be understood with reference to the second indication information mentioned above. The stop flow indication information can be a low-power code stream, or a code stream with normal power consumption, which is not specifically limited in this application. The PCS generates a stop flow code block (that is, the second indication code block) according to the stop flow indication, and the stop flow code block takes the pattern of N*8-bit~64-bit blocks (N is a natural number, N=1~8, etc.) as an example. The pattern can be composed of multiple interval patterns (8-bit to 64-bit), and the size and interval of each pattern are definable, such as based on symbol (10-bit) as the interval pattern, based on 64-bit block as the interval pattern, or based on codeword (2720 / 5280 / 5440-bit) as the boundary. Figure 8 B0 and B1 are used as an example, where B0 is separated by multiple B1s. The number of stop-flow code blocks can be multiple to ensure that RX can receive it. The specific setting is not specifically limited in this application. PCS can be transmitted through PCS lane ( Figure 8 The stop-flow code block is transmitted to the FEC layer, and the FEC layer is transmitted to the PMA through the virtual channel. The PMA transmits the code block to the FEC layer through the PMA lane ( Figure 8 The stop-flow code block is transmitted to the PMD, and the PMD transmits the stop-flow code block through the physical channel ( Figure 8 In the figure, four 50G PMD lanes are used as an example, and the physical channels are indicated by solid lines) to the SerDes of TX. Since the physical channels correspond to SerDes one by one, four physical channels correspond to four SerDes. The SerDes of TX and the SerDes of RX transmit the stop-flow code blocks, and then transmit them to the PMD of RX. The PMD of RX transmits the stop-flow code blocks through the PMA lane ( Figure 8The PMA uses fuzzy matching to identify the received stop-flow code blocks. If the number of received stop-flow code blocks exceeds the predefined stop-flow threshold, the detected code blocks are determined to be legal stop-flow indications. The PMA can convert the stop-flow code blocks into stop-flow indication information and transmit them to the PMA through the PCS lane ( Figure 8 4 50G PCS lanes are used as an example in the figure) to the FEC layer, and then through the PCS, which is then transmitted to the MAC layer through the MII. Afterwards, the PCS, PMA, PMD of TX and the PCS, PMA, PMD of RX are switched from the working state to the sleeping state, and the SerDes of TX and the SerDes of RX are also switched from the working state to the keep-alive state. In addition, the PMA of TX can generate a pseudo-random code block (i.e., a keep-alive code block, such as a pseudo-random code block, a scrambled IDLE code block) according to the stop flow indication code block, and transmit it between the SerDes of TX and the SerDes of RX to ensure that the SerDes is in the keep-alive state. Once the service is restored, the SerDes can respond promptly to resume the transmission of the service.

[0219] In addition, once the service of the sending device is restored, the MAC layer of TX detects the service message, generates a flow indication information (that is, the first indication information mentioned above), and transmits the flow indication information to the PCS. The flow indication information can be a notification message, etc., which can be understood with reference to the first indication information mentioned above. The flow indication information can be a low-power code stream or a normal power code stream, which is not specifically limited in this application. The PCS generates a flow code block (that is, the first indication code block) according to the flow indication. The flow code block takes a pattern of N*8-bit~64-bit blocks (N is a natural number, N=1~8, etc.) as an example. The pattern can be composed of multiple patterns with intervals (8-bit~64-bit), and the size and interval of each pattern are definable, such as based on symbol (10-bit) as an interval pattern, based on 64-bit block as an interval pattern, or based on codeword (2720 / 5280 / 5440-bit) as a boundary. Figure 8 B0 and B1 are used as an example, where B0 is separated by multiple B1s. The number of the transmission code blocks can be multiple to ensure that the RX can receive it. The specific setting is not specifically limited in this application. The PCS can transmit the transmission code block to the FEC layer through the PCS lane, and then transmit it to the PMA. The PMA transmits the transmission code block to the FEC layer through the PMAlane ( Figure 86 items are described as examples in the figure) and the transmission code block is transmitted to the PMD, the PMD transmits the transmission code block to the SerDes of TX through the physical channel, the SerDes of TX and the SerDes of RX transmit the stop flow code block, and then transmits the PMD of RX, the PMD of RX transmits the transmission code block to the PMA through the PMA lane, and the PMA uses a fuzzy matching method to identify, if the number of received transmission code blocks exceeds the predefined service flow recovery threshold, it is determined that the detected code block is a legal transmission indication. The PMA can convert the transmission code block into transmission indication information, and transmit it to the FEC layer through the PCS lane, and then transmit it to the PCS, and the PCS transmits it to the MAC layer through the MII. Afterwards, the PCS and PMA of TX and the PCS and PMA of RX are switched from the sleep state to the working state, the PMD of TX and the PMD of RX are switched from the keep-alive state to the working state, and the SerDes of the PMD is also switched from the keep-alive state to the working state.

[0220] When the data processing method of the present application is adopted, the data recovery time for different scenarios is relatively fast, which can be understood by referring to the following Tables 2-4, wherein Table 2 shows the scenario for NO FEC and the link is NRZ (low bit error rate), and the corresponding stop flow and resume flow indication adopts a 2*66-bit block size, the sending interval is 0-bit, the required flow recovery time, the service flow recovery time is usually at the nanosecond level, and the user experience is good, such as, the SerDes rate is 10.3125Gbps, the PHY rate is 10G, the working mode (that is, the interface data carrying capacity) is 1*10G, the code blocks for stop flow and start flow are both 66bit Blocks, the stop flow and start flow are both 2 times, the number of virtual channels is 1, the data size carried by each virtual channel is 1*66+1*66bit, the stop flow and start flow interval is 0bit (that is, there is no interval between stop flow and start flow, which is a "back-to-back" transmission mode), and the time required for service flow recovery response is 12.8ns.

[0221] Table 2

[0222]

[0223]

[0224] Among them, Table 3 shows that for the scenario with FEC and the link is NRZ (low bit error rate), the corresponding stop flow and resume flow indication uses a 2*64-bit block size, the sending interval is 0-bit, and the required flow recovery time is shown in Table 3. For example, the SerDes rate is 25.78125Gbps, the PHY rate is 50G, the working mode (that is, the interface data carrying capacity) is 2*25G, the code blocks for stop flow and start flow are both 2*64bit Blocks, the stop flow and start flow are both 2 times, the number of virtual channels is 2, the data size carried by each virtual channel is 1*64+1*64bit, the stop flow and start flow interval is 0bit, and the time required for service flow recovery response is 4.96ns.

[0225] Table 3

[0226]

[0227] Among them, Table 4 shows that for the scenario with FEC and the link is PAM4 (low bit error rate), the corresponding stop flow and resume flow indication adopts (2+2)*64-bit block (to ensure reliability) size, the sending interval is 2*64-bit (the block and interval size can be adjusted according to reliability requirements), and the required flow recovery time is shown in Table 4. For example, the SerDes rate is 53.125Gbps, the PHY rate is 200G, the working mode (that is, the interface data carrying capacity) is 8*25G, the code blocks of stop flow and start flow are both 32*64bit Blocks, the stop flow and start flow are both 2 times, the number of virtual channels is 8, the data size carried by each virtual channel is 2*64+2*64bit, the stop flow and start flow interval is 2*64bit (that is, the interval between stop flow and start flow is the transmission time occupied by 2*64bit), and the time required for service flow recovery response is 14.46ns.

[0228] Table 4

[0229]

[0230]

[0231] It should be noted that, if the solution of the present application has traffic services occupying 50% of the average bandwidth, the total power consumption of the PHY logic can be saved by an estimated 35%. If the traffic services occupy 25% of the average bandwidth, the total power consumption of the PHY logic can be saved by an estimated 60%. If the traffic services occupy 10% of the average bandwidth, the total power consumption of the PHY logic can be saved by an estimated 75%.

[0232] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of device interaction. It is understandable that, in order to implement the above functions, each device may include a hardware structure and / or software module corresponding to each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0233] The embodiment of the present application can divide the functional units of the device according to the above method example, for example, each functional unit can be divided according to each function, or two or more functions can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of software functional units.

[0234] In the case of an integrated unit, Fig. 9 A possible exemplary block diagram of a data processing device involved in an embodiment of the present application is shown. Fig. 9 As shown, the data processing device 900 may include: a processing unit 901 and a transceiver unit 902. The processing unit 901 is used to control and manage the actions of the data processing device 900. The transceiver unit 902 is used to support the communication between the data processing device 900 and other devices. Optionally, the transceiver unit 902 may include a receiving unit and / or a sending unit, which are respectively used to perform receiving and sending operations. Optionally, the data processing device 900 may also include a storage unit for storing program code and / or data of the data processing device 900. The transceiver unit may be called an input-output unit, a communication unit, etc., and the transceiver unit may be a transceiver; the processing unit may be a processor. When the image processing device is a module (such as a chip) in a communication device, the transceiver unit may be an input-output interface, an input-output circuit or an input-output pin, etc., and may also be called an interface, a communication interface or an interface circuit, etc.; the processing unit may be a processor, a processing circuit or a logic circuit, etc. Specifically, the data processing device may be the above-mentioned sending device or receiving device, which is not specifically limited in this application.

[0235] In one embodiment, the data processing device is a sending device, the sending device includes a first MAC layer and a first PHY, the sending device includes a transceiver unit 902 and a processing unit 901, wherein the transceiver unit 902 is used to receive first indication information from the first MAC layer through the first PHY, and the first indication information is used to instruct the sending device to send a service flow to the receiving device; the processing unit 901 is used to obtain a first indication code block according to the first indication information through the first PHY, and the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct the second corresponding to the second PHY to switch from a keep-alive state to a working state; the transceiver unit 902 is also used to send the first indication code block to the receiving device through the first PHY.

[0236] In an optional manner, the processing unit 901 is further configured to switch the first PHY from a sleep state to a working state and switch a first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information through the first PHY.

[0237] In an optional manner, the first PHY includes a first PCS and a first PMA, wherein the switching of the first PHY from a sleep state to an operating state includes the switching of the first PCS from a sleep state to an operating state and the switching of the first PMA from a sleep state to an operating state.

[0238] In an optional manner, the transceiver unit 902 is also used to receive second indication information from the first MAC layer through the first PHY, and the second indication information is used to instruct the sending device to stop sending the service flow to the receiving device; the processing unit 901 is also used to obtain a second indication code block through the first PHY according to the second indication information, and the second indication code block is used to instruct the second PHY of the receiving device to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; the transceiver unit 902 is also used to send a second indication code block to the receiving device through the first PHY.

[0239] In an optional manner, the processing unit 901 is configured to switch the first PHY from a working state to a sleep state and switch a first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information through the first PHY.

[0240] In an optional manner, the first PHY includes a first PCS and a first PMA, wherein the switching of the first PHY from a working state to a sleeping state includes the switching of the first PCS from a working state to a sleeping state and the switching of the first PMA from a working state to a sleeping state.

[0241] In an optional manner, the processing unit 901 is specifically used to switch the first PCS from a sleep state to a working state according to the first indication information through the first PCS, and obtain a first indication code block; the transceiver unit 902 is specifically used to send the first indication code block to the first PMA through the first PCS; the processing unit 901 is specifically used to switch the first PMA from a sleep state to a working state through the first PMA according to the received first indication code block.

[0242] In an optional manner, the processing unit 901 is specifically used to switch the first PCS from a sleep state to a working state according to the first indication information through the first PCS, and send the first indication information to the first PMA; the processing unit 901 is specifically used to switch the first PMA from a sleep state to a working state according to the received first indication information through the first PMA, and obtain a first indication code block.

[0243] In an optional manner, the processing unit 901 is specifically used to switch the first PCS from a working state to a sleep state according to the second indication information through the first PCS, and obtain a second indication code block; the transceiver unit 902 is specifically used to send the second indication code block to the first PMA through the first PCS; the processing unit 901 is specifically used to switch the first PMA from a working state to a sleep state through the first PMA according to the received second indication code block.

[0244] In an optional manner, the processing unit 901 is specifically used to switch the first PCS from a working state to a sleep state according to the second indication information through the first PCS, and send the second indication information to the first PMA; the processing unit 901 is specifically used to switch the first PMA from a working state to a sleep state according to the received second indication information through the first PMA, and obtain a second indication code block.

[0245] In an optional manner, the first PCS includes multiple first PCS channels, and the processing unit 901 is specifically used to switch the multiple first PCS channels from a sleep state to a working state through the first PCS; or, the first PCS switches some of the multiple first PCS channels from a sleep state to a working state according to a first service flow rate threshold.

[0246] In an optional manner, the first PCS includes multiple first PCS channels, and the processing unit 901 is specifically used to switch the multiple first PCS channels from a working state to a sleep state through the first PCS; or, the first PCS switches some of the multiple first PCS channels from a working state to a sleep state according to a second service flow rate threshold.

[0247] In an optional manner, the first PCS includes multiple first PCS channels, and the transceiver unit 902 is specifically configured to send the first indication code block through the first PCS via at least one first PCS channel among the multiple first PCS channels.

[0248] In an optional manner, the first PCS includes multiple first PCS channels, and the transceiver unit 902 is specifically configured to send the second indication code block through the first PCS via at least one first PCS channel among the multiple first PCS channels.

[0249] In an optional manner, the first PHY includes a first PMD, and a processing unit 901 is specifically used to switch the first PMD from a keep-alive state to a working state according to first indication information through the first PHY; the first PHY switches the first SerDes corresponding to the first PMD from a keep-alive state to a working state.

[0250] In an optional manner, the first PMD includes multiple first PMD channels, and the processing unit 901 is specifically used to switch the multiple first PMD channels from a keep-alive state to a working state through the first PMD; or, the first PMD switches some of the multiple first PMD channels from a keep-alive state to a working state according to a first service flow rate threshold.

[0251] In an optional manner, when the first SerDes is in a keep-alive state, the transceiver unit 902 is further configured to periodically send a keep-alive code block to a receiving device via the first SerDes through the first PHY.

[0252] In an optional manner, the length of the first indication code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0253] In another embodiment, the data processing device is a receiving device, the receiving device includes a second PHY, the receiving device includes a transceiver unit 902 and a processing unit 901, wherein the transceiver unit 902 is used to receive a first indication code block sent by a first PHY in the sending device through the second PHY, the first indication code block is used to indicate that the second PHY switches from a sleep state to a working state, and indicates that a second SerDes corresponding to the second PHY switches from a keep-alive state to a working state; the processing unit 901 is used to switch the second PHY from a sleep state to a working state and switch the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block through the second PHY.

[0254] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the second PHY switching from a sleep state to an operating state includes the second PCS switching from a sleep state to an operating state and the second PMA switching from a sleep state to an operating state.

[0255] In an optional manner, the transceiver unit 902 is also used to receive a second indication code block sent by the first PHY in the sending device through the second PHY, and the second indication code block is used to indicate that the second PHY switches from a working state to a sleep state, and indicates that the second SerDes corresponding to the second PHY switches from a working state to a keep-alive state; the processing unit 901 is also used to switch the second PHY from a working state to a sleep state and switch the second SerDes corresponding to the second PHY from a working state to a keep-alive state according to the second indication code block through the second PHY.

[0256] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the second PHY switching from a working state to a sleep state includes the second PCS switching from a working state to a sleep state and the second PMA switching from a working state to a sleep state.

[0257] In an optional manner, the processing unit 901 is specifically used to switch the second PMA from a sleep state to a working state according to the first indication code block through the second PMA; the transceiver unit 902 is specifically used to send the first indication information to the second PCS through the second PMA; the transceiver unit 902 is specifically used to receive the first indication information through the second PCS and switch the second PCS from a sleep state to a working state.

[0258] In an optional manner, the processing unit 901 is specifically used to switch the second PMA from a working state to a sleep state according to a second indication code block through the second PMA; the transceiver unit 902 is specifically used to send second indication information to the second PCS through the second PMA; the transceiver unit 902 is specifically used to receive the second indication information through the second PCS and switch the second PCS from a working state to a sleep state.

[0259] In an optional manner, the second PCS includes multiple second PCS channels, and the processing unit 901 is specifically used to switch the multiple second PCS channels from a sleep state to a working state through the second PCS; or, the second PCS switches some of the multiple second PCS channels from a sleep state to a working state according to a first service flow rate threshold.

[0260] In an optional manner, the second PCS includes multiple second PCS channels, and the processing unit 901 is specifically used to switch the multiple second PCS channels from a working state to a sleep state through the second PCS; or, the second PCS switches some of the multiple second PCS channels from a working state to a sleep state according to a second service flow rate threshold.

[0261] In an optional manner, the second PHY includes a second PMD, and the processing unit 901 is specifically used to switch the second PMD from a keep-alive state to a working state according to the first indication code block through the second PHY; the second PHY switches the second SerDes corresponding to the second PMD from a keep-alive state to a working state.

[0262] In an optional manner, the second PMD includes multiple second PMD channels, and the processing unit 901 is specifically used to switch the multiple second PMD channels from the keep-alive state to the working state through the second PMD; or, the second PMD switches some of the second PMD channels among the multiple second PMD channels from the keep-alive state to the working state according to the first service flow rate threshold.

[0263] In an optional manner, the second PCS includes multiple second PCS channels, and the transceiver unit 902 is specifically configured to receive the second indication information through the second PCS via at least one second PCS channel among the multiple second PCS channels.

[0264] In an optional manner, when the second SerDes is in a keep-alive state, the transceiver unit 902 is specifically configured to periodically receive a keep-alive code block via the second SerDes through the second PHY.

[0265] In an optional manner, the length of the first indication code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0266] In another embodiment, the data processing device is a sending device, the sending device includes a first MAC layer and a first PHY, the sending device includes a transceiver unit 902 and a processing unit 901, wherein the transceiver unit 902 is used to receive second indication information from the first MAC layer through the first PHY, and the second indication information is used to instruct the sending device to stop sending a service flow to the receiving device; the processing unit 901 is used to obtain a second indication code block according to the second indication information through the first PHY, and the second indication code block is used to instruct the second PHY of the receiving device to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; the transceiver unit 902 is also used to send the second indication code block to the receiving device through the first PHY.

[0267] In an optional manner, the processing unit 901 is configured to switch the first PHY from a working state to a sleep state and switch a first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information through the first PHY.

[0268] In an optional manner, the first PHY includes a first PCS and a first PMA, a processing unit 901, which is specifically used to switch the first PCS from a working state to a sleep state according to second indication information through the first PCS, and obtain a second indication code block; a transceiver unit 902, which is specifically used to send a second indication code block to the first PMA through the first PCS; the processing unit 901, which is specifically used to switch the first PMA from a working state to a sleep state through the first PMA according to the received second indication code block.

[0269] In an optional manner, the processing unit 901 is specifically used to switch the first PCS from a working state to a sleep state according to the second indication information through the first PCS, and send the second indication information to the first PMA; the processing unit 901 is specifically used to switch the first PMA from a working state to a sleep state according to the received second indication information through the first PMA, and obtain a second indication code block.

[0270] In an optional manner, the first PCS includes multiple first PCS channels, and the processing unit 901 is specifically used to switch the multiple first PCS channels from a working state to a sleep state through the first PCS; or, the first PCS switches some of the multiple first PCS channels from a working state to a sleep state according to a second service flow rate threshold.

[0271] In an optional manner, the first PCS includes multiple first PCS channels, and the transceiver unit 902 is specifically configured to send the second indication code block through the first PCS via at least one first PCS channel among the multiple first PCS channels.

[0272] In an optional manner, when the first SerDes is in a keep-alive state, the transceiver unit 902 is specifically configured to periodically send a keep-alive code block to a receiving device via the first SerDes through the first PHY.

[0273] In an optional manner, the length of the second indication code block is 10 bits, 64 bits, 66 bits, 128 bits, or 130 bits.

[0274] In another embodiment, the data processing device is a receiving device, the receiving device includes a second PHY, the receiving device includes a transceiver unit 902 and a processing unit 901, wherein the transceiver unit 902 is used to receive a second indication code block sent by a first PHY in the sending device through the second PHY, the second indication code block is used to indicate that the second PHY switches from a working state to a sleep state, and indicates that a second SerDes corresponding to the second PHY switches from a working state to a keep-alive state; the processing unit 901 is used to switch the second PHY from a working state to a sleep state and switch the second SerDes corresponding to the second PHY from a working state to a keep-alive state through the second PHY according to the second indication code block.

[0275] In an optional manner, the second PHY includes a second PCS and a second PMA, wherein the second PHY switching from a working state to a sleep state includes the second PCS switching from a working state to a sleep state and the second PMA switching from a working state to a sleep state.

[0276] In an optional manner, the processing unit 901 is specifically used to switch the second PMA from a working state to a sleep state according to a second indication code block through the second PMA; the transceiver unit 902 is specifically used to send second indication information to the second PCS through the second PMA; the transceiver unit 902 is specifically used to receive the second indication information through the second PCS and switch the second PCS from a working state to a sleep state.

[0277] In an optional manner, the second PCS includes multiple second PCS channels, and the transceiver unit 902 is specifically configured to receive the second indication information through the second PCS via at least one second PCS channel among the multiple second PCS channels.

[0278] In an optional manner, the second PCS includes multiple second PCS channels, and the transceiver unit 902 is specifically used to switch the multiple second PCS channels from a working state to a sleep state through the second PCS; or, the second PCS switches some of the multiple second PCS channels from a working state to a sleep state according to a second service flow rate threshold.

[0279] In an optional manner, when the second SerDes is in a keep-alive state, the transceiver unit 902 is specifically configured to periodically receive a keep-alive code block via the second SerDes through the second PHY.

[0280] In an optional manner, the length of the second indication code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

[0281] The present application provides an integrated circuit (equivalent to a sending device), which includes an interface circuit and a control circuit, wherein the interface circuit is coupled to the control circuit; the interface circuit is used to receive first indication information from a first MAC layer through a first PHY, wherein the first indication information is used to instruct the sending device to send a service flow to a receiving device; the control circuit is used to obtain a first indication code block according to the first indication information through the first PHY, wherein the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct the second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the interface circuit is also used to send the first indication code block to the receiving device through the first PHY.

[0282] The present application provides another integrated circuit (equivalent to a receiving device), the integrated circuit includes an interface circuit and a control circuit, the interface circuit is coupled to the control circuit; the interface circuit is used to receive a first indication code block sent by a first PHY in a sending device through a second PHY, the first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct the second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; the control circuit is used to switch the second PHY from a sleep state to a working state and switch the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block through the second PHY.

[0283] See also Fig.10 , Fig.10 The data processing device 2100 provided in the present application is shown in FIG. Figure 3 — Figure 8 The sending device and the receiving device in the apparatus 2100 are, for example, a switch, a router, etc. The apparatus 2100 can be implemented by a bus architecture.

[0284] like Fig.10 As shown, the device 2100 includes: a main control board 2110 and an interface board 2130 .

[0285] The main control board is also called a main processing unit (MPU) or a route processor card. The main control board 2110 is used to control and manage various components in the device 2100, including route calculation, device management, device maintenance, and protocol processing functions. The main control board 2110 includes: a central processing unit 2111 and a memory 2112.

[0286] The interface board 2130 is also called a line processing unit (LPU), a line card or a service board. The interface board 2130 is used to provide various service interfaces and realize the forwarding of data packets. The service interface includes but is not limited to an Ethernet interface, a POS (Packet over SONET / SDH) interface, etc., and the Ethernet interface is, for example, a Flexible Ethernet Client (FlexE Client). The interface board 2130 includes: a central processing unit 2131, a network processor 2132, a forwarding table entry memory 2134 and a physical interface card (physical interface card, PIC) 2133.

[0287] The central processor 2131 on the interface board 2130 is used to control and manage the interface board 2130 and communicate with the central processor 2111 on the main control board 2110 .

[0288] The network processor 2132 is used to implement the forwarding processing of the message. The network processor 2132 can be in the form of a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented by an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 2132 is used to forward the received message based on the forwarding table stored in the forwarding table entry memory 2134. If the destination address of the message is the address of the device 2100, the message is sent to the CPU (such as the central processor 2131) for processing; if the destination address of the message is not the address of the device 2100, the next hop and the output interface corresponding to the destination address are found from the forwarding table according to the destination address, and the message is forwarded to the output interface corresponding to the destination address. Among them, the processing of the uplink message may include: processing of the message input interface, forwarding table search; the processing of the downlink message may include: forwarding table search, etc. In some embodiments, the central processor can also perform the function of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that the forwarding chip is not required in the interface board.

[0289] The physical interface card 2133 is used to implement the docking function of the physical layer, from which the original traffic enters the interface board 2130, and the processed message is sent from the physical interface card 2133. The physical interface card 2133, also known as a daughter card, can be installed on the interface board 2130, and is responsible for converting the optical signal into a message and forwarding the message to the network processor 2132 for processing after checking the legitimacy of the message. In some embodiments, the central processor 2131 can also perform the functions of the network processor 2132, such as implementing software forwarding based on a general-purpose CPU, so that the network processor 2132 is not required in the physical interface card 2133. The physical interface card 2133 can be used to implement the PHY in the sending device or the receiving device in this application, which will not be repeated here.

[0290] Optionally, the device 2100 includes a plurality of interface boards, for example, the device 2100 further includes an interface board 2140, and the interface board 2140 includes: a central processing unit 2141, a network processor 2142, a forwarding table entry memory 2144, and a physical interface card 2143. The functions and implementations of the components in the interface board 2140 are the same or similar to those of the interface board 2130, and are not described in detail herein. The interface board includes one or more interfaces described in the above embodiments.

[0291] Optionally, the device 2100 further includes a switching fabric board 2120. The switching fabric board 2120 may also be referred to as a switch fabric unit (SFU). When the device has multiple interface boards, the switching fabric board 2120 is used to complete data exchange between the interface boards. For example, the interface board 2130 and the interface board 2140 may communicate through the switching fabric board 2120.

[0292] The main control board 2110 is coupled to the interface board. For example, the main control board 2110, the interface board 2130, the interface board 2140, and the switching network board 2120 are connected to the system backplane through the system bus to achieve intercommunication. In a possible implementation, an inter-process communication (IPC) channel is established between the main control board 2110 and the interface board 2130 and the interface board 2140, and the main control board 2110 and the interface board 2130 and the interface board 2140 communicate through the IPC channel.

[0293] Logically, the device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board 2110 and a central processor 2111. The forwarding plane includes various components for performing forwarding, such as a forwarding table entry memory 2134, a physical interface card 2133, and a network processor 2132. The control plane performs functions such as a router, generating a forwarding table, processing signaling and protocol messages, and configuring and maintaining the status of the device. The control plane sends the generated forwarding table to the forwarding plane. On the forwarding plane, the network processor 2132 forwards the message received by the physical interface card 2133 based on the forwarding table sent by the control plane. The forwarding table sent by the control plane can be stored in the forwarding table entry memory 2134. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same device.

[0294] It is worth noting that there may be one or more main control boards, and when there are multiple boards, they may include a primary main control board and a backup main control board. There may be one or more interface boards, and the more interface boards provided, the stronger the data processing capability of the device. There may also be one or more physical interface cards on the interface board. There may be no switching network board, or there may be one or more switching network boards, and when there are multiple switching network boards, they can jointly realize load sharing and redundant backup. Under a centralized forwarding architecture, the device may not need a switching network board, and the interface board is responsible for the processing function of the business data of the entire system. Under a distributed forwarding architecture, the device may have at least one switching network board, and the switching network board is used to realize data exchange between multiple interface boards, providing large-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of the device with a distributed architecture are greater than those of the device with a centralized architecture. Optionally, the device may have only one board, that is, no switching board, and the functions of the interface board and the main control board are integrated on the board. In this case, the central processor on the interface board and the central processor on the main control board can be combined into one central processor on the board to perform the functions of the two. This type of device has low data exchange and processing capabilities (for example, low-end switches or routers). The specific architecture to be adopted depends on the specific networking deployment scenario, and no limitation is made here.

[0295] It should be understood that the above processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting the advanced RISC machines (ARM) architecture.

[0296] Further, in an optional embodiment, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0297] The memory may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory. Among them, the nonvolatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM) and direct memory bus random access memory (DR RAM).

[0298] See also Fig.11 , Fig.11 A schematic structural diagram of an apparatus 4000 provided in an exemplary embodiment of the present application is shown. Fig.11 The device 4000 shown is used to perform the above Figure 3 — Figure 8 The device 4000 is, for example, a switch, a router, a controller, etc., and may also be a server, a storage device, a network device, etc. The device 4000 may be implemented by a bus architecture.

[0299] like Fig.11 As shown, the apparatus 4000 includes at least one processor 4001 and at least one communication interface 4004. In some embodiments, the processor 4001 is coupled to a memory 4003. The communication interface 4004 can be used to implement the PHY in the transmitting device or the receiving device in the present application, which will not be described in detail here.

[0300] Processor 4001 is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing units (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, processor 4001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present invention. The processor may also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0301] Optionally, the device 4000 further includes a bus. The bus is used to transmit information between the components of the device 4000. The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.11 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0302] The memory 4003 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 4003 is, for example, independent and connected to the processor 4001 via a bus. The memory 4003 can also be integrated with the processor 4001.

[0303] The communication interface 4004 uses any transceiver-like device to communicate with other devices or communication networks, and the communication network can be Ethernet, a radio access network (RAN) or a wireless local area network (WLAN), etc. The communication interface 4004 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 4004 can be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an Asynchronous Transfer Mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface or a combination thereof. In an embodiment of the present application, the communication interface 4004 can be used for the device 4000 to communicate with other devices.

[0304] In a specific implementation, as an embodiment, the processor 4001 may include one or more CPUs, such as Fig.11 0 and CPU1 shown in FIG. Each of these processors may be a single-CPU processor or a multi-CPU processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0305] In a specific implementation, as an embodiment, the apparatus 4000 may include multiple processors, such as Fig.11 4001 and processor 4005 shown in . Each of these processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here can refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0306] In a specific implementation, as an embodiment, the device 4000 may also include an output device and an input device. The output device communicates with the processor 4001 and can display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 4001 and can receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0307] In some embodiments, the memory 4003 is used to store the program code 4010 for executing the solution of the present application, and the processor 4001 can execute the program code 4010 stored in the memory 4003. That is, the apparatus 4000 can implement the program code 4010 in the processor 4001 and the memory 4003. Figure 3-8 The program code 4010 may include one or more software modules. Optionally, the processor 4001 itself may also store program codes or instructions for executing the solution of the present application.

[0308] In some embodiments, the communication interface 4004 is used to perform the above Figure 3-8 The operations involved in any of the interface functions shown.

[0309] Based on the above embodiments, the embodiments of the present application further provide a computer-readable storage medium, which stores instructions. When the instructions are executed, the method executed by each device in any of the above method embodiments is implemented, for example, Figure 4 The method executed by the image encoding device and the image decoding device in the illustrated embodiment is implemented. The computer readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and other media that can store program codes.

[0310] Based on the above embodiments, an embodiment of the present application provides a data processing system, which communication system includes the sending device and the receiving device mentioned in any of the above method embodiments, and can be used to execute the method executed by each device in any of the above method embodiments.

[0311] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0312] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0313] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0314] These computer program instructions can also be loaded onto a computer or other programmable image processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

Claims

1. A data processing method, applied to a sending device, wherein the sending device comprises a first media access control MAC layer and a first physical layer PHY, characterized in that: include: The first PHY receives first indication information from the first MAC layer, where the first indication information is used to instruct the sending device to send a service flow to the receiving device; The first PHY obtains a first indication code block according to the first indication information, where the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct a second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; The first PHY sends the first indication code block to the receiving device.

2. The method according to claim 1, characterized in that Also includes: The first PHY switches the first PHY from a sleep state to a working state and switches a first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information.

3. The method according to claim 2, characterized in that The first PHY includes a first physical coding sublayer PCS and a first physical medium attachment PMA, wherein the switching of the first PHY from a sleep state to an operating state includes the switching of the first PCS from a sleep state to an operating state and the switching of the first PMA from a sleep state to an operating state.

4. The method according to any one of claims 1 to 3, characterized in that: Also includes: The first PHY receives second indication information from the first MAC layer, where the second indication information is used to instruct the sending device to stop sending the service flow to the receiving device; The first PHY obtains a second indication code block according to the second indication information, where the second indication code block is used to instruct the second PHY of the receiving device to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; The first PHY sends the second indication code block to the receiving device.

5. The method according to claim 4, characterized in that Also includes: The first PHY switches the first PHY from a working state to a sleep state and switches the first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information.

6. The method according to claim 5, characterized in that The first PHY includes a first PCS and a first PMA, wherein the switching of the first PHY from a working state to a sleeping state includes the switching of the first PCS from a working state to a sleeping state and the switching of the first PMA from a working state to a sleeping state.

7. The method according to claim 3, characterized in that The first PHY obtains a first indication code block according to the first indication information, including: The first PCS switches the first PCS from a sleep state to a working state according to the first indication information, and obtains the first indication code block; The first PCS sends the first indication code block to the first PMA; The first PMA switches the first PMA from a sleep state to a working state according to the received first indication code block.

8. The method according to claim 3, characterized in that The first PHY obtains a first indication code block according to the first indication information, including: The first PCS switches the first PCS from a sleep state to a working state according to the first indication information, and sends the first indication information to the first PMA; The first PMA switches the first PMA from a sleep state to a working state according to the received first indication information, and obtains the first indication code block.

9. The method according to claim 6, characterized in that The first PHY obtains a second indication code block according to the second indication information, including: The first PCS switches the first PCS from a working state to a dormant state according to the second indication information, and obtains the second indication code block; The first PCS sends the second indication code block to the first PMA; The first PMA switches the first PMA from a working state to a sleeping state according to the received second indication code block.

10. The method according to claim 6, characterized in that The first PHY obtains a second indication code block according to the second indication information, including: The first PCS switches the first PCS from a working state to a dormant state according to the second indication information, and sends the second indication information to the first PMA; The first PMA switches the first PMA from a working state to a sleeping state according to the received second indication information, and obtains the second indication code block.

11. The method according to claim 7 or 8, characterized in that: The first PCS includes a plurality of first PCS channels, wherein the first PCS switches the first PCS from a sleep state to a working state according to the first indication information, including: The first PCS switches the plurality of first PCS channels from a sleep state to a working state; or, The first PCS switches some of the first PCS channels among the plurality of first PCS channels from a sleep state to a working state according to a first service flow rate threshold.

12. The method according to claim 9 or 10, characterized in that: The first PCS includes a plurality of first PCS channels, wherein the first PCS switches the first PCS from a working state to a dormant state according to the second indication information, including: The first PCS switches the plurality of first PCS channels from a working state to a dormant state; or, The first PCS switches part of the plurality of first PCS channels from a working state to a dormant state according to a second service flow rate threshold.

13. The method according to claim 7, characterized in that The first PCS includes a plurality of first PCS channels, and the first PCS sends the first indication code block to the first PMA, including: The first PCS sends the first indication code block via at least one first PCS channel among the plurality of first PCS channels.

14. The method according to claim 9, characterized in that The first PCS includes a plurality of first PCS channels, and the first PCS sends the second indication code block to the first PMA, including: The first PCS sends the second indication code block via at least one first PCS channel among the plurality of first PCS channels.

15. The method according to any one of claims 2 to 14, characterized in that: The first PHY includes a first physical medium dependent PMD, and the first PHY switches the first PHY from a sleep state to a working state and switches a first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information, including: The first PHY switches the first PMD from a keep-alive state to a working state according to the first indication information; The first PHY switches the first SerDes corresponding to the first PMD from a keep-alive state to a working state.

16. The method according to claim 15, characterized in that The first PMD includes a plurality of first PMD channels, and the first PHY switches the first PMD from a keep-alive state to a working state according to the first indication information, including: The first PMD switches the plurality of first PMD channels from a keep-alive state to a working state; or, The first PMD switches some of the first PMD channels among the multiple first PMD channels from a keep-alive state to a working state according to a first service flow rate threshold.

17. The method according to claim 2 or 5, characterized in that: When the first SerDes is in a keep-alive state, the method further includes: The first PHY periodically sends a keep-alive code block to the receiving device via the first SerDes.

18. The method according to any one of claims 1 to 17, characterized in that: The length of the first indication code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

19. A data processing method, applied to a receiving device, wherein the receiving device comprises a second physical layer PHY, characterized in that: include: The second PHY receives a first indication code block sent by a first PHY in a transmitting device, where the first indication code block is used to indicate that the second PHY switches from a sleep state to a working state, and indicates that a second serializer / deserializer SerDes corresponding to the second PHY switches from a keep-alive state to a working state; The second PHY switches the second PHY from a sleep state to a working state and switches the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block.

20. The method according to claim 19, characterized in that The second PHY includes a second physical coding sublayer PCS and a second physical medium attachment PMA, wherein the switching of the second PHY from a sleep state to an operating state includes the switching of the second PCS from a sleep state to an operating state and the switching of the second PMA from a sleep state to an operating state.

21. The method according to claim 19 or 20, characterized in that Also includes: The second PHY receives a second indication code block sent by the first PHY in the sending device, where the second indication code block is used to indicate that the second PHY is switched from a working state to a sleeping state, and indicates that the second SerDes corresponding to the second PHY is switched from a working state to a keep-alive state; The second PHY switches the second PHY from a working state to a sleep state and switches the second SerDes corresponding to the second PHY from a working state to a keep-alive state according to the second indication code block.

22. The method according to claim 21, characterized in that The second PHY includes a second PCS and a second PMA, wherein the switching of the second PHY from an operating state to a sleep state includes the switching of the second PCS from an operating state to a sleep state and the switching of the second PMA from an operating state to a sleep state.

23. The method according to claim 20, characterized in that The second PHY switches the second PHY from a sleep state to a working state according to the first indication code block, including: The second PMA switches the second PMA from a sleep state to a working state according to the first indication code block; The second PMA sends first indication information to the second PCS; The second PCS receives the first indication information, and switches the second PCS from a sleep state to a working state.

24. The method according to claim 22, characterized in that The second PHY switches the second PHY from a working state to a sleep state according to the second indication code block, including: The second PMA switches the second PMA from a working state to a dormant state according to the second indication code block; The second PMA sends second indication information to the second PCS; The second PCS receives the second indication information, and switches the second PCS from a working state to a sleeping state.

25. The method according to claim 22, characterized in that The second PCS includes a plurality of second PCS channels, wherein the second PCS receives the first indication information and switches the second PCS from a sleep state to a working state, including: The second PCS switches the plurality of second PCS channels from a dormant state to a working state; or, The second PCS switches part of the plurality of second PCS channels from a dormant state to a working state according to a first service flow rate threshold.

26. The method according to any one of claims 19 to 25, characterized in that: The second PHY includes a second physical medium dependent PMD, and the second PHY switches the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block, including: The second PHY switches the second PMD from a keep-alive state to a working state according to the first indication code block; The second PHY switches the second SerDes corresponding to the second PMD from a keep-alive state to a working state.

27. The method according to claim 26, characterized in that The second PMD includes a plurality of second PMD channels, and the second PHY switches the second PMD from a keep-alive state to a working state according to the first indication code block, including: The second PMD switches the plurality of second PMD channels from a keep-alive state to a working state; or, The second PMD switches some of the second PMD channels among the multiple second PMD channels from a keep-alive state to a working state according to the first service flow rate threshold.

28. The method according to claim 24, characterized in that The second PCS includes a plurality of second PCS channels, and the second PCS receives the second indication information, including: The second PCS receives the second indication information via at least one second PCS channel among the plurality of second PCS channels.

29. The method according to claim 19 or 21, characterized in that When the second SerDes is in a keep-alive state, the method further includes: The second PHY periodically receives a keep-alive code block via the second SerDes.

30. The method according to any one of claims 19 to 29, characterized in that: The length of the first indication code block is 10 bits, 64 bits, 66 bits, 128 bits or 130 bits.

31. A sending device, comprising a first media access control MAC layer and a first physical layer PHY, characterized in that: include: a transceiver unit, configured to receive first indication information from a first MAC layer through the first PHY, where the first indication information is used to instruct the sending device to send a service flow to the receiving device; a processing unit, configured to obtain a first indication code block through the first PHY according to the first indication information, wherein the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct a second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; The transceiver unit is further configured to send the first indication code block to the receiving device through the first PHY.

32. The device according to claim 31, characterized in that The processing unit is further configured to switch the first PHY from a sleep state to a working state and switch a first SerDes corresponding to the first PHY from a keep-alive state to a working state according to the first indication information through the first PHY.

33. The device according to claim 32, characterized in that The first PHY includes a first physical coding sublayer PCS and a first physical medium attachment PMA, wherein the switching of the first PHY from a sleep state to an operating state includes the switching of the first PCS from a sleep state to an operating state and the switching of the first PMA from a sleep state to an operating state.

34. The device according to any one of claims 31 to 33, characterized in that The transceiver unit is further used to receive second indication information from the first MAC layer through the first PHY, where the second indication information is used to instruct the sending device to stop sending the service flow to the receiving device; The processing unit is further used to obtain a second indication code block through the first PHY according to the second indication information, where the second indication code block is used to instruct the second PHY of the receiving device to switch from a working state to a sleep state, and to instruct the second SerDes corresponding to the second PHY to switch from a working state to a keep-alive state; The transceiver unit is further configured to send the second indication code block to the receiving device through the first PHY.

35. The device according to claim 34, characterized in that Also includes: The transceiver unit is further configured to switch the first PHY from a working state to a sleep state and switch the first SerDes corresponding to the first PHY from a working state to a keep-alive state according to the second indication information through the first PHY.

36. The device according to claim 35, characterized in that The first PHY includes a first PCS and a first PMA, wherein the switching of the first PHY from a working state to a sleeping state includes the switching of the first PCS from a working state to a sleeping state and the switching of the first PMA from a working state to a sleeping state.

37. The device according to claim 33, characterized in that The processing unit is specifically configured to switch the first PCS from a sleep state to a working state according to the first indication information through the first PCS, and obtain the first indication code block; The transceiver unit is specifically configured to send the first indication code block to the first PMA through the first PCS; The processing unit is specifically configured to switch the first PMA from a sleep state to a working state according to the received first indication code block through the first PMA.

38. The device according to claim 33, characterized in that The processing unit is specifically configured to switch the first PCS from a sleep state to a working state according to the first indication information through the first PCS, and send the first indication information to the first PMA; The processing unit is specifically configured to switch the first PMA from a sleep state to a working state according to the received first indication information through the first PMA, and obtain the first indication code block.

39. The device according to claim 36, characterized in that The processing unit is specifically configured to switch the first PCS from a working state to a dormant state according to the second indication information through the first PCS, and obtain the second indication code block; The transceiver unit is specifically configured to send the second indication code block to the first PMA through the first PCS; The processing unit is specifically configured to switch the first PMA from a working state to a sleeping state according to the received second indication code block through the first PMA.

40. The apparatus according to claim 36, characterized in that The processing unit is specifically configured to switch the first PCS from a working state to a dormant state according to the second indication information through the first PCS, and send the second indication information to the first PMA; The processing unit is specifically configured to switch the first PMA from a working state to a sleeping state according to the received second indication information through the first PMA, and obtain the second indication code block.

41. The apparatus according to claim 37 or 38, characterized in that The first PCS includes a plurality of first PCS channels, wherein the processing unit is specifically configured to switch the plurality of first PCS channels from a sleep state to a working state through the first PCS; or, The first PCS switches some of the first PCS channels among the plurality of first PCS channels from a sleep state to a working state according to a first service flow rate threshold.

42. The apparatus according to claim 39 or 40, characterized in that The first PCS includes a plurality of first PCS channels, and the processing unit is specifically configured to switch the plurality of first PCS channels from a working state to a dormant state through the first PCS; or, The first PCS switches part of the plurality of first PCS channels from a working state to a dormant state according to a second service flow rate threshold.

43. A receiving device, comprising a second physical layer PHY, characterized in that: include: a transceiver unit, configured to receive, through the second PHY, a first indication code block sent by the first PHY in the transmitting device, wherein the first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct a second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; A processing unit is used to switch the second PHY from a sleep state to a working state and switch the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block through the second PHY.

44. The device according to claim 43, characterized in that The second PHY includes a second physical coding sublayer PCS and a second physical medium attachment PMA, wherein the switching of the second PHY from a sleep state to an operating state includes the switching of the second PCS from a sleep state to an operating state and the switching of the second PMA from a sleep state to an operating state.

45. Apparatus according to claim 43 or 44, characterised in that The transceiver unit is further used to receive, through the second PHY, a second indication code block sent by the first PHY in the sending device, wherein the second indication code block is used to indicate that the second PHY is switched from a working state to a sleep state, and indicates that the second SerDes corresponding to the second PHY is switched from a working state to a keep-alive state; The processing unit is further configured to switch the second PHY from a working state to a sleep state and switch the second SerDes corresponding to the second PHY from a working state to a keep-alive state according to the second indication code block through the second PHY.

46. ​​The device according to claim 45, characterized in that The second PHY includes a second PCS and a second PMA, wherein the switching of the second PHY from an operating state to a sleep state includes the switching of the second PCS from an operating state to a sleep state and the switching of the second PMA from an operating state to a sleep state.

47. The apparatus according to claim 44, characterized in that The processing unit is specifically configured to switch the second PMA from a sleep state to a working state according to the first indication code block through the second PMA; The transceiver unit is specifically configured to send first indication information to the second PCS through the second PMA; The transceiver unit is specifically configured to receive the first indication information through the second PCS, and switch the second PCS from a sleep state to a working state.

48. The apparatus according to claim 46, characterized in that The processing unit is specifically configured to switch the second PMA from a working state to a dormant state according to the second indication code block through the second PMA; The transceiver unit is specifically configured to send second indication information to the second PCS through the second PMA; The transceiver unit is specifically configured to receive the second indication information through the second PCS, and switch the second PCS from a working state to a dormant state.

49. The device according to claim 46, characterized in that The second PCS includes a plurality of second PCS channels, and the processing unit is specifically configured to switch the plurality of second PCS channels from a sleep state to a working state through the second PCS; or, The second PCS switches part of the plurality of second PCS channels from a dormant state to a working state according to a first service flow rate threshold.

50. The device according to any one of claims 43 to 49, characterized in that The second PHY includes a second physical medium dependent PMD, and the processing unit is specifically configured to switch the second PMD from a keep-alive state to a working state according to the first indication code block through the second PHY; The second PHY switches the second SerDes corresponding to the second PMD from a keep-alive state to a working state.

51. A chip, characterized in that: The chip comprises a processor, and the processor is used to execute the method according to any one of claims 1-18 or to execute the method according to any one of claims 19-30.

52. An integrated circuit, characterized in that: The integrated circuit comprises an interface circuit and a control circuit, wherein the interface circuit is coupled to the control circuit; The interface circuit is used to receive first indication information from the first MAC layer through the first PHY, where the first indication information is used to instruct the sending device to send a service flow to the receiving device; The control circuit is used to obtain a first indication code block according to the first indication information through the first PHY, where the first indication code block is used to instruct the second PHY of the receiving device to switch from a sleep state to a working state, and to instruct the second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; The interface circuit is further configured to send the first indication code block to the receiving device through the first PHY.

53. An integrated circuit, characterized in that: The integrated circuit comprises an interface circuit and a control circuit, wherein the interface circuit is coupled to the control circuit; The interface circuit is used to receive, through the second PHY, a first indication code block sent by a first PHY in a transmitting device, wherein the first indication code block is used to instruct the second PHY to switch from a sleep state to a working state, and to instruct a second serializer / deserializer SerDes corresponding to the second PHY to switch from a keep-alive state to a working state; The control circuit is used to switch the second PHY from a sleep state to a working state and switch the second SerDes corresponding to the second PHY from a keep-alive state to a working state according to the first indication code block through the second PHY.

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