FPGA prototype verification platform based on vehicle gauge level millimeter wave radar SOC chip

Abstract

The invention discloses an FPGA prototype verification platform based on a vehicle gauge level millimeter wave radar SOC chip, and belongs to the technical field of chip verification. Comprising a data selection unit, a data generation unit, a data storage unit, a data transmission unit, a data processing unit, an analysis and verification unit and a result display unit. A signal selector is used for selecting different data, a dial switch is dialed to 0 to select data actually collected by a radio frequency front end and dialed to 1 to select test data in an HBM, and a verification platform is built by integrating a radio frequency front end analog chip, an ADC chip and an FPGA minimum system to verify the overall function of the millimeter wave radar SOC chip. The verification platform built by using a plurality of discrete devices can restore the function of a real millimeter wave radar SOC chip as much as possible, the risk of tape-out failure is greatly reduced, the HBM high-bandwidth memory integrated in the FPGA can replace plug-in DDR particles, and a higher transmission rate can be obtained, so that the development cost and power consumption of the verification platform can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to an FPGA prototype verification platform based on an automotive-grade millimeter-wave radar SOC chip. Background Art

[0002] With the development of science and technology, millimeter-wave radar is increasingly used in various fields, such as autonomous driving, drone navigation, industrial inspection, etc. Millimeter-wave radar is regarded as the first choice for long-distance detection in intelligent driving because of its advantages such as high accuracy, strong anti-interference ability, long detection distance, wide-angle detection and wide detection range.

[0003] In order to fully verify the functions of the millimeter-wave radar chip, ensure the reliability and stability of each functional module of the chip, and comprehensively cover the functional points, the FPGA verification platform should be used to restore the real usage scenario as much as possible before the SOC chip is taped out, because the FPGA implementation is closest to the real chip. At the same time, the design of the control software outside the chip can also be verified in advance on the verification platform. Compared with the slow speed of VCS simulation verification, FPGA prototype verification can find design problems faster. This FPGA-based verification method can not only discover potential problems in the design early, but also support the verification requirements of complex system-level integration, thereby reducing the risk of tape-out failure. At present, the general FPGA prototype verification platform only has the FPGA minimum system and some extended GPIOs, which can only meet the verification of some chips for intermediate frequency signal processing. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to provide an FPGA prototype verification platform based on an automotive-grade millimeter-wave radar SOC chip; it can solve the problem that the current common FPGA prototype verification platforms only have a minimum FPGA system and some extended GPIOs, and can only meet the verification of some intermediate frequency signal processing chips.

[0005] Technical solution: To solve the above technical problems, according to one aspect of the present invention, more specifically, an FPGA prototype verification platform based on an automotive-grade millimeter-wave radar SOC chip includes: a data selection unit, a data generation unit, a data storage unit, a data transmission unit, a data processing unit, an analysis and verification unit, and a result display unit;

[0006] Data selection unit: used to select data to be processed;

[0007] Data generation unit: used to generate various data required by the FPGA prototype verification platform;

[0008] Data storage unit: used to store the generated intermediate frequency test data of different configurations and different targets;

[0009] Data transmission unit: used to transmit data between various units of the platform;

[0010] Data processing unit: used to process data so that the data meets the requirements of use;

[0011] Analysis and verification unit: used to receive and analyze the data that needs to be analyzed and verified, and to determine the analysis results of the data;

[0012] Result display unit: used to display the results obtained by the analysis and calculation of the analysis and verification unit.

[0013] Furthermore, the data generation unit includes: a test data generation module and a real data simulation module;

[0014] Test data generation module: used to generate intermediate frequency test data with different configurations and targets;

[0015] Real data simulation module: used to set up the simulator to simulate different targets and provide real target data.

[0016] Furthermore, the analysis and verification unit includes: a data receiving module, a data analysis module and a result determination module;

[0017] Data receiving module: used to receive data that needs to be analyzed and verified;

[0018] Data analysis module: used to analyze, calculate and compare the data received by the data receiving module;

[0019] Result judgment module: used to judge the results of analysis, calculation and comparison of the data analysis module.

[0020] Going further, it includes: RF transceiver analog chip, ADC chip, and FPGA.

[0021] Furthermore, the FPGA adopts stacked silicon interconnect (SSI) technology, integrates high-bandwidth memory (HBM), deploys all the functions of the digital end of the SOC chip, integrates a 32-bit high-performance MCU processor, integrates commonly used peripheral interfaces, chip GPIO and radar algorithm system.

[0022] Furthermore, the data selection unit is a signal selector, and different data are selected through the signal selector. When the dip switch is turned to 0, the data actually collected by the RF front end is selected, and when it is turned to 1, the test data in the HBM is selected.

[0023] Furthermore, the analysis verification unit includes: a main verification test process and an auxiliary verification test process when performing analysis verification;

[0024] The main verification test process is the millimeter-wave radar chip target recognition process, and the auxiliary verification test process is the verification of each peripheral function.

[0025] Furthermore, the main verification test process is as follows: according to different configurations, the RF front end is controlled, the transmitting antenna is turned on to transmit the FMCW signal, and the echo signal is received through the receiving antenna of the RF front end at the same time, and converted into an intermediate frequency signal after mixing and filtering, and the corresponding 4-channel intermediate frequency signal is collected through the ADC, and the LVDS serial data is received, and serial-to-parallel conversion is performed, and the data source to be processed is selected according to the data selection switch, wherein the data actually collected by the RF front end is selected by dialing 0, and the test data in the HBM is selected by dialing 1, and the millimeter wave radar algorithm is started after collecting a frame of data, and the position, speed and azimuth of the target are calculated, and the calculated results are reported to the simulated MCU core, and the MCU core reports the information to the host computer through the network port and displays it in a graphical manner;

[0026] The auxiliary verification test process is: test the peripheral interfaces attached to the chip, including SPIA / B / C, QSPI, DEBUG_SPI, UARTA / B / C, CAN / CAN-FD, I2C0 / 1 and other peripheral interfaces, and verify the functions of the peripheral interfaces by comparing the sent and received data in the MCU core, and judge the comparison results in the MCU core. If the comparison result PASS, return to the initialization state, if the comparison result FAIL, repeat the verification test, and debug and locate related problems.

[0027] Furthermore, the RF transceiver analog chip is a RF transceiver analog chip with 4 transmit and 4 receive functions and a frequency band range of 76 GHz to 81 GHz.

[0028] Beneficial effects: FPGA integrates high bandwidth memory (HBM), which can provide terabit-level memory, and integrates a 32-bit high-performance MCU processor to schedule and control the entire system. This FPGA integrates 8GB of HBM. The host computer can download the echo intermediate frequency data under different configurations to the HBM through the optical port, and can verify the function of the SOC chip offline without using the RF front end. Due to the particularity of the application of the millimeter-wave radar SOC chip, the ultimate goal is to identify the distance, speed and azimuth angle of the target. Normal testing should be carried out in a dark room with absorbing materials, and the target is placed at a specified position, or a simulator simulating various targets is placed. However, in order to be able to reproduce and locate the problem more accurately in the early stage, and without building a complex test environment, the verification platform has added a data option. The host computer can download the echo intermediate frequency data under different configurations to the HBM inside the FPGA through the 10 Gigabit network optical port. Here, a signal selector is used to select different data. The DIP switch is turned to 0 to select the data actually collected by the RF front end, and turned to 1 to select the test data in the HBM. The verification platform is built by integrating the RF front-end analog chip, ADC chip and FPGA minimum system to verify the overall function of the millimeter-wave radar SOC chip. The verification platform built with multiple discrete devices can restore the function of the real millimeter-wave radar SOC chip as much as possible, greatly reducing the risk of tape-out failure. The HBM high-bandwidth memory integrated in the FPGA can replace the external DDR particles and obtain a higher transmission rate, which can reduce the development cost and power consumption of the verification platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is the overall framework diagram of the FPGA prototype verification platform;

[0030] Figure 2 It is a data flow diagram;

[0031] Figure 3 It is a process flow chart of the verification platform;

[0032] Figure 4 It is a schematic diagram of the principle of the verification platform. DETAILED DESCRIPTION

[0033] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] Example 1

[0035] exist Figure 1The structure block diagram of the overall verification platform is given in the figure. The platform uses a 4-transmit, 4-receive RF transceiver analog chip with a frequency range of 76GHz to 81GHz and an ADC chip that receives intermediate frequency signals to simulate the analog part of the SOC chip. Since the data interface of the ADC chip is an LVDS interface, the FPGA needs to add an LVDS interface driver in addition to the functions of the SOC chip. The FPGA in the figure uses stacked silicon interconnect (SSI) technology and integrates high-bandwidth memory (HBM), which can provide terabit-level memory. Figure 1 It can be seen that the FPGA deploys all the functions of the digital end of the SOC chip, including an integrated 32-bit high-performance MCU processor to schedule and control the entire system. In addition, it also integrates commonly used peripheral interfaces, chip GPIO and radar algorithm systems. Since this FPGA integrates 8GB of HBM, the host computer can download echo intermediate frequency data under different configurations to HBM through the optical port, and can test and verify the functions of the SOC chip offline without using the RF front end. The verification platform built with multiple discrete devices can restore the functions of the real millimeter-wave radar SOC chip as much as possible, greatly reducing the risk of tape-out failure. The HBM high-bandwidth memory integrated in the FPGA can replace the external DDR particles and obtain a higher transmission rate, which can reduce the development cost and power consumption of the verification platform.

[0036] exist Figure 2 The verification platform data flow is given in the figure. Due to the particularity of the millimeter wave radar SOC chip application, the ultimate goal is to identify the distance, speed and azimuth angle of the target. Normal testing should be carried out in a darkroom with absorbing materials, and the target should be placed in a specified position, or a simulator simulating various targets should be placed. However, in order to be able to reproduce and locate the problem more accurately in the early stage, and without building a complex test environment, the verification platform has added a data selection channel. The host computer can download the echo intermediate frequency data under different configurations to the HBM inside the FPGA through the 10 Gigabit network optical port. Here, use the signal selector to select different data. Turn the dip switch to 0 to select the data actually collected by the RF front end, and turn it to 1 to select the test data in the HBM.

[0037] exist Figure 3 The processing flow of the verification platform is given in , which includes the main verification test flow and the auxiliary verification test flow. The main verification test flow is the millimeter-wave radar chip target recognition process, and the auxiliary verification test flow is the verification of each peripheral function.

[0038] The main verification test process is as follows: according to different configurations, control the RF front end, turn on the transmitting antenna to transmit the FMCW signal, and at the same time receive the echo signal through the receiving antenna of the RF front end, and convert it into an intermediate frequency signal after mixing and filtering. The corresponding 4-channel intermediate frequency signal is collected through the ADC, and the LVDS serial data is received, and serial-to-parallel conversion is performed. According to the data selection switch, the data source to be processed is selected, where 0 is selected to select the data actually collected by the RF front end, and 1 is selected to select the test data in the HBM. After collecting a frame of data, the millimeter wave radar algorithm is started to process, and the position, speed and azimuth of the target are calculated, and the calculated results are reported to the simulated MCU core. The MCU core reports the information to the host computer through the network port and displays it in a graphical form.

[0039] The auxiliary verification test process is as follows: test the peripheral interfaces attached to the chip, including SPIA / B / C, QSPI, DEBUG_SPI, UARTA / B / C, CAN / CAN-FD, I2C0 / 1 and other peripheral interfaces. In the MCU core, the functions of the peripheral interfaces are verified by comparing the sent and received data. The comparison results are judged in the MCU core. If the comparison result is PASS, return to the initialization state. If the comparison result is FAIL, repeat the verification test and debug to locate related problems.

[0040] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An FPGA prototype verification platform based on an automotive-grade millimeter-wave radar SOC chip, characterized in that: include: Data selection unit, data generation unit, data storage unit, data transmission unit, data processing unit, analysis and verification unit and result display unit; Data selection unit: used to select data to be processed; Data generation unit: used to generate various data required by the FPGA prototype verification platform; Data storage unit: used to store the generated intermediate frequency test data of different configurations and different targets; Data transmission unit: used to transmit data between various units of the platform; Data processing unit: used to process data so that the data meets the requirements of use; Analysis and verification unit: used to receive and analyze the data that needs to be analyzed and verified, and to determine the analysis results of the data; Result display unit: used to display the results obtained by the analysis and calculation of the analysis and verification unit.

2. The FPGA prototype verification platform based on the automotive-grade millimeter-wave radar SOC chip according to claim 1 is characterized in that: The data generation unit includes: a test data generation module and a real data simulation module; Test data generation module: used to generate intermediate frequency test data with different configurations and targets; Real data simulation module: used to set up the simulator to simulate different targets and provide real target data.

3. The FPGA prototype verification platform based on the automotive-grade millimeter-wave radar SOC chip according to claim 1 is characterized in that: The analysis and verification unit includes: a data receiving module, a data analysis module and a result determination module; Data receiving module: used to receive data that needs to be analyzed and verified; Data analysis module: used to analyze, calculate and compare the data received by the data receiving module; Result determination module: used to determine the results of analysis, calculation and comparison of the data analysis module.

4. The FPGA prototype verification platform based on the automotive-grade millimeter-wave radar SOC chip according to claim 1 is characterized in that: include: RF transceiver analog chip, ADC chip, FPGA.

5. The FPGA prototype verification platform based on the automotive-grade millimeter-wave radar SOC chip according to claim 4 is characterized in that: The FPGA adopts stacked silicon interconnect (SSI) technology, integrates high bandwidth memory (HBM), deploys all the functions of the digital end of the SOC chip, integrates a 32-bit high-performance MCU processor, integrates commonly used peripheral interfaces, chip GPIO and radar algorithm system.

6. The FPGA prototype verification platform based on the automotive-grade millimeter-wave radar SOC chip according to claim 5 is characterized in that: The data selection unit is a signal selector, through which different data are selected. The dip switch is turned to 0 to select the data actually collected by the RF front end, and is turned to 1 to select the test data in the HBM.

7. The FPGA prototype verification platform based on the automotive-grade millimeter-wave radar SOC chip according to claim 6 is characterized in that: The analysis verification unit includes: a main verification test process and an auxiliary verification test process when performing analysis verification; The main verification test process is the millimeter-wave radar chip target recognition process, and the auxiliary verification test process is the verification of each peripheral function.

8. The FPGA prototype verification platform based on the automotive-grade millimeter-wave radar SOC chip according to claim 7 is characterized in that: The main verification test process is as follows: according to different configurations, the RF front end is controlled, the transmitting antenna is turned on to transmit the FMCW signal, and the echo signal is received through the receiving antenna of the RF front end at the same time, and converted into an intermediate frequency signal after mixing and filtering, and the corresponding 4-channel intermediate frequency signal is collected through the ADC, and the LVDS serial data is received, and serial-to-parallel conversion is performed, and the data source to be processed is selected according to the data selection switch, wherein the data actually collected by the RF front end is selected by dialing 0, and the test data in the HBM is selected by dialing 1, and the millimeter wave radar algorithm is started after collecting a frame of data, and the position, speed and azimuth of the target are calculated, and the calculated results are reported to the simulated MCU core, and the MCU core reports the information to the host computer through the network port and displays it in a graphical manner; The auxiliary verification test process is: test the peripheral interfaces attached to the chip, including SPIA / B / C, QSPI, DEBUG_SPI, UARTA / B / C, CAN / CAN-FD, I2C0 / 1 and other peripheral interfaces, and verify the functions of the peripheral interfaces by comparing the sent and received data in the MCU core, and judge the comparison results in the MCU core. If the comparison result PASS, return to the initialization state, if the comparison result FAIL, repeat the verification test, and debug and locate related problems.

9. The FPGA prototype verification platform based on the automotive-grade millimeter-wave radar SOC chip according to claim 8 is characterized in that: The radio frequency transceiver analog chip is a radio frequency transceiver analog chip with 4 transmit and 4 receive functions and a frequency band range of 76 GHz to 81 GHz.

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