Voltage supply module, voltage supply method and touch display device

Abstract

This invention provides a voltage supply module, a voltage supply method, and a touch display device. The voltage supply module is applied to a touch display device, which includes a driving module and multiple pixels. The driving module includes multi-stage driving circuits, and each pixel includes a switching transistor. The driving circuits provide a driving signal to the gate of the switching transistor. The voltage supply module includes a voltage supply circuit. During the touch phase, the voltage supply circuit controls the voltage signal supplied to the driving circuit to control the driving signal, thereby keeping the switching transistor in a turned-off state and controlling the leakage current of the switching transistor to be greater than or equal to 40pA and less than or equal to 120pA. This invention ensures flicker-free operation while avoiding excessive noise.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a voltage supply module, a voltage supply method, and a touch display device. Background Technology

[0002] In related technologies, with major mobile phone manufacturers constantly innovating, LPWG (Low Power Wake-up Gesture) functionality is becoming increasingly popular. During the touch phase, if the leakage current of the transistors in the driving circuit of the touch display product is too small, it cannot effectively release the charge, which can easily lead to LPWG sleep screen flickering problems; while if the leakage current is too large, touch noise is likely to occur during production and testing. Summary of the Invention

[0003] The main objective of this invention is to provide a voltage supply module, a voltage supply method, and a touch display device, which solves the problem that during the touch stage, the leakage current of the transistors in the driving circuit of the touch display product is too small, thus failing to effectively release charge and easily causing LPWG sleep flickering; while when the leakage current is too large, it easily causes touch noise during production and testing.

[0004] In one aspect, embodiments of the present invention provide a voltage supply module applied to a touch display device, the touch display device including a driving module and a plurality of pixels, the driving module including a multi-stage driving circuit, the pixels including switching transistors; the driving circuit providing a driving signal to the gate of the switching transistors; the voltage supply module including a voltage supply circuit;

[0005] The voltage supply circuit is used to control the driving signal during the touch phase by controlling the voltage signal supplied to the driving circuit, so that the switching transistor is in the off state, and to control the leakage current of the switching transistor to be greater than or equal to 40pA and less than or equal to 120pA.

[0006] Optionally, the driving circuit includes an output circuit, which is electrically connected to the first node, the output clock signal terminal, and the driving signal output terminal, respectively. The output circuit is used to provide the output clock signal provided by the output clock signal terminal to the driving signal output terminal under the control of the potential of the first node.

[0007] The voltage supply circuit is used to provide a positive modulation voltage signal or a negative modulation voltage signal to the output clock signal terminal during the touch phase;

[0008] The positive modulation voltage signal is a superposition signal of a DC positive voltage signal and an AC modulation voltage signal, the voltage value of the positive modulation voltage signal is greater than 0, and the AC modulation voltage signal is a square wave voltage signal;

[0009] The negative modulation voltage signal is a superposition signal of a DC negative voltage signal and an AC modulation voltage signal, and the voltage value of the negative modulation voltage signal is less than 0.

[0010] Optionally, the driving circuit further includes a frame reset circuit; the frame reset circuit is electrically connected to the frame reset terminal, the driving signal output terminal and the first voltage terminal respectively, and is used to write the first voltage signal provided by the first voltage terminal into the driving signal output terminal under the control of the frame reset signal provided by the frame reset terminal;

[0011] The voltage supply circuit is used to provide the negative modulation voltage signal to the frame reset terminal and the first voltage terminal during the touch phase.

[0012] Optionally, the driving circuit further includes a first node control circuit; the first node control circuit is electrically connected to the first node, the input terminal, the first control voltage terminal, the reset terminal, and the second control voltage terminal respectively, and is used to control the potential of the first node according to the first control voltage provided by the first control voltage terminal and the second control voltage provided by the second control voltage terminal under the control of the input signal provided by the input terminal and the reset signal provided by the reset terminal;

[0013] The voltage supply circuit is used to provide the negative modulation voltage signal to the first control voltage terminal and the second control voltage terminal during the touch phase.

[0014] Optionally, the driving circuit further includes a second node control circuit; the second node control circuit is electrically connected to the second voltage terminal, the first node, the first voltage terminal and the second node respectively, and is used to control the potential of the second node according to the first voltage signal provided by the first voltage terminal and the second voltage signal provided by the second voltage terminal under the control of the potential of the first node;

[0015] The voltage supply circuit is used to provide the negative modulation voltage signal to the first voltage terminal and the second voltage terminal during the touch phase.

[0016] Optionally, the driving circuit further includes an output control circuit; the output control circuit is electrically connected to the control clock signal terminal, the driving signal output terminal and the first voltage terminal respectively, and is used to control the connection or disconnection between the driving signal output terminal and the first voltage terminal under the control of the control clock signal provided by the control clock signal terminal;

[0017] The voltage supply circuit is used to provide the negative modulation voltage signal to the control clock signal terminal and the first voltage terminal during the touch phase.

[0018] Optionally, the input terminal of the first-stage drive circuit included in the drive module is electrically connected to the starting voltage terminal;

[0019] The voltage supply circuit is used to provide a negative modulated voltage signal to the starting voltage terminal during the touch phase.

[0020] In a second aspect, embodiments of the present invention provide a voltage supply method applied to the aforementioned voltage supply module, wherein the voltage supply module is applied to a touch display device, the touch display device including a driving module and a plurality of pixels, the driving module including a multi-stage driving circuit, and the pixels including switching transistors; the driving circuit provides a driving signal to the gate of the switching transistor; the voltage supply method includes:

[0021] During the touch phase, the voltage supply circuit controls the voltage signal supplied to the drive circuit to control the drive signal, so that the switching transistor is in the off state, and controls the leakage current of the switching transistor to be greater than or equal to 40pA and less than or equal to 120pA.

[0022] Optionally, the driving circuit includes an output circuit, which is electrically connected to the first node, the output clock signal terminal, and the driving signal output terminal, respectively. The output circuit is used to provide the output clock signal provided by the output clock signal terminal to the driving signal output terminal under the control of the potential of the first node. The voltage provision method includes:

[0023] During the touch phase, the voltage supply circuit provides a positive modulation voltage signal or a negative modulation voltage signal to the output clock signal terminal;

[0024] The positive modulation voltage signal is a superposition signal of a DC positive voltage signal and an AC modulation voltage signal, the voltage value of the positive modulation voltage signal is greater than 0, and the AC modulation voltage signal is a square wave voltage signal;

[0025] The negative modulation voltage signal is a superposition signal of a DC negative voltage signal and an AC modulation voltage signal, and the voltage value of the negative modulation voltage signal is less than 0.

[0026] Optionally, the driving circuit further includes a frame reset circuit; the frame reset circuit is electrically connected to the frame reset terminal, the driving signal output terminal, and the first voltage terminal respectively, and is used to write the first voltage signal provided by the first voltage terminal to the driving signal output terminal under the control of the frame reset signal provided by the frame reset terminal; the voltage providing method includes:

[0027] During the touch phase, the voltage supply circuit is used to provide the negative modulation voltage signal to the frame reset terminal and the first voltage terminal.

[0028] In a third aspect, embodiments of the present invention provide a touch display device, including a driving module and a plurality of pixels, wherein each pixel includes a switching transistor; the driving circuit provides a driving signal to the gate of the switching transistor; the touch display device further includes the voltage supply module described above.

[0029] The touch display device according to at least one embodiment of the present invention includes a timing controller;

[0030] The voltage supply module is included in the timing controller.

[0031] Optionally, the pixel further includes a pixel electrode; the gate of the switching transistor is electrically connected to the drive signal output terminal of the driving circuit, the first electrode of the switching transistor is electrically connected to the corresponding column data line, and the second electrode of the switching transistor is electrically connected to the pixel electrode.

[0032] The driving circuit includes an output circuit, an energy storage circuit, and a frame reset circuit;

[0033] The output circuit is electrically connected to the first node, the output clock signal terminal and the drive signal output terminal respectively, and is used to provide the output clock signal provided by the output clock signal terminal to the drive signal output terminal under the control of the potential of the first node.

[0034] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the drive signal output end.

[0035] The frame reset circuit is electrically connected to the frame reset terminal, the drive signal output terminal, and the first voltage terminal, respectively, and is used to write the first voltage signal provided by the first voltage terminal into the drive signal output terminal under the control of the frame reset signal provided by the frame reset terminal.

[0036] The voltage supply module, voltage supply method, and touch display device described in this embodiment of the invention can ensure flicker-free operation and avoid excessive noise. Attached Figure Description

[0037] Figure 1 This is a structural diagram of the voltage supply module according to at least one embodiment of the present invention;

[0038] Figure 2 This is a structural diagram of the voltage supply module according to at least one embodiment of the present invention;

[0039] Figure 3 This is a structural diagram of the voltage supply module according to at least one embodiment of the present invention;

[0040] Figure 4 This is a structural diagram of the voltage supply module according to at least one embodiment of the present invention;

[0041] Figure 5 This is a structural diagram of the voltage supply module according to at least one embodiment of the present invention;

[0042] Figure 6 This is a structural diagram of the voltage supply module according to at least one embodiment of the present invention;

[0043] Figure 7 This is a structural diagram of the voltage supply module according to at least one embodiment of the present invention;

[0044] Figure 8 This is a structural diagram of the voltage supply module according to at least one embodiment of the present invention;

[0045] Figure 9 This is a circuit diagram of at least one embodiment of the driving circuit;

[0046] Figure 10 yes Figure 9 The timing diagram of at least one embodiment of the driving circuit shown;

[0047] Figure 11A yes Figure 9 The timing diagram of at least one embodiment of the driving circuit shown;

[0048] Figure 11B This is a schematic diagram showing the relationship between the gate voltage Vg of the switching transistor and the leakage current Id of the switching transistor.

[0049] Figure 12 This is a circuit diagram of at least one embodiment of the driving circuit;

[0050] Figure 13 yes Figure 12 The timing diagram of at least one embodiment of the driving circuit shown;

[0051] Figure 14 This is a circuit diagram of at least one embodiment of the driving circuit;

[0052] Figure 15 yes Figure 14 The timing diagram of at least one embodiment of the driving circuit shown;

[0053] Figure 16 This is a circuit diagram of at least one embodiment of a pixel. Detailed Implementation

[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0056] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0057] The voltage supply module described in this embodiment of the invention is applied to a touch display device. The touch display device includes a driving module and multiple pixels. The driving module includes a multi-stage driving circuit, and each pixel includes a switching transistor. The driving circuit provides a driving signal to the gate of the switching transistor. The voltage supply module includes a voltage supply circuit.

[0058] The voltage supply circuit is used to control the driving signal during the touch phase by controlling the voltage signal supplied to the driving circuit, so that the switching transistor is in the off state, and to control the leakage current of the switching transistor to be greater than or equal to 40pA and less than or equal to 120pA.

[0059] When the voltage supply module described in this embodiment of the invention is working, during the touch stage, the voltage supply circuit controls the voltage signal supplied to the driving circuit to control the driving signal supplied to the gate of the switching transistor, so that the switching transistor is turned off, and the leakage current of the switching transistor is greater than or equal to 40pA and less than or equal to 120pA, which can ensure no screen flicker and avoid excessive noise.

[0060] Furthermore, the leakage current value can be greater than or equal to 50pA and less than or equal to 110pA.

[0061] For example, the leakage current value can be 40pA, 45pA, 50pA, 55pA, 60pA, 65pA, 70pA, 75pA, 80pA, 85pA, 90pA, 95pA, 96.7pA, 100pA, 105pA, 106pA, 110pA, 115pA, or 120pA.

[0062] In practical implementation, based on actual verification results, the safe leakage current range for LPWG (Low Power Wake-up Gesture) to prevent screen flicker is above 40pA. Furthermore, the leakage current of the switching transistor should not be too large in order to avoid excessive touch noise.

[0063] The voltage supply module described in this embodiment of the invention is applied to a touch display device. The touch display device includes a driving module and multiple pixels. The driving module includes a multi-stage driving circuit, and each pixel includes a switching transistor. The driving circuit provides a driving signal to the gate of the switching transistor. Figure 1 As shown, the voltage supply module includes a voltage supply circuit 11;

[0064] The voltage supply circuit 11 is electrically connected to the drive circuit 10. During the touch phase, it controls the voltage signal supplied to the drive circuit 10 to control the drive signal, so that the switching transistor is in the off state, and controls the leakage current of the switching transistor to be greater than or equal to 40pA and less than or equal to 120pA.

[0065] In at least one embodiment of the present invention, the driving circuit includes an output circuit, which is electrically connected to a first node, an output clock signal terminal and a driving signal output terminal, respectively. The output circuit is used to provide the output clock signal provided by the output clock signal terminal to the driving signal output terminal under the control of the potential of the first node.

[0066] The voltage supply circuit is used to provide a positive modulation voltage signal or a negative modulation voltage signal to the output clock signal terminal during the touch phase;

[0067] The positive modulation voltage signal is a superposition signal of a DC positive voltage signal and an AC modulation voltage signal, the voltage value of the positive modulation voltage signal is greater than 0, and the AC modulation voltage signal is a square wave voltage signal;

[0068] The negative modulation voltage signal is a superposition signal of a DC negative voltage signal and an AC modulation voltage signal, and the voltage value of the negative modulation voltage signal is less than 0.

[0069] Optionally, the voltage value of the positive DC voltage signal can be 6V, and the voltage value of the negative DC voltage signal can be -6V;

[0070] The AC modulated voltage signal can be a clock signal, and the absolute value of the AC modulated voltage signal can be greater than or equal to 3V and less than or equal to 4V.

[0071] In practice, during the touch phase, an AC modulated voltage signal is provided to the touch electrodes included in the touch display device for touch detection.

[0072] like Figure 2 As shown, the driving circuit includes an output circuit 21;

[0073] The output circuit 21 is electrically connected to the first node PU, the output clock signal terminal CLK, and the drive signal output terminal OT, respectively, and is used to provide the output clock signal provided by the output clock signal terminal CLK to the drive signal output terminal OT under the control of the potential of the first node PU.

[0074] The voltage supply circuit 11 is electrically connected to the output clock signal terminal CLK and is used to provide a positive modulation voltage signal or a negative modulation voltage signal to the output clock signal terminal CLK during the touch control phase.

[0075] In at least one embodiment of the present invention, the driving circuit further includes a frame reset circuit; the frame reset circuit is electrically connected to a frame reset terminal, a driving signal output terminal and a first voltage terminal respectively, and is used to write a first voltage signal provided by the first voltage terminal into the driving signal output terminal under the control of the frame reset signal provided by the frame reset terminal;

[0076] The voltage supply circuit is used to provide the negative modulation voltage signal to the frame reset terminal and the first voltage terminal during the touch phase.

[0077] like Figure 3 As shown, in Figure 2 Based on at least one embodiment shown, the driving circuit further includes a frame reset circuit 31;

[0078] The frame reset circuit 31 is electrically connected to the frame reset terminal STV0, the drive signal output terminal OT and the first voltage terminal V1 respectively, and is used to write the first voltage signal provided by the first voltage terminal V1 into the drive signal output terminal OT under the control of the frame reset signal provided by the frame reset terminal STV0.

[0079] The voltage supply circuit 11 is electrically connected to the frame reset terminal STV0 and the first voltage terminal V1 respectively, and is used to provide the negative modulation voltage signal to the frame reset terminal STV0 and the first voltage terminal V1 during the touch phase.

[0080] In at least one embodiment of the present invention, the driving circuit further includes a first node control circuit; the first node control circuit is electrically connected to a first node, an input terminal, a first control voltage terminal, a reset terminal, and a second control voltage terminal, respectively, and is used to control the potential of the first node according to the first control voltage provided by the first control voltage terminal and the second control voltage provided by the second control voltage terminal under the control of the input signal provided by the input terminal and the reset signal provided by the reset terminal;

[0081] The voltage supply circuit is used to provide the negative modulation voltage signal to the first control voltage terminal and the second control voltage terminal during the touch phase.

[0082] Optionally, the first voltage terminal can be a low voltage terminal.

[0083] like Figure 4 As shown, in Figure 3 Based on at least one embodiment shown, the driving circuit further includes a first node control circuit 41;

[0084] The first node control circuit 41 is electrically connected to the first node PU, the input terminal I1, the first control voltage terminal VDS, the reset terminal RST, and the second control voltage terminal VSD, respectively. It is used to control the potential of the first node PU under the control of the input signal provided by the input terminal I1 and the reset signal provided by the reset terminal RST, according to the first control voltage provided by the first control voltage terminal VDS and the second control voltage provided by the second control voltage terminal VSD.

[0085] The voltage supply circuit 11 is electrically connected to the first control voltage terminal VDS and the second control voltage terminal VSD, respectively, and is used to provide the negative modulation voltage signal to the first control voltage terminal VDS and the second control voltage terminal VSD during the touch phase.

[0086] exist Figure 4 In at least one embodiment shown, the first node control circuit 41 can control the connection or disconnection between the first node PU and the first control voltage terminal VDS under the control of the input signal, and control the connection or disconnection between the first node PU and the second control voltage terminal VSD under the control of the reset signal.

[0087] In at least one embodiment of the present invention, the driving circuit further includes a second node control circuit; the second node control circuit is electrically connected to a second voltage terminal, a first node, a first voltage terminal, and a second node, respectively, and is used to control the potential of the second node according to a first voltage signal provided by the first voltage terminal and a second voltage signal provided by the second voltage terminal under the control of the potential of the first node;

[0088] The voltage supply circuit is used to provide the negative modulation voltage signal to the first voltage terminal and the second voltage terminal during the touch phase.

[0089] like Figure 5 As shown, in Figure 4 Based on at least one embodiment shown, the driving circuit further includes a second node control circuit 51;

[0090] The second node control circuit 51 is electrically connected to the second voltage terminal V2, the first node PU, the first voltage terminal V1, and the second node PD, respectively, and is used to control the potential of the second node PD according to the first voltage signal provided by the first voltage terminal V1 and the second voltage signal provided by the second voltage terminal V2 under the control of the potential of the first node PU.

[0091] The voltage supply circuit 11 is also electrically connected to the second voltage terminal V2, and is used to provide the negative modulation voltage signal to the first voltage terminal V1 and the second voltage terminal V2 during the touch phase.

[0092] Optionally, the second voltage terminal can be a high voltage terminal.

[0093] In at least one embodiment of the present invention, the input terminal of the first-stage driving circuit included in the driving module is electrically connected to the starting voltage terminal;

[0094] The voltage supply circuit is used to provide a negative modulated voltage signal to the starting voltage terminal during the touch phase.

[0095] like Figure 6 As shown, in Figure 5 Based on at least one of the embodiments shown, the voltage supply circuit 11 is electrically connected to the starting voltage terminal STV for providing a negative modulation voltage signal to the starting voltage terminal STV during the touch phase.

[0096] In at least one embodiment of the present invention, the driving circuit further includes an output control circuit; the output control circuit is electrically connected to a control clock signal terminal, a driving signal output terminal and a first voltage terminal respectively;

[0097] The voltage supply circuit is used to provide the negative modulation voltage signal to the control clock signal terminal and the first voltage terminal during the touch phase.

[0098] like Figure 7 As shown, the driving circuit may include an output control circuit 71;

[0099] The output control circuit 71 is electrically connected to the control clock signal terminal CLKB, the drive signal output terminal OT, and the first voltage terminal V1, respectively, and is used to control the connection or disconnection between the drive signal output terminal OT and the first voltage terminal V1 under the control of the control clock signal provided by the control clock signal terminal CLKB.

[0100] The voltage supply circuit 11 is electrically connected to the control clock signal terminal CLKB and the first voltage terminal V1, respectively, and is used to provide the negative modulation voltage signal to the control clock signal terminal CLKB and the first voltage terminal V1 during the touch phase.

[0101] like Figure 8 As shown, at least one embodiment of the driving circuit may include an output circuit 21;

[0102] The output circuit 21 is electrically connected to the first node PU, the output clock signal terminal CLK, and the drive signal output terminal OT, respectively, and is used to provide the output clock signal provided by the output clock signal terminal CLK to the drive signal output terminal OT under the control of the potential of the first node PU.

[0103] The driving circuit also includes a frame reset circuit 31;

[0104] The frame reset circuit 31 is electrically connected to the frame reset terminal STV0, the drive signal output terminal OT and the first voltage terminal V1 respectively, and is used to write the first voltage signal provided by the first voltage terminal V1 into the drive signal output terminal OT under the control of the frame reset signal provided by the frame reset terminal STV0.

[0105] The driving circuit also includes a first node control circuit 41;

[0106] The first node control circuit 41 is electrically connected to the first node PU, the input terminal I1, the first control voltage terminal VDS, the reset terminal RST, and the second control voltage terminal VSD, respectively. It is used to control the potential of the first node PU under the control of the input signal provided by the input terminal I1 and the reset signal provided by the reset terminal RST, according to the first control voltage provided by the first control voltage terminal VDS and the second control voltage provided by the second control voltage terminal VSD.

[0107] The driving circuit also includes a second node control circuit 51;

[0108] The second node control circuit 51 is electrically connected to the second voltage terminal V2, the first node PU, the first voltage terminal V1, and the second node PD, respectively, and is used to control the potential of the second node PD according to the first voltage signal provided by the first voltage terminal V1 and the second voltage signal provided by the second voltage terminal V2 under the control of the potential of the first node PU.

[0109] The frame reset circuit 31 is also electrically connected to the first node PU, and is used to write the first voltage signal into the first node PU under the control of the frame reset signal.

[0110] The driving circuit also includes an output reset circuit 70;

[0111] The output reset circuit 70 is electrically connected to the second node PD, the drive signal output terminal OT, and the first voltage terminal V1, respectively, and is used to write the first voltage signal provided by the first voltage terminal V1 into the drive signal output terminal OT under the control of the potential of the second node PD.

[0112] like Figure 9 As shown, in Figure 8 Based on at least one of the embodiments shown, the first node control circuit includes a first transistor M1 and a second transistor M2; the frame reset circuit includes a third transistor M3 and a fourth transistor M4; the second node control circuit includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8; the output circuit includes an output transistor M0; the output reset circuit includes an output reset transistor MR; the driving circuit further includes a first capacitor C1; and the first node control circuit further includes a ninth transistor M9.

[0113] The gate of M1 is electrically connected to the input terminal I1, the source of M1 is electrically connected to the first control voltage terminal VDS, and the drain of M1 is electrically connected to the first node PU.

[0114] The gate of M2 is electrically connected to the reset terminal RST, the source of M1 is electrically connected to the first node PU, and the drain of M1 is electrically connected to the low voltage terminal VGL.

[0115] The gate of M3 is electrically connected to the frame reset terminal STV0, the source of M3 is electrically connected to the drive signal output terminal OT, and the drain of M3 is electrically connected to the low voltage terminal VGL.

[0116] The gate of M4 is electrically connected to the frame reset terminal STV0, the source of M4 is electrically connected to the first node PU, and the drain of M4 is electrically connected to the low voltage terminal VGL.

[0117] The gate of M5 is electrically connected to the pull-down control node PDCN, the source of M5 is electrically connected to the high voltage terminal GCH, and the drain of M5 is electrically connected to the second node PD.

[0118] The gate of M6 is electrically connected to the first node PU, the source of M6 is electrically connected to the second node PD, and the drain of M6 is electrically connected to the low voltage terminal VGL.

[0119] The gate and source of M7 are electrically connected to the high voltage terminal GCH, and the drain of M7 is electrically connected to the pull-down control node PDCN.

[0120] The gate of M8 is electrically connected to the first node PU, the source of M8 is electrically connected to the pull-down control node PDCN, and the drain of M8 is electrically connected to the low voltage terminal VGL.

[0121] The gate of M9 is electrically connected to the second node PD, the source of M9 is electrically connected to the first node PU, and the drain of M9 is electrically connected to the low voltage terminal VGL.

[0122] The first end of C1 is electrically connected to the first node PU, and the second end of C1 is electrically connected to the drive signal output terminal OT.

[0123] The gate of M0 is electrically connected to the first node PU, the source of M0 is electrically connected to the output clock signal terminal CLK, and the drain of M0 is electrically connected to the drive signal output terminal OT.

[0124] The gate of MR is electrically connected to the second node PD, the source of MR is electrically connected to the drive signal output terminal OT, and the drain of MR is electrically connected to the low voltage terminal VGL.

[0125] exist Figure 9 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, and the gate of the switching transistor included in the pixel is electrically connected to the driving signal output terminal OT, wherein the switching transistor is an n-type transistor.

[0126] exist Figure 9 In at least one embodiment of the driving circuit shown, during the display stage, the high-voltage terminal GCH outputs a high-voltage signal and the low-voltage terminal VGL outputs a low-voltage signal.

[0127] like Figure 10 As shown, Figure 9 At least one embodiment of the driving circuit shown, during operation, in the touch phase ST,

[0128] Provide a positive modulation voltage signal to the output clock signal terminal CLK;

[0129] Provide a negative modulation voltage signal to the frame reset terminal STV0;

[0130] Provide a negative modulation voltage signal to the high-voltage terminal GCH;

[0131] Provide a negative modulation voltage signal to the low voltage terminal VGL;

[0132] A negative modulation voltage signal is provided to the first control voltage terminal VDS;

[0133] Provide a negative modulation voltage signal to the second control voltage terminal VSD;

[0134] Provide a negative modulation voltage signal to the starting voltage terminal STV;

[0135] Provide a negative modulation voltage signal to the data line DL;

[0136] A negative modulation voltage signal is provided to the common electrode line Com;

[0137] During the touch phase ST, Figure 9 In at least one embodiment of the driving circuit shown, the transistors are all in the off state.

[0138] There is a first capacitor C1 between CLK and OT, and there is a large overlapping area. Under the coupling effect of C1, it is possible to achieve a -2V voltage signal output by OT during the touch stage ST. At this time, the leakage current of the switching transistor in the pixel (the gate of the switching transistor is electrically connected to OT) is beneficial to controlling touch noise and can also ensure the effective release of charge during the touch signal transmission process, so as to ensure that there is no screen flickering problem in LPWG mode.

[0139] like Figure 11A As shown, Figure 9 At least one embodiment of the driving circuit shown, during operation, in the touch phase ST,

[0140] Provide a negative modulation voltage signal to the output clock signal terminal CLK;

[0141] Provide a negative modulation voltage signal to the frame reset terminal STV0;

[0142] Provide a negative modulation voltage signal to the high-voltage terminal GCH;

[0143] Provide a negative modulation voltage signal to the low voltage terminal VGL;

[0144] A negative modulation voltage signal is provided to the first control voltage terminal VDS;

[0145] Provide a negative modulation voltage signal to the second control voltage terminal VSD;

[0146] Provide a negative modulation voltage signal to the starting voltage terminal STV;

[0147] Provide a negative modulation voltage signal to the data line DL;

[0148] A negative modulation voltage signal is provided to the common electrode line Com;

[0149] During the touch phase ST, Figure 9 In at least one embodiment of the driving circuit shown, the transistors are all in the off state.

[0150] There is a first capacitor C1 between CLK and OT, and there is a large overlapping area. Under the coupling effect of C1, it is possible to achieve a -1V voltage signal output by OT during the touch stage ST. At this time, the leakage current of the switching transistor in the pixel (the gate of the switching transistor is electrically connected to OT) is beneficial to controlling touch noise and can also ensure the effective release of charge during the touch signal transmission process, so as to ensure that there is no screen flickering problem in LPWG mode.

[0151] Figure 11B This is a schematic diagram showing the relationship between the gate voltage Vg of the switching transistor and the leakage current Id of the switching transistor.

[0152] exist Figure 11B In the diagram, the horizontal axis represents the gate voltage Vg of the switching transistor, and the vertical axis represents the leakage current of the switching transistor.

[0153] like Figure 11B As shown, when the gate voltage Vg of the switching transistor is greater than or equal to -2V and less than or equal to -1V, the current value of Id is moderate, which is beneficial to control touch noise and ensures the effective release of charge during the touch signal transmission process, so as to ensure that there is no screen flickering problem in LPWG mode.

[0154] like Figure 12 As shown, at least one embodiment of the driving circuit may include a first node control circuit, an output circuit, an output reset circuit, a second node control circuit, a frame reset circuit, and an output control circuit.

[0155] The first node control circuit includes a first transistor M1, a second transistor M2, and a ninth transistor M9; the frame reset circuit includes a third transistor M3; the second node control circuit includes a tenth transistor M10 and a second capacitor C2; the output circuit includes an output transistor M0; the output reset circuit includes an output reset transistor MR; the driving circuit also includes a first capacitor C1; and the output control circuit includes an eleventh transistor M11 and a twelfth transistor M12.

[0156] The gate of M1 is electrically connected to the input terminal I1, the source of M1 is electrically connected to the first control voltage terminal VDS, and the drain of M1 is electrically connected to the first node PU.

[0157] The gate of M2 is electrically connected to the reset terminal RST, the source of M1 is electrically connected to the first node PU, and the drain of M1 is electrically connected to the low voltage terminal VGL.

[0158] The gate of M9 is electrically connected to the second node PD, the source of M9 is electrically connected to the first node PU, and the drain of M9 is electrically connected to the low voltage terminal VGL.

[0159] The gate of M10 is electrically connected to the first node PU, the source of M10 is electrically connected to the second node PD, and the drain of M10 is electrically connected to the low voltage terminal VGL.

[0160] The first terminal of C2 is electrically connected to the output clock signal terminal CLK, and the second terminal of C2 is electrically connected to the second node PD.

[0161] The gate of M3 is electrically connected to the frame reset terminal STV0, the source of M3 is electrically connected to the drive signal output terminal OT, and the drain of M3 is electrically connected to the low voltage terminal VGL.

[0162] The gate of M11 is electrically connected to the control clock signal terminal CLKB, the source of M11 is electrically connected to the drive signal output terminal OT, and the drain of M11 is electrically connected to the low voltage terminal VGL.

[0163] The gate of M12 is electrically connected to the first control terminal TPC, the source of M12 is electrically connected to the drive signal output terminal OT, and the drain of M12 is electrically connected to the low voltage terminal VGL.

[0164] The first end of C1 is electrically connected to the first node PU, and the second end of C1 is electrically connected to the drive signal output terminal OT.

[0165] The gate of M0 is electrically connected to the first node PU, the source of M0 is electrically connected to the output clock signal terminal CLK, and the drain of M0 is electrically connected to the drive signal output terminal OT.

[0166] The gate of MR is electrically connected to the second node PD, the source of MR is electrically connected to the drive signal output terminal OT, and the drain of MR is electrically connected to the low voltage terminal VGL.

[0167] exist Figure 12 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, and the gate of the switching transistor included in the pixel is electrically connected to the driving signal output terminal OT, wherein the switching transistor is an n-type transistor.

[0168] like Figure 13 As shown, Figure 12 At least one embodiment of the driving circuit shown, during operation, in the touch phase ST,

[0169] Provide a negative modulation voltage signal to the output clock signal terminal CLK;

[0170] Provide a negative modulation voltage signal to the frame reset terminal STV0;

[0171] Provide a negative modulation voltage signal to the low voltage terminal VGL;

[0172] A negative modulation voltage signal is provided to the first control voltage terminal VDS;

[0173] Provide a negative modulation voltage signal to the second control voltage terminal VSD;

[0174] Provide a negative modulation voltage signal to the starting voltage terminal STV;

[0175] Provide a negative modulation voltage signal to the control clock signal terminal CLKB;

[0176] Provide a negative modulation voltage signal to the first control terminal TPC;

[0177] Provide a negative modulation voltage signal to the data line DL;

[0178] A negative modulation voltage signal is provided to the common electrode line Com;

[0179] During the touch phase ST, Figure 12 In at least one embodiment of the driving circuit shown, the transistors are all in the off state.

[0180] There is a first capacitor C1 between CLK and OT, and there is a large overlapping area. Under the coupling effect of C1, the leakage current of the switching transistor in the pixel (the gate of the switching transistor is electrically connected to OT) during the touch stage ST can be controlled. This is beneficial to controlling touch noise and ensuring the effective release of charge during the touch signal transmission process, so as to ensure that there is no screen flickering problem in LPWG mode.

[0181] like Figure 14 As shown, at least one embodiment of the driving circuit may include a first node control circuit, an output circuit, an output reset circuit, a second node control circuit, a frame reset circuit, and an output control circuit; the first node control circuit includes a first transistor M1, a second transistor M2, and a ninth transistor M9; the frame reset circuit includes a third transistor M3, a fourth transistor M4, and a thirteenth transistor M13; the second node control circuit includes a tenth transistor M10, a fourteenth transistor M14, and a fifteenth transistor M15; the output circuit includes an output transistor M0; the output reset circuit includes an output reset transistor MR; the driving circuit also includes a first capacitor C1; and the output control circuit includes an eleventh transistor M11.

[0182] The gate of M1 is electrically connected to the input terminal I1, the source of M1 is electrically connected to the first control voltage terminal VDS, and the drain of M1 is electrically connected to the first node PU.

[0183] The gate of M2 is electrically connected to the reset terminal RST, the source of M1 is electrically connected to the first node PU, and the drain of M1 is electrically connected to the low voltage terminal VGL.

[0184] The gate of M9 is electrically connected to the second node PD, the source of M9 is electrically connected to the first node PU, and the drain of M9 is electrically connected to the low voltage terminal VGL.

[0185] The gate of M3 is electrically connected to the frame reset terminal STV0, the source of M3 is electrically connected to the drive signal output terminal OT, and the drain of M3 is electrically connected to the low voltage terminal VGL.

[0186] The gate of M4 is electrically connected to the frame reset terminal STV0, the source of M4 is electrically connected to the first node PU, and the drain of M4 is electrically connected to the low voltage terminal VGL.

[0187] The gate of M13 is electrically connected to the frame reset terminal STV0, the source of M13 is electrically connected to the second node PD, and the drain of M13 is electrically connected to the low voltage terminal VGL.

[0188] The gate and source of M14 are electrically connected to the output clock signal terminal CLK, and the drain of M14 is electrically connected to the second node PD.

[0189] The gate of M10 is electrically connected to the first node PU, the source of M10 is electrically connected to the second node PD, and the drain of M10 is electrically connected to the low voltage terminal VGL.

[0190] The gate of M15 is electrically connected to the control clock signal terminal CLKB, the source of M15 is electrically connected to the second node PD, and the drain of M15 is electrically connected to the low voltage terminal VGL.

[0191] The gate of M11 is electrically connected to the control clock signal terminal CLKB, the source of M11 is electrically connected to the drive signal output terminal OT, and the drain of M11 is electrically connected to the low voltage terminal VGL.

[0192] The first end of C1 is electrically connected to the first node PU, and the second end of C1 is electrically connected to the drive signal output terminal OT.

[0193] The gate of M0 is electrically connected to the first node PU, the source of M0 is electrically connected to the output clock signal terminal CLK, and the drain of M0 is electrically connected to the drive signal output terminal OT.

[0194] The gate of MR is electrically connected to the second node PD, the source of MR is electrically connected to the drive signal output terminal OT, and the drain of MR is electrically connected to the low voltage terminal VGL.

[0195] exist Figure 14 In at least one embodiment of the driving circuit shown, all transistors are n-type transistors, and the gate of the switching transistor included in the pixel is electrically connected to the driving signal output terminal OT, wherein the switching transistor is an n-type transistor.

[0196] like Figure 15 As shown, Figure 14 At least one embodiment of the driving circuit shown, during operation, in the touch phase ST,

[0197] Provide a negative modulation voltage signal to the output clock signal terminal CLK;

[0198] Provide a negative modulation voltage signal to the frame reset terminal STV0;

[0199] Provide a negative modulation voltage signal to the low voltage terminal VGL;

[0200] A negative modulation voltage signal is provided to the first control voltage terminal VDS;

[0201] Provide a negative modulation voltage signal to the second control voltage terminal VSD;

[0202] Provide a negative modulation voltage signal to the starting voltage terminal STV;

[0203] Provide a negative modulation voltage signal to the control clock signal terminal CLKB;

[0204] Provide a negative modulation voltage signal to the data line DL;

[0205] A negative modulation voltage signal is provided to the common electrode line Com;

[0206] During the touch phase ST, Figure 14 In at least one embodiment of the driving circuit shown, the transistors are all in the off state.

[0207] There is a first capacitor C1 between CLK and OT, and there is a large overlapping area. Under the coupling effect of C1, the leakage current of the switching transistor in the pixel (the gate of the switching transistor is electrically connected to OT) during the touch stage ST can be controlled. This is beneficial to controlling touch noise and ensuring the effective release of charge during the touch signal transmission process, so as to ensure that there is no screen flickering problem in LPWG mode.

[0208] The voltage supply method described in this embodiment of the invention is applied to the aforementioned voltage supply module, which is applied to a touch display device. The touch display device includes a driving module and multiple pixels. The driving module includes a multi-stage driving circuit, and each pixel includes a switching transistor. The driving circuit provides a driving signal to the gate of the switching transistor. The voltage supply method comprises:

[0209] During the touch phase, the voltage supply circuit controls the voltage signal supplied to the drive circuit to control the drive signal, so that the switching transistor is in the off state, and controls the leakage current of the switching transistor to be greater than or equal to 40pA and less than or equal to 120pA.

[0210] In the voltage supply method described in this embodiment of the invention, during the touch stage, the voltage supply circuit controls the voltage signal supplied to the driving circuit to control the driving signal supplied to the gate of the switching transistor, so that the switching transistor is turned off, and the leakage current of the switching transistor is greater than or equal to 40pA and less than or equal to 120pA, which can ensure no screen flicker and avoid excessive noise.

[0211] In at least one embodiment of the present invention, the touch display device may include a plurality of pixels;

[0212] like Figure 16 As shown, the pixel includes a switching transistor KT and a pixel electrode PJ;

[0213] The gate of the switching transistor KT is electrically connected to the scan line GT, the source of the switching transistor KT is electrically connected to the data line DL, and the drain of the switching transistor KT is electrically connected to the pixel electrode PJ.

[0214] KT is an n-type transistor;

[0215] The scan line GT is electrically connected to the drive signal output terminal of the drive circuit, receives the drive signal from the drive circuit, and provides the drive signal to the gate of the switching transistor KT.

[0216] Figure 16 In at least one embodiment of the pixel shown, when the driving circuit provides a high voltage signal to the gate of the KT, the KT is turned on to provide the data voltage provided by the data line DL to the pixel electrode PJ.

[0217] In a specific implementation, KT can also be a p-type transistor. When KT is a p-type transistor, the driving circuit provides a low voltage signal to the gate of KT so that KT is turned on and the data voltage provided by the data line DL is written to the pixel electrode PJ.

[0218] In at least one embodiment of the present invention, the driving circuit includes an output circuit, which is electrically connected to a first node, an output clock signal terminal, and a driving signal output terminal, respectively. The output circuit is used to provide an output clock signal provided by the output clock signal terminal to the driving signal output terminal under the control of the potential of the first node; the voltage providing method includes:

[0219] During the touch phase, the voltage supply circuit provides a positive modulation voltage signal or a negative modulation voltage signal to the output clock signal terminal;

[0220] The positive modulation voltage signal is a superposition signal of a DC positive voltage signal and an AC modulation voltage signal, the voltage value of the positive modulation voltage signal is greater than 0, and the AC modulation voltage signal is a square wave voltage signal;

[0221] The negative modulation voltage signal is a superposition signal of a DC negative voltage signal and an AC modulation voltage signal, and the voltage value of the negative modulation voltage signal is less than 0.

[0222] In at least one embodiment of the present invention, the driving circuit further includes a frame reset circuit; the frame reset circuit is electrically connected to a frame reset terminal, a driving signal output terminal, and a first voltage terminal, respectively, and is used to write a first voltage signal provided by the first voltage terminal into the driving signal output terminal under the control of a frame reset signal provided by the frame reset terminal; the voltage providing method includes:

[0223] During the touch phase, the voltage supply circuit is used to provide the negative modulation voltage signal to the frame reset terminal and the first voltage terminal.

[0224] The touch display device according to the embodiments of the present invention includes a driving module and a plurality of pixels, wherein each pixel includes a switching transistor; the driving circuit provides a driving signal to the gate of the switching transistor; the touch display device further includes the voltage supply module described above.

[0225] The touch display device according to at least one embodiment of the present invention includes a timing controller;

[0226] The voltage supply module is included in the timing controller.

[0227] In at least one embodiment of the present invention, the pixel further includes a pixel electrode; the gate of the switching transistor is electrically connected to the driving signal output terminal of the driving circuit, the first electrode of the switching transistor is electrically connected to the corresponding column data line, and the second electrode of the switching transistor is electrically connected to the pixel electrode.

[0228] The driving circuit includes an output circuit, an energy storage circuit, and a frame reset circuit;

[0229] The output circuit is electrically connected to the first node, the output clock signal terminal and the drive signal output terminal respectively, and is used to provide the output clock signal provided by the output clock signal terminal to the drive signal output terminal under the control of the potential of the first node.

[0230] The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the drive signal output end.

[0231] The frame reset circuit is electrically connected to the frame reset terminal, the drive signal output terminal, and the first voltage terminal, respectively, and is used to write the first voltage signal provided by the first voltage terminal into the drive signal output terminal under the control of the frame reset signal provided by the frame reset terminal.

[0232] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A voltage supply module applied to a touch display device, the touch display device including a driving module and a plurality of pixels, the driving module including a multi-stage driving circuit, and the pixels including switching transistors; The driving circuit provides a driving signal to the gate of the switching transistor; characterized in that, The voltage supply module includes a voltage supply circuit; The voltage supply circuit is used to control the driving signal during the touch phase by controlling the voltage signal supplied to the driving circuit, thereby controlling the driving signal so that the switching transistor is in a turned-off state, and controlling the leakage current of the switching transistor to be greater than or equal to 40pA and less than or equal to 120pA; The driving circuit includes an output circuit, which is electrically connected to the first node, the output clock signal terminal, and the driving signal output terminal, respectively. The output circuit is used to provide the output clock signal provided by the output clock signal terminal to the driving signal output terminal under the control of the potential of the first node. The voltage supply circuit is used to provide a positive modulation voltage signal or a negative modulation voltage signal to the output clock signal terminal during the touch phase; The positive modulation voltage signal is a superposition of a DC positive voltage signal and an AC modulation voltage signal, the voltage value of the positive modulation voltage signal is greater than 0, and the AC modulation voltage signal is a square wave voltage signal; the negative modulation voltage signal is a superposition of a DC negative voltage signal and the AC modulation voltage signal, and the voltage value of the negative modulation voltage signal is less than 0. The AC modulated voltage signal is a clock signal.

2. The voltage supply module as described in claim 1, characterized in that, The driving circuit further includes a frame reset circuit; the frame reset circuit is electrically connected to the frame reset terminal, the driving signal output terminal and the first voltage terminal respectively, and is used to write the first voltage signal provided by the first voltage terminal into the driving signal output terminal under the control of the frame reset signal provided by the frame reset terminal; The voltage supply circuit is used to provide the negative modulation voltage signal to the frame reset terminal and the first voltage terminal during the touch phase.

3. The voltage supply module as described in claim 1, characterized in that, The driving circuit further includes a first node control circuit; the first node control circuit is electrically connected to the first node, the input terminal, the first control voltage terminal, the reset terminal, and the second control voltage terminal respectively, and is used to control the potential of the first node according to the first control voltage provided by the first control voltage terminal and the second control voltage provided by the second control voltage terminal under the control of the input signal provided by the input terminal and the reset signal provided by the reset terminal; The voltage supply circuit is used to provide the negative modulation voltage signal to the first control voltage terminal and the second control voltage terminal during the touch phase.

4. The voltage supply module as described in claim 1, characterized in that, The driving circuit further includes a second node control circuit; the second node control circuit is electrically connected to the second voltage terminal, the first node, the first voltage terminal and the second node respectively, and is used to control the potential of the second node according to the first voltage signal provided by the first voltage terminal and the second voltage signal provided by the second voltage terminal under the control of the potential of the first node; The voltage supply circuit is used to provide the negative modulation voltage signal to the first voltage terminal and the second voltage terminal during the touch phase.

5. The voltage supply module as described in claim 1, characterized in that, The driving circuit further includes an output control circuit; the output control circuit is electrically connected to the control clock signal terminal, the driving signal output terminal and the first voltage terminal respectively, and is used to control the connection or disconnection between the driving signal output terminal and the first voltage terminal under the control of the control clock signal provided by the control clock signal terminal; The voltage supply circuit is used to provide the negative modulation voltage signal to the control clock signal terminal and the first voltage terminal during the touch phase.

6. The voltage supply module as described in claim 1, characterized in that, The input terminal of the first-stage drive circuit in the drive module is electrically connected to the starting voltage terminal; The voltage supply circuit is used to provide a negative modulated voltage signal to the starting voltage terminal during the touch phase.

7. A voltage supply method applied to a voltage supply module as described in any one of claims 1 to 6, the voltage supply module being applied to a touch display device, the touch display device including a driving module and a plurality of pixels, the driving module including a multi-stage driving circuit, and the pixels including switching transistors; The driving circuit provides a driving signal to the gate of the switching transistor; characterized in that, The voltage supply method includes: During the touch control phase, the voltage supply circuit controls the voltage signal supplied to the drive circuit to control the drive signal, thereby turning off the switching transistor and controlling the leakage current of the switching transistor to be greater than or equal to 40pA and less than or equal to 120pA. The driving circuit includes an output circuit, which is electrically connected to the first node, the output clock signal terminal, and the driving signal output terminal, respectively. The output circuit, under the control of the potential of the first node, provides the output clock signal provided by the output clock signal terminal to the driving signal output terminal. The voltage provision method includes: During the touch phase, the voltage supply circuit provides a positive modulation voltage signal or a negative modulation voltage signal to the output clock signal terminal; The positive modulation voltage signal is a superposition of a DC positive voltage signal and an AC modulation voltage signal, the voltage value of the positive modulation voltage signal is greater than 0, and the AC modulation voltage signal is a square wave voltage signal; the negative modulation voltage signal is a superposition of a DC negative voltage signal and the AC modulation voltage signal, and the voltage value of the negative modulation voltage signal is less than 0. The AC modulated voltage signal is a clock signal.

8. The voltage supply method as described in claim 7, characterized in that, The driving circuit further includes a frame reset circuit; the frame reset circuit is electrically connected to the frame reset terminal, the driving signal output terminal and the first voltage terminal respectively, and is used to write the first voltage signal provided by the first voltage terminal into the driving signal output terminal under the control of the frame reset signal provided by the frame reset terminal; The voltage supply method includes: During the touch phase, the voltage supply circuit is used to provide the negative modulation voltage signal to the frame reset terminal and the first voltage terminal.

9. A touch display device, comprising a driving module and a plurality of pixels, wherein each pixel includes a switching transistor; the driving circuit provides a driving signal to the gate of the switching transistor; characterized in that, The touch display device further includes a voltage supply module as described in any one of claims 1 to 6.

10. The touch display device as claimed in claim 9, characterized in that, Including timing controllers; The voltage supply module is included in the timing controller.

11. The touch display device as claimed in claim 9, characterized in that, The pixel further includes a pixel electrode; the gate of the switching transistor is electrically connected to the drive signal output terminal of the driving circuit, the first electrode of the switching transistor is electrically connected to the corresponding column data line, and the second electrode of the switching transistor is electrically connected to the pixel electrode. The driving circuit includes an output circuit, an energy storage circuit, and a frame reset circuit; The output circuit is electrically connected to the first node, the output clock signal terminal and the drive signal output terminal respectively, and is used to provide the output clock signal provided by the output clock signal terminal to the drive signal output terminal under the control of the potential of the first node. The first end of the energy storage circuit is electrically connected to the first node, and the second end of the energy storage circuit is electrically connected to the drive signal output end. The frame reset circuit is electrically connected to the frame reset terminal, the drive signal output terminal, and the first voltage terminal, respectively, and is used to write the first voltage signal provided by the first voltage terminal into the drive signal output terminal under the control of the frame reset signal provided by the frame reset terminal.

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