Separation gate trench MOSFET device and preparation method thereof

Abstract

The invention discloses a preparation method of a separated gate trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which comprises the following steps of: 1) selecting a substrate with an N-epitaxial layer, and photoetching a trench on the N-epitaxial layer through a hard mask; 2) removing the mask plate, and performing wet oxygen oxidation to form a first oxide layer; (3) a layer of polycrystalline silicon is deposited on the first oxide layer through chemical vapor deposition, then redundant polycrystalline silicon is etched away through etching, and the remaining polycrystalline silicon reserved in the groove is polycrystalline silicon I; (4) the redundant oxide layer is etched away; (5) growing a second polycrystalline silicon oxide layer, and performing gate back etching; and 6) filling the polysilicon gate in the groove through chemical vapor deposition again, and performing dry back-etching until the polysilicon gate is flush with the upper surface of the N-type epitaxial layer. According to the split gate trench MOSFET device, a split gate structure is adopted, and a produced power device has higher process stability and reliability, higher switching speed, smaller gate-drain capacitance and higher application efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a separated-gate trench MOSFET device and a preparation method thereof. Background Art

[0002] The working principle of the split-gate trench MOSFET is the same as that of the general MOSFET. They are both gate-controlled devices. They use the charge compensation principle to introduce a split polysilicon gate with the same potential as the source into the bottom of the polysilicon gate of the ordinary trench MOSFET. The internal field plate is used to assist the depletion of the drift region of the MOSFET. By setting a low-resistance drift region while ensuring the withstand voltage level, the RDS(ON) of the low-power MOS device can be significantly reduced. At present, the split-gate trench MOSFET is not only used as a power switch, but also used in many linear applications in many scenarios, such as linear regulators, linear amplifiers, electronic loads, hot-swap circuits, etc.

[0003] However, most split-gate trench MOSFET devices suffer from poor transconductance stability due to the shielding effect of the split-gate structure on the channel voltage under high Vds voltage. Summary of the invention

[0004] The object of the present invention is to provide a split-gate trench MOSFET device and a method for preparing the same.

[0005] To achieve this object, the present invention adopts the following technical solutions: A method for preparing a split-gate trench MOSFET device comprises the following steps: 1) Select a substrate with an N-epitaxial layer and photolithograph a groove on the N-epitaxial layer through a hard mask; 2) Remove the mask, dry oxidize at 945℃~955℃ and normal pressure for 15-25min, and then continue wet oxygen oxidation at 945℃~955℃ and normal pressure for 150-200min to form the first oxide layer; 3) A layer of polysilicon is deposited on the first oxide layer by chemical vapor deposition, and then the polysilicon on the first oxide layer outside the trench is etched away by etching, and part of the polysilicon in the trench is etched away, and the remaining polysilicon in the trench is polysilicon I; 4) On the basis of step 3), etching away the excess oxide layer, wherein the excess oxide layer includes the first oxide layer on the N-epitaxial layer outside the trench and a portion of the first oxide layer in the trench; 5) Dry oxygen oxidation is performed again at 945℃~955℃ and atmospheric pressure for 105~115min, and then wet oxygen oxidation is performed at 945℃~955℃ and atmospheric pressure for 150-200min on the second polysilicon oxide layer, and gate etching is performed. The thickness of the second polysilicon oxide layer is less than the thickness of the first oxide layer; 6) Fill the trench with polysilicon gate again by chemical vapor deposition and dry-etch back until it is flush with the upper surface of the N-type epitaxial layer.

[0006] As a specific implementation manner, the depth of the groove photoetched in step 1) is 1.8-2 μm.

[0007] As a specific implementation, in step 2), the thickness of the first oxide layer formed by wet oxygen oxidation is 950-1050 Å.

[0008] As a specific implementation manner, in step 3), the thickness of the polysilicon I retained in the trench is 0.8±0.05 μm.

[0009] As a specific implementation manner, the thickness of the second polysilicon oxide layer is 555±20 Å.

[0010] As a specific implementation manner, the width of the groove photoetched in step 1) is 0.7±0.05 μm.

[0011] Another object of the present invention is to provide a separated gate trench MOSFET device, which is prepared by the above-mentioned preparation method, and the device includes a substrate with an N-epitaxial layer, a groove is opened on the N-epitaxial layer, a first oxide layer and a second polysilicon oxide layer are arranged in the groove, the second polysilicon oxide layer is located above the first oxide layer, the first oxide layer is filled with polysilicon I, the second polysilicon oxide layer is filled with a polysilicon gate, and the polysilicon I and the polysilicon gate are separated by an oxide layer.

[0012] Compared with the prior art, the technical solution of the present invention has the following advantages: the separated gate trench MOSFET device of the present invention adopts a separated gate structure, and the power device produced has higher process stability and reliability, faster switching speed, smaller gate-drain capacitance and higher application efficiency, and is widely used in the field of medium and low voltage MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A process flow chart of manufacturing a split-gate trench MOSFET device according to the present invention; Wherein: 1. substrate; 2. N-epitaxial layer; 3. trench; 4. hard mask; 5. first oxide layer; 6. polysilicon; 7. polysilicon I; 8. second polysilicon oxide layer; 9. polysilicon gate. DETAILED DESCRIPTION

[0014] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific embodiments.

[0015] The present invention provides a separated gate trench MOSFET device, which comprises a substrate 1 with an N-epitaxial layer 2, a trench 3 is formed on the N-epitaxial layer 2, a first oxide layer 5 and a second polysilicon oxide layer 8 are arranged in the trench 3, the second polysilicon oxide layer 8 is located above the first oxide layer 5, the first oxide layer 5 is filled with polysilicon I7, the second polysilicon oxide layer 8 is filled with polysilicon gate 9, and the polysilicon I7 and the polysilicon gate 9 are separated by an oxide layer.

[0016] Here, the groove 3 has a depth of 1.8~2μm and a width of 0.7±0.05μm; the thickness of the first oxide layer is 950~1050A; the thickness of polysilicon I is 0.8±0.05μm; and the thickness of the second polysilicon oxide layer is 555±20A.

[0017] The specific preparation process of the above device is as follows, see Figure 1 As shown: 1) Select a substrate with an N-epitaxial layer 2, and photoetch a groove 3 on the N-epitaxial layer 2 through a hard mask 4, wherein the groove 3 has a depth of 2 μm and a width of 0.7 μm; 2) removing the mask, performing dry oxidation at 950°C and normal pressure for 15 minutes, and then continuing wet oxygen oxidation at 950°C and normal pressure for 150 minutes to form a first oxide layer 5, the thickness of the first oxide layer 5 is 1050A; 3) A layer of polysilicon 6 is deposited on the first oxide layer by chemical vapor deposition, and then the polysilicon on the first oxide layer outside the trench is etched away by two etchings, and part of the polysilicon in the trench is etched away, and the remaining polysilicon in the trench is polysilicon I 7, and the thickness of polysilicon I is 0.8 μm; 4) On the basis of step 3), etching away the excess oxide layer, wherein the excess oxide layer includes the first oxide layer 5 on the N-epitaxial layer 2 outside the trench and part of the first oxide layer 5 in the trench 3; 5) Dry oxygen oxidation is performed again at 950° C. and atmospheric pressure for 115 minutes, and then wet oxygen oxidation is performed at 950° C. and atmospheric pressure for 150-200 minutes to grow the second polysilicon oxide layer 8, and gate etching is performed. The thickness of the second polysilicon oxide layer 8 is 555A; 6) Fill the trench 3 with polysilicon gate 9 again by chemical vapor deposition and dry-etch back until it is flush with the upper surface of the N-type epitaxial layer 2 .

[0018] The above contents are only preferred embodiments of the present invention. For ordinary technicians in this field, according to the concept of the present invention, there will be changes in the specific implementation methods and application scopes. The content of this specification should not be understood as limiting the present invention.

Claims

1. A method for preparing a split-gate trench MOSFET device, characterized in that: The following steps are involved: 1) Select a substrate with an N-epitaxial layer and photolithograph a groove on the N-epitaxial layer through a hard mask; 2) Remove the mask, dry oxidize at 945℃~955℃ and normal pressure for 15-25min, and then continue wet oxygen oxidation at 945℃~955℃ and normal pressure for 150-200min to form the first oxide layer; 3) A layer of polysilicon is deposited on the first oxide layer by chemical vapor deposition, and then the polysilicon on the first oxide layer outside the trench is etched away by etching, and part of the polysilicon in the trench is etched away, and the remaining polysilicon in the trench is polysilicon I; 4) On the basis of step 3), etching away the excess oxide layer, wherein the excess oxide layer includes the first oxide layer on the N-epitaxial layer outside the trench and a portion of the first oxide layer in the trench; 5) Dry oxygen oxidation is performed again at 945℃~955℃ and atmospheric pressure for 105~115min, and then wet oxygen oxidation is performed at 945℃~955℃ and atmospheric pressure for 150-200min on the second polysilicon oxide layer, and gate etching is performed. The thickness of the second polysilicon oxide layer is less than the thickness of the first oxide layer; 6) Fill the trench with polysilicon gate again by chemical vapor deposition and dry-etch back until it is flush with the upper surface of the N-type epitaxial layer.

2. The method for preparing a split-gate trench MOSFET device according to claim 1, characterized in that: The depth of the grooves photoetched in step 1) is 1.8~2μm.

3. The method for preparing a split-gate trench MOSFET device according to claim 1, characterized in that: In step 2), the thickness of the first oxide layer formed by wet oxygen oxidation is 950~1050A.

4. The method for preparing a split-gate trench MOSFET device according to claim 1, characterized in that: In step 3), the thickness of the polysilicon I retained in the trench is 0.8±0.05 μm.

5. The method for preparing a split-gate trench MOSFET device according to claim 1, characterized in that: The thickness of the second polysilicon oxide layer is 555±20 Å.

6. The method for preparing a split-gate trench MOSFET device according to claim 1, characterized in that: The width of the grooves photolithographically formed in step 1) is 0.7±0.05 μm.

7. A split-gate trench MOSFET device, prepared by the preparation method according to any one of claims 1 to 6, characterized in that: The device includes a substrate with an N-epitaxial layer, a groove is opened on the N-epitaxial layer, a first oxide layer and a second polysilicon oxide layer are arranged in the groove, the second polysilicon oxide layer is located above the first oxide layer, the first oxide layer is filled with polysilicon I, the second polysilicon oxide layer is filled with polysilicon gates, and polysilicon I and the polysilicon gates are separated by an oxide layer.

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