Low power inter-die communication using delay lines

Abstract

A low power phase interpolator circuit has: a phase generator that receives an input clock signal and generates a plurality of intermediate clock signals having different phase shifts using the input clock signal; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range defined by phases of two of the intermediate clock signals; a frequency multiplier circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a phase difference of 180 DEG; and a quadrature clock generation circuit that receives the two frequency doubled clock signals and provides four output signals including in-phase and quadrature versions of the two frequency doubled clock signals.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. application No. 17 / 887,282, filed on August 12, 2022, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to serial communications between integrated circuits, and more particularly to efficient, compact, low-power serializer and deserializer circuits. Background Art

[0004] Electronic device technology has exploded over the past few years. For example, better communications, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablet devices, laptop computers, etc.) have become more powerful and complex than ever before. Wireless devices may include high-speed bus interfaces for signal communication between hardware components.

[0005] High-speed serial buses offer advantages over parallel communication links when reduced power consumption and a smaller footprint are required, such as in integrated circuit (IC) devices. In a serial interface, a serializer is used to convert data from parallel words to a serial bit stream, and a deserializer is used to convert the data back to parallel words at the receiver. For example, a high-speed bus interface can be implemented using a peripheral component interconnect express (PCIe) bus, a universal serial bus (USB), or a serial advanced technology attachment (SATA), etc.

[0006] IC devices may include a serializer / deserializer (SERDES) that transmits and receives over a serial communication link. In some cases, the serial communication link is deployed between dies on a chip carrier. The increased power and complexity of hardware and software functions implemented in IC devices has led to a continued increase in demand for higher data throughput with lower power consumption. There is a continuing need for new technologies that provide reliable, low-power SERDES circuits for high-speed serial links. Summary of the invention

[0007] Certain aspects of the present disclosure relate to circuits, systems, apparatus, methods, and techniques for supporting high-speed serial communications within and between IC devices. A low-power, high-speed serializer circuit is disclosed that can reduce power consumption in a transmitting device. A low-power, high-speed deserializer circuit is disclosed that can reduce power consumption in a receiving device.

[0008] In various aspects of the present disclosure, a serializer includes a delay line, a plurality of buffers, and a clock generation circuit. The delay line has a plurality of delay stages coupled in series. The delay line is configured to output N delay line signals, which are versions of an input signal and include outputs of a plurality of delay stages coupled in series. A plurality of buffers are coupled to a data source. Each buffer is enabled by a corresponding delay line signal and is configured to couple a signal representing an associated bit in a data source to a data line of a serial communication link when a pulse is present in the corresponding delay line signal. A clock generation circuit responsive to edges in two of the N delay line signals is configured to generate a transmit clock signal to be transmitted through a clock line of the serial communication link.

[0009] In various aspects of the present disclosure, a method for serializing data includes: using a delay line to generate N delay line signals that are versions of an input signal provided to the delay line; providing the N delay line signals to a plurality of buffers coupled to a data source; and coupling a transmit clock signal to a clock line of a serial communication link. Each of the plurality of buffers is enabled by a corresponding delay line signal and is configured to couple a signal representing an associated bit in the data source to a data line of the serial communication link when a pulse is present in the corresponding delay line signal. The transmit clock signal is generated using edges in two of the N delay line signals.

[0010] In various aspects of the present disclosure, the deserializer includes one or more delay lines, a plurality of latches, and a clock generation circuit. The delay line is configured to output N delay line signals. Each delay line signal is a version of an input signal provided to one of the delay lines. A plurality of latches are coupled to a data line of a serial communication link. Each latch is enabled by a corresponding delay line signal in the N delay line signals. Each latch is configured to capture the state of the data line when a pulse is present in the corresponding delay line signal. The clock generation circuit is configured to use edges in two of the N delay line signals to generate a regenerated transmit clock signal. The regenerated transmit clock signal corresponds to a clock signal received from a clock line of the serial communication link. The pulses in the input signal of each of the delay lines are generated from edges in the clock signal received from the clock line.

[0011] In various aspects of the present disclosure, a method for deserializing data includes: generating N delay line signals using one or more delay lines; providing the N delay line signals to N latches coupled to a data line of a serial communication link; and regenerating a transmit clock signal using edges in two of the N delay line signals. Each delay line signal is a version of an input signal provided to one of the one or more delay lines. Each latch is enabled by a corresponding delay line signal and is configured to capture a state of the data line when a pulse is present in the corresponding delay line signal. The transmit clock signal corresponds to a clock signal received from a clock line of the serial communication link. The pulses in the input signal of the delay line are generated from edges in the received clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 An example of a system on a chip (SOC) according to certain aspects of the present disclosure is illustrated.

[0013] Figure 2 An example of a data communication system that may be adapted according to certain aspects of the present disclosure is illustrated.

[0014] Figure 3 The architecture of a serial interface that may be adapted or configured according to certain aspects of the present disclosure is illustrated.

[0015] Figure 4 Examples of delay lines that may be employed or adapted according to certain aspects of the present disclosure are illustrated.

[0016] Figure 5 A serializer configured according to certain aspects of the present disclosure is illustrated.

[0017] Figure 6 Example of Figure 5 Some aspects of the timing of signals generated or used by the serializer in the

[0018] Figure 7 A deserializer configured according to certain aspects of the present disclosure is illustrated.

[0019] Figure 8 is exemplified by Figure 7 A timing diagram that illustrates some aspects of the timing of signals generated or used by the deserializer in the .

[0020] Fig. 9 A deserializer with clock edge regeneration configured in accordance with certain aspects of the present disclosure is illustrated.

[0021] Fig.10 is a flow chart illustrating an example of a method for serializing data according to certain aspects of the present disclosure.

[0022] Fig.11is a flow chart illustrating an example of a method for deserializing data according to certain aspects of the present disclosure. DETAILED DESCRIPTION

[0023] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration with which the concepts described herein can be practiced. In order to provide a thorough understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid blurring these concepts.

[0024] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] The terms "computing device" and "mobile device" are used interchangeably herein to refer to any or all of the following: servers, personal computers, smart phones, cellular phones, tablet computers, laptop computers, netbooks, ultrabooks, palmtop computers, personal data assistants (PDAs), wireless email receivers, multimedia Internet-enabled cellular phones, global positioning system (GPS) receivers, wireless game controllers, and similar personal electronic devices that include programmable processors. While various aspects are particularly useful in mobile devices (e.g., smart phones, laptop computers, etc.) with limited resources (e.g., processing power, battery, size, etc.), these aspects are generally useful in any computing device that can benefit from increased processor performance and reduced energy consumption.

[0026] The term "multi-core processor" is used herein to refer to a single integrated circuit (IC) chip or chip package that contains two or more independent processing units or cores (e.g., CPU cores, etc.) configured to read and execute program instructions. The term "multiprocessor" is used herein to refer to a system or device that includes two or more processing units configured to read and execute program instructions.

[0027] The term "system on chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip that includes multiple resources and / or processors integrated on a single substrate. A single SoC may include circuits for digital, analog, mixed signal, and radio frequency functions. A single SoC may also include any number of general and / or special-purpose processors (digital signal processors (DSPs), modem processors, video processors, etc.), storage blocks (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.), any or all of which may be included in one or more cores.

[0028] The memory technologies described herein may be suitable for storing instructions, programs, control signals, and / or data for use in or by a computer or other digital electronic device. Any reference to terms and / or technical details related to individual memory types, interfaces, standards, or memory technologies is for illustrative purposes only and is not intended to limit the scope of the claims to a particular memory system or technology unless specifically stated in the claim language. The complexity of mobile computing device architectures has grown and now typically includes multiple processor cores, SoCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnects (e.g., buses and / or fabrics), and many other resources to execute complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0029] Process technologies used to manufacture semiconductor devices (including IC devices) are constantly improving. Process technologies include manufacturing methods used to manufacture IC devices and define transistor size, operating voltage, and switching speed. Features that are components of circuits in IC devices may be referred to as technology nodes and / or process nodes. The terms "technology node," "process node," and "process technology" may be used to characterize a particular semiconductor manufacturing process and corresponding design rules. Faster and more efficient technology nodes are constantly being developed by using smaller feature sizes to produce smaller transistors that enable the manufacture of higher density ICs.

[0030] Figure 1Example components and interconnects in a system on chip (SoC) 100 that may be suitable for implementing certain aspects of the present disclosure are illustrated. SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. Processors 102, 104, 106, 108 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.) so that the processors may operate at much higher frequencies / clock rates than would be possible if signals were propagated off-chip. The proximity of the cores may also allow for sharing of on-chip memory and resources (e.g., voltage rails), as well as allowing for more coordinated collaboration between the cores.

[0031] SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversion, and / or wireless data transmission, as well as for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.). System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and / or other similar components for supporting processors and software clients running on the computing device. System components and resources 110 may also include circuits for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0032] SoC 100 may also include a universal serial bus (USB) or other serial bus controller 112, one or more memory controllers 114, and a centralized resource manager (CRM) 116. SoC 100 may also include an input / output module (not illustrated) for communicating with resources external to the SoC, each of which may be shared by two or more of the internal SoC components.

[0033] Processors 102, 104, 106, 108 may be interconnected to USB controller 112, memory controller 114, system components and resources 110, CRM 116, and / or other system components via interconnect / bus module 122, which may include a reconfigurable logic gate array and / or implement a bus architecture. Communications may also be provided by advanced interconnects such as a high-performance network-on-chip (NoC).

[0034] The interconnect / bus module 122 may include or provide a bus master system that is configured to grant the SoC component (e.g., processor, peripheral device, etc.) exclusive control of the bus (e.g., transfer data in burst mode, block transfer mode, etc.) to achieve a set duration, number of operations, number of bytes, etc. In some cases, the interconnect / bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus at the same time. The memory controller 114 may be a dedicated hardware module configured to manage the flow of data to and from the memory 124 via the memory interface / bus 126.

[0035] The memory controller 114 may include one or more processors configured to perform read and write operations on the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic components, discrete hardware circuits, and other suitable hardware configured to perform various functionalities described throughout the present disclosure. In some aspects, the memory 124 may be part of the SoC 100.

[0036] Figure 2 An example of a data communication system 200 that may be adapted according to certain aspects of the present disclosure is illustrated. The data communication system 200 includes a transmitter 202, a data communication channel 210, and a receiver 222. The transmitter 202 may be disposed in a first device configured to transmit a data signal to a second device. The data communication channel 210 provides a transmission medium through which the data signal propagates from the first device to the second device. The receiver 222 may be disposed in the second device and may be configured to receive and process the data signal.

[0037] In one example, the transmitter 202 includes a serializer 204 configured to convert N-bit parallel data into a serial data stream. The transmitter 202 also includes a transmit driver 206 configured to generate a data signal representing the serial data stream for transmission to the receiver 222 via the data communication channel 210.

[0038] The data communication channel 210 may be implemented using any type of transmission medium through which a data signal may propagate from the transmitter 202 to the receiver 222. Examples of the data communication channel 210 include one or more metallized traces on a printed circuit board (PCB) (the one or more metallized traces may include one or more vias), stripline, microstrip, coaxial cable, twisted pair, etc. Certain aspects of the present disclosure are applicable to serial communication between two dies provided on a chip carrier. In some cases, the two dies may be coupled using a trace having a length that may be measured as one millimeter or several millimeters. In some cases, the two dies may be coupled using a trace having a length that may be measured as a fraction of a millimeter. In the latter example, the data communication channel 210 includes millimeter-scale traces, input / output pads, interconnects, through-holes, and traces within a semiconductor device.

[0039] The receiver 222 includes a receiving circuit (receiver 224), a clock data recovery circuit (CDR 226), and a deserializer 228. In some implementations, the receiver 222 includes a circuit that can be configured to perform equalization and amplification on the received data signal. The equalization circuit can boost the higher frequency components of the signal received from the data communication channel 210 so that all frequency components of the signal have similar amplitudes and reduce jitter. The CDR 226 is configured to receive the transmit clock signal 208 and generate a receive clock signal that can be used to sample or otherwise recover serial data from the data signal based on information in the transmit clock signal 208. The CDR 226 can be configured to generate multiple signals from the transmit clock signal 208 received from the transmitter 202. The deserializer 228 is configured to convert the serial data back into parallel data.

[0040] When the data signal or transmit clock signal 208 arrives at the receiver 222, the data signal or transmit clock signal may be distorted. Distortion may occur for a variety of reasons, including impedance mismatches, interference, and reflected energy in the data communication channel 210. Signal distortion may make it difficult to recover the clock and data by the CDR 226, and may limit the stability window during which data can be sampled. In some examples, distortion caused by high-frequency attenuation can be addressed by increasing equalization and amplification of the high-frequency components of the data signal to increase the data rate at which the data signal can be transmitted through the data communication channel 210 and reliably recovered at the receiver 222. Distortion can produce timing errors and introduce timing uncertainty or jitter, which can impair the operation of the data and deserializer 228.

[0041] Improvements in semiconductor device technology and the ever-increasing demands on the performance of mobile communication devices and other battery-powered devices generally require increasing data communication rates between IC devices. The increased data communication rates obtained by increasing the data transmission rate can significantly increase power consumption and reduce the maximum or rated operating time between battery charging events. Common serial link architectures consume approximately 1 picojoule per bit (pJ / bit) in the 10 to 20 gigabits per second (Gbps) data rate range. Certain aspects of the present disclosure can deliver high data rate communications at lower power levels, including in data communication links that can be used for die-to-die communication links within the same package.

[0042] In some aspects of the disclosure, power consumption can be reduced by limiting the number of logic and driver devices that switch at the highest clock frequency employed by the communication interface. In some aspects of the disclosure, the frequency of the clock signal sent between IC devices can be less than the frequency at which data bits are sent over the serial bus.

[0043] Figure 3 The architecture of a serial interface for obtaining high data rate communications at lower power levels that can be adapted or configured according to certain aspects of the present disclosure is illustrated. In the example shown, the serial interface can deliver 40 Gbps data throughput between the transceiver die 300 and the modem die 320 using four serial data lines 314a, 314b, 314c, and 314d, each configured for 10 Gbps operation, and a clock line 312 carrying a 1.25 MHz clock signal. The reduced frequency of the signals sent by the serial data lines 314a to 314d and the clock line 312 relative to the total data throughput can eliminate the need for shielding between the serial data lines 314a to 314d and / or the clock line 312, and allow the serial data lines 314a to 314d and the clock line 312 to be implemented using single-ended line drivers and line receivers. In some applications, it may be desirable to implement the serial data lines 314a to 314d and / or the clock line 312 using differential line drivers and line receivers. For example, differential signaling may be used in interfaces that include longer lines or interconnects and / or when levels of electromagnetic interference may damage, distort, or otherwise impair transmitting single-ended lines.

[0044] In the transceiver die 300, four parallel data sources 304a, 304b, 304c, 304d may be provided. In the example shown, the parallel data sources 304a to 304d are implemented using 8-bit latches clocked by a transmit clock signal 310 having a frequency of 1.25 MHz. In other examples, the parallel data sources 304a to 304d may be implemented using registers, shift registers, and / or bus interface circuits. The transmit clock signal 312 may be generated using a clock generator 302. The clock generator 302 may include a variable oscillator, a pulse generator, a delay locked loop (DLL), a phase locked loop (PLL), and / or other suitable clock generation circuits.

[0045] In the example shown, the outputs of the parallel data sources 304a to 304d are provided to a multi-channel serializer 306 configured to provide four serial data streams, each of which is derived from the output of the corresponding parallel data source 304a, 304b, 304c or 304d. The bit rate of each data stream is 8×1.25GHz=10GHz. A set of single-ended line drivers 308 includes four drivers configured to drive four serial data lines 314a to 314d and a driver configured to drive a clock line 312.

[0046] In the modem die 320, a set of single-ended line receivers 322 includes four data line receivers configured to couple a multi-channel deserializer 328 to four serial data lines 314a to 314d and a clock line receiver configured to couple the multi-channel deserializer 328 to the clock line 312. The deserializer derives a receive clock signal 326 from the signal received from the clock line 312 and uses the timing information derived from the signal received from the clock line 312 to deserialize the serial data stream received from the four serial data lines 314a to 314d. The deserialized data is output as four 8-bit representations 324a, 324b, 324c, and 324d of the data provided by the parallel data sources 304a to 304d in the transceiver die 300. The receive clock signal 326 can be used to sample or capture the parallel data output by the deserializer 328.

[0047] Shift registers or flip-flops connected in series are commonly used to implement serializers and deserializers in conventional serial interfaces. In one example of a conventional serializer, N bits of parallel data are loaded into N flip-flops connected in series that are timed by a common clock signal. The output of each flip-flop is usually connected to the input of the next flip-flop in the sequence, and the output of the Nth flip-flop connected in series provides a serialized output. Similarly, a conventional deserializer receives a serial data input at the first series flip-flop in a group of N series-connected flip-flops timed by a common clock signal. The output of each flip-flop is usually connected to the input of the next flip-flop in the sequence. After N clock cycles, N bits of parallel data can be read from the combined output of the N series-connected flip-flops. In these conventional serializers and deserializers, N flip-flops are timed at the serial transmit clock frequency in both the transmitter and the receiver, and the flip-flops can be the main power consumers during the operation of the serial data link.

[0048] According to certain aspects of the present disclosure, a serial interface can be operated using a serializer and deserializer implemented without triggers. The serializer and deserializer configured according to certain aspects disclosed herein employ delay lines and clock regeneration circuits. The clock regeneration circuit can limit jitter accumulation to half a cycle of the transmitter or receiver clock signal or less. In some specific implementations, power consumption at a data rate of 40Gbps can be less than 0.15pJ / bit, which is advantageous compared to the 1pJ / bit observed in conventional interfaces operating at 10 to 20Gbps.

[0049] Figure 4 An example of a delay line 400 that can be configured according to certain aspects of the present disclosure is shown. In some implementations, other types or configurations of delay lines can be used. Here, the delay line 400 shown is implemented using an inverter including a delay line inverter 408 and a phase select inverter 412. The phase select inverter 412 is coupled to the input of the delay line 400 and can be bypassed using a bypass switch 404. The phase select inverter 412 can be used to select between a non-inverted (in-phase) signal and an inverted signal (180°-out of phase) to drive the delay line 400.

[0050] The delay line 400 can be configured to receive a single-ended signal at an input and provide a plurality of output signals 410 that are delayed versions of the input signal and are generated using a series of stages. In some examples, each stage includes at least one delay element (such as delay element 406 or delay element 416) and output elements 418a to 418h. In various implementations, the delay elements 406, 416 are configurable because the delay provided can be adjusted to some extent. In the example shown, the variable capacitor 414 can be used to change the capacitance of the interconnect between the gate or inverter and thus adjust the delay provided by the delay element 406. In other examples, the delay provided by the delay element 406 can be adjusted by configuring one or more variable resistors in the delay element 406. In other examples, the delay introduced by the delay element 406 can be adjusted by configuring the bias of one or more transistors in the delay element 406. In some implementations, one or more delay elements 406 can be configured to provide a desired delay during a calibration or configuration process. In one example, calibration can be performed to limit the variation of the delay provided by the delay element in the delay line 400. The delay line 400 may include any number of delay elements. For example, in other implementations, calibration may be performed to limit the variation in the total delay between two sets of delay elements to obtain a desired duty cycle. In some implementations, a delay line is provided using a circuit with closely matched characteristics, and the delay elements may provide matched delays without calibration.

[0051] In the example shown, the output signal 410 provided by the delay line 400 includes eight signals delayed relative to each other. Seven delay elements (eg, delay elements 406 and 416) each provide the same nominal delay. The delay line 400 can be configured to generate phase-shifted or delayed versions of a signal.

[0052] Timing diagram 420 illustrates an example of the operation of delay line 400 in accordance with certain aspects of the present disclosure. In the example shown, a transmit clock signal (TxClock 402) may be received at an input of delay line 400. TxClock 402 may be received from a processing circuit or sequencer that feeds data to a serializer in which delay line 400 is incorporated or included. In accordance with certain aspects of the present disclosure, TxClock 402 has a period that defines or is defined by the time required to serialize a byte of data, which may be related to t 延迟线 In the example shown, the delay line 400 is configured to respond to a rising edge 422 in TxClock 402 by generating a set of delayed versions of the signal, wherein each delayed version of the signal includes a delay of t 延迟线In other examples, the rising edge 422 in TxClock 402 may cause the delay line 400 to generate pulses 424a to 424h that are one eighth (1 / 8) of the duration of t 延迟线 A different or selectable number (N) of delayed versions of the signal of pulses of 1 / N of the duration of 430.

[0053] The rising edge 422 in TxClock 402 produces a change in signaling state at the input of delay line 400, which transitions from a low state to a high state. In the example shown, delay line 400 can be configured to respond to a rising edge in TxClock 402 when bypass switch 404 is turned on, causing TxClock 402 to bypass phase selection inverter 412. Delay line 400 can also be configured to respond to a falling edge in TxClock 402 when bypass switch 404 is turned off, causing phase selection inverter 412 to invert TxClock 402. Each stage provides a delayed version of the output signal, and pulses 424a to 424h in the delayed version each have a t 延迟线 1 / 8 of the duration of 430.

[0054] In one aspect of the present disclosure, the duration of pulses 424a to 424h closely matches the duration (t 延迟 ). Each of the output elements 418a to 418h may be configured to terminate a pulse output by its corresponding delay element at a leading edge of a pulse generated by a next delay stage in the delay line. Figure 4 4. An example of a pulse control circuit 440 that may be included in output elements 418a to 418h is illustrated in FIG. 4. According to certain aspects of the present disclosure, some implementations use different types of circuits for pulse control. The illustrated example of the pulse control circuit 440 limits the duration of the output pulse to the duration of the delay 426 provided by the stages of the delay line 400. The pulse control circuit 440 is based on a set-reset circuit 442 that responds to edges detected at a pair of inputs 444, 446. A rising edge at the set input 444 sets the output 448 of the set-reset circuit 442 to a high signaling state, and a rising edge at the reset input 446 resets the output 448 of the set-reset circuit 442 to a low signaling state.

[0055] For use in the illustrated delay line 400, the set input 444 of the set-reset circuit 442 is coupled to the output 454 (Dly) of the first delay stage 450a. N ), and the reset input 446 of the set-reset circuit 442 is coupled to the output 456 (Dly) of the second delay stage 450b after or downstream of the first delay stage 450a. N+1The input of the first delay stage 450a is the output 452 (Dly) of the previous delay stage (not shown). N-1 ), except when the first delay stage 450a corresponds to the delay element 406, in which case the input is coupled to TxClock 402. Dly N The rising edge in causes the output 448 of the set-reset circuit 442 to be driven to a high signaling state. N The rising edge in Dly propagates through the second delay stage 450b, and the output 448 of the set-reset circuit 442 is at Dly N+1 The duration of the pulse output by the set-reset circuit 442 closely matches the duration of the delay provided by the first delay stage 450a.

[0056] In the example shown, the pulse control circuit 440 responds to the edge in the signal provided to its input 444, 446. This example is provided to facilitate the description of certain aspects of the delay line 400. According to certain aspects of the present disclosure, other circuits can be used to control the pulse width. For example, in some specific implementations, the output elements 418a to 418h may include gating logic, and the gating logic is configured to terminate the pulse at the output of the delay element when a high signaling state exists on any one of a plurality of subsequent delay elements. For example, the gating logic may be configured to terminate the pulse by driving the output of the Nth delay element to a low signaling state when a high signaling state exists on any one of three or more subsequent delay elements in the delay line 400, and the subsequent delay elements include the N+1th delay element, the N+2th delay element, and the N+3th delay element. In the latter example, the value of N can be a modulo 8 number.

[0057] In the delay line 400 shown, the rising edge 422 in TxClock 402 propagates through seven delay elements, with the last delay element 416 generating a rising edge at time (t 延迟线 The pulse terminates after 430 t 延迟线 The duration of 430 can be calculated as:

[0058] t 延迟线 =8×t 延迟 .

[0059] According to one aspect, a version of the delay line 400 can be configured to operate as a DLL acting as a clock generator. The delay line 400 can be configured to operate as a DLL by coupling the output of the delay element 416 to the input of the delay line 400 to form a loop. The bypass switch 404 can be configured to ensure that an odd number of inverters connected in series are provided in the loop. The resulting DLL oscillates at a frequency determined by the delay introduced by the delay element in the loop.

[0060] Figure 5 Serializer 500 configured in accordance with certain aspects of the present disclosure is illustrated. Figure 6 Including examples by Figure 5 A timing diagram 600 illustrates certain aspects of the timing of signals generated or used by a serializer 500 in FIG. 5 . The serializer 500 includes a delay line 502 and a set of buffers 506. The delay line 502 may be connected to Figure 4 The delay line 502 may operate in a manner similar to the delay line 400. The delay line 502 is shown outputting eight delayed versions of a signal in response to edges in a transmit clock signal (TxClock 510) coupled to an input of the delay line 502. The TxClock 510 may have a period 604 corresponding to eight bit transmission intervals 610.

[0061] Each of the delay line outputs 512 acts as an enable signal to one of the group of buffers 506. When the leading edge in TxClock 510 propagates through the delay line 502, pulses are sequentially provided at each of the delay line outputs 512. Nominally, at any given time, only one of the delay line outputs 512 is high or otherwise active. When one of the delay line outputs 512 is high or otherwise active, a corresponding buffer in the group of buffers 506 is turned on and drives the input of the line driver 508. The line driver 508 is configured to drive the serial data line 518. In the serializer 500 shown, each buffer in the group of buffers 506 is implemented using a tri-state buffer with an input, an output, and an enable input. When the buffer is enabled, the output of each buffer follows the input. When the buffer is disabled, the output of each buffer is in a high impedance state.

[0062] In one example, the Dly7 output of the delay line 502 is coupled to the enable input of a buffer 514 in the set of buffers 506, and a pulse 606 on the Dly7 output selects the D7 data bit provided by the data source 504 for transmission over the serial data line 518. In another example, the Dly3 output of the delay line 502 is coupled to the enable control input of a buffer 516 in the set of buffers 506, and a pulse 608 on the Dly3 output selects the D3 data bit provided by the data source 504 for transmission over the serial data line 518. The delay line output 512 operates to control the set of buffers 506 so that each bit from the data source 504 is transmitted sequentially over the serial data line 518, as shown in FIG. Figure 6 5. The signal transmitted on the serial data line 518 is shown in FIG. Among the data source 504, the set of buffers 506 and the line driver 508, only the line driver 508 is actively switched for all transmissions of 8 bits of serial data.

[0063] In other aspects of the present disclosure, the serializer 500 can be configured to derive a regenerated transmit clock signal 602 from the delay line output 512. In some implementations, the regenerated transmit clock signal 602 can be generated using a set-reset circuit 630, an example of which is also described in Figure 6 6. In the illustrated set-reset circuit 630, the rising edge 614 of the pulse 606 on the Dly7 output of the delay line 502 sets the output of the set-reset circuit 630 and produces a rising edge 618 in the regenerated transmit clock signal 602. The rising edge 620 on the Dly3 output of the delay line 502 resets the output of the set-reset circuit 630 and produces a falling edge 624 in the regenerated transmit clock signal 602. This combination of setting and resetting produces a regenerated transmit clock signal 602 whose period 604 corresponds to the eight bit transmission intervals 610 and has edges 618 and 624 that are synchronized with certain edges in the delay line output 512. The synchronization of the edges 618 and 624 in the regenerated transmit clock signal 602 prevents jitter accumulation beyond each half period of the regenerated transmit clock signal 602. In some implementations, combinatorial logic can be used to generate the regenerated transmit clock signal 602. For example, the regenerated transmit clock signal 602 may be obtained by performing an OR function on four of the eight delay line outputs 512 .

[0064] Figure 7 A deserializer 700 configured in accordance with certain aspects of the present disclosure is illustrated. Figure 8 is exemplified by Figure 7 A timing diagram 800 is provided that illustrates certain aspects of the timing of signals generated or used by the deserializer 700 in FIG. The deserializer 700 includes a pair of delay lines 702, 722 and two latch groups 704, 724. The structure of the delay lines 702, 722 may be similar in some aspects to the Figure 4 4. Each of the delay lines 702, 722 outputs four delayed versions of a signal generated in response to an edge in a receive clock signal (RxClock 710). RxClock 710 may be received along with a serial data signal 720 from a serial communication link. In the example shown, the inputs of the delay lines 702, 722 are coupled to RxClock 710. In some cases, RxClock 710 is generated by Figure 5. The serializer 500 shown in FIG. 7 is a serializer 500 forwarding a received version of the regenerated transmit clock signal 602. The latches in the two latch groups 704 and 724 may be referred to as transparent latches. When enabled by their associated selection signals 712, 714, 716, 718, 732, 734, 736, 738, the output of each transparent latch follows its input and maintains the output state after the latch is disabled. The latches in the two latch groups 704 and 724 may also be referred to as asynchronous latches because the output may change without reference to an edge in the clock signal. In some specific implementations, the latch groups 704 and 724 may be replaced by a set of flip-flops, wherein the output changes in response to an edge in the associated selection signals 712, 714, 716, 718, 732, 734, 736, 738.

[0065] According to certain aspects of the present disclosure, the first delay line 702 generates pulses 806a-806d in response to a rising edge 812a in RxClock 710. Pulses 806a-806d are generated with a duration 804 that closely matches the delay duration 808 provided by each stage of the first delay line 702. Pulses 806a-806d may be as described with respect to Figure 4 For example, each pulse may terminate after a delay duration 808 attributable to a delay element in the first delay line 702. In the example shown, the total duration of the pulses 806a to 806d output by the first delay line 702 corresponds to half of the period of RxClock 710.

[0066] Each of the four select signals 712, 714, 716, 718 output by the first delay line 702 controls the operation of a corresponding latch in the first set of latches 704. A high signaling state on the select signals 712, 714, 716, 718 enables the corresponding latch to capture the state of the serial data signal 720. The pulses in the select signals 712, 714, 716, 718 are configured to enable each latch in the first set of latches 704 to capture a specified bit in the data stream encoded in the serial data signal 720. The first set of latches 704 is configured to capture data bits D7 to D4 from the serial data signal 720.

[0067] According to certain aspects of the present disclosure, the second delay line 722 generates pulses 826a to 826d in response to the falling edge 812a in the RxClock 710. In some cases, the first delay line 702 and the second delay line 722 have the same design and configuration, except that the second delay line 722 inverts its input or receives an inverted version of the RxClock 710. In one example, the second delay line 722 may use an input inverter (such as Figure 4The second delay line 722 generates pulses 826a to 826d having a duration 824 that closely matches the delay duration 828 provided by each stage of the second delay line 722. The pulses 826a to 826d may be as described with respect to Figure 4 For example, each pulse may terminate after a delay duration 828 attributable to a delay element in the second delay line 722. In the example shown, the total duration of the pulses 826a to 826d output by the second delay line 722 corresponds to half of the period of RxClock 710.

[0068] Each of the four select signals 732, 734, 736, 738 output by the second delay line 722 controls the operation of a corresponding latch in the second set of latches 724. A high signaling state on the select signals 732, 734, 736, 738 enables the corresponding latch to capture the state of the serial data signal 720. The pulses in the select signals 732, 734, 736, 738 are configured to enable each latch in the second set of latches 724 to capture a specified bit in the data stream encoded in the serial data signal 720. The second set of latches 724 is configured to capture data bits D3 to D0 from the serial data signal 720.

[0069] Each of the two latch sets 704, 724 provides an output 706, 726 representing four bits of the eight-bit serial transmission associated with each cycle of RxClock 710. The outputs 706, 726 of the two latch sets 704, 724 may be combined to provide an 8-bit data output 730 of the deserializer 700.

[0070] Using two delay lines 702, 722 triggered by alternating edges in RxClock 710 can limit jitter accumulation to half a period of RxClock 710. The deserializer 700 operates without the need for serially connected flip-flops and can be characterized by substantially reduced power consumption.

[0071] Fig. 9 A deserializer 900 with clock edge regeneration configured in accordance with certain aspects of the present disclosure is illustrated. In the example shown, data transitions are used to Figure 7 The deserializer 700 shown in FIG. 9 extracts clock edge information. The deserializer 900 operates in the same manner as the deserializer 700 , except that specific latch enable signaling may be selected based on edges detected in the data stream received from the serial data signal 720 .

[0072] In the deserializer 900 shown, edge detection in the serial data signal 720 is supported for transitions between the D7 and D6 bit positions, the D6 and D5 bit positions, the D3 and D2 bit positions, and the D2 and D1 bit positions. The two auxiliary latch groups 902, 922 are controlled by the inversion of the corresponding selection signals 712, 714, 716, 718, 732, 734, 736, 738 output by the delay line 702 or 722. The two auxiliary latch groups 902, 922 are configured to maintain a copy of the output of the original latch group 704, 724 in the previous bit transmission interval. For convenience, the original latch group 704, 724 can be referred to as the main latch 704, 724, and the two auxiliary latch groups 902, 922 can be referred to as auxiliary latches. In the illustrated example, when the primary latch 902 , 922 is disabled, the secondary latch 902 , 922 is enabled, and when the secondary latch 704 , 724 is disabled, the primary latch 704 , 724 is enabled.

[0073] When enabled, the master latches 704, 724 follow the state of the serial data signal 720. Each of the master latches 704, 724 is enabled during the bit transmission interval corresponding to the data bit to be captured. XOR gates 904a to 904d can be configured to detect the transition in the serial data signal 720. The output of the XOR gates 904a to 904d is gated by the corresponding window signals 912a to 912c using the AND gates 906a to 906d. The window signals 912a to 912c block the outputs of the XOR gates 904a to 904d, except during the time interval of the associated transition in the expected serial data signal 720. The transition in the serial data signal 720 generates pulses in the signal output by the AND gates 906a to 906d, and these pulses are fed to the delay lines 908a to 908d. The delay lines provide enable signals 914a to 914d which may be used to replace certain of the select signals 712, 714, 716, 718, 732, 734, 736, 738 output by the delay lines 702, 722. Certain delay lines 908a, 908c provide two delayed outputs which may be used as gate signals for two subsequent bit intervals.

[0074] The deserializer 900 includes multiplexers 910a to 910d or other logic circuitry that can select between the select signals 712, 714, 716, 718 output by the delay lines 702, 722 and the select signals 914a to 914d generated using the delay lines 908a to 908d. Regeneration of the clock edge from the data edge information can limit jitter accumulation to the two delay stages in the delay lines 702, 722. For example, accumulation of jitter can occur in the output of the delay line 702 or 722 due to the effects of temperature or voltage changes on the delay stages. The select signals 914a to 914d generated from the data edges can provide more recent timing information than the timing information generated from the edges 812a, 814 in the RxClock 710, thereby limiting the number of bit intervals where jitter can accumulate.

[0075] Fig.10 1 is a flow chart illustrating an example of a method 1000 for serializing data according to certain aspects of the present disclosure. The method 1000 may be implemented in an IC device and used to communicate data between the IC device and another IC device. In one example, the sending IC device and the receiving IC device are embodied in a die on a chip carrier. The method may involve, for example, Figures 3 to 6 Certain aspects of the present disclosure described herein. At block 1002, a delay line may be used to generate N delay line signals, the N delay line signals being versions of an input signal provided to the delay line. At block 1004, the N delay line signals may be provided to a plurality of buffers coupled to a data source. Each of the plurality of buffers may be enabled by a corresponding delay line signal. Each of the plurality of buffers may be configured to couple a signal representing an associated bit in the data source to a data line of a serial communication link when a pulse is present in the corresponding delay line signal. At block 1006, a transmit clock signal may be coupled to a clock line of the serial communication link, the transmit clock signal being generated using edges in two of the N delay line signals.

[0076] In various examples, the input signal includes pulses that repeat at a frequency corresponding to the frequency of the transmit clock signal. The input signal may include pulses having a duration corresponding to 1 / N of a period of the transmit clock signal. Pulses in the input signal may be generated having a duration corresponding to 1 / N of a period of the transmit clock signal. 18. In some cases, N represents the number of bits in a parallel unit of data received from a data source for transmission over a serial communication link.

[0077] In some examples, the delay line includes a plurality of delay stages coupled in series. Each of the plurality of delay stages coupled in series may be configured to delay a signal conducted between an input and an output of the delay stage for a duration corresponding to 1 / N of a period of a transmitted clock signal. At least one of the plurality of delay stages coupled in series may be configured to delay a signal conducted between an input and an output of at least one delay stage for a calibrable duration. For example, a variable capacitor, a resistor, or by controlling a bias current provided to a transistor may be used to calibrate the duration of the delay introduced by the delay stage. The pulse in each of the N delay line signals may have a duration corresponding to 1 / N of a period of a transmitted clock signal. The leading edge of a pulse output by each of a sequential pair of delay stages coupled in series in the delay line may be separated by a duration corresponding to 1 / N of a period of a transmitted clock signal.

[0078] In some examples, each buffer in the plurality of buffers is configured to present its output to an input of a line driver at a high impedance when a pulse is not present in a corresponding delay line signal. The output of each buffer in the plurality of buffers is coupled to the input of the line driver. The output of the line driver is configured to be coupled to a data line of the serial communication link.

[0079] Fig.11 1 is a flow chart illustrating an example of a method 1000 for deserializing data according to certain aspects of the present disclosure. The method 1100 may be implemented in an IC device and used to communicate data between the IC device and another IC device. In one example, the sending IC device and the receiving IC device are embodied in a die on a chip carrier. The method may involve, for example, Figures 7 to 9 Certain aspects of the present disclosure described herein. At block 1102, one or more delay lines may be used to generate N delay line signals. Each delay line signal is a version of an input signal provided to one of the one or more delay lines. At block 1104, the N delay line signals may be provided to N latches coupled to a data line of a serial communication link. Each latch may be enabled by a corresponding delay line signal and configured to capture a state of the data line when a pulse is present in the corresponding delay line signal. At block 1106, edges in two of the N delay line signals may be used to regenerate a transmit clock signal. The transmit clock signal may correspond to a clock signal received from a clock line of the serial communication link. Pulses in the input signal to the delay line are generated from edges in the received clock signal.

[0080] In some examples, a pulse in the first input signal may be generated in response to a rising edge in the received clock signal. The pulse in the first input signal may have a duration corresponding to 1 / N of a period of the transmitted clock signal. The first delay line may be used to generate a first N / 2 of the delay line signal as a version of the first input signal. A pulse in the second input signal may be generated in response to a falling edge in the received clock signal. The pulse in the second input signal may have a duration corresponding to 1 / N of a period of the transmitted clock signal. The second delay line may be used to generate a second N / 2 of the delay line signal as a version of the second input signal.

[0081] In some examples, pulses in a first N / 2 of the delay line signal terminate within a first half cycle of the transmit clock signal, and pulses in a second N / 2 of the delay line signal terminate within a second half cycle of the transmit clock signal. The first input signal and the second input signal may each include a pulse having a duration corresponding to 1 / N of a period of the transmit clock signal.

[0082] In some embodiments, one or more delay lines include a plurality of delay stages coupled in series. Each of the plurality of delay stages coupled in series may be configured to delay a signal conducted between an input and an output of the delay stage by a duration corresponding to 1 / N of a period of a transmitted clock signal. At least one of the plurality of delay stages coupled in series may be configured to delay a signal conducted between an input and an output of at least one delay stage by a calibrable duration. A pulse in each of the N delay line signals may have a duration corresponding to 1 / N of a period of a transmitted clock signal. The leading edges of the pulses output by each of the sequential pairs of delay stages coupled in series may be separated by a duration corresponding to 1 / N of a period of a transmitted clock signal.

[0083] Some specific implementation examples are described in the following numbered clauses:

[0084] 1. A serializer, the serializer comprising: a delay line having a plurality of delay stages coupled in series, the delay line being configured to output N delay line signals, the N delay line signals being versions of an input signal and comprising outputs of the plurality of delay stages coupled in series; a plurality of buffers coupled to a data source, each buffer being enabled by a corresponding delay line signal and being configured to couple a signal representing an associated bit in the data source to a data line of a serial communication link when a pulse is present in the corresponding delay line signal; and a clock generation circuit responsive to edges in two of the N delay line signals and configured to generate a transmit clock signal to be transmitted over a clock line of the serial communication link.

[0085] 2 . The serializer of claim 1 , wherein the input signal comprises pulses that repeat at a frequency corresponding to a frequency of the transmit clock signal.

[0086] 3 . The serializer according to claim 1 , wherein the input signal comprises a pulse having a duration corresponding to 1 / N of a period of the transmission clock signal.

[0087] 4 . The serializer according to claim 1 , wherein the pulse generating circuit is configured to generate a pulse having a duration corresponding to 1 / N of a period of the transmission clock signal in the input signal.

[0088] 5. A serializer according to any one of claims 1 to 4, wherein each of the plurality of delay stages coupled in series is configured to delay a signal conducted between an input and an output of each delay stage by a duration corresponding to 1 / N of a period of the transmit clock signal.

[0089] 6. A serializer according to any of clauses 1 to 5, wherein at least one delay stage of the plurality of serially coupled delay stages is configured to delay a signal conducted between an input and an output of the at least one delay stage by a calibrable duration.

[0090] 7. A serializer according to any one of clauses 1 to 6, wherein a pulse in each of the N delay line signals has a duration corresponding to 1 / N of a period of the transmit clock signal, and wherein a leading edge of a pulse output by each of the sequential pairs of the plurality of serially coupled delay stages passes through a period corresponding to 1 / N of a period of the transmit clock signal.

[0091] The durations corresponding to 1 / N are separated.

[0092] 8. A serializer according to any one of clauses 1 to 7, further comprising: a line driver having an input coupled to the output of each of the plurality of buffers and an output configured to be coupled to the data line of the serial communication link, wherein each of the plurality of buffers is configured to have its output present a high impedance to the input of the line driver when the pulse is not present in the corresponding delay line signal.

[0093] 9. A serializer according to any of clauses 1 to 8, wherein N represents the number of bits in parallel units of data received from the data source for transmission by the serializer over the serial communications link.

[0094] 10. A method for serializing data, the method comprising: using a delay line to generate N delay line signals, the N delay line signals being versions of an input signal provided to the delay line; providing the N delay line signals to a plurality of buffers coupled to a data source, each of the plurality of buffers being enabled by a corresponding delay line signal and configured to couple a signal representing an associated bit in the data source to a data line of a serial communication link when a pulse is present in the corresponding delay line signal; and coupling a transmit clock signal to a clock line of the serial communication link, the transmit clock signal being generated using edges in two of the N delay line signals.

[0095] 11. The method of clause 10, wherein the input signal comprises pulses that repeat at a frequency corresponding to a frequency of the transmit clock signal.

[0096] 12. A method as described in clause 10 or 11, wherein the input signal comprises a pulse having a duration corresponding to 1 / N of a period of the transmit clock signal.

[0097] 13. The method according to any one of clauses 10 to 12, further comprising:

[0098] A pulse having a duration corresponding to 1 / N of the period of the transmitting clock signal is generated.

[0099] 14. A method according to any one of clauses 10 to 13, wherein the delay line comprises a plurality of delay stages coupled in series, each of the plurality of delay stages coupled in series being configured to delay a signal conducted between an input and an output of each delay stage for a duration corresponding to 1 / N of a period of the transmitted clock signal.

[0100] 15. A method according to any one of clauses 10 to 14, wherein the delay line comprises a plurality of delay stages coupled in series, at least one of the plurality of delay stages coupled in series being configured to delay a signal conducted between an input and an output of the at least one delay stage by a calibrable duration.

[0101] 16. A method according to any one of clauses 10 to 15, wherein a pulse in each of the N delay line signals has a duration corresponding to 1 / N of the period of the transmitting clock signal, and wherein the leading edges of pulses output by each of a sequential pair of series coupled delay stages in the delay line are separated by a duration corresponding to 1 / N of the period of the transmitting clock signal.

[0102] 17. A method according to any one of clauses 10 to 16, wherein each of the plurality of buffers is configured to present a high impedance to an input of a line driver at its output when the pulse is not present in the corresponding delay line signal, and wherein the output of each of the plurality of buffers is coupled to the input of the line driver, and wherein the output of the line driver is configured to couple to the data line of the serial communication link.

[0103] 18. The method of clause 17, wherein N represents the number of bits in a parallel unit of data received from the data source for transmission over the serial communication link.

[0104] 19. A deserializer, the deserializer comprising: one or more delay lines, the one or more delay lines configured to output N delay line signals, each delay line signal being a version of an input signal provided to one of the one or more delay lines; a plurality of latches coupled to a data line of a serial communication link, each latch being enabled by a corresponding one of the N delay line signals and configured to capture a state of the data line when a pulse is present in the corresponding delay line signal; and a clock generation circuit configured to generate a regenerated transmit clock signal using edges in two of the N delay line signals, the regenerated transmit clock signal corresponding to a clock signal received from a clock line of the serial communication link, wherein a pulse in the input signal of each of the one or more delay lines is generated from an edge in the received clock signal.

[0105] 20. A deserializer according to claim 19, wherein the deserializer includes: a first pulse generating circuit, the first pulse generating circuit being configured to generate a pulse in a first input signal in response to a rising edge in the received clock signal, the pulse in the first input signal having a duration corresponding to 1 / N of the period of the transmitted clock signal; a second pulse generating circuit, the second pulse generating circuit being configured to generate a pulse in a second input signal in response to a falling edge in the received clock signal, the pulse in the second input signal having a duration corresponding to 1 / N of the period of the transmitted clock signal; a first delay line, the first delay line being configured to receive the first input signal and output a first N / 2 of the delay line signal; and a second delay line, the second delay line being configured to receive the second input signal and output a second N / 2 of the delay line signal.

[0106] 21. A deserializer according to clause 19 or 20, wherein the pulses in the first N / 2 of the delay line signal terminate within a first half-cycle of the transmit clock signal, and wherein the pulses in the second N / 2 of the delay line signal terminate within a second half-cycle of the transmit clock signal, and wherein each of the first input signal and the second input signal includes a pulse having a duration corresponding to 1 / N of the period of the transmit clock signal.

[0107] 22. A deserializer according to any one of clauses 19 to 21, wherein the one or more delay lines include a plurality of delay stages coupled in series, wherein each delay stage is configured to delay a signal conducted between an input and an output of each delay stage for a duration corresponding to 1 / N of a period of the transmit clock signal.

[0108] 23. A deserializer according to any one of clauses 19 to 22, wherein the one or more delay lines include a plurality of delay stages coupled in series, wherein at least one of the plurality of delay stages coupled in series is configured to delay a signal conducted between an input and an output of the at least one delay stage by a calibrable duration.

[0109] 24. A deserializer according to any one of clauses 19 to 23, wherein a pulse in each of the N delay line signals has a duration corresponding to 1 / N of a period of the transmit clock signal, and wherein the one or more delay lines comprise a plurality of delay stages coupled in series, wherein a leading edge of a pulse output by each of a sequential pair of the plurality of delay stages coupled in series passes through a period corresponding to 1 / N of the period of the transmit clock signal.

[0110] The durations corresponding to 1 / N are separated.

[0111] 25. A method for deserializing data, the method comprising: using one or more delay lines to generate N delay line signals, each delay line signal being a version of an input signal provided to one of the one or more delay lines; providing the N delay line signals to N latches coupled to a data line of a serial communication link, each latch being enabled by a corresponding delay line signal and configured to capture a state of the data line when a pulse is present in the corresponding delay line signal; and using edges in two of the N delay line signals to regenerate a transmit clock signal corresponding to a clock signal received from a clock line of the serial communication link, wherein pulses in the input signal to the delay line are generated from edges in the received clock signal.

[0112] 26. According to the method described in clause 25, the method also includes: generating a pulse in a first input signal in response to a rising edge in the received clock signal, the pulse in the first input signal having a duration corresponding to 1 / N of the period of the transmitted clock signal; generating a pulse in a second input signal in response to a falling edge in the received clock signal, the pulse in the second input signal having a duration corresponding to 1 / N of the period of the transmitted clock signal; using a first delay line to generate a first N / 2 of the delay line signal as a version of the first input signal; and using a second delay line to generate a second N / 2 of the delay line signal as a version of the second input signal.

[0113] 27. A method according to clause 25 or 26, wherein the pulses in the first N / 2 of the delay line signal terminate within a first half-cycle of the transmit clock signal, and wherein the pulses in the second N / 2 of the delay line signal terminate within a second half-cycle of the transmit clock signal, and wherein each of the first input signal and the second input signal includes a pulse having a duration corresponding to 1 / N of the period of the transmit clock signal.

[0114] 28. A method according to any one of clauses 25 to 27, wherein the one or more delay lines include a plurality of delay stages coupled in series, each of the plurality of delay stages coupled in series being configured to delay a signal transmitted between an input and an output of each delay stage for a duration corresponding to 1 / N of a period of the transmitted clock signal.

[0115] 29. A method according to any one of clauses 25 to 28, wherein the one or more delay lines include a plurality of delay stages coupled in series, at least one of the plurality of delay stages coupled in series being configured to delay a signal conducted between an input and an output of the at least one delay stage by a calibrable duration.

[0116] 30. A method according to any one of clauses 25 to 29, wherein a pulse in each of the N delay line signals has a duration corresponding to 1 / N of the period of the transmitting clock signal, and wherein the one or more delay lines comprise a plurality of delay stages coupled in series, wherein the leading edges of pulses output by each of a sequential pair of delay stages coupled in series are separated by a duration corresponding to 1 / N of the period of the transmitting clock signal.

[0117] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). As an example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple of the same elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0118] The present disclosure is provided to enable any person skilled in the art to make or use the various aspects of the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A serializer, comprising: a delay line having a plurality of delay stages coupled in series, the delay line being configured to output N delay line signals that are delayed versions of an input signal and include outputs of the plurality of delay stages coupled in series; a plurality of buffers coupled to a data source, each buffer being enabled by a corresponding delay line signal and configured to couple a signal representing an associated bit in the data source to a data line of a serial communication link when a pulse is present in the corresponding delay line signal; as well as A clock generation circuit is responsive to edges in two of the N delay line signals and is configured to generate a transmit clock signal to be transmitted over a clock line of the serial communication link. 2 . The serializer of claim 1 , wherein the input signal comprises pulses that repeat at a frequency corresponding to a frequency of the transmit clock signal. 3 . The serializer of claim 1 , wherein the input signal comprises a pulse having a duration corresponding to 1 / N of a period of the transmit clock signal.

4. The serializer according to claim 1, further comprising: A pulse generating circuit is configured to generate a pulse having a duration corresponding to 1 / N of a period of the transmission clock signal in the input signal.

5. The serializer of claim 1 , wherein each of the plurality of delay stages coupled in series is configured to delay a signal conducted between an input and an output of each delay stage by a duration corresponding to 1 / N of a period of the transmit clock signal.

6. The serializer of claim 1, wherein at least one delay stage of the plurality of serially coupled delay stages is configured to delay a signal conducted between an input and an output of the at least one delay stage by a calibrable duration.

7. A serializer according to claim 1, wherein the pulse in each of the N delay line signals has a duration corresponding to 1 / N of the period of the transmit clock signal, and wherein the leading edges of the pulses output by each of the sequential pairs of the plurality of series-coupled delay stages are separated by a duration corresponding to 1 / N of the period of the transmit clock signal.

8. The serializer according to claim 1, further comprising: a line driver having an input coupled to an output of each of the plurality of buffers and an output configured to be coupled to the data line of the serial communication link, Wherein each buffer of the plurality of buffers is configured to have its output present a high impedance to the input of the line driver when the pulse is not present in the corresponding delay line signal.

9. The serializer of claim 1, wherein N represents the number of bits in parallel units received from the data source for data sent by the serializer over the serial communication link.

10. A method for serializing data, the method comprising: generating, using a delay line, N delay line signals that are delayed versions of an input signal provided to the delay line; providing the N delay line signals to a plurality of buffers coupled to a data source, each buffer of the plurality of buffers being enabled by a corresponding delay line signal and configured to couple a signal representing an associated bit in the data source to a data line of a serial communication link when a pulse is present in the corresponding delay line signal; as well as A transmit clock signal is coupled to a clock line of the serial communication link, the transmit clock signal being generated using edges in two of the N delay line signals.

11. The method of claim 10, wherein the input signal comprises pulses that repeat at a frequency corresponding to a frequency of the transmit clock signal. 12 . The method of claim 10 , wherein the input signal comprises a pulse having a duration corresponding to 1 / N of a period of the transmit clock signal.

13. The method according to claim 10, further comprising: A pulse having a duration corresponding to 1 / N of the period of the transmission clock signal is generated in the input signal.

14. The method of claim 10 , wherein the delay line comprises a plurality of delay stages coupled in series, each of the plurality of delay stages coupled in series being configured to delay a signal conducted between an input and an output of each delay stage by a duration corresponding to 1 / N of a period of the transmit clock signal.

15. The method of claim 10, wherein the delay line comprises a plurality of delay stages coupled in series, at least one of the plurality of delay stages coupled in series being configured to delay a signal conducted between an input and an output of the at least one delay stage by a calibrable duration.

16. A method according to claim 10, wherein a pulse in each of the N delay line signals has a duration corresponding to 1 / N of the period of the transmit clock signal, and wherein the leading edges of the pulses output by each of the sequential pairs of series coupled delay stages in the delay line are separated by a duration corresponding to 1 / N of the period of the transmit clock signal.

17. The method of claim 10, wherein each of the plurality of buffers is configured to have its output present a high impedance to an input of a line driver when the pulse is not present in the corresponding delay line signal, and wherein the output of each of the plurality of buffers is coupled to the input of the line driver, and wherein the output of the line driver is configured to couple to the data line of the serial communication link.

18. The method of claim 10, wherein N represents the number of bits in parallel units of data received from the data source for transmission over the serial communication link.

19. A deserializer, the deserializer comprising: one or more delay lines configured to output N delay line signals, each delay line signal being a delayed version of an input signal provided to one of the one or more delay lines; a plurality of latches coupled to a data line of the serial communication link, each latch being enabled by a corresponding one of the N delay line signals and configured to capture a state of the data line when a pulse is present in the corresponding delay line signal; as well as a clock generation circuit configured to generate a regenerated transmit clock signal using edges in two of the N delay line signals, the regenerated transmit clock signal corresponding to a clock signal received from a clock line of the serial communication link, wherein pulses in the input signal to each of the one or more delay lines are generated from edges in the received clock signal.

20. The deserializer according to claim 19, wherein the deserializer comprises: a first pulse generating circuit configured to generate a pulse in a first input signal in response to a rising edge in the received clock signal, the pulse in the first input signal having a duration corresponding to 1 / N of a period of the transmit clock signal; a second pulse generating circuit configured to generate a pulse in a second input signal in response to a falling edge in the received clock signal, the pulse in the second input signal having a duration corresponding to 1 / N of the period of the transmit clock signal; a first delay line configured to receive the first input signal and output a first N / 2 of the delay line signals; as well as A second delay line is configured to receive the second input signal and output a second N / 2 of the delay line signal.

21. A deserializer according to claim 20, wherein the pulses in the first N / 2 of the delay line signal terminate within a first half-cycle of the transmit clock signal, and wherein the pulses in the second N / 2 of the delay line signal terminate within a second half-cycle of the transmit clock signal, and wherein each of the first input signal and the second input signal includes a pulse having a duration corresponding to 1 / N of the period of the transmit clock signal.

22. A deserializer according to claim 19, wherein the one or more delay lines include a plurality of delay stages coupled in series, wherein each delay stage is configured to delay a signal transmitted between an input and an output of each delay stage for a duration corresponding to 1 / N of a period of the transmit clock signal.

23. A deserializer according to claim 19, wherein the one or more delay lines include a plurality of delay stages coupled in series, wherein at least one delay stage of the plurality of delay stages coupled in series is configured to delay a signal conducted between an input and an output of the at least one delay stage by a calibrable duration.

24. A deserializer according to claim 19, wherein a pulse in each of the N delay line signals has a duration corresponding to 1 / N of the period of the transmit clock signal, and wherein the one or more delay lines include a plurality of delay stages coupled in series, wherein the leading edges of pulses output by each of the sequential pairs of the plurality of delay stages coupled in series are separated by a duration corresponding to 1 / N of the period of the transmit clock signal.

25. A method for deserializing data, the method comprising: generating N delay line signals using one or more delay lines, each delay line signal being a delayed version of an input signal provided to one of the one or more delay lines; providing the N delay line signals to N latches coupled to a data line of a serial communication link, each latch being enabled by a corresponding delay line signal and configured to capture a state of the data line when a pulse is present in the corresponding delay line signal; as well as Edges in two of the N delay line signals are used to regenerate a transmit clock signal corresponding to a clock signal received from a clock line of the serial communication link, wherein pulses in the input signal of the delay line are generated from edges in the received clock signal.

26. The method according to claim 25, further comprising: generating a pulse in a first input signal in response to a rising edge in the received clock signal, the pulse in the first input signal having a duration corresponding to 1 / N of a period of the transmit clock signal; generating a pulse in a second input signal in response to a falling edge in the received clock signal, the pulse in the second input signal having a duration corresponding to 1 / N of the period of the transmit clock signal; generating a first N / 2 of the delay line signals as versions of the first input signal using a first delay line; as well as A second N / 2 of the delay line signal is generated as a version of the second input signal using a second delay line.

27. A method according to claim 26, wherein the pulses in the first N / 2 of the delay line signal terminate within a first half-cycle of the transmit clock signal, and wherein the pulses in the second N / 2 of the delay line signal terminate within a second half-cycle of the transmit clock signal, and wherein each of the first input signal and the second input signal includes a pulse having a duration corresponding to 1 / N of the period of the transmit clock signal.

28. A method according to claim 25, wherein the one or more delay lines include a plurality of delay stages coupled in series, each of the plurality of delay stages coupled in series being configured to delay a signal conducted between an input and an output of each delay stage by a duration corresponding to 1 / N of a period of the transmitted clock signal.

29. The method of claim 25, wherein the one or more delay lines comprise a plurality of delay stages coupled in series, at least one of the plurality of delay stages coupled in series being configured to delay a signal conducted between an input and an output of the at least one delay stage by a calibrable duration.

30. A method according to claim 25, wherein a pulse in each of the N delay line signals has a duration corresponding to 1 / N of the period of the transmitting clock signal, and wherein the one or more delay lines include a plurality of delay stages coupled in series, wherein the leading edges of pulses output by each of the sequential pairs of the serially coupled delay stages are separated by a duration corresponding to 1 / N of the period of the transmitting clock signal.

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