Method for realizing seismic data acquisition clock synchronization through Beidou time service and FPGA phase-locked loop

Abstract

The invention discloses a method for realizing data acquisition clock synchronization through Beidou time service and an FPGA phase-locked loop, and the method comprises the steps: obtaining a short message service signal of a Beidou satellite navigation system, and carrying out the analysis to obtain time service information; controlling a digital phase-locked loop to calibrate a local clock signal according to the time service information; monitoring the deviation between the time service information and the local clock signal, and adjusting the frequency and phase of the local clock signal through feedback control of the digital phase-locked loop; monitoring a clock synchronization state, setting a clock deviation threshold value, judging the synchronization state of the time service information and the local clock signal, if the deviation exceeds a threshold value range, triggering an alarm signal, and taking a recovery measure according to an abnormity type and duration time; a hardware timestamp function is integrated, clock synchronization with other acquisition nodes is carried out through a precise time protocol, and the acquisition time of seismic data is recorded.

Description

Technical Field

[0001] The present invention relates to the field of information technology, and in particular to a method for realizing clock synchronization of seismic data acquisition by using Beidou timing and FPGA phase-locked loop. Background Art

[0002] At present, data acquisition is a very critical link in the field of earthquake detection. The time synchronization accuracy directly affects the quality of seismic signals and the accuracy of analysis. Therefore, time synchronization accuracy has become an important indicator of seismic data collectors. Excellent time synchronization accuracy can obtain more accurate signal data, which can improve the accuracy of results of projects such as earthquake positioning and waveform inversion. However, modern widely used seismic data collectors mostly use ARM processors (Advanced RISCMachine, ARM) or digital signal processors (Digital Signal Processing, DSP) as the control core, and FPGA chips have the advantages of high clock frequency, small internal delay, fast computing speed, and pure hardware parallel control. Therefore, compared with ARM chips and DSP chips, its time synchronization accuracy will be better, more efficient and simple. FPGA phase-locked loop (PLL) is a core building block used inside FPGA to create frequency alignment or frequency regeneration between external clock sources. In FPGA design, PLL can be used to generate complex clock networks, including phase locking, frequency division, frequency multiplication, etc. Therefore, the time synchronization of data collectors can be improved by using FPGA phase-locked loop technology to improve the efficiency and accuracy of its time synchronization.

[0003] In the seismic data acquisition system, various acquisition nodes are distributed in different geographical locations. How to ensure that their clocks remain consistent is a key technical problem. Although the traditional GPS timing solution can provide high timing accuracy, signal blocking or interference may occur in certain special environments, resulting in reduced timing accuracy or even timing failure. The short message service of the Beidou satellite navigation system can provide stable and reliable timing signals, but the extraction and application of its time information still requires further technical means.

[0004] How to receive and analyze Beidou timing signals in FPGA and combine them with the phase-locked loop inside FPGA to achieve accurate calibration and synchronization of local clocks is a technical problem that needs to be solved urgently. Since there is a certain delay and jitter in the transmission of Beidou timing signals, how to design a suitable clock synchronization algorithm in FPGA to achieve dynamic compensation for clock drift and ensure long-term stable operation is also a technical difficulty that needs to be overcome. In addition, in a complex seismic data acquisition environment, it is also necessary to consider the capture and tracking strategy of Beidou timing signals, as well as how to achieve free operation and rapid recapture of the clock when the timing signal is interrupted or lost, to ensure the continuity and reliability of data acquisition. Summary of the invention

[0005] The method for realizing clock synchronization of seismic data acquisition by using Beidou timing and FPGA phase-locked loop provided by the present invention mainly comprises: Acquire the short message service signal of the Beidou satellite navigation system and parse it to obtain the timing information; according to the timing information, control the digital phase-locked loop to calibrate the local clock signal; monitor the deviation between the timing information and the local clock signal, and adjust the frequency and phase of the local clock signal through the feedback control of the digital phase-locked loop; adopt a multi-mode timing signal capture and tracking strategy, receive the Beidou dual-frequency signal, and use the frequency and phase differences of the signal to achieve the capture and tracking of the timing signal. If the timing signal of a single frequency point is blocked or interfered, switch to another frequency point; integrate a high-stability local crystal oscillator as The backup clock source synchronizes the timing information with the local crystal oscillator through the digital phase-locked loop. If the timing signal is detected to be interrupted or lost, it switches to the free running mode of the local crystal oscillator and starts the fast recapture mechanism; monitors the clock synchronization state, sets the clock deviation threshold, and determines the synchronization state of the timing information and the local clock signal. If the deviation exceeds the threshold range, an alarm signal is triggered, and recovery measures are taken according to the type and duration of the abnormality; integrates the hardware timestamp function, synchronizes the clock with other acquisition nodes through the precise time protocol, and records the acquisition time of the seismic data.

[0006] Furthermore, the method of acquiring the short message service signal of the Beidou satellite navigation system and parsing it to obtain the timing information includes: receiving the radio frequency signal sent by the Beidou satellite navigation system through a radio frequency front end; down-converting, filtering and amplifying the radio frequency signal to obtain an intermediate frequency signal; performing analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal; capturing and tracking the digital signal to obtain a pseudo code and carrier phase information; decoding and demodulating the pseudo code and carrier phase information to obtain a navigation message; extracting short message service data from the navigation message; and parsing the short message service data to obtain the timing information.

[0007] Furthermore, the method of controlling the digital phase-locked loop to calibrate the local clock signal according to the timing information includes: taking the pulse-per-second signal in the timing information as a reference input signal; taking the pulse-per-second signal generated by the local clock signal as a feedback input signal; comparing the phase difference between the reference input signal and the feedback input signal through a phase detector; generating a control voltage through a loop filter according to the phase difference; adjusting the output frequency of a voltage-controlled oscillator according to the control voltage; and generating the calibrated local clock signal according to the output frequency of the voltage-controlled oscillator.

[0008] Furthermore, the monitoring of the deviation between the timing information and the local clock signal and adjusting the frequency and phase of the local clock signal through feedback control of the digital phase-locked loop include: continuously monitoring the time difference between the second pulse signal in the timing information and the second pulse signal generated by the local clock signal; calculating the frequency deviation and phase offset of the local clock signal according to the time difference; generating a digital control word according to the frequency deviation and phase offset; sending the digital control word to the loop filter of the digital phase-locked loop; adjusting the parameters of the loop filter according to the digital control word; generating a new control voltage according to the adjusted parameters of the loop filter; and adjusting the frequency and phase of the local clock signal according to the new control voltage.

[0009] Furthermore, the multi-mode timing signal capture and tracking strategy is adopted to receive Beidou dual-frequency signals, and the frequency and phase differences of the signals are used to capture and track the timing signals. If the timing signal of a single frequency point is blocked or interfered, it is switched to another frequency point, including: simultaneously receiving Beidou B1I and B1C dual-frequency signals; capturing and tracking the B1I and B1C dual-frequency signals respectively to obtain their respective pseudo-codes and carrier phase information; calculating the respective timing information according to the pseudo-codes and carrier phase information of the B1I and B1C dual-frequency signals; comparing the quality of the timing information of the B1I and B1C dual-frequency signals, and selecting the timing information with better quality as the main timing information; if the frequency point signal corresponding to the main timing information is blocked or interfered, the timing information of another frequency point is switched to the main timing information; and clock synchronization is performed according to the switched main timing information.

[0010] Furthermore, the integrated high-stability local crystal oscillator is used as a backup clock source, and the timing information is synchronized with the local crystal oscillator through the digital phase-locked loop. If it is detected that the timing information is interrupted or lost, it is switched to the free running mode of the local crystal oscillator, and a fast recapture mechanism is started, including: selecting a temperature compensated crystal oscillator as the high-stability local crystal oscillator; inputting the second pulse signal in the timing information and the second pulse signal generated by the local crystal oscillator into the digital phase-locked loop; locking the frequency and phase of the local crystal oscillator to the timing information through the digital phase-locked loop; continuously monitoring the status of the timing information, if the timing information is interrupted or lost, switching the input of the digital phase-locked loop to the local crystal oscillator; maintaining the clock output according to the frequency and phase of the local crystal oscillator; and simultaneously starting the fast recapture mechanism of the Beidou timing signal; when the Beidou timing signal is restored, switching the input of the digital phase-locked loop back to the timing information.

[0011] Furthermore, the clock synchronization status is monitored, a clock deviation threshold is set, and the synchronization status of the timing information and the local clock signal is determined. If the deviation exceeds the threshold range, an alarm signal is triggered, and recovery measures are taken according to the type and duration of the abnormality, including: setting a clock deviation threshold to obtain the deviation between the timing information and the local clock signal; if the deviation is less than a first threshold, the clock synchronization status is judged to be normal; if the deviation is greater than the first threshold and less than a second threshold, the clock synchronization status is judged to be a slight abnormality, and a slight alarm signal is triggered; if the deviation is greater than the second threshold, the clock synchronization status is judged to be a serious abnormality, and a serious alarm signal is triggered; different recovery measures are taken according to the type and duration of the alarm signal, including adjusting the parameters of the digital phase-locked loop, recapturing the timing signal, or switching to a backup clock source.

[0012] Furthermore, the integrated hardware timestamp function performs clock synchronization with other acquisition nodes through the precise time protocol to record the acquisition time of the seismic data, including: integrating a network interface that supports the hardware timestamp function in the seismic data acquisition system; configuring the network interface to operate in the master clock mode or slave clock mode of the precise time protocol; periodically sending or receiving synchronization messages through the network interface; calculating the time deviation between the master clock and the slave clock based on the synchronization message; adjusting the frequency and phase of the local clock signal based on the time deviation; when acquiring seismic data, using the hardware timestamp function to record the acquisition time of each data packet; storing the acquisition time together with the corresponding seismic data for subsequent data processing and analysis.

[0013] Furthermore, it also includes: unified setting and adjustment of the clock synchronization parameters of each acquisition node through remote configuration and management functions; optimizing the capture and tracking strategy of Beidou timing according to the geographical location and environmental conditions of the nodes; and timely detection and handling of abnormal situations by remotely monitoring the clock synchronization status of each node.

[0014] Further, it includes: establishing a remote configuration and management system to obtain the device identification and network address of each acquisition node; establishing a communication connection with each acquisition node through the network address; querying the clock synchronization parameter configuration information of each acquisition node according to the device identification; generating a unified clock synchronization parameter configuration instruction according to a preset clock synchronization strategy; sending the clock synchronization parameter configuration instruction to each acquisition node; each acquisition node updates the local clock synchronization parameters according to the received clock synchronization parameter configuration instruction.

[0015] The technical solution provided by the embodiment of the present invention may have the following beneficial effects: The invention discloses a Beidou timing synchronization method based on FPGA, which is used for high-precision time synchronization of seismic data acquisition. The invention receives and analyzes Beidou short message service signals through FPGA, extracts timing information and controls a digital phase-locked loop to calibrate a local clock. Aiming at the transmission delay and jitter problems of timing signals, an adaptive clock synchronization algorithm is designed to dynamically adjust the local clock frequency and phase. The B1I and B1C dual-frequency signal receiving strategies are adopted to improve the reliability of timing. A high-stability crystal oscillator is integrated as a backup clock source to deal with timing signal interruptions. Real-time monitoring and exception handling of clock synchronization status are achieved to ensure synchronization reliability. The IEEE 1588 protocol hardware timestamp function is integrated to achieve clock consistency of distributed systems. The timing parameters of each node are optimized through remote configuration management. The invention solves the problem of high-precision time synchronization of seismic data acquisition systems in complex environments, improves the reliability and stability of timing, ensures the time correlation of distributed node data, and provides important technical support for earthquake monitoring and early warning. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of the present invention.

[0017] Figure 2 It is a schematic diagram of the present invention.

[0018] Figure 3 It is another schematic diagram of the present invention.

[0019] Figure 4 It is another schematic diagram of the present invention.

[0020] Figure 5 It is another schematic diagram of the present invention.

[0021] Figure 6 It is another schematic diagram of the present invention.

[0022] Figure 7 It is another schematic diagram of the present invention.

[0023] Figure 8 It is another schematic diagram of the present invention.

[0024] Fig. 9 and Fig.10 It is a system modular architecture diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] like Figure 1-Figure 8 , this embodiment may specifically include: Step S101, receive and analyze the short message service signal of the Beidou satellite navigation system through FPGA, extract the timing information contained therein, and obtain a high-precision time reference. According to the extracted timing information, control the digital phase-locked loop inside the FPGA, accurately calibrate the local clock signal of the FPGA chip, eliminate the frequency deviation and phase offset of the local clock, and achieve synchronization with the Beidou timing.

[0027] Step S102, in order to solve the delay and jitter problems in the transmission process of Beidou timing signal, an adaptive clock synchronization algorithm is designed in FPGA. The algorithm continuously monitors the deviation between Beidou timing signal and local clock, dynamically adjusts the frequency and phase of local clock through feedback control of digital phase-locked loop, compensates for the clock drift caused by signal delay and jitter, and ensures the long-term synchronization stability with Beidou timing.

[0028] Step S103, in a complex seismic data acquisition environment, a multi-mode timing signal capture and tracking strategy is adopted to improve the reliability of Beidou timing. The simultaneous reception and analysis of Beidou B1I and B1C dual-frequency signals are realized through FPGA, and the frequency and phase differences of the signals are used to achieve accurate capture and stable tracking of timing signals. If the timing signal of a single frequency point is blocked or interfered, it is switched to another frequency point in time to ensure the continuity of timing.

[0029] Step S104, in case of interruption or loss of lock of Beidou timing signal, a highly stable local crystal oscillator is integrated in FPGA as a backup clock source. Beidou timing is synchronized with the local crystal oscillator for a long time through a digital phase-locked loop to establish a stable clock relationship. Once the interruption or loss of lock of Beidou timing signal is detected, it is switched to the free running mode of the local crystal oscillator in time to maintain the continuous output of the clock. At the same time, the fast recapture mechanism is started to speed up the resynchronization with Beidou timing.

[0030] Step S105, implement real-time monitoring and exception handling of clock synchronization status in FPGA. By setting the clock deviation threshold, determine the synchronization status of Beidou timing and local clock. If the deviation exceeds the threshold range, trigger an alarm signal in time to indicate clock synchronization abnormality. According to the type and duration of the abnormality, take corresponding recovery measures, such as adjusting the parameters of the digital phase-locked loop, recapture the timing signal, etc., to ensure the reliability of clock synchronization.

[0031] Step S106: In view of the distributed nature of the seismic data acquisition system, the hardware timestamp function of the IEEE 1588 Precision Time Protocol (PTP) is integrated in the FPGA. The clock is synchronized with other acquisition nodes through the PTP protocol to achieve clock consistency of the entire system. The hardware timestamp capability of the FPGA is used to accurately record the acquisition time of the seismic data and ensure the time correlation of data from different nodes.

[0032] Step S107, during the system deployment and operation and maintenance phase, the FPGA clock synchronization parameters of each acquisition node are uniformly set and adjusted through remote configuration and management functions. According to the geographical location and environmental conditions of the node, the capture and tracking strategy of Beidou timing is optimized to improve the reliability of timing. By remotely monitoring the clock synchronization status of each node, abnormal situations can be discovered and handled in a timely manner to ensure the long-term stable operation of the system.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

[0034] like Fig. 9 and Fig.10 As shown, this embodiment provides a system for time synchronization based on FPGA phase-locked loop technology, including a BDS module, a phase-locked loop module, an IRIG decoding module, a clock synchronization module, an SSC interface module, and an MCU module.

[0035] Step 1: The BDS module generates a time information signal every second - IRIG-B signal Step 2: At the same time, the FPGA's DLL module will expand the external 19.2MHz (nominal frequency) temperature-compensated crystal oscillator clock input to 16 times the system clock, that is, 131.072 MHz (nominal frequency).

[0036] Step 3: The IRIG module decodes the IRIG-B module generated in step 1, and the decoded IRIG code data is sent to the SSC interface module through the FIFO buffer. The IRIG module also decodes the P0 and Pr signals in the IRIG-B signal, and the parsed second pulse signal is used as the synchronization pulse signal for system clock synchronization.

[0037] Step 4: The clock synchronization module counts the clock with a nominal frequency of 131.072 MHz generated in step 2 according to the rising edge of the second pulse, thereby obtaining a count value of 1 second.

[0038] When the count value is equal to 131072000, the system frequency division coefficient is set to 16. After the 131.072Mhz clock is divided by 16, the 8.192Mhz system clock is obtained. At this time, the system clock is synchronized with the second pulse.

[0039] When the count value is less than 131072000, two division coefficients 15 and 16 are set. Assuming the design value is m less than 131072000, it means that the system clock needs to be divided by 15 m times within 1 second, and the rest by 16. The system clock generated at this time is 8.192Mhz system clock, which is synchronized with the second pulse.

[0040] When the count value is greater than 131072000, two division coefficients 16 and 17 are set. Assuming that the design value is m greater than 131072000, it means that the system clock needs to be divided by 17 m times within 1 second, and the rest by 16. The system clock generated at this time is 8.192Mhz system clock, which is synchronized with the second pulse.

[0041] When the BDS module signal is lost, the clock synchronization circuit divides the 131.072Mhz clock according to the division coefficient calculated by the previous count value within 1 second to obtain the 8.192Mhz system clock. The drift of the 8.192Mhz system clock generated at this time depends on the drift of the external 19.2Mhz crystal oscillator. Therefore, we use a temperature compensated crystal oscillator (TCXO) when selecting the FPGA external crystal oscillator, which can ensure that its drift is small and the time synchronization error is small.

[0042] Step 5. FPGA further divides the generated 8.192 MHz system clock as the clock for other parts of the system. The 4096Khz encoding clock is used as the clock for SSC, FIFO, encoding, etc.; the 1024Khz encoding clock is used as the system encoding clock; and the 1024Khz decoding clock is used as the system decoding clock. All encoding clocks are triggered on the rising edge of the master clock, and all decoding clocks are triggered on the falling edge of the master clock. This ensures that the encoding clock and the decoding clock differ by 1 / 2 of the master clock, resulting in the decoding clock avoiding the transition edge of the encoded data.

[0043] The technical route in this embodiment that is different from the prior art is: When using the FPGA decoding module for encoding and decoding, the encoding and decoding differ by 1 / 2 of the main clock, so that the decoding clock avoids the transition edge of the encoded data, and the decoding result is more stable; the FPGA module can be used alone to synchronize the time of the seismic data collector without adding other peripheral circuits; when the external input BDS module signal is lost, the present invention creatively uses a temperature-compensated crystal oscillator of the corresponding frequency for calculation and frequency division, ensuring small time drift and high time keeping accuracy.

[0044] The applicant further declares that the present invention illustrates the implementation method and device structure of the present invention through the above-mentioned embodiments, but the present invention is not limited to the above-mentioned implementation methods, that is, it does not mean that the present invention must rely on the above-mentioned methods and structures to be implemented. Those skilled in the art should understand that any improvement of the present invention, equivalent replacement of the implementation method selected by the present invention, addition of steps, selection of specific methods, etc., all fall within the protection scope and disclosure scope of the present invention.

[0045] The present invention is not limited to the above-mentioned embodiments, and all embodiments that use structures and methods similar to the present invention to achieve the purpose of the present invention are within the protection scope of the present invention.

Claims

1. A method for realizing clock synchronization of seismic data acquisition by using Beidou timing and FPGA phase-locked loop, characterized in that: include: Obtain the short message service signal of the Beidou satellite navigation system and parse it to obtain the timing information; According to the timing information, a digital phase-locked loop is controlled to calibrate a local clock signal; Monitoring the deviation between the timing information and the local clock signal, and adjusting the frequency and phase of the local clock signal through feedback control of the digital phase-locked loop; Adopt multi-mode timing signal capture and tracking strategy, receive Beidou dual-frequency signals, and use the frequency and phase differences of the signals to capture and track timing signals. If the timing signal of a single frequency point is blocked or interfered, switch to another frequency point. Integrate a high-stability local crystal oscillator as a backup clock source, synchronize the timing information with the local crystal oscillator through the digital phase-locked loop, and switch to the free-running mode of the local crystal oscillator and start a fast recapture mechanism if the timing signal is detected to be interrupted or lost; Monitor the clock synchronization status, set the clock deviation threshold, determine the synchronization status of the timing information and the local clock signal, and trigger an alarm signal if the deviation exceeds the threshold range, and take recovery measures according to the abnormality type and duration; The integrated hardware timestamp function synchronizes the clock with other acquisition nodes through the precise time protocol to record the acquisition time of the seismic data.

2. The method for realizing clock synchronization of seismic data acquisition by using Beidou timing and FPGA phase-locked loop according to claim 1, characterized in that: Obtain the short message service signal of the Beidou satellite navigation system and parse it to obtain timing information, including: Receive the radio frequency signal sent by the Beidou satellite navigation system through the radio frequency front end; Down-converting, filtering and amplifying the radio frequency signal to obtain an intermediate frequency signal; Performing analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal; Capturing and tracking the digital signal to obtain pseudo code and carrier phase information; Decoding and demodulating the pseudo code and carrier phase information to obtain a navigation message; extracting short message service data from the navigation message; The short message service data is parsed to obtain the timing information.

3. The method for realizing clock synchronization of seismic data acquisition by using Beidou timing and FPGA phase-locked loop according to claim 1, characterized in that: According to the timing information, controlling a digital phase-locked loop to calibrate a local clock signal includes: Using the pulse-per-second signal in the timing information as a reference input signal; Using the pulse per second signal generated by the local clock signal as a feedback input signal; Comparing the phase difference between the reference input signal and the feedback input signal by a phase detector; generating a control voltage through a loop filter according to the phase difference; adjusting the output frequency of the voltage-controlled oscillator according to the control voltage; The calibrated local clock signal is generated according to the output frequency of the voltage-controlled oscillator.

4. The method for realizing clock synchronization of seismic data acquisition by using Beidou timing and FPGA phase-locked loop according to claim 1, characterized in that: Monitoring the deviation between the timing information and the local clock signal, and adjusting the frequency and phase of the local clock signal through feedback control of the digital phase-locked loop, including: Continuously monitoring the time difference between the pulse-per-second signal in the timing information and the pulse-per-second signal generated by the local clock signal; Calculating the frequency deviation and phase offset of the local clock signal according to the time difference; generating a digital control word according to the frequency deviation and the phase offset; Sending the digital control word to a loop filter of the digital phase-locked loop; According to the digital control word, adjusting the parameters of the loop filter; generating a new control voltage according to the adjusted parameters of the loop filter; The frequency and phase of the local clock signal are adjusted according to the new control voltage.

5. The method for realizing clock synchronization of seismic data acquisition by using Beidou timing and FPGA phase-locked loop according to claim 1, characterized in that: Adopt multi-mode timing signal capture and tracking strategy, receive Beidou dual-frequency signals, and use the frequency and phase differences of the signals to capture and track timing signals. If the timing signal of a single frequency point is blocked or interfered, switch to another frequency point, including: Receive Beidou B1I and B1C dual-frequency signals simultaneously; Capturing and tracking the B1I and B1C dual-frequency signals respectively to obtain their respective pseudo codes and carrier phase information; Calculate the respective timing information according to the pseudo code and carrier phase information of the B1I and B1C dual-frequency signals; Comparing the quality of the timing information of the B1I and B1C dual-frequency signals, and selecting the timing information with better quality as the main timing information; If the frequency signal corresponding to the primary timing information is blocked or interfered, the timing information of another frequency is switched to the primary timing information; Clock synchronization is performed according to the master timing information after switching.

6. The method for realizing clock synchronization of seismic data acquisition by using Beidou timing and FPGA phase-locked loop according to claim 1, characterized in that: Integrate a high-stability local crystal oscillator as a backup clock source, synchronize the timing information with the local crystal oscillator through the digital phase-locked loop, and switch to the free-running mode of the local crystal oscillator if the timing information is detected to be interrupted or lost, and start a fast recapture mechanism, including: Selecting a temperature compensated crystal oscillator as the high-stability local crystal oscillator; Inputting the pulse-per-second signal in the timing information and the pulse-per-second signal generated by the local crystal oscillator into the digital phase-locked loop; Locking the frequency and phase of the local crystal oscillator to the timing information through the digital phase-locked loop; Continuously monitoring the state of the timing information, and if the timing information is interrupted or unlocked, switching the input of the digital phase-locked loop to the local crystal oscillator; Maintaining a clock output according to the frequency and phase of the local crystal oscillator; At the same time, the rapid recapture mechanism of Beidou timing signal is started; When the Beidou timing signal is restored, the input of the digital phase-locked loop is switched back to the timing information.

7. The method for realizing clock synchronization of seismic data acquisition by using Beidou timing and FPGA phase-locked loop according to claim 1, characterized in that: Monitor the clock synchronization status, set the clock deviation threshold, determine the synchronization status of the timing information and the local clock signal, and trigger an alarm signal if the deviation exceeds the threshold range. Take recovery measures according to the abnormality type and duration, including: Setting a clock deviation threshold to obtain a deviation between the timing information and the local clock signal; If the deviation is less than the first threshold, the clock synchronization state is determined to be normal; If the deviation is greater than the first threshold and less than the second threshold, the clock synchronization state is judged to be slightly abnormal, and a slight alarm signal is triggered; If the deviation is greater than the second threshold, the clock synchronization state is judged to be seriously abnormal, and a serious alarm signal is triggered; Different recovery measures are taken according to the type and duration of the alarm signal, including adjusting the parameters of the digital phase-locked loop, recapturing the timing signal, or switching to a backup clock source.

8. The method for realizing clock synchronization of seismic data acquisition by using Beidou timing and FPGA phase-locked loop according to claim 1, characterized in that: The integrated hardware timestamp function synchronizes the clock with other acquisition nodes through the precise time protocol and records the acquisition time of seismic data, including: Integrate a network interface that supports hardware time stamping in seismic data acquisition systems; Configuring the network interface to operate in a master clock mode or a slave clock mode of a precision time protocol; Periodically sending or receiving synchronization messages through the network interface; Calculating the time deviation between the master clock and the slave clock according to the synchronization message; According to the time deviation, adjusting the frequency and phase of the local clock signal; When collecting seismic data, the hardware timestamp function is used to record the collection time of each data packet; The acquisition time is stored together with the corresponding seismic data for subsequent data processing and analysis.

9. The method for realizing clock synchronization of seismic data acquisition by using Beidou timing and FPGA phase-locked loop according to claim 1, characterized in that: Also includes: Through remote configuration and management functions, the clock synchronization parameters of each acquisition node can be uniformly set and adjusted; Optimize the acquisition and tracking strategy of Beidou timing according to the geographical location and environmental conditions of the node; By remotely monitoring the clock synchronization status of each node, abnormal situations can be discovered and handled in a timely manner; The clock synchronization parameters of each acquisition node are uniformly set and adjusted through remote configuration and management functions, including: establishing a remote configuration and management system to obtain the device identification and network address of each acquisition node; establishing a communication connection with each acquisition node through the network address; querying the clock synchronization parameter configuration information of each acquisition node according to the device identification; generating a unified clock synchronization parameter configuration instruction according to a preset clock synchronization strategy; sending the clock synchronization parameter configuration instruction to each acquisition node; each acquisition node updates the local clock synchronization parameters according to the received clock synchronization parameter configuration instruction.

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