Three-core master-slave processor self-correction method, system, device and program
By adopting self-correction methods in the three-core master-slave processor system, the problems of data inconsistency and errors in the multi-core processor system are solved, the stability and reliability of the system are improved, and it is suitable for application scenarios such as high-performance computing and real-time control.
CN119668911APending Publication Date: 2025-03-21BEIJING GUOXIN TRUSTED TECHNOLOGY CO LTD
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Patent Information
- Application Number
- CN202411742314.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-03-21
AI Technical Summary
Technical Problem
In multi-core processor systems, especially under the master-slave processor architecture, data inconsistency and error problems have become important factors that restrict system performance.
Method used
The three-core master-slave processor self-correction method is adopted. After each instruction is completed, the main processor accesses two secondary processors respectively. By comparing each processor, the processor runs stably. If an error is found, it can be corrected in real time.
Benefits of technology
It effectively increases the stability and reliability of the system, reduces the hardware delay caused by the polling method, improves the efficiency of the processor, and is suitable for application scenarios such as high-performance computing and real-time control.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention discloses a three-core master-slave processor self-correction method, system, device and program. The method comprises the steps that three processor cores of a three-core master-slave processor send instructions to a register file; wherein the three-core master-slave processor comprises one master processor and two slave processors; the main processor sends register information to the two slave processors, and the two slave processors compare the register information to generate comparison result control codes; the slave processor sends a processor number, register information and a comparison result control code to the master processor; and the main processor executes a preset operation based on the comparison result control code. Through the processing scheme disclosed by the invention, data errors can be monitored in real time and automatically corrected, so that the stability and reliability of the system are ensured, and powerful support is provided for application scenes such as high-performance calculation and real-time control.
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