Display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprising: a pixel circuit and a light emitting element; the pixel circuit comprising a driving module, a data writing module, a compensation module and a reset module; the driving module comprising a driving transistor; the data writing module being connected to a first electrode of the driving transistor; the compensation module being connected between a gate electrode and a second electrode of the driving transistor; the reset module being connected to the gate electrode or the second electrode of the driving transistor; wherein, a working process of the pixel circuit comprises a first bias adjustment stage, the first bias adjustment stage comprising a first stage; in the first stage, the data writing module and the reset module are turned off, and the compensation module is turned on. The technical scheme of the application can perform bias adjustment of different degrees on the driving transistor under different gray scales, thereby improving display uniformity of the display panel.

Description

[0001] This application is a divisional application filed on August 25, 2022, with application number 202211028570.2 and titled "Display Panel and Display Device". Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0003] Display panels typically contain pixel circuits and light-emitting elements. The driving transistors in the pixel circuits can provide driving current to the light-emitting elements based on the data signals they receive, thereby driving the light-emitting elements to emit light and enabling the display panel to display the corresponding image.

[0004] However, over time, the internal characteristics of the driving transistors in the pixel circuit change slowly, causing the threshold voltage of the driving transistors to drift. Moreover, the threshold drift of the driving transistors varies under different display brightness, thus affecting the display uniformity of the display panel. Summary of the Invention

[0005] The present invention provides a display panel and a display device to improve display abnormalities under different display brightness and enhance the display uniformity of the display panel.

[0006] According to one aspect of the present invention, a display panel is provided, comprising:

[0007] Pixel circuits and light-emitting elements;

[0008] The pixel circuit includes a driving module, a data writing module, a compensation module, and a reset module;

[0009] The driving module includes a driving transistor;

[0010] The data writing module is connected to the first electrode of the driving transistor;

[0011] The compensation module is connected between the gate and the second electrode of the driving transistor;

[0012] The reset module is connected to the gate or the second electrode of the driving transistor; wherein,

[0013] The operation of the pixel circuit includes a first bias adjustment stage, which includes a first stage.

[0014] In the first stage, the data writing module and the reset module are turned off, and the compensation module is turned on.

[0015] According to another aspect of the present invention, a display device is provided, including the above-described display panel.

[0016] The technical solution of this invention, by controlling the compensation module to be turned on and the data writing module and reset module to be turned off in the first stage of bias adjustment, allows the gate potential of the driving transistor carrying the data signal to be transmitted to its second electrode. This enables different degrees of bias adjustment of the driving transistor for different gray levels, so that the threshold drift phenomenon caused by the voltage difference between the gate and the second electrode of the driving transistor can be improved or eliminated at each gray level, thereby improving the display uniformity of the display panel and improving the display effect of the display panel.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the pixel circuit in a display panel provided by an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the pixel circuit structure in another display panel provided by an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0025] Figure 7 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0026] Figure 8This is a timing diagram of the pixel circuit in another display panel provided by an embodiment of the present invention;

[0027] Figure 9 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0028] Figure 10 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0029] Figure 11 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0030] Figure 12 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0031] Figure 13 This is a schematic diagram of the structure of a pixel circuit in a display panel provided in another embodiment of the present invention;

[0032] Figure 14 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0033] Figure 15 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0034] Figure 16 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0035] Figure 17 This is a timing diagram of the pixel circuit in another display panel provided by an embodiment of the present invention.

[0036] Figure 18 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0037] Figure 19 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0038] Figure 20 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0039] Figure 21 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0040] Figure 22 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0041] Figure 23 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0042] Figure 24 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0043] Figure 25 This is a timing diagram of the operation of a pixel circuit in a display panel provided by an embodiment of the present invention;

[0044] Figure 26 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] Self-emissive display panels include pixel circuits and light-emitting elements. The pixel circuits include driving transistors. By providing a data signal to the gate of the driving transistor, the driving transistor converts the data signal into a driving current to drive the light-emitting element to emit light. However, when the driving transistor is turned on, for PMOS type driving transistors, its gate potential may be higher than its drain potential, and for NMOS type driving transistors, its gate potential may be lower than its drain potential. If this state is maintained for a long time, the ions inside the driving transistor will become polarized, resulting in a built-in electric field inside the driving transistor. This causes the threshold voltage of the driving transistor to continuously drift, biasing the driving transistor and affecting the stability of the driving current provided by the driving transistor, thereby affecting the light emission stability of the light-emitting element.

[0048] In existing technologies, a fixed bias adjustment signal is provided to the driving transistor to mitigate the impact of driving transistor bias on the display panel's performance. However, because the data signals supplied to the gate of the driving transistor differ at different gray levels, the gate potential of the driving transistor varies, resulting in different potential differences between the gate and drain of the driving transistor, i.e., different bias degrees of the driving transistor. When the same bias adjustment signal is provided to driving transistors with different gate-drain potential differences, the recovery speed and recovery degree of driving transistors with different bias degrees will differ. Therefore, using only a fixed bias adjustment signal cannot simultaneously address the different bias conditions of the driving transistors at different gray levels, thus affecting the display uniformity of the display panel.

[0049] To solve the above-mentioned technical problems, in the first stage of the first bias adjustment stage, the data writing module and the reset module are turned off, and only the compensation module is turned on, so that a path is formed between the gate of the driving transistor and its second electrode, and the gate potential of the driving transistor is applied to its second electrode. In this way, the gate potential of the driving transistor is different at different gray levels, and the potential applied to its second electrode is also different, so that the gate potential of the driving transistor can be kept consistent with the potential of its second electrode at each gray level. Thus, the different bias degrees of the driving transistor at different gray levels can be adjusted in a targeted manner.

[0050] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0051] Figure 1 This is a schematic diagram of the pixel circuit in a display panel according to an embodiment of the present invention. Figure 2This is a schematic diagram of the pixel circuit structure in another display panel provided by an embodiment of the present invention, as shown below. Figure 1 As shown in Figure 2, the display panel includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 includes a driving module 11, a data writing module 12, a compensation module 13, and a reset module 14. The driving module 11 includes a driving transistor T. The data writing module 12 is connected to the first terminal of the driving transistor T. The compensation module 13 is connected between the gate and the second terminal of the driving transistor T. The reset module 14 is connected to either the gate or the second terminal of the driving transistor T. The operation of the pixel circuit 10 includes a first bias adjustment stage, which includes a first phase. In the first phase, the data writing module 12 and the reset module 14 are turned off, and the compensation module 13 is turned on.

[0052] Specifically, the reset module 14 can control the reset signal Vref to be written to the second gate of the driving transistor T to reset the gate and / or the second gate of the driving transistor T, so as to prevent the potential of the gate or the second gate of the driving transistor T from affecting the writing of the data signal Vdata in the next working cycle in the previous working cycle; the data writing module 12 can control the data signal Vdata to be written to the gate of the driving transistor T; the compensation module 13 can compensate the threshold voltage Vth of the driving transistor T so that the driving current provided by the driving transistor T to the light-emitting element 20 is independent of its own threshold voltage. The period during which the driving transistor T provides driving current to the light-emitting element 20 is the light-emitting phase. The period during which the data writing module 12 writes the data signal Vdata to the gate of the driving transistor T and the compensation module 13 performs threshold voltage compensation on the driving transistor T is the data writing phase. The period during which the reset module 14 writes the reset signal to the gate of the driving transistor T is the reset phase. That is, the operation of the pixel circuit includes at least the reset phase, the data writing phase, and the light-emitting phase. In one driving cycle of the pixel circuit, the reset phase, the data writing phase, and the light-emitting phase are usually performed sequentially. That is, after resetting the driving transistor T in the reset phase, the data writing phase will be entered to write the data signal to the driving transistor T. After the data writing phase is completed, the light-emitting phase will be entered, and the driving transistor T will provide driving current to the light-emitting element 20 to drive the light-emitting element to emit light. After the light-emitting phase ends, the next driving cycle will begin. Before the pixel circuit 10 enters the reset phase of the current driving cycle after the light emission phase of the previous driving cycle, the gate potential of the driving transistor T carries the data signal of the previous working process. Since the data signal corresponding to the driving transistor T is different under different gray levels, the bias degree of the driving transistor T is different under different gray levels at the end of the light emission phase.

[0053] For example, in the case where the driving transistor T is a PMOS transistor, the gate of the driving transistor is electrically connected to the first node N1, the first electrode of the driving transistor T is electrically connected to the second node N2 and coupled to the positive power supply PVDD through the second node N2, the second electrode of the driving transistor T is electrically connected to the third node N3 and coupled to the anode of the light-emitting element 20 through the third node N3, and the cathode of the light-emitting element 20 is electrically connected to the negative power supply PVEE. This results in a lower potential at the second electrode of the driving transistor T during the light-emitting phase, and the higher the display brightness required by the light-emitting element 20, the higher its grayscale, and the lower the corresponding data signal voltage; for example, in a white screen, the corresponding... The lower voltage of the corresponding data signal results in a lower gate potential written to the driving transistor T. During the light-emitting phase, the potential difference between the gate and its second electrode of the driving transistor T is small, and the bias degree of the driving transistor T is relatively low. Conversely, the higher voltage of the corresponding data signal during the black screen phase results in a higher gate potential written to the driving transistor T. During the light-emitting phase, the potential difference between the gate and its second electrode of the driving transistor T is large, and the bias degree of the driving transistor T is relatively severe. Thus, the bias degree of the driving transistor T differs between black and white screens, requiring different bias adjustments for each type of screen.

[0054] In this embodiment, in the first stage of the first bias adjustment stage, the control compensation module 13 is turned on, and the control data writing module 12 and the reset module 14 are turned off, so that the potential of the gate of the driving transistor T flows to its second electrode. For a white screen, the gate potential of the driving transistor T is inherently low, and the potential it is loaded onto the second electrode is also relatively low. At this time, the potential difference between the gate and the second electrode of the driving transistor is still small. For a black screen, the gate potential of the driving transistor is inherently high, and the potential it is loaded onto the second electrode is also relatively high. At this time, the potential difference between the gate and the second electrode of the driving transistor can also be relatively reduced. Thus, different degrees of bias adjustment can be achieved for different gray levels (i.e., black screen and white screen), so that the driving transistor T can be targeted for bias adjustment at each gray level, improving or eliminating the threshold drift phenomenon caused by the voltage difference between the gate and the second electrode of the driving transistor T, thereby improving the display uniformity of the display panel and improving the display effect of the display panel. The first bias adjustment stage can be located after the light emission stage of the previous driving cycle of the pixel circuit ends and before the reset stage of the current driving cycle begins. Under the premise of targeted bias adjustment of the driving transistor at different gray levels, the embodiments of the present invention do not specifically limit the time period of the first bias adjustment stage in a driving cycle.

[0055] Understandable Figure 1 and Figure 2The examples shown all exemplify the case where the driving transistor T is a PMOS type transistor. However, in embodiments of the present invention, the driving transistor T can also be an NMOS type transistor. For example, as shown... Figure 3 or Figure 4 As shown, when the driving transistor T is an NMOS transistor, its second electrode is coupled to the positive power supply PVDD, its first electrode is coupled to the anode of the light-emitting element 20, and the cathode of the light-emitting element 20 is electrically connected to the negative power supply PVEE. At this time, during the light-emitting phase, the potential of the second electrode of the driving transistor T is relatively high, and the higher the display brightness required by the light-emitting element 20, the higher its grayscale, and the higher the corresponding data signal voltage. For example, under a white screen, the corresponding data signal voltage is high, and the gate potential of the driving transistor T is high. During the light-emitting phase, the potential difference between the gate and its second electrode of the driving transistor T is still small, and the bias degree of the driving transistor T is relatively low. In the first stage of the first bias adjustment phase, the control compensation module 13 is activated. The control data writing module 12 and reset module 14 are turned off, causing the potential of the gate of the driving transistor T to flow to its second electrode, thereby loading a higher potential onto the second electrode of the driving transistor T, so that the potential difference between the gate and the second electrode of the driving transistor T remains small. Similarly, in a black screen, the voltage of the corresponding data signal is low, and the gate potential of the driving transistor T is low. In the light-emitting stage, the potential difference between it and the second electrode is large. By turning on the compensation module 13 and turning off the data writing module 12 and reset module 14 in the first stage of the first bias adjustment stage, the potential of the gate of the driving transistor T flows to its second electrode, thereby loading a lower potential onto the second electrode of the driving transistor T, and the potential difference between the gate and the second electrode of the driving transistor can also be relatively reduced. In this way, different degrees of bias adjustment can be performed for black and white screens, so that the driving transistor T can quickly recover to a state close to non-bias at different gray levels.

[0056] In one exemplary embodiment, reference is made to... Figure 1-4In any of the accompanying drawings, the reset module 14 can be turned on or off under the control of the scan signal S1. When the scan signal S1 controls the reset module 14 to be turned on, the reset module 14 can control the reset signal Vref to be written to the gate and / or the second terminal of the driving transistor T to reset the driving transistor T. When the scan signal S1 controls the reset module 14 to be turned off, the writing of the reset signal Vref can be prevented. At this time, the reset module 14 may include a reset transistor M1. The gate of the reset transistor M1 can receive the scan signal S1, the first terminal of the reset transistor M1 receives the reset signal Vref, and the second terminal of the reset transistor M1 is electrically connected to the gate or the second terminal of the driving transistor T. The reset transistor M1 can be either an NMOS or PMOS transistor. When M1 is an NMOS transistor, it is turned on when the scan signal S1 is high and turned off when S1 is low. Conversely, when M1 is a PMOS transistor, it is turned on when S1 is low and turned off when S1 is high. This embodiment of the invention does not specifically limit the type of reset transistor M1.

[0057] It should be noted that, in this embodiment of the invention, the reset module 14 can be connected to the gate or the second electrode of the driving transistor T, i.e., as shown below. Figure 1 and 3 As shown, the reset module 14 is connected to the gate of the driving transistor T. In this case, the reset module 14 can directly reset the gate of the driving transistor T. In some special cases, the reset module 14 can also indirectly reset the second terminal of the driving transistor T. In this case, both the reset module 14 and the compensation module 13 need to be activated simultaneously; or, as shown... Figure 2 and 4 As shown, the reset module 14 is connected to the second terminal of the driving transistor T. At this time, the reset module 14 can directly reset the second terminal of the driving transistor T, or indirectly reset the gate of the driving transistor T. At this time, the reset module 14 and the compensation module 13 need to be turned on at the same time.

[0058] In other embodiments, such as Figure 5Alternatively, as shown in Figure 6, the reset module 14 can also be electrically connected to the gate and second terminal of the driving transistor T, respectively. In this case, the reset module 14 may include a first reset transistor M11 and a second reset transistor M12. The first terminal of the first reset transistor M11 can receive a reset signal Vref, and the second terminal of the first reset transistor M11 can be electrically connected to the gate of the driving transistor T, so that the first reset transistor M11 can directly reset the gate of the driving transistor T. The first terminal of the second reset transistor M12 can receive a reset signal Vref, and the second terminal of the second reset transistor M12 can be electrically connected to the second terminal of the driving transistor T, so that the second reset transistor M12 can directly reset the gate of the driving transistor T. The two transistors are reset simultaneously. When the gate and the second terminal of the driving transistor T are reset at the same time, and the first reset transistor M11 and the second reset transistor M12 are of the same type, the gate of the first reset transistor M11 and the gate of the second reset transistor M12 can receive the same scan signal S1. However, when the gate and the second terminal of the driving transistor T are reset at different times, or when the first reset transistor M11 and the second reset transistor M12 are of different types, the gate of the first reset transistor M11 and the gate of the second reset transistor M12 can receive scan signals S11 and S12 respectively, and the turn-on times of the scan signals S11 and S12 are different for the gate of the first reset transistor M11 and the second reset transistor M12. The reset signal Vref received by the first reset transistor M11 and the second reset transistor M12 can be the same or different; this embodiment of the invention does not specifically limit this.

[0059] For ease of description, unless otherwise specified, the embodiments of the present invention will be illustrated by taking the example of the reset module being connected to the gate of the driving transistor T, and the technical solutions of the embodiments of the present invention will be described by way of example.

[0060] Optional, continue to refer to Figure 1-4In any of the accompanying drawings, the data writing module 12 can be turned on or off under the control of the scan signal S2, and the compensation module 13 can be turned on or off under the control of the scan signal S3. When the scan signal S2 controls the data writing module 12 to turn on, and the scan signal S3 controls the compensation module 13 to start simultaneously, the data signal Vdata can be written to the gate of the driving transistor T in sequence through the data writing module 12, the driving transistor T, and the compensation module 13. When the scan signal S2 controls the data writing module 12 to turn off, the writing of the data signal Vdata can be prevented. At this time, the data writing module 12 may include a data writing transistor M2, the gate of which can receive the scan signal S2, the first terminal of the data writing transistor M2 receives the data signal Vdata, and the second terminal of the data writing transistor M2 is electrically connected to the first terminal of the driving transistor T. The data writing transistor M2 can be either an NMOS or PMOS transistor. When M2 is an NMOS transistor, it is turned on when the scan signal S2 is high and turned off when S2 is low. Conversely, when M2 is a PMOS transistor, it is turned on when the scan signal S2 is low and turned off when S2 is high. This embodiment of the invention does not specifically limit the type of the data writing transistor M2.

[0061] Similarly, the compensation module 13 may include a compensation transistor M3, the gate of which can receive a scan signal S3. The first terminal of the compensation transistor M3 is electrically connected to the second terminal of the driving transistor T at a third node N3, and the second terminal of the compensation transistor M3 is electrically connected to the gate of the driving transistor T at a first node N1. The compensation transistor M3 can be an NMOS or PMOS transistor. When the compensation transistor M3 is an NMOS transistor, it is turned on when the scan signal S3 is high and turned off when the scan signal S3 is low. Conversely, when the compensation transistor M3 is a PMOS transistor, it is turned on when the scan signal S3 is low and turned off when the scan signal S3 is high. This embodiment of the invention does not specifically limit the type of compensation transistor M3.

[0062] Optional, continue to refer to Figure 1-4In any of the accompanying drawings, the pixel circuit 10 may further include a light-emitting control module 15. The light-emitting control module 15 can be turned on or off under the control of the light-emitting control signal EM. The light-emitting control module 15, the driving transistor T, and the light-emitting element 20 are connected in series between the positive power supply PVDD and the negative power supply PVEE. When the light-emitting control signal EM controls the light-emitting control module 15 to be turned on, a current path can be formed between the positive power supply PVDD and the negative power supply PVEE, so that the driving transistor T can provide the driving current it generates to the light-emitting element 20 to drive the light-emitting element 20 to emit light. When the light-emitting control signal EM controls the light-emitting control module 15 to be turned off, the driving transistor T cannot provide the driving current to the light-emitting element 20, and the light-emitting element 20 does not emit light.

[0063] For example, the light-emitting control module 15 may include a first light-emitting control transistor M4 and a second light-emitting control transistor M5. The first terminal of the first light-emitting control transistor M4 is electrically connected to the positive power supply PVDD, the second terminal of the first light-emitting control transistor M4 is electrically connected to the first terminal of the driving transistor T and to the second node N2, the second light-emitting control transistor M5 is electrically connected to the second terminal of the driving transistor T and to the third node N3, and the second light-emitting control transistor M5 is electrically connected to the anode of the light-emitting element 20. When the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are of the same type and are simultaneously turned on or off, the gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 can receive the same light-emitting control signal EM. However, in some special cases, if the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are of different types or if one of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 needs to be in the on state during the non-light-emitting stage of the light-emitting element 20, the gates of the first light-emitting control transistor M4 and the second light-emitting control transistor M5 need to receive different light-emitting control signals. Taking the first light-emitting control transistor M4 and the second light-emitting control transistor M5 as examples where they are of the same type and are simultaneously turned on or off, both the first light-emitting control transistor M4 and the second light-emitting control transistor M5 can be NMOS or PMOS transistors. When both the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are NMOS transistors, when the light-emitting control signal EM is high, both the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are turned on simultaneously, and when the light-emitting control signal EM is low, both the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are turned off simultaneously. Conversely, when both the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are PMOS transistors, when the light-emitting control signal EM is low, both the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are turned on simultaneously, and when the light-emitting control signal EM is high, both the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are turned off simultaneously. This embodiment of the invention does not specifically limit the type of the first light-emitting control transistor M4 and the second light-emitting control transistor M5.

[0064] Optional, continue to refer to Figure 1-4In any of the accompanying drawings, the pixel circuit 10 may further include an initialization module 16, which is connected to the anode of the light-emitting element 20. This initialization module 16 initializes the anode of the light-emitting element 20 before it emits light, clearing the anode potential of the light-emitting element 20 to prevent the anode potential of the light-emitting element 20 in the previous driving cycle from affecting the display brightness of the light-emitting element 20 in the current driving cycle. The initialization module 16 can be turned on or off under the control of the scan signal S4. When the scan signal S4 controls the initialization module 16 to be on, the initialization signal Vini can be written to the anode of the light-emitting element 20 through the initialization module 16 to initialize the anode. When the scan signal S4 controls the initialization module 16 to be off, the initialization module 16 can prevent the writing of the initialization signal Vini. The initialization signal Vini may be the same as or different from the reset signal Vref; this embodiment of the invention does not specifically limit this.

[0065] For example, the initialization module 16 may include an initialization transistor M6. The gate of the initialization transistor M6 can receive a scan signal S4, the first terminal of the initialization transistor M6 receives an initialization signal Vini, and the second terminal of the initialization transistor M6 is electrically connected to the anode of the light-emitting element 20. The initialization transistor M6 can be an NMOS transistor or a PMOS transistor. When the initialization transistor M6 is an NMOS transistor, it is turned on when the scan signal S4 is high and turned off when the scan signal S4 is low. Conversely, when the initialization transistor M6 is a PMOS transistor, it is turned on when the scan signal S4 is low and turned off when the scan signal S4 is high. This embodiment of the invention does not specifically limit the type of the initialization transistor M6.

[0066] In an optional embodiment, the type of initialization transistor M6 can be the same as that of data writing transistor M2. In this case, since data writing transistor M2 controls the writing of data signal Vdata before the light-emitting element 20 emits light, and initialization transistor M6 also initializes the anode of the light-emitting element 20 before the light-emitting element 20 emits light, the scan signal S2 received by the gate of data writing transistor M2 can be multiplexed into the scan signal S4 received by the gate of initialization transistor M6, so that initialization transistor M6 and data writing transistor M2 can be turned on or off simultaneously.

[0067] In addition, the pixel circuit 10 may also include a storage capacitor C1, which is connected between a fixed power supply (e.g., a positive power supply PVDD or a negative power supply PVEE) and the gate of the driving transistor T. The storage capacitor C1 is used to store the potential of the gate (i.e., the first node N1) of the driving transistor T to ensure that the driving transistor T can continuously provide driving current to the light-emitting element 20 during the light-emitting phase.

[0068] For ease of description, the operation of the pixel circuit is illustrated by taking an example where the initialization transistor, data writing transistor, driving transistor, first light-emitting control transistor, and second light-emitting control transistor are all PMOS transistors, and the reset transistor and compensation transistor are both NMOS transistors.

[0069] For example, Figure 7 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to... Figure 1 and Figure 7 As shown, because a certain voltage difference is maintained between the gate and the second electrode of the driving transistor T for a long time during the light-emitting phase of the previous driving cycle, the driving transistor T is in a biased state for a long time. After the light-emitting phase of the previous driving cycle ends and the current driving cycle begins, the light-emitting control signal EM jumps from low level to high level, and both the first light-emitting control transistor M4 and the second light-emitting control transistor M5 are turned off, and the light-emitting element 20 no longer emits light.

[0070] When entering the first stage T11 of the first bias adjustment stage T1 of the current driving cycle, the scan signal S1 remains low, the reset transistor M1 is turned off, and the reset signal Vref is not transmitted to the gate of the driving transistor T. The gate of the driving transistor T still carries the data signal from the previous driving cycle. The scan signal S2 is high, the data writing transistor M2 is turned off, and the data signal Vdata is not transmitted to the first terminal of the driving transistor T. The scan signal S3 jumps from low to high, the compensation transistor M3 is turned on, and the gate of the driving transistor T is connected to its second terminal, that is, the first node N1 and the third node N3 are connected, so that the gate of the driving transistor T is electrically closed. The current flows to its second terminal, making the potential of the second terminal of the driving transistor T approach its gate potential, reducing the potential difference between the gate and the second terminal of the driving transistor T, and making the driving transistor T approach an unbiased state, preparing for subsequent operation. Since the gate potential of the driving transistor T carries the data signal Vdata from the previous driving cycle when the compensation transistor M3 is turned on, when the gate potential of the driving transistor T flows to its second terminal, it can perform targeted bias adjustment based on the data signal provided to the gate of the driving transistor T in the previous driving cycle, so that the driving transistor T can quickly return to an unbiased state at different gray levels. After the first stage T11 of the first bias adjustment stage T1 ends, the scan signal S3 will jump to a low level, causing the compensation transistor M3 to turn off.

[0071] After entering reset phase T2, the scan signal S1 changes from low to high, turning on the reset transistor M1. The reset signal Vref is transmitted to the gate of the driving transistor T to reset the gate of the driving transistor T and the storage capacitor C1, clearing the data signal written to the gate of the driving transistor T in the previous driving cycle. Simultaneously, after writing the reset signal Vref, the gate of the driving transistor T has a lower potential, ensuring that when the data writing transistor M2 provides the data signal Vdata to the first terminal of the driving transistor T, the driving transistor T is in the on state, preparing for the writing of the data signal Vdata. After reset phase T2 ends, the scan signal S1 changes to low, and the reset transistor M1 turns off.

[0072] After entering the data writing stage T3, the scan signal S3 jumps high again, turning on the compensation transistor M3. Simultaneously, the scan signal S2 jumps low, turning on the data writing transistor M2. The data writing transistor M2 controls the data signal Vdata to be written to the first terminal of the driving transistor T, and then sequentially transmitted through the driving transistor T and the compensation transistor M3 to the gate of the driving transistor T. This continues until the voltage difference between the gate and the first terminal of the driving transistor T reaches the threshold voltage Vth of the driving transistor T. At this point, the driving transistor T turns off, ceasing the writing of the data signal Vdata. At this time, the gate potential VN1 of the driving transistor T equals Vdata + Vth. During this stage, the scan signal S4 can also jump low, turning on the initialization transistor M6. The initialization transistor M6 transmits the initialization signal Vini to the anode of the light-emitting element 20 to initialize the anode of the light-emitting element 20. After the data writing stage T3 ends, the scan signal S3 jumps low again, and both the scan signals S2 and S4 jump high, turning off the compensation transistor M3, the data writing transistor M2, and the initialization transistor M6.

[0073] After entering the light-emitting stage T4, the light-emitting control signal EM jumps from high level to low level again, causing both the first light-emitting control transistor M4 and the second light-emitting control transistor M5 to turn on. A current path is formed between the positive power supply PVDD and the negative power supply PVEE. The first terminal potential of the driving transistor T will become PVDD due to the turn-on of the first light-emitting control transistor M4. The gate potential of the driving transistor T is Vdata + Vth. At this time, the driving current Id generated by the driving transistor T is Id = K * (Vdata - PVDD). 2 In other words, the driving current generated by the driving transistor T is independent of its own threshold voltage, thereby preventing the threshold voltage of the driving transistor T from affecting the driving current Id it generates, so that when the driving current Id is provided to the light-emitting element 20, the light-emitting element 20 can emit light accurately. Here, K is a coefficient related to the size and material of the driving transistor T.

[0074] It is understood that the above-described pixel circuit operation process is merely an exemplary process. Under the premise that the bias adjustment of the driving transistor can be specifically adjusted in the first stage of the first bias adjustment stage, the present invention does not specifically limit the operation process of the pixel circuit.

[0075] Optional, continue to refer to Figure 1-4 In any of the attached figures, the first bias adjustment stage also includes a second stage, and the first stage and the second stage are performed sequentially; wherein, in the second stage, the compensation module 13 is turned off and the reset module 14 is turned on.

[0076] Specifically, when the compensation module 13 is turned off and the reset module 14 is turned on, the reset signal Vref can be transmitted to the gate or the second electrode of the driving transistor T to reset the gate or the second electrode of the driving transistor T. When the driving transistor T is a PMOS transistor and the reset module 14 is connected to the gate of the driving transistor T, during the light-emitting stage, the gate potential of the driving transistor T is usually higher than the potential of its second electrode, thus keeping the driving transistor T in a biased state for a long time. In the first stage, the gate potential of the driving transistor T, carrying data signals corresponding to different images, is input to the second electrode of the driving transistor T to adjust the bias of the driving transistor T to different degrees according to different images, so that the potential of the second electrode of the driving transistor T tends to be consistent with its gate potential. After the first stage, the second stage is performed. After the compensation module 13 is turned off and the reset module 14 is turned on, the reset signal Vref can be written to the driving transistor. The gate of transistor T is reset to a lower level after the reset signal Vref is written, because the gate potential carrying the data signal Vdata has been input to the second terminal of the driving transistor T. At this time, the potential of the second terminal of the driving transistor T is also the potential carrying the data signal Vdata. The gate potential of the driving transistor T is lower than the potential of its second terminal. This is the opposite of the case where the gate potential of the driving transistor T is higher than the potential of its second terminal during the light-emitting stage. Therefore, by reversing the bias of the driving transistor, the bias state of the driving transistor T can be further corrected, thereby further improving the display effect.

[0077] For example, consider a scenario where both the reset module 14 and the compensation module 13 are turned on under the control of a high-level scan signal and turned off under the control of a low-level scan signal. Figure 8 This is another timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention. Figure 8 Zhongyu Figure 7 The similarities can be found in the above examples. Figure 7 The description will not be repeated here; only the description of the previous section will be provided. Figure 8 Zhongyu Figure 7 The differences are illustrated by example. Refer to the reference. Figure 1 and Figure 8As shown, after the first stage T11 of the first bias adjustment stage T1, the second stage T12 of the first bias adjustment stage T1 is performed, causing the scan signal S3 to jump to a low level and the scan signal S1 to jump to a high level. This causes the compensation module 13 to be turned off under the control of the low level of the scan signal S3, while the reset module 14 is turned on under the control of the high level of the scan signal S1. The reset signal Vref is transmitted to the gate of the driving transistor T through the turned-on reset module 14, so that the gate of the driving transistor T can have a sufficiently low potential. The gate potential of the driving transistor T will be lower than the potential of its second electrode, thereby achieving the purpose of bias adjustment of the driving transistor T.

[0078] It is understood that when the signals controlling the opening and closing of each module are other, the scanning signals, light emission control signals, and reset signals can be adjusted as appropriate. Provided that the first and second stages of the first bias adjustment stage can be executed sequentially, and the driving transistor can be reverse biased in the second stage, the embodiments of the present invention do not make specific limitations in this regard.

[0079] In an alternative embodiment, the reference continues... Figure 1 and Figure 8 In the first stage T11 of the first bias adjustment phase T1, only the compensation module 13 is turned on, causing the gate potential of the driving transistor T to flow into its second electrode, that is, the potential of the first node N1 flows into the third node N3. Since neither the first node N1 nor the second node N3 is connected to any other electrical signal, this process is similar to the charging and discharging process of a capacitor. This process is relatively slow. If the potential of the gate of the driving transistor T and its second electrode are to be consistent, the first stage T11 of the first bias adjustment phase T1 requires a long time. In the second stage T12 of the first bias adjustment phase T1, only the reset module 14 is turned on, causing the external reset signal Vref to be input to the gate of the driving transistor T. This process is the writing process of the reset signal Vref at a fixed potential, so that the gate of the driving transistor T can be charged to the reset signal Vref in a short time.

[0080] Furthermore, since the display brightness of the display panel is related to the driving current supplied to the light-emitting element and the light-emitting duration of the element, that is, when the driving current is constant, the longer the light-emitting time of the element in one driving cycle, the better it is for improving the display brightness of the display panel. Also, when the driving cycle of the pixel circuit is constant, the longer the light-emitting time of its element, the shorter its non-light-emitting time needs to be. In the first bias adjustment stage T1, the light-emitting element 20 does not emit light; that is, the first bias adjustment stage T1 is the non-light-emitting stage of the light-emitting element 20, and its duration needs to be shortened as much as possible. Thus, while ensuring that both the first stage T11 and the second stage T12 can effectively bias the driving transistor T, the duration of the first stage T11 can be made longer than the duration of the second stage T12 to minimize the duration of the first bias adjustment stage T1, thereby ensuring sufficient display brightness of the display panel and improving its display effect.

[0081] In other embodiments of the present invention, the duration of the first stage may be shorter than that of the second stage. In this case, during the second stage, the reset signal can be fully written to the gate of the driving transistor through the activated reset module to fully reset the gate of the driving transistor, thereby making it suitable for display modes that have very high requirements for reset effect.

[0082] It is understandable that, such as Figure 8 As shown, since the first bias adjustment stage T1 is a non-light-emitting stage, under the premise of a fixed driving cycle of the pixel circuit, when the duration of the non-light-emitting stage is long, the duration of the light-emitting stage T4 will be relatively short. Furthermore, the display brightness of the display panel is related to its light-emitting duration; when the duration of the light-emitting stage T4 is short, the display brightness of the display panel will be relatively low, thus affecting the overall display brightness. For display panels operating at higher frequencies, the driving cycle of their pixel circuits is relatively short. When the duration of their non-light-emitting stage is long, the duration of their light-emitting stage T4 will be limited to a shorter duration, severely affecting the display brightness. Therefore, the second stage T12 can be started simultaneously with the end of the first stage T11, meaning the end time of the first stage T11 and the start time of the second stage T12 are the same moment. This minimizes the duration of the first bias adjustment stage T1, i.e., shortens the duration of the non-light-emitting stage in one driving cycle, thereby relatively increasing the duration of the light-emitting stage T4, which in turn helps improve the display brightness and display effect of the display panel.

[0083] In other embodiments of the present invention Figure 9 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 1 and Figure 9 Since the compensation module 13 is turned on in the first stage T11, the gate of the driving transistor T is connected to its second terminal, and the gate potential of the driving transistor T is input to its second terminal. In the second stage T12, the reset module 14 is turned on, and the reset signal Vref is written to the gate of the driving transistor T, so that the gate of the driving transistor T can have a lower potential. If the turn-on time of the reset module 14 and the compensation module 13 overlaps, the reset signal Vref will be transmitted to the gate of the driving transistor T and also to the second terminal of the driving transistor T at the same time, so that the gate potential of the driving transistor T cannot be lower than the potential of its second terminal, and thus the driving transistor T cannot be biased by reverse biasing. Thus, when the display panel operates at a low frequency and the driving cycle of the pixel circuit is long enough, the duration of the non-light-emitting phase in a driving cycle can be appropriately extended, so that the duration of the first bias adjustment phase T1 in the non-light-emitting phase can be relatively increased. At this time, a first interval phase T01 can be set between the first phase T11 and the second phase T12, so that after the first phase T11 ends, it will not immediately enter the second phase T12, but will go through the first interval T01 before entering the second phase T12, to ensure that the reset module 14 and the compensation module 13 will not be turned on at the same time, and thus the bias adjustment of the driving transistor T can be performed by reverse biasing the driving transistor T.

[0084] Optional, continue to refer to the references Figure 1 and Figure 9 The duration of the first interval stage T01 is less than the duration of the first stage T11; and / or, the duration of the first interval stage T01 is less than the duration of the second stage T12.

[0085] Specifically, since the first interval stage T01 is set to isolate the first stage T11 and the second stage T12, it is sufficient to completely turn off the compensation module 13 during the first interval stage T01, and this process does not require a long time. The first stage T11 is the process of balancing the potential of the gate and its second electrode of the driving transistor T, which requires a certain amount of time to ensure that the potential between the gate and its second electrode of the driving transistor T is consistent. Therefore, the duration of the first interval stage T01 can be less than the total duration of the first stage T11 to minimize the duration of the first bias adjustment stage T1. Similarly, the second stage T12 is the process of writing the reset signal Vref to the gate of the driving transistor T. A certain amount of time is required for the gate of the driving transistor T to be charged to the reset signal Vref. Therefore, the duration of the first interval stage T01 can also be less than the duration of the second stage T12, so as to minimize the total duration of the first bias adjustment stage T1 while ensuring good bias adjustment of the driving transistor T, thereby improving the display effect of the display panel.

[0086] Optionally, based on the above embodiments, refer to Figure 10 or Figure 11 The pixel circuit 10 also includes a bias adjustment module 17, which is connected to the first or second pole of the driving transistor T, and in the first stage, the bias adjustment module 17 is turned off.

[0087] Specifically, the bias adjustment module 17 can provide a bias adjustment signal V0 to the driving transistor T to adjust the bias of the driving transistor T. Since the compensation module 13 is turned on in the first stage of the first bias adjustment phase, the gate potential of the driving transistor T is input to its second electrode to balance the potentials of the gate and the second electrode of the driving transistor T, thus performing targeted bias adjustment on the driving transistor T; at this time, the bias adjustment module 17 does not need to provide a bias adjustment signal to the first or second electrode of the driving transistor T. Therefore, in the first stage, the bias adjustment module 17 is turned off, and only the compensation module 13 needs to be turned on.

[0088] Furthermore, although the compensation module 13 is activated in the first stage of the first bias adjustment phase, enabling targeted bias adjustment of the driving transistor T, the bias adjustment is limited by the gate potential of the driving transistor T. This means that relying solely on the flow of the gate potential of the driving transistor T to its second terminal for bias adjustment is insufficient to meet higher bias adjustment requirements. Therefore, the bias adjustment module 17 can be activated before or after the first stage of the first bias adjustment phase to provide a bias adjustment signal to either the first or second terminal of the driving transistor T, thereby adjusting the bias of the driving transistor T. This improves the situation where insufficient bias adjustment occurs due to relying solely on the flow of the gate potential of the driving transistor T to its second terminal, further enhancing the display uniformity of the display panel and ultimately improving its display effect.

[0089] For example, the bias adjustment module 17 can be turned on or off under the control of the scan signal SV. When the scan signal SV controls the bias adjustment module 17 to be turned on, the bias adjustment module 17 can directly write the bias adjustment signal V0 to the first or second terminal of the driving transistor T. In some special cases, the bias adjustment module 17 can also indirectly write the bias adjustment signal V0 to the gate of the driving transistor T. In this case, the bias adjustment module 17 and the compensation module 13 need to be turned on simultaneously. The bias adjustment module 17 may include a bias adjustment transistor M7. The gate of the bias adjustment transistor M7 can receive the scan signal SV, the first terminal of the bias adjustment transistor M7 receives the bias adjustment signal V0, and the second terminal of the bias adjustment transistor M7 is electrically connected to the first or second terminal of the driving transistor T. In this embodiment of the invention, the bias adjustment transistor M7 can be an NMOS transistor or a PMOS transistor. When the bias adjustment transistor M7 is an NMOS transistor, it is turned on when the scan signal SV is high and turned off when the scan signal SV is low. Conversely, when the bias adjustment transistor M7 is a PMOS transistor, it is turned on when the scan signal SV is low and turned off when the scan signal SV is high. This embodiment of the invention does not specifically limit the type of bias adjustment transistor M7.

[0090] It should be noted that, Figure 10 and Figure 11 The example shown is only exemplarily a PMOS transistor for the driving transistor T. In this case, when the bias adjustment module 17 is connected to the first terminal of the driving transistor T, both the bias adjustment module 17 and the first terminal of the driving transistor T are coupled to the positive power supply PVDD; while when the bias adjustment module 17 is connected to the first terminal of the driving transistor T, both the bias adjustment module 17 and the first terminal of the driving transistor T are coupled to the anode of the light-emitting element 20. In other embodiments of the present invention, such as... Figure 12or Figure 13 The driving transistor T can also be an NMOS transistor. In this case, when the bias adjustment module 17 is connected to the first terminal of the driving transistor T, both the bias adjustment module 17 and the first terminal of the driving transistor T are coupled to the anode of the light-emitting element 20; and when the bias adjustment module 17 is connected to the first terminal of the driving transistor T, both the bias adjustment module 17 and the first terminal of the driving transistor T are coupled to the positive power supply PVDD. This embodiment of the invention does not specifically limit the type of driving transistor T. For ease of description, the following uses a PMOS transistor as an example to illustrate the operation of the pixel circuit in this embodiment.

[0091] For example, the bias adjustment module 17 is turned on under the control of a low-level scan signal SV and turned off under the control of a high-level scan signal SV. Figure 14 This is a timing diagram of the pixel circuit in a display panel provided by another embodiment of the present invention. Figure 14 and Figure 7 For similarities, please refer to the above. Figure 7 The description will not be repeated here; only the description of the previous section will be provided. Figure 14 and Figure 7 The differences are illustrated by example. (Refer to the reference.) Figure 10 and Figure 14Since the bias adjustment signal V0 is typically at a high level, such as 5V, while the data signal Vdata written to the gate of the driving transistor T is typically at a low level, such as 3V when writing to the gate of the driving transistor T in a black screen, the bias adjustment signal V0 cannot be directly written to the gate of the driving transistor T. Therefore, the operation of the pixel circuit 10 may also include a second bias adjustment stage T20 located between the end of the first bias adjustment stage T1 and the beginning of the reset stage T2. In the second bias adjustment stage T20, the bias adjustment module 17 and the compensation module 13 can be turned on simultaneously, so that the bias adjustment signal V0 can be transmitted sequentially to the first terminal, the second terminal, and the gate of the driving transistor T, so that the potentials of the first terminal, the second terminal, and the gate of the driving transistor T tend to be consistent, thereby improving or eliminating the threshold drift phenomenon of the driving transistor T caused by the potential difference between the gate of the driving transistor T and its first and second terminals. Thus, in the first bias adjustment stage T1, by activating the compensation module 13, the potential difference between the gate and the second electrode of the driving transistor T under different screen conditions is balanced, thereby achieving the purpose of preliminary bias adjustment of the driving transistor T. Then, in the second bias adjustment stage T20, a bias adjustment signal V0 with a higher level is used to further bias adjust the driving transistor T, thereby ensuring that the driving transistor T can be fully biased, eliminating or improving the phenomenon that the long-term voltage difference between the gate and the first or second electrode of the driving transistor T affects the light emission accuracy of the light-emitting element 20 driven by the driving transistor T, thereby improving the display effect of the display panel.

[0092] In addition, continue to combine references Figure 10 and Figure 14Because during the data writing stage T3, different data signals are provided to the driving transistor T of the pixel circuit 10 according to the display screen, and the data signal Vdata is not directly written to the gate of the driving transistor T, but is written to the first terminal of the driving transistor T through the data writing module 12, transmitted to its second terminal via the driving transistor T, and then written to the gate of the driving transistor T through the compensation module 13, at the end of the data writing stage, both the first terminal and its second terminal of the driving transistor T carry the data signal Vdata written in the data writing stage T3. Furthermore, the data signal Vdata is different for different gray levels, resulting in different potentials at the end of the data writing stage between the first terminal and its second terminal of the driving transistor T. This will affect the driving current generated in the light-emitting stage T4. At this time, the operation of the pixel circuit 10 may also include a third bias adjustment stage T30 located between the end of the data writing stage T3 and the beginning of the light-emitting stage T4. In the third bias adjustment stage T30, the bias adjustment module 17 is turned on, and the data writing module 12, the compensation module 13, and the reset module 14 are all turned off, so that the bias adjustment signal V0 can be transmitted to the first and / or second terminals of the driving transistor T through the bias adjustment module 17, so that the first and / or second terminals of the driving transistor T change from the data signal Vdata to the bias adjustment signal V0, thereby eliminating or improving the situation where the potentials of the first and second terminals of the driving transistor T are different due to the different data signals written at different gray levels, which affects the driving current generated in the light emission stage T4.

[0093] It should be noted that, Figure 14 The pixel circuit operation process is merely an example of an embodiment of the present invention. In this embodiment, the second bias adjustment stage T20 and / or the third bias adjustment stage T30 may be set as appropriate, provided that the bias adjustment of the driving transistor T can be specifically adjusted. This embodiment of the present invention does not impose any specific limitations on this.

[0094] Optional, see reference Figures 10-13 In any of the accompanying drawings, the first bias adjustment stage further includes a third stage, which is performed sequentially with the first stage, or the first stage and the third stage are performed sequentially; wherein, in the third stage, the bias adjustment module 17 is turned on and the compensation module 13 is turned off.

[0095] For example, with Figure 10 Taking the pixel circuit shown as an example, Figure 15 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 10 and Figure 15Although the gate potential of the driving transistor T in the first stage T11 is input to its second terminal to balance the potential difference between the gate and the second terminal of the driving transistor T, the bias adjustment of the driving transistor T can only be performed within a limited range due to the limited gate potential of the driving transistor T. At this point, before the gate potential of the driving transistor T is input to its second terminal, i.e. before the first stage T11, the third stage T13 can be performed, causing the compensation module 13 to be turned off and the bias adjustment module 17 to be turned on. The bias adjustment signal V0 is sequentially input to the first and second terminals of the driving transistor T through the turned-on bias adjustment module 17, so that the second terminal of the driving transistor T carries the bias adjustment signal V0. After the third stage T13 ends and the first stage T11 begins, the compensation module 13 is turned on and the bias adjustment module 17 is turned off. The gate potential of the driving transistor will flow to its second terminal, so that the second terminal of the driving transistor T carries both the bias adjustment signal V0 and the grayscale-related data signal Vdata. In this way, the bias adjustment of the driving transistor T can be adjusted to different degrees for different grayscales, and the driving transistor T can meet higher bias adjustment requirements, which is beneficial to improving the display effect of the display panel.

[0096] In an alternative embodiment, the reference continues... Figure 10 and Figure 15 Since the first bias adjustment stage T1 is a non-light-emitting stage, under the premise that the driving cycle of the pixel circuit is fixed, when the duration of the non-light-emitting stage is long, the duration of the light-emitting stage T4 will be relatively shortened, thus affecting the overall display brightness of the display panel. Moreover, for display panels operating at higher frequencies, the driving cycle of the pixel circuit 10 is relatively short. In order to ensure that the display panel has sufficient display brightness, the duration of the non-light-emitting stage in a driving cycle can be shortened as much as possible. At this time, the first stage T11 can be started at the same time as the end of the third stage T13, that is, the end time of the third stage T13 and the start time of the first stage T11 are the same time, so as to relatively increase the duration of the light-emitting stage T4, thereby improving the display brightness of the display panel and improving the display effect of the display panel.

[0097] In other alternative embodiments, Figure 16 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 10 and Figure 16 When the third stage T13 and the first stage T11 are performed sequentially, a second interval stage T02 may be included between the end of the third stage T13 and the start of the first stage T11.

[0098] Specifically, when the bias adjustment module 17 and the compensation module 13 are turned on at the same time, the bias adjustment signal V0 will be written to the first, second and third terminals of the driving transistor T at the same time, thereby affecting the gate potential of the driving transistor T. This may cause the data signal Vdata carried by the gate of the driving transistor T to be cleared, thus making it impossible to adjust the bias of the driving transistor T to different degrees according to different gray levels. Thus, when the display panel operates at a low frequency and the driving cycle of the pixel circuit is long enough, the duration of the non-light-emitting phase in one driving cycle can be appropriately increased. That is, the duration of the first bias adjustment phase T1 can be appropriately increased. The first bias adjustment phase T1 has extra time to set the second interval phase T02, and the third phase T13 and the first phase T11 are isolated by the second interval phase T02. That is, after the third phase T13 ends, it will not immediately enter the first phase T11, but will go through the second interval phase T02 before entering the first phase T11. This ensures that the bias adjustment module 17 and the compensation module 13 will not be turned on at the same time, so that the driving transistor T can be targeted for bias adjustment and the high bias adjustment requirements can be met.

[0099] Optional, continue to refer to the references Figure 10 and Figure 16 The duration of the second interval stage T02 is less than the duration of the third stage T13; and / or, the duration of the second interval stage T02 is less than the duration of the first stage T11.

[0100] Specifically, since the second interval stage T02 is set to isolate the third stage T13 and the first stage T11, it is sufficient to completely turn off the bias adjustment module 17 during the second interval stage T02, and this process does not require a long time. The third stage T13 is the process of providing the bias adjustment signal V0 to the first and second terminals of the driving transistor T. To ensure that the bias adjustment signal V0 is fully written to the first and second terminals of the driving transistor T, this process requires a relatively long time. Therefore, the duration of the second interval stage T02 should be shorter than the duration of the third stage T13 to minimize the total duration of the first bias adjustment stage T1. Similarly, the first stage T11 is the process of balancing the potential of the gate and the second terminal of the driving transistor T. This process requires a certain duration to ensure that the potential between the gate and the second terminal of the driving transistor T remains consistent. Therefore, the duration of the second interval stage T02 should be shorter than the duration of the first stage T11 to minimize the duration of the first bias adjustment stage T1.

[0101] In other exemplary embodiments, Figure 17 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 10 and Figure 17In the first stage T11, the gate potential of the driving transistor T is input to its second electrode to balance the potential difference between the gate and the second electrode of the driving transistor T. Although the potential difference between the gate and the second electrode of the driving transistor T can be balanced in the first stage T11, its bias adjustment of the driving transistor T is limited. At this time, after the first stage T11, the third stage T13 can be entered, so that the bias adjustment signal V0 is written to the second electrode of the driving transistor T. The bias adjustment signal V0 is usually a high-level signal, so that after the bias adjustment signal V0 is written to the second electrode of the driving transistor T, the potential of the second electrode of the driving transistor T will be higher than its gate potential. This is the opposite of the case in the light-emitting stage T4, where the gate potential of the driving transistor T is higher than its second electrode potential. This allows the driving transistor T to quickly return to the unbiased state.

[0102] In an alternative embodiment, the reference continues... Figure 10 and Figure 17 Since the first bias adjustment stage T1 is a non-light-emitting stage, under the premise that the driving cycle of the pixel circuit is fixed, when the duration of the non-light-emitting stage is long, the duration of the light-emitting stage T4 will be relatively short, thus affecting the overall display brightness of the display panel. Moreover, for display panels operating at higher frequencies, the driving cycle of the pixel circuit 10 is relatively short. In order to ensure that the display panel has sufficient display brightness, the duration of the non-light-emitting stage in a driving cycle can be shortened as much as possible. At this time, the third stage T13 can be started at the same time as the end of the first stage T11, that is, the end time of the first stage T11 and the start time of the third stage T13 are the same time, so as to relatively increase the duration of the light-emitting stage T4, thereby improving the display brightness of the display panel and improving the display effect of the display panel.

[0103] In other alternative embodiments, Figure 18 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 10 and Figure 18 When the first stage T11 and the third stage T13 are carried out sequentially, a third interval stage T03 may also be included between the end of the first stage T11 and the start of the third stage T13.

[0104] Thus, when the display panel operates at a low frequency and the driving cycle of the pixel circuit is long enough, the duration of the non-light-emitting phase in one driving cycle can be appropriately increased. That is, the duration of the first bias adjustment phase T1 can be appropriately increased. The first bias adjustment phase T1 has extra time to set the third interval phase T03, and the first phase T11 and the third phase T13 are isolated through the third interval phase T03. That is, after the first phase T11 ends, the third phase T13 will not be entered immediately, but will go through the third interval phase T03 before entering the third phase T13, so as to ensure that the first phase T11 and the third phase T13 do not affect each other.

[0105] Optional, continue to refer to the references Figure 10 and Figure 16 The duration of the third interval stage T03 is less than the duration of the first stage T11; and / or, the duration of the third interval stage T03 is less than the duration of the third stage T13.

[0106] Since the third interval stage T03 is set to isolate the first stage T11 and the third stage T13, the duration of the third interval stage T03 does not need to be long. At this time, by making the duration of the third interval stage T03 shorter than the duration of the first stage T11, and / or making the duration of the third interval stage T03 shorter than the duration of the third stage T13, the total duration of the first bias adjustment stage T1 is shortened as much as possible while ensuring that the first stage T11 and the third stage T13 do not affect each other.

[0107] Understandably, in the first stage T11, only the compensation module 13 is turned on, causing the gate potential of the driving transistor T to flow into its second electrode, that is, the potential of the first node N1 flows into the third node N3. Since neither the first node N1 nor the second node N3 is connected to any other electrical signals, this process is similar to the charging and discharging process of a capacitor. This process is relatively slow. If the potential of the gate of the driving transistor T and its second electrode are to be consistent, the first stage T11 of the first bias adjustment stage T1 requires a long time. In the third stage T13, only the bias adjustment module 17 is turned on, causing the external bias adjustment signal V0 to be input to the gate of the driving transistor T. This process is the writing process of the bias adjustment signal V0 with a fixed potential, so that the first electrode and the second electrode of the driving transistor T can be charged to the bias adjustment signal V0 in a short time. Thus, while ensuring that both the first stage T11 and the third stage T13 can effectively adjust the bias of the driving transistor T, the duration of the first stage T11 can be longer than that of the third stage T13, so as to shorten the duration of the first bias adjustment stage T1 as much as possible. This ensures that the display panel has sufficient display brightness, which in turn helps to improve the display effect of the display panel.

[0108] In other embodiments of the present invention, the duration of the first stage may be shorter than that of the third stage. In this case, during the third stage, the bias adjustment signal can be fully written to the first and second poles of the driving transistor through the enabled bias adjustment module, so as to fully adjust the bias of the first and second poles of the driving transistor T, thereby making it suitable for display modes that have very high requirements for bias adjustment effect.

[0109] It is understood that the above description is only illustrative of the cases where the first bias adjustment stage includes only the first stage, or the first bias adjustment stage includes both the first stage and the second stage, or the first bias adjustment stage includes both the first stage and the third stage. In other embodiments of the present invention, the first bias adjustment stage may include the first stage, the second stage, and the third stage simultaneously.

[0110] Optional, continue to refer to Figure 10-13 In any of the accompanying drawings, when the first bias adjustment stage simultaneously includes a first stage, a second stage, and a third stage, the third stage, the first stage, and the second stage can be performed sequentially; wherein, in the first stage, the bias adjustment module 17, the data writing module 12, and the reset module 14 are turned off, and the compensation module 13 is turned on; in the second stage, the compensation module 13 is turned off, and the reset module 14 is turned on; in the third stage, the bias adjustment module 17 is turned on, and the compensation module 13 is turned off; the period from the end of the first stage to the beginning of the second stage includes a first interval stage, and the period from the end of the third stage to the beginning of the first stage includes a second interval stage; and when the time length of the first interval stage is t1 and the time length of the second interval stage is t2, t1≠t2.

[0111] For example, continue with Figure 10 Taking the pixel circuit shown as an example, Figure 19 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 10 and Figure 19The third stage T13 of the first bias adjustment stage T1 is located before the first stage T11, and the first stage T11 is located before the second stage T12. In the third stage T13, the bias adjustment module 17 is turned on, and the bias adjustment signal V0 is sequentially input to the first and second terminals of the driving transistor T through the turned-on bias adjustment module 17, so that the second terminal of the driving transistor T carries the bias adjustment signal V0. After the third stage T13 ends and the first stage T11 begins, the compensation module 13 is turned on, the bias adjustment module 17 is turned off, and the gate potential of the driving transistor flows to its second terminal, so that the second terminal of the driving transistor T carries both the bias adjustment signal V0 and the grayscale-related data signal Vdata. After the first stage T11 ends and the second stage T12 begins, the compensation module 13 is turned off, the reset module 14 is turned on, and the reset signal Vref can be written to the gate of the driving transistor T, so that the gate of the driving transistor is reset to a lower level. At this time, the gate potential of the driving transistor T is lower than the potential of its second terminal, thereby further correcting the bias state of the driving transistor T. Thus, by sequentially performing the third stage T13, the first stage T11, and the second stage T12, higher offset adjustment requirements can be met, thereby further improving the display effect of the display panel.

[0112] Furthermore, by setting a second interval stage T02 between the third stage T13 and the first stage T11, the third stage T13 and the first stage T11 can be made independent of each other. Simultaneously, by setting a first interval stage T01 between the first stage T11 and the second stage T12, the first stage T11 and the second stage T12 can be made independent of each other. This allows for targeted bias adjustment of the driving transistor T, meeting higher bias adjustment requirements. The duration t1 of the first interval stage T01 can be the same as or different from the duration t2 of the second interval stage T02. When the duration t1 of the first interval stage T01 is different from the duration t2 of the second interval stage T02, the duration t1 of the first interval stage T01 and the duration t2 of the second interval stage T02 can be set separately as needed.

[0113] In an optional embodiment, when the time length t1 of the first interval stage T01 is different from the time length t2 of the second interval stage T02, the time length t1 of the first interval stage T01 can be less than the time length t2 of the second interval stage T02, that is, t1 < t2.

[0114] In other optional embodiments of the present invention, when the time length t1 of the first interval stage T01 is different from the time length t2 of the second interval stage T02, the time length t1 of the first interval stage T01 may also be greater than the time length t2 of the second interval stage T02, i.e., t1>t2. The embodiments of the present invention do not specifically limit the relationship between the time length t1 of the first interval stage T01 and the time length t2 of the second interval stage T02.

[0115] It is understood that when the first bias adjustment phase includes a first stage, a second stage, and a third stage, the order of the first stage, the second stage, and the third stage can be interchanged, and the embodiments of the present invention do not specifically limit this.

[0116] In an alternative embodiment, reference continues. Figure 10-13 In any of the accompanying figures, when the first bias adjustment stage simultaneously includes a first stage, a second stage, and a third stage, and in the first stage, the bias adjustment module 17, the data writing module 12, and the reset module 14 are turned off, and the compensation module 13 is turned on; in the second stage, the compensation module 13 is turned off, and the reset module 14 is turned on; and in the third stage, the bias adjustment module 17 is turned on, and the compensation module 13 is turned off, the first stage, the third stage, and the second stage can be performed sequentially; wherein, between the end of the first stage and the beginning of the third stage, a third interval stage may also be included, and between the end of the third stage and the beginning of the second stage, a fourth interval stage may also be included, and when the time length of the third interval stage is t3 and the time length of the fourth interval stage is t4, t3 ≠ t4 can be made.

[0117] Specifically, continue with Figure 10 Taking the pixel circuit shown as an example, Figure 20 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 10 and Figure 20The first bias adjustment stage T11 is located before the third stage T13, and the third stage T13 is located before the second stage T12. In the first stage T11, the compensation module 13 is turned on, and the gate potential of the driving transistor flows to its second electrode to balance the potential difference between the gate and the second electrode of the driving transistor T for different gray levels. This ensures that at the end of the first stage T11, both the gate and the second electrode of the driving transistor T carry data signals. After the first stage T11 ends and the third stage T13 begins, the compensation module 13 is turned off, and the bias adjustment module 17 is turned on. The bias adjustment signal V0 is sequentially input to the first and second electrodes of the driving transistor T through the turned-on bias adjustment module 17, resulting in a higher-level bias adjustment signal V0 at the second electrode of the driving transistor T. At this time, the gate of the driving transistor T still... Without any other signals written, the driving transistor T is at a lower potential carrying the data signal, causing its gate potential to be lower than its second terminal potential. This reverse biases the driving transistor T, allowing it to further approach an unbiased state. After the third stage T13 ends and the second stage T12 begins, the bias adjustment module 17 is turned off, and the reset module 14 is turned on. The reset signal Vref is then written to the gate of the driving transistor T, resetting it to a lower level. At this point, the gate potential of the driving transistor T is further lower than its second terminal potential, further correcting its bias state. Thus, by sequentially performing the first stage T11, the third stage T13, and the second stage T12, higher bias adjustment requirements can be met, thereby further improving the display effect of the display panel.

[0118] Furthermore, by setting a third interval stage T03 between the first stage T11 and the third stage T13, the first stage T11 and the third stage T13 can be made independent of each other. Simultaneously, by setting a fourth interval stage T04 between the third stage T13 and the second stage T12, the third stage T13 and the second stage T12 can be made independent of each other. This allows for targeted bias adjustment of the driving transistor T, meeting higher bias adjustment requirements. The duration t3 of the third interval stage T03 can be the same as or different from the duration t4 of the fourth interval stage T04. When the duration t3 of the third interval stage T03 is different from the duration t4 of the fourth interval stage T04, the duration t3 of the third interval stage T03 can be set to be the same as or different from the duration t4 of the fourth interval stage T04, as needed.

[0119] In an optional embodiment, when the time length t3 of the third interval stage T03 can be different from the time length t4 of the fourth interval stage T04, the time length t3 of the third interval stage T03 can be less than the time length t4 of the fourth interval stage T04, that is, t3 < t4.

[0120] In other optional embodiments of the present invention, when the time length t3 of the third interval stage T03 can be different from the time length t4 of the fourth interval stage T04, the time length t3 of the third interval stage T03 can also be greater than the time length t4 of the fourth interval stage T04, that is, t3>t4. The embodiments of the present invention do not specifically limit the relationship between the time length t3 of the third interval stage T03 and the time length t4 of the fourth interval stage T04.

[0121] Understandably, when the third, first, and second stages proceed sequentially, a first interval stage is set between the first and second stages, and a second interval stage is set between the third and first stages. Similarly, when the first, third, and second stages proceed sequentially, a third interval stage is set between the first and third stages, and a fourth interval stage is set between the third and second stages. In other words, an interval stage is set between any two adjacent stages in the first bias adjustment stage to isolate them from each other. This provides a better bias adjustment effect for display panels operating at lower frequencies. However, for display panels operating at higher frequencies, the time of the first bias adjustment stage needs to be further limited.

[0122] Optional, continue to refer to Figure 10-13 In any of the accompanying figures, the first bias adjustment phase simultaneously includes a first stage, a second stage, and a third stage. In the first stage, the bias adjustment module 17, the data writing module 12, and the reset module 14 are turned off, and the compensation module 13 is turned on. In the second stage, the compensation module 13 is turned off, and the reset module 14 is turned on. In the third stage, when the bias adjustment module 17 is turned on and the compensation module 13 is turned off, at least a portion of the time of the second stage and the third stage overlaps.

[0123] For example, with Figure 10 Taking the pixel circuit shown as an example, Figure 21 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 10 and Figure 21The third stage T13 and the second stage T12 have an overlap time T05. During this overlap time T05, the bias adjustment module 17 and the reset module 14 are turned on simultaneously. That is, the process of the reset module 14 writing a reset signal to the gate of the driving transistor T and the process of the bias adjustment module 17 writing a bias adjustment signal V0 to the first and second poles of the driving transistor T are performed simultaneously. Since the compensation module 13 is in the off state at this time, the gate reset of the driving transistor T and the bias adjustment process of the first and second poles of the driving transistor T do not affect each other. Thus, given that the durations of the third stage T13 and the second stage T12 are fixed, by having the third stage T13 overlap with the second stage T12 at least partially, the total duration of the first bias adjustment stage T1 can be shortened, thereby shortening the duration of the non-light-emitting stage and improving the display brightness of the display panel; or, given that the duration of the first bias adjustment stage T1 is fixed, by having the third stage T13 overlap with the second stage T12 at least partially, the durations of the third stage T13 and / or the second stage T12 can be relatively increased, thereby meeting higher bias adjustment requirements.

[0124] In an optional embodiment, when at least a portion of the time of the second stage T12 overlaps with that of the third stage T13, the start time of the second stage T12 may be the same as or earlier than the start time of the third stage T13; and / or, the end time of the second stage T12 may be the same as or later than the end time of the third stage T13.

[0125] For example, Figure 22 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 10 and Figure 22 The start time of the second stage T12 is the same as the start time of the third stage T13, and the end time of the second stage T12 is later than the end time of the third stage T13. At this time, the third stage T13 begins simultaneously with the entry into the second stage T12, causing the reset signal Vref to be written to the gate of the driving transistor T, while the bias adjustment signal V0 is simultaneously written to the first and second terminals of the driving transistor T. Simultaneously, since the end time of the second stage T12 is later than the end time of the third stage T13, when the bias adjustment module 17 is turned off and stops writing the bias adjustment signal V0 to the first and second terminals of the driving transistor T, the reset module 14 remains on, allowing the reset signal Vref to continue being written. This ensures that the gate of the driving transistor T can be fully reset, making the gate potential of the driving transistor T much lower than its second terminal potential, ensuring that the driving transistor T can quickly return to the unbiased state. Therefore, the duration of the second stage T12 is longer than the duration of the third stage T13.

[0126] In another exemplary embodiment, Figure 23 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 10 and Figure 23 The second stage T12 starts earlier than the third stage T13, and the second stage T12 ends at the same time as the third stage T13. Upon entering the second stage T12, the reset module 14 first writes the reset signal Vref to the gate of the driving transistor T to reset the gate of the driving transistor T. After a period of reset, it enters the third stage T13. At this time, the bias adjustment module 17 and the reset module 14 are simultaneously activated, allowing the reset signal Vref to continue being fed into the gate of the driving transistor T. Simultaneously, the bias adjustment signal V0 is written into the first and second terminals of the driving transistor T. The third stage T13 ends simultaneously with the end of the second stage T12, and the writing of signals to the gate, first terminal, and second terminal of the driving transistor T ceases. Thus, the duration of the second stage T12 is still longer than the duration of the third stage T13.

[0127] In yet another exemplary embodiment, Figure 24 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 10 and Figure 24 The second stage T12 starts earlier than the third stage T13, and ends later than the third stage T13. Upon entering the second stage T12, the reset module 14 first writes the reset signal Vref to the gate of the driving transistor T to reset the gate. After a period of reset, it enters the third stage T13. At this time, the bias adjustment module 17 and the reset module 14 are simultaneously activated, allowing the reset signal Vref to continue flowing into the gate of the driving transistor T. Simultaneously, the bias adjustment signal V0 is written to the first and second terminals of the driving transistor T. When the third stage T13 ends, the second stage T12 continues; that is, after the bias adjustment module 17 is turned off, the reset module 14 remains on. After the second stage T12 ends, the reset module 14 is turned off and no longer provides the reset signal Vref to the driving transistor. Thus, the duration of the second stage T12 is also longer than the duration of the third stage T13.

[0128] It is understood that the above description is only exemplarily provided for the case where the duration of the second stage T12 is greater than the duration of the third stage T13. In the embodiments of the present invention, the duration of the second stage T12 may also be equal to the duration of the third stage T13. In this case, the start time of the second stage T12 is the same as the start time of the third stage T13, and the end time of the second stage T12 is the same as the end time of the third stage T13.

[0129] In other embodiments of the present invention, the start time of the second stage may be earlier than the start time of the third stage, and the end time of the second stage may also be earlier than the end time of the third stage.

[0130] For example, continue with Figure 10 Taking the pixel circuit shown as an example, Figure 25 This is a timing diagram of the pixel circuit in a display panel provided by an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 10 and Figure 25 When the start time of the second stage T12 is earlier than the start time of the third stage T13, and the end time of the second stage T12 is earlier than the end time of the third stage T13, after entering the second stage T12, the reset module 14 is turned on and the bias adjustment module 17 is turned off. The reset module 14 will first write the reset signal Vref to the gate of the driving transistor T to reset the gate of the driving transistor T. After a period of reset, the third stage T13 will be entered. At this time, the bias adjustment module 17 and the reset module 14 are turned on simultaneously, so that the reset signal Vref continues to be charged to the gate of the driving transistor T. At the same time, the bias adjustment signal V0 is written to the first and second terminals of the driving transistor T. After the bias adjustment module 17 and the reset module 14 are turned on synchronously for a period of time, the second stage T12 ends and the third stage T13 continues. At this time, the reset module 14 is turned off and the bias adjustment module 17 remains on, continuing to provide the bias adjustment signal V0 to the first and second terminals of the driving transistor T until the third grounding T13 ends, at which point the bias adjustment module 17 is turned off.

[0131] It should be noted that the above is only based on Figure 10 The example illustrates the operation of the pixel circuit under different conditions. When the pixel circuit is in other conditions, the scanning signals, light emission control signals, bias adjustment signals, data signals and reset signals can be adaptively adjusted to achieve the same beneficial effects. These will not be elaborated on here.

[0132] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in the embodiments of the present invention. Therefore, this display device possesses the technical features of the display panel and its driving method provided in the embodiments of the present invention, and can achieve the beneficial effects of the display panel provided in the embodiments of the present invention. Similarities can be found in the above description of the display panel provided in the embodiments of the present invention, and will not be repeated here.

[0133] For example, Figure 26 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 26As shown, the display device 200 includes the display panel 100 provided in this embodiment of the invention. The display device 200 provided in this embodiment of the invention can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this embodiment of the invention does not make any special limitations on these categories.

[0134] It should be understood that the working process of the various forms of pixel circuits shown above can be used to reorder, add, or delete stages. For example, the stages in the working process of the pixel circuits described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is made herein.

[0135] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module, a data writing module, a compensation module, a reset module, and a bias adjustment module; The driving module includes a driving transistor; The data writing module is connected to the first electrode of the driving transistor; The compensation module is connected between the gate and the second electrode of the driving transistor; The reset module is connected to the gate or the second electrode of the driving transistor; The bias adjustment module is connected to either the first or second terminal of the driving transistor; wherein... The operation of the pixel circuit includes a first bias adjustment stage, which includes a first stage and a third stage. In the first stage, the data writing module and the reset module are turned off, and the compensation module is turned on; in the third stage, the bias adjustment module is turned on, and the compensation module is turned off.

2. The display panel according to claim 1, characterized in that, The duration of the first stage is longer than the duration of the third stage.

3. The display panel according to claim 1, characterized in that, The duration of the first stage is shorter than the duration of the third stage.

4. The display panel according to claim 1, characterized in that, The first phase begins simultaneously with the end of the third phase; or... The third phase begins at the same time the first phase ends.

5. The display panel according to claim 1, characterized in that, A third interval phase is included between the first phase and the third phase.

6. The display panel according to claim 5, characterized in that, The period between the end of the first phase and the start of the third phase includes a third interval phase.

7. The display panel according to claim 5, characterized in that, The duration of the third interval phase is less than the duration of the first phase; and / or, The duration of the third interval phase is less than the duration of the third phase.

8. The display panel according to claim 1, characterized in that, The first bias adjustment stage also includes a second stage, in which the data writing module and the compensation module are turned off, and the reset module is turned on.

9. The display panel according to claim 8, characterized in that... A fourth interval phase is included between the second stage and the third stage; a third interval phase is included between the first stage and the third stage; wherein... The duration of the third interval is t3, and the duration of the fourth interval is t4, where t3 ≠ t4.

10. The display panel according to claim 9, characterized in that, t3 < t4.

11. The display panel according to claim 8, characterized in that, The second phase and the third phase overlap in time at least partially.

12. The display panel according to claim 11, characterized in that, The start time of the second stage is the same as or earlier than the start time of the third stage; and / or, The end time of the second stage is the same as or later than the end time of the third stage.

13. The display panel according to claim 11, characterized in that, The second phase starts earlier than the third phase, and... The second stage ends earlier than the third stage.

14. The display panel according to claim 1, characterized in that, The compensation module includes a compensation transistor, the first terminal of which is electrically connected to the second terminal of the driving transistor, and the second terminal of which is electrically connected to the gate of the driving transistor.

15. The display panel according to claim 14, characterized in that, The gate of the compensation transistor receives a scan signal; Upon entering the first stage, the scanning signal transitions from a low level to a high level.

16. The display panel according to claim 14, characterized in that, The compensation transistor is an NMOS transistor or a PMOS transistor.

17. The display panel according to claim 1, characterized in that, The reset module includes a reset transistor, the first terminal of which receives a reset signal, and the second terminal of which is electrically connected to the gate or second terminal of the driving transistor.

18. The display panel according to claim 17, characterized in that, The reset transistor is an NMOS transistor or a PMOS transistor.

19. The display panel according to claim 1, characterized in that, The data writing module includes a data writing transistor, the first terminal of which receives a data signal, and the second terminal of which is electrically connected to the first terminal of the driving transistor.

20. The display panel according to claim 1, characterized in that, The driving transistor is an NMOS transistor or a PMOS transistor.

21. The display panel according to claim 1, characterized in that, The bias adjustment module includes a bias adjustment transistor, the first terminal of which receives a bias adjustment signal, and the second terminal of which is electrically connected to the first or second terminal of the driving transistor.

22. A display device, characterized in that, Includes the display panel as described in any one of claims 1-21.

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