Controllable direct-current fault current limiter based on adjustment control voltage, method and medium

Abstract

The invention relates to a controllable direct-current fault current limiter based on adjustment of control voltage, a method and a medium, the current limiter comprises a magnetic structure, the magnetic structure is provided with a main winding and a secondary winding, and the number of turns of the main winding is smaller than that of the secondary winding; the main winding is connected with a direct-current power grid, the secondary winding is connected with an adjustable control voltage source, and a switch is arranged at any end, connected with the secondary winding, of the adjustable control voltage source; the magnetic structure is configured to have a magnetic circuit saturated when a fault does not occur and a magnetic circuit desaturated when the fault occurs; the fault detector is used for detecting whether a direct-current power grid has a direct-current fault or not and connecting the adjustable control voltage source to the circuit when the direct-current fault occurs; the voltage intensity of the adjustable control voltage source is adjustable. According to the current limiter disclosed by the invention, the performance of other units such as a direct current circuit breaker (DCCB) is improved, the power loss of a system in a fault state is reduced, and the design and manufacturing processes of an iron core structure are simplified, so that the safety and reliability of a whole direct current network are improved.

Description

Technical Field

[0001] The present disclosure relates to a controllable DC fault current limiter, a method and a medium based on adjusting a control voltage, and relates to the technical field of DC fault current limiters. Background Art

[0002] Compared with traditional AC power grids, flexible DC power grids have higher power supply quality and better control capabilities, and can effectively solve various problems in power transmission. However, DC power grids also face the problem of rapid rise in fault current during operation, which poses a serious threat to the safety and reliability of equipment.

[0003] In a DC power grid, once a short circuit occurs, the fault current rises very quickly and may reach a peak value in just a few milliseconds. This fast-rising fault current will not only damage key equipment in the power grid, but may also cause the failure of the entire system. Therefore, how to effectively limit the fault current and ensure the safe operation of the DC power grid has become a hot topic in current research.

[0004] To solve this problem, researchers have proposed a variety of technical solutions, the most common of which include DC fault current limiters (FCLs) and DC circuit breakers. FCLs mainly suppress the rising speed of fault current by increasing the inductance or resistance of the line, thereby protecting grid equipment. DC circuit breakers achieve protection by quickly cutting off the fault current, usually requiring the breaking to be completed within 5-6 milliseconds to avoid damage to the system caused by the fault current.

[0005] Existing DC circuit breaker technologies, such as hybrid DCCB, have been applied in some projects, but their development and cost remain a challenge. According to research, the cost of DCCB accounts for almost two-thirds of the cost of the entire DC grid system, which affects the economic viability of the DC grid. In addition, the effectiveness and reliability of existing DCCBs under high fault current conditions also need to be verified through actual engineering.

[0006] In terms of fault current limiters, new technologies such as superconducting fault current limiters (SCFCLs) and active fault current limiters (AFLs) are also developing. Superconducting current limiters use the characteristics of superconducting materials to quickly change to a high resistance state when a fault occurs, thereby limiting the flow of current. Active fault current limiters control power electronic devices to force the fault current to flow into a branch with higher inductance to achieve fault current limitation.

[0007] In addition, recent studies have proposed a new type of device that combines a fault current limiter and a circuit breaker, aiming to have both fault current limiting and breaking functions. This new device can give full play to the advantages of both and improve the economy and reliability of the system. By building a physical prototype in the laboratory and performing digital simulations, the researchers verified the effectiveness of the device in fault current suppression.

[0008] Existing DC network fault current limiting technology still has many shortcomings, which limit its effectiveness and reliability in practical applications. First, it is difficult for existing DC circuit breakers to quickly cut off the current when the fault current rises. Since DC fault current lacks a natural zero point, the current zero point must be created by artificial means, which makes the design and implementation of circuit breakers complicated and difficult. In addition, the response speed and reliability of existing DCCBs under high fault current conditions still need to be further verified, especially in multi-terminal high-voltage DC transmission systems, where the rapid rise of fault current has a huge impact on the equipment and may cause the system to shut down.

[0009] Secondly, although the existing fault current limiter can limit the fault current to a certain extent, its control ability and response speed are still insufficient. Existing FCL technology often relies on mechanical switches or power electronic devices, and the response speed and accuracy of these devices in the face of sudden faults cannot meet the needs of high-voltage DC grids. In addition, many FCLs are expensive, and in high-power DC grids, FCLs alone cannot completely isolate faults, which limits their scope of application.

[0010] In addition, key equipment in the flexible DC grid, such as DC circuit breakers and DC transformers, have a high failure rate, which has a negative impact on the reliability of the entire system. Although technology is constantly improving, the reliability of the DC distribution network is still lower than that of the AC distribution network due to the manufacturing level and design complexity of existing equipment. At the same time, the existing technical solutions also have problems in terms of cost. The cost of DCCB often accounts for a large part of the cost of the entire DC grid system, which affects the economic feasibility of the DC grid and limits its promotion and application. Summary of the invention

[0011] In order to overcome the above problems, the present disclosure provides a controllable DC fault current limiter, method and medium based on adjusting the control voltage.

[0012] The technical solution of the present disclosure is as follows:

[0013] In a first aspect, there is provided a controllable DC fault current limiter based on adjusting a control voltage, comprising a magnetic structure;

[0014] The magnetic structure is provided with a main winding and a secondary winding, and the number of turns of the main winding is less than the number of turns of the secondary winding;

[0015] The main winding is connected to a DC power grid, the secondary winding is connected to an adjustable control voltage source, and a switch is provided on any end of the adjustable control voltage source connected to the secondary winding;

[0016] The magnetic structure is configured such that the magnetic circuit is saturated when no fault occurs and the magnetic circuit is desaturated when a fault occurs;

[0017] a fault detector, the fault being used to detect whether a DC grid has a DC fault, and connecting the adjustable control voltage source to the circuit when a DC fault occurs;

[0018] The voltage intensity of the adjustable control voltage source is adjustable.

[0019] Furthermore, the speed of impedance increase and the time of connecting to the system are controlled by adjusting the coil density of the main winding, specifically:

[0020] By reducing the coil density of the main winding, the speed of impedance increase is accelerated and the time of connection to the system is shortened;

[0021] By increasing the coil density of the main winding, the rate of impedance increase is reduced and the connection time to the system is extended.

[0022] Furthermore, the reduction time of the fault current is controlled by adjusting the voltage intensity of the adjustable control voltage source, specifically:

[0023] Shortening the reduction time of the fault current by increasing the voltage intensity of the adjustable control voltage source;

[0024] The reduction time of the fault current is shortened by increasing the voltage intensity of the adjustable control voltage source.

[0025] In a second aspect, a controllable DC fault current limiting method based on adjusting a control voltage is provided, wherein the controllable DC fault current limiter based on adjusting a control voltage is connected to a flexible DC grid to perform fault current limiting on the flexible DC grid.

[0026] Furthermore, a current change rate model of the flexible DC grid after connecting to the controllable DC fault current limiter is constructed:

[0027]

[0028] Among them, L 11 is the network side inductance, i 1 for, is the network side self-inductance voltage, L 12 For 2 for, Measure the mutual inductance voltage of the network, V Network is the flexible DC circuit voltage, V Loadis the load voltage;

[0029] The time for the fault current to decrease is regulated by adjusting the voltage intensity of the adjustable control voltage source or the coil density of the main winding according to the above model, or adjusting both the voltage intensity of the adjustable control voltage source and the coil density of the main winding.

[0030] Furthermore, the speed of impedance increase and the time of connecting to the system are controlled by adjusting the coil density of the main winding, specifically:

[0031] By reducing the coil density of the main winding, the speed of impedance increase is accelerated and the time of connection to the system is shortened;

[0032] By increasing the coil density of the main winding, the rate of impedance increase is reduced and the connection time to the system is extended.

[0033] Furthermore, the reduction time of the fault current is controlled by adjusting the voltage intensity of the adjustable control voltage source, specifically:

[0034] Shortening the reduction time of the fault current by increasing the voltage intensity of the adjustable control voltage source;

[0035] The reduction time of the fault current is shortened by increasing the voltage intensity of the adjustable control voltage source.

[0036] In a third aspect, a computer scale storage medium is provided, and when a computer program stored thereon is executed, the controllable DC fault current limiting method based on adjusting the control voltage as described in the second aspect is implemented to achieve DC fault current limiting for a flexible DC power grid.

[0037] The present disclosure has the following beneficial effects:

[0038] Controllability: In the PMFCL (permanent magnet fault current limiter) structure, the rate of increase of the fault current is used to desaturate the core, and the time for the inductance increase is uncontrollable. In the CMFCL structure, the time for the current to decrease can be adjusted by controlling the voltage and the number of turns of the winding.

[0039] Structural complexity: CMFCL does not need to change the main structure of the core, reducing structural complexity.

[0040] Power loss: CMFCL adjusts the current reduction time by increasing the control voltage without changing the number of winding turns, only by changing the coil winding density, thus reducing the power loss under fault conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Schematic diagram of a controllable DC fault current limiter according to an embodiment of the present disclosure.

[0042] Figure 2This is a working circuit diagram of a controllable DC fault current limiter connected to a DC circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components.

[0045] The present disclosure is described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] First, refer to Figure 1-2 , a controllable DC fault current limiter based on adjusting a control voltage is provided, comprising a magnetic structure;

[0047] The magnetic structure is provided with a main winding and a secondary winding, and the number of turns of the main winding is less than the number of turns of the secondary winding;

[0048] The main winding is connected to a DC power grid, the secondary winding is connected to an adjustable control voltage source, and a switch is provided on any end of the adjustable control voltage source connected to the secondary winding;

[0049] The magnetic structure is configured such that the magnetic circuit is saturated when no fault occurs and the magnetic circuit is desaturated when a fault occurs;

[0050] a fault detector, the fault being used to detect whether a DC grid has a DC fault, and connecting the adjustable control voltage source to the circuit when a DC fault occurs;

[0051] The voltage intensity of the adjustable control voltage source is adjustable.

[0052] When no fault occurs, it can be seen from the following formula that due to the reduction in magnetic permeability, the impedance is reduced, thereby reducing the inductance of the line.

[0053] When no fault occurs, the magnetic flux of the winding is enhanced, overcoming the magnetic flux caused by the permanent magnet, and the operating point moves. As can be seen from the following formula, the inductance of the line increases significantly, resulting in an increase in impedance and an instantaneous decrease in current, making it easier for the DC circuit breaker (DCCB) to perform the disconnection operation.

[0054]

[0055] Among them, L 11 is the line inductance, μ 0 is the vacuum permeability, μ r is the relative magnetic permeability, N 1 The number of turns of the main winding, A e is the cross-sectional area of ​​the main winding coil, l e is the length of the main winding coil, R is the resistance value, ρ is the resistivity, l is the conductor length, and A is the cross-sectional area of ​​the conductor;

[0056] In one embodiment of the present disclosure, the speed of impedance increase and the time of connecting to the system are controlled by adjusting the coil density of the main winding, specifically:

[0057] By reducing the coil density of the main winding, the speed of impedance increase is accelerated and the time of connection to the system is shortened;

[0058] By increasing the coil density of the main winding, the rate of impedance increase is reduced and the connection time to the system is extended.

[0059] In one embodiment of the present disclosure, the reduction time of the fault current is controlled by adjusting the voltage intensity of the adjustable control voltage source, specifically:

[0060] Shortening the reduction time of the fault current by increasing the voltage intensity of the adjustable control voltage source;

[0061] The reduction time of the fault current is shortened by increasing the voltage intensity of the adjustable control voltage source.

[0062] In a second aspect, a controllable DC fault current limiting method based on adjusting a control voltage is provided, wherein the controllable DC fault current limiter based on adjusting a control voltage is connected to a flexible DC grid to perform fault current limiting on the flexible DC grid.

[0063] In one embodiment of the present disclosure, a current change rate model of a flexible DC grid after connecting to a controllable DC fault current limiter is constructed:

[0064]

[0065] Among them, L 11 is the network side inductance, i 1 for, is the network side self-inductance voltage, L 12 For 2 for, Measure the mutual inductance voltage of the network, V Network is the flexible DC circuit voltage, V Load is the load voltage;

[0066] The time for the fault current to decrease is regulated by adjusting the voltage intensity of the adjustable control voltage source or the coil density of the main winding according to the above model, or adjusting both the voltage intensity of the adjustable control voltage source and the coil density of the main winding.

[0067] The inductance of CMFCL seen from the network side in the model is its mutual inductance. When a fault occurs, the magnitude of the control side winding flux is higher than that of the network side, so the inductance increases. The right side of the above formula decreases, resulting in a decrease in the fault current.

[0068] The performance of the CMFCL (DC Fault Current Limiter) can be improved by changing the network side coil winding density. Specifically, the network side coil winding density is changed by changing the length of the network side coil. The winding density refers to the ratio of the number of wires in the coil to the cross-sectional area of ​​the coil. Increasing the coil length means that the wires are distributed over a longer coil length with a fixed number of wires, resulting in a decrease in the winding density.

[0069] As the winding density decreases (i.e. the coil length increases), the fault to rated state impedance ratio increases. This is attributed to the change in the flux linkage of the coil under different core conditions.

[0070] In the rated state, the core is saturated and the coupling between the windings is weak; in the fault state, the core is desaturated, the magnetic interaction between the windings and the core is enhanced, and the coupling between the windings increases, resulting in an increase in the fault state impedance.

[0071] Reducing the winding density can increase the impedance ratio of the device, thereby improving the performance of the CMFCL.

[0072] Winding density is an important parameter in CMFCL design, and the performance of CMFCL can be changed by changing the winding density in the network-side coil. For a deeply saturated core, lower winding density leads to a decrease in the mutual inductance between windings, while when the core is desaturated, the mutual inductance increases. This shows that the mutual inductance of the windings can be used as an additional degree of freedom in the design of CMFCL, and this design parameter can be changed by changing the winding density in the network-side coil.

[0073] In one embodiment of the present disclosure, the speed of impedance increase and the time of connecting to the system are controlled by adjusting the coil density of the main winding, specifically:

[0074] By reducing the coil density of the main winding, the speed of impedance increase is accelerated and the time of connection to the system is shortened;

[0075] By increasing the coil density of the main winding, the rate of impedance increase is reduced and the connection time to the system is extended.

[0076] In one embodiment of the present disclosure, the reduction time of the fault current is controlled by adjusting the voltage intensity of the adjustable control voltage source, specifically:

[0077] Shortening the reduction time of the fault current by increasing the voltage intensity of the adjustable control voltage source;

[0078] The reduction time of the fault current is shortened by increasing the voltage intensity of the adjustable control voltage source.

[0079] In a third aspect, a computer scale storage medium is provided, and when a computer program stored thereon is executed, the controllable DC fault current limiting method based on adjusting the control voltage as described in the second aspect is implemented to achieve DC fault current limiting for a flexible DC power grid.

[0080] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0081] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

[0082] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0083] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.

[0084] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0085] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

[0086] There are a few points to note about this disclosure:

[0087] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0088] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0089] The above descriptions are merely embodiments of the present disclosure and are not intended to limit the patent scope of the present disclosure. Any equivalent structures made using the contents of the present disclosure and the drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present disclosure.

Claims

1. A controllable DC fault current limiter based on adjusting the control voltage, characterized in that: including a magnetic structure; The magnetic structure is provided with a main winding and a secondary winding, and the number of turns of the main winding is less than the number of turns of the secondary winding; The main winding is connected to a DC power grid, the secondary winding is connected to an adjustable control voltage source, and a switch is provided on any end of the adjustable control voltage source connected to the secondary winding; The magnetic structure is configured such that the magnetic circuit is saturated when no fault occurs and the magnetic circuit is desaturated when a fault occurs; a fault detector, the fault being used to detect whether a DC grid has a DC fault, and connecting the adjustable control voltage source to the circuit when a DC fault occurs; The voltage intensity of the adjustable control voltage source is adjustable.

2. The controllable DC fault current limiter based on adjusting the control voltage according to claim 1, characterized in that: The speed of impedance increase and the time to connect to the system are controlled by adjusting the coil density of the main winding, specifically: By reducing the coil density of the main winding, the speed of impedance increase is accelerated and the time of connection to the system is shortened; By increasing the coil density of the main winding, the rate of impedance increase is reduced and the connection time to the system is extended.

3. The controllable DC fault current limiter based on adjusting the control voltage according to claim 1, characterized in that: The reduction time of the fault current is controlled by adjusting the voltage intensity of the adjustable control voltage source, specifically: Shortening the reduction time of the fault current by increasing the voltage intensity of the adjustable control voltage source; The reduction time of the fault current is shortened by increasing the voltage intensity of the adjustable control voltage source.

4. A controllable DC fault current limiting method based on adjusting the control voltage, characterized in that: The controllable DC fault current limiter based on adjusting the control voltage described in claim 1 is connected to a flexible DC power grid to perform fault current limiting on the flexible DC power grid.

5. The controllable DC fault current limiting method based on adjusting the control voltage according to claim 4, characterized in that: Construct a current change rate model of the flexible DC grid after connecting to the controllable DC fault current limiter: Among them, l 11 is the network side inductance, i1 is, is the network side self-inductance voltage, l 12 is, i2 is, Measure the mutual inductance voltage of the network, V Network is the flexible DC circuit voltage, V Load is the load voltage; The time for the fault current to decrease is regulated by adjusting the voltage intensity of the adjustable control voltage source or the coil density of the main winding according to the above model, or adjusting both the voltage intensity of the adjustable control voltage source and the coil density of the main winding.

6. The controllable DC fault current limiting method based on adjusting the control voltage according to claim 5, characterized in that: The speed of impedance increase and the time to connect to the system are controlled by adjusting the coil density of the main winding, specifically: By reducing the coil density of the main winding, the speed of impedance increase is accelerated and the time of connection to the system is shortened; By increasing the coil density of the main winding, the rate of impedance increase is reduced and the connection time to the system is extended.

7. The controllable DC fault current limiting method based on adjusting the control voltage according to claim 6, characterized in that: The reduction time of the fault current is controlled by adjusting the voltage intensity of the adjustable control voltage source, specifically: Shortening the reduction time of the fault current by increasing the voltage intensity of the adjustable control voltage source; The reduction time of the fault current is shortened by increasing the voltage intensity of the adjustable control voltage source.

8. A computer scale storage medium, characterized in that: When the computer program stored thereon is executed, the controllable DC fault current limiting method based on adjusting the control voltage as described in any one of claims 4 to 7 is implemented to achieve DC fault current limiting for the flexible DC power grid.

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