Hall disc sensitivity test circuit applied to wheel speed sensor and method thereof

Abstract

The invention discloses a Hall disc sensitivity test circuit applied to a wheel speed sensor and a method thereof, the Hall disc sensitivity test circuit comprises a Hall disc HallR, a Hall disc HallC, a Hall disc HallL, a first signal link, a second signal link, a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6 and a switch S7, differential output signals of the Hall disc HallR and the Hall disc HallC are input to the first signal link, and differential output signals of the Hall disc HallL are input to the second signal link. Differential output signals of the Hall disc HallC and the Hall disc HallL are input to the second signal link, two ends of the switches S1, S2 and S3 are respectively connected with differential output signals of the Hall discs HallR, HallC and HallL, and the switches S4, S5, S6 and S7 are connected with detection signals VPR, VNR, VPL and VNL. The improvement cost is low, and the test method is simple.

Description

Technical Field

[0001] The present invention relates to a Hall plate sensitivity test circuit and method thereof, in particular to a Hall plate sensitivity test circuit and method thereof applied to a wheel speed sensor, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] As the core component of the wheel speed sensor chip, the Hall disk converts the external magnetic signal into an electrical signal that is easy for the chip to process through the Hall effect, thereby realizing the detection of wheel speed and direction. However, the sensitivity of the Hall disk is sensitive to the process temperature, resulting in large differences in the voltage signal output by the Hall disk under the same magnetic signal, which affects the performance of the wheel speed sensor chip. In order to ensure the performance of the wheel speed sensor chip, a Hall disk sensitivity compensation circuit is designed inside the chip to avoid affecting the performance of the wheel speed sensor chip due to the decrease in the sensitivity of the Hall disk. Therefore, in order to accurately compensate for the sensitivity of the Hall disk, it is necessary to accurately test the sensitivity of the Hall disk to ensure the performance of the wheel speed sensor chip.

[0003] The signal processing circuits traditionally used in wheel speed sensors are as follows: Figure 2As shown in the figure, the entire wheel speed sensor chip includes three Hall plates, Hall_R, Hall_C, and Hall_L, and two symmetrical left and right signal links. Each signal link includes a differential differential amplifier DDA, a programmable gain amplifier PGA, an analog-to-digital converter ADC, a digital processing unit Digital, and a current rudder digital-to-analog converter IDAC for calibration, and a current signal output module IOUT. The three Hall plates convert the external sinusoidal magnetic signal into an electrical signal that is easy for the chip to process. The electrical signals sensed by Hall_R and Hall_C are input into the differential differential amplifier DDA_R of the right signal link. The electrical signals sensed by Hall_R and Hall_C are subtracted to eliminate most of the offset and perform preliminary amplification. The signal amplified by the differential differential amplifier DDA_R is input into the programmable gain amplifier PGA_R and amplified again. The output signal of the programmable gain amplifier PGA_R is input into the analog-to-digital converter ADC_R for quantization, and a digital code stream that is easy for the digital processing unit Digital to process is obtained. The digital processing unit Digital performs algorithm operations on it to calculate the corresponding offset information, amplitude information, and speed information. The offset information is calculated to obtain the corresponding calibration digital code, which is input into the current steering digital-to-analog converter IDAC_R, and together with the programmable gain amplifier PGA_R, the offset is calibrated. The amplitude information is calculated to obtain the corresponding gain adjustment code, which is input into the programmable gain amplifier PGA_R to adjust the gain of the programmable gain amplifier PGA_R and amplify the input signal to a suitable size. The speed information is used to control the current signal output module IOUT, and the speed information is transmitted to the outside world in the form of current through encoding. Similarly, the electrical signals sensed by Hall_C and Hall_L are input into the signal link on the left, and similar operations are performed. The digital processing unit Digital calculates the information of the two channels to obtain the direction information, and also transmits the direction information to the outside world in the form of current through encoding.

[0004] The sensitivity of the three Hall disks, Hall_R, Hall_C, and Hall_L, varies under different temperatures and process conditions, which has a great impact on the performance of the wheel speed sensor chip. Therefore, the sensitivity of the Hall disk needs to be compensated to avoid large differences in the sensitivity of the Hall disks of different chips. However, in the circuit of the prior art, the electrical signals sensed by Hall_R, Hall_C, and Hall_L are equal in size and phase, and the output signals of Hall_R and Hall_C are input to the differential amplifier DDA_R and the output is zero after subtraction. The output signals of Hall_C and Hall_L are input to the differential amplifier DDA_L and the output is zero after subtraction. The sensitivity of Hall_R, Hall_C, and Hall_L cannot be tested. Therefore, the prior art cannot compensate for the sensitivity of the Hall disk, which has a great impact on the performance of the wheel speed sensor chip. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a Hall plate sensitivity test circuit and method applied to a wheel speed sensor, so as to realize the test of the Hall plate sensitivity of the wheel speed sensor.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A Hall plate sensitivity test circuit for a wheel speed sensor comprises a Hall plate Hall_R, a Hall plate Hall_C, a Hall plate Hall_L, a first signal chain, a second signal chain, a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6 and a switch S7, wherein the differential output signal of the Hall plate Hall_R and the Hall plate Hall_C is input to the first signal chain, the differential output signal of the Hall plate Hall_C and the Hall plate Hall_L is input to the second signal chain, the two ends of the switch S1 are respectively connected to the differential output signal of the Hall plate Hall_R, the two ends of the switch S2 are respectively connected to the differential output signal of the Hall plate Hall_C, the two ends of the switch S3 are respectively connected to the differential output signal of the Hall plate Hall_L One end of the switch S4 is connected to the first output end of the first programmable gain amplifier PGA_R in the first signal chain, and the other end of the switch S4 is connected to the detection signal VP_R. One end of the switch S5 is connected to the second output end of the first programmable gain amplifier PGA_R in the first signal chain, and the other end of the switch S5 is connected to the detection signal VN_R. One end of the switch S6 is connected to the second output end of the second programmable gain amplifier PGA_R in the second signal chain, and the other end of the switch S6 is connected to the detection signal VP_L. One end of the switch S7 is connected to the first output end of the second programmable gain amplifier PGA_R in the second signal chain, and the other end of the switch S7 is connected to the detection signal VN_L.

[0007] Further, the first output end of the Hall disk Hall_R generates an output signal VR+, the second output end of the Hall disk Hall_R generates an output signal VR-, the output signal VR+ and the output signal VR- constitute the differential output signal of the Hall disk Hall_R, the first output end of the Hall disk Hall_C generates an output signal VC+, the second output end of the Hall disk Hall_C generates an output signal VC-, the output signal VC+ and the output signal VC- constitute the differential output signal of the Hall disk Hall_C, the first output end of the Hall disk Hall_L generates an output signal VL+, the second output end of the Hall disk Hall_L generates an output signal VL-, the output signal VL+ and the output signal VL- constitute the differential output signal of the Hall disk Hall_L.

[0008] Further, the first signal chain includes a first differential difference amplifier DDA_R, a first programmable gain amplifier PGA_R, a first analog-to-digital converter ADC_R, a digital processing unit Digital, a first current steering digital-to-analog converter IDAC_R and a current signal output module IOUT, the first input end of the first differential difference amplifier DDA_R is connected to the output signal VR+, the second input end of the first differential difference amplifier DDA_R is connected to the output signal VR-, the third input end of the first differential difference amplifier DDA_R is connected to the output signal VC+, the fourth input end of the first differential difference amplifier DDA_R is connected to the output signal VC-, the first output end of the first differential difference amplifier DDA_R is connected to the first input end of the first programmable gain amplifier PGA_R, and the second output end of the first differential difference amplifier DDA_R is connected to the first programmable gain amplifier PGA_R. The second input end of GA_R, the first output end of the first programmable gain amplifier PGA_R is connected to the first input end of the first analog-to-digital converter ADC_R, the second output end of the first programmable gain amplifier PGA_R is connected to the second input end of the first analog-to-digital converter ADC_R, the output end of the first analog-to-digital converter ADC_R is connected to the first input end of the digital processing unit Digital, the first output end of the digital processing unit Digital is connected to the input end of the first current-steering digital-to-analog converter IDAC_R, the output end of the first current-steering digital-to-analog converter IDAC_R is connected to the second control end of the first programmable gain amplifier PGA_R, the second output end of the digital processing unit Digital is connected to the first control end of the first programmable gain amplifier PGA_R, and the third output end of the digital processing unit Digital is connected to the input end of the current signal output module IOUT.

[0009] Further, the second signal chain includes a second differential difference amplifier DDA_L, a second programmable gain amplifier PGA_L, a second analog-to-digital converter ADC_L, a digital processing unit Digital, a second current steering digital-to-analog converter IDAC_L and a current signal output module IOUT, the first input end of the second differential difference amplifier DDA_L is connected to the output signal VL-, the second input end of the second differential difference amplifier DDA_L is connected to the output signal VL+, the third input end of the second differential difference amplifier DDA_L is connected to the output signal VC-, the fourth input end of the second differential difference amplifier DDA_L is connected to the output signal VC+, the first output end of the second differential difference amplifier DDA_L is connected to the first input end of the second programmable gain amplifier PGA_L, and the second output end of the second differential difference amplifier DDA_L is connected to the second programmable gain amplifier PGA_L. The second input end of the second programmable gain amplifier PGA_L is connected to the first input end of the second analog-to-digital converter ADC_L, the second output end of the second programmable gain amplifier PGA_L is connected to the second input end of the second analog-to-digital converter ADC_L, the output end of the second analog-to-digital converter ADC_L is connected to the second input end of the digital processing unit Digital, the fourth output end of the digital processing unit Digital is connected to the input end of the second current-steering digital-to-analog converter IDAC_L, the output end of the second current-steering digital-to-analog converter IDAC_L is connected to the second control end of the second programmable gain amplifier PGA_L, the fifth output end of the digital processing unit Digital is connected to the first control end of the second programmable gain amplifier PGA_L, and the third output end of the digital processing unit Digital is connected to the input end of the current signal output module IOUT.

[0010] Furthermore, a coil L_R is arranged on the outer side of the Hall disk Hall_R, one end of the coil L_R is connected to the detection signal ITEST_R, and the other end of the coil L_R is grounded, a coil L_C is arranged on the outer side of the Hall disk Hall_C, one end of the coil L_C is connected to the detection signal ITEST_C, and the other end of the coil L_C is grounded, and a coil L_L is arranged on the outer side of the Hall disk Hall_L, one end of the coil L_L is connected to the detection signal ITEST_L, and the other end of the coil L_L is grounded.

[0011] A test method for a Hall plate sensitivity test circuit applied to a wheel speed sensor comprises the following steps: In the normal working mode, the switches S1, S2, S3, S4, S5, S6 and S7 are all turned off, and no current flows through the coils L_R, L_C and L_L, and the coils L_R, L_C and L_L will not affect the normal working of the wheel speed sensor chip; After entering the test mode, firstly, the switches S2, S4, S5, S6 and S7 are closed through the timing control, and the switches S1 and S3 are kept off. At this time, the differential output signal of the Hall disk Hall_C is short-circuited, the coil L_C does not inject current, the coil L_R and the coil L_L inject current I, and the current I generates a fixed DC magnetic field M on the coil L_R and the coil L_L; the Hall disk Hall_C has no magnetic field, and the differential output signal of the Hall disk Hall_C is short-circuited, and the signal size of the Hall disk Hall_C input to the first differential difference amplifier DDA_R is zero; The differential output signal sensed by the Hall disk Hall_R is input into the first differential difference amplifier DDA_R with an amplification factor of Gain_DDA_R in the first signal chain, and the differential output signal sensed by the Hall disk Hall_R is preliminarily amplified. The differential output signal amplified by the first differential difference amplifier DDA_R is input into the first programmable gain amplifier PGA_R with an amplification factor of Gain_PGA_R for further amplification; the differential output signal of the first programmable gain amplifier PGA_R outputs a detection signal VP_R and a detection signal VN_R through switches S4 and S5; then the sensitivity SR of the Hall disk Hall_R is expressed as: SR=(VP_R-VN_R) / (Gain_DDA_R*Gain_PGA_R*M); The differential output signal sensed by the Hall disk Hall_L is input into the second differential difference amplifier DDA_L with an amplification factor of Gain_DDA_L in the second signal chain, and the differential output signal sensed by the Hall disk Hall_L is preliminarily amplified. The differential output signal amplified by the second differential difference amplifier DDA_L is input into the second programmable gain amplifier PGA_L with an amplification factor of Gain_PGA_L for further amplification; the differential output signal of the second programmable gain amplifier PGA_L outputs a detection signal VP_L and a detection signal VN_L through switches S6 and S7; then the sensitivity SL of the Hall disk Hall_L is expressed as: SL=-(VP_L-VN_L) / (Gain_DDA_L*Gain_PGA_L*M); The timing control closes switches S1, S3, S4, S5, S6 and S7, and switches S2 is turned off. At this time, the differential output signals of the Hall disk Hall_R and the Hall disk Hall_L are short-circuited, no current is injected into the coil L_R and the coil L_L, and the current I is injected into the coil L_C. The current I generates a fixed DC magnetic field M on the coil L_C; the differential output signal induced by the Hall disk Hall_C is input into the second differential difference amplifier DDA_L with an amplification factor of Gain_DDA_L in the second signal chain, and the differential output signal induced by the Hall disk Hall_C is preliminarily amplified; the differential output signal amplified by the second differential difference amplifier DDA_L is input into the second programmable gain amplifier PGA_L with an amplification factor of Gain_PGA_L for further amplification; the differential output signal of the second programmable gain amplifier PGA_L outputs a detection signal VP_L and a detection signal VN_L through switches S6 and S7; then the sensitivity SC of the Hall disk Hall_C is expressed as: SC=(VP_C-VN_C) / (Gain_DDA_L*Gain_PGA_L*M); After measuring the sensitivities of the Hall plates Hall_R, Hall_C and Hall_L under different temperatures and process conditions, the sensitivity of the Hall plates is compensated by adjusting the injected current of the Hall plates to avoid large differences in the sensitivity of the Hall plates of different wheel speed sensor chips.

[0012] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a Hall disk sensitivity test circuit and method for a wheel speed sensor. The circuit of the present invention does not require major changes to the traditional signal processing circuit for the wheel speed sensor. Only a small number of switches need to be added to achieve the test of the sensitivity of the Hall disk. The modification cost is low. In addition, the present invention performs a Hall disk sensitivity test by injecting current into a coil to generate a fixed DC magnetic field, and the test method is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The present invention is a schematic diagram of a Hall plate sensitivity test circuit applied to a wheel speed sensor.

[0014] Figure 2 It is a schematic diagram of a signal processing circuit applied to a wheel speed sensor in the prior art. DETAILED DESCRIPTION

[0015] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0016] like Figure 1 As shown, a Hall plate sensitivity test circuit for a wheel speed sensor of the present invention comprises a Hall plate Hall_R, a Hall plate Hall_C, a Hall plate Hall_L, a first signal chain, a second signal chain, a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6 and a switch S7, the differential output signal of the Hall plate Hall_R and the Hall plate Hall_C is input to the first signal chain, the differential output signal of the Hall plate Hall_C and the Hall plate Hall_L is input to the second signal chain, the two ends of the switch S1 are respectively connected to the differential output signal of the Hall plate Hall_R, the two ends of the switch S2 are respectively connected to the differential output signal of the Hall plate Hall_C, and the two ends of the switch S3 are respectively connected to the differential output signal of the Hall plate Hall_R. The differential output signal of the Hall disk Hall_L is connected, one end of the switch S4 is connected to the first output end of the first programmable gain amplifier PGA_R in the first signal chain, and the other end of the switch S4 is connected to the detection signal VP_R, one end of the switch S5 is connected to the second output end of the first programmable gain amplifier PGA_R in the first signal chain, and the other end of the switch S5 is connected to the detection signal VN_R, one end of the switch S6 is connected to the second output end of the second programmable gain amplifier PGA_R in the second signal chain, and the other end of the switch S6 is connected to the detection signal VP_L, one end of the switch S7 is connected to the first output end of the second programmable gain amplifier PGA_R in the second signal chain, and the other end of the switch S7 is connected to the detection signal VN_L.

[0017] The first output end of the Hall disk Hall_R generates an output signal VR+, the second output end of the Hall disk Hall_R generates an output signal VR-, the output signal VR+ and the output signal VR- constitute the differential output signal of the Hall disk Hall_R, the first output end of the Hall disk Hall_C generates an output signal VC+, the second output end of the Hall disk Hall_C generates an output signal VC-, the output signal VC+ and the output signal VC- constitute the differential output signal of the Hall disk Hall_C, the first output end of the Hall disk Hall_L generates an output signal VL+, the second output end of the Hall disk Hall_L generates an output signal VL-, the output signal VL+ and the output signal VL- constitute the differential output signal of the Hall disk Hall_L.

[0018] The first signal chain includes a first differential difference amplifier DDA_R, a first programmable gain amplifier PGA_R, a first analog-to-digital converter ADC_R, a digital processing unit Digital, a first current steering digital-to-analog converter IDAC_R and a current signal output module IOUT, a first input end of the first differential difference amplifier DDA_R is connected to an output signal VR+, a second input end of the first differential difference amplifier DDA_R is connected to an output signal VR-, a third input end of the first differential difference amplifier DDA_R is connected to an output signal VC+, a fourth input end of the first differential difference amplifier DDA_R is connected to an output signal VC-, a first output end of the first differential difference amplifier DDA_R is connected to a first input end of the first programmable gain amplifier PGA_R, and a second output end of the first differential difference amplifier DDA_R is connected to a first programmable gain amplifier PGA_R. The first input terminal of the first programmable gain amplifier PGA_R is connected to the first input terminal of the first analog-to-digital converter ADC_R, the second output terminal of the first programmable gain amplifier PGA_R is connected to the second input terminal of the first analog-to-digital converter ADC_R, the output terminal of the first analog-to-digital converter ADC_R is connected to the first input terminal of the digital processing unit Digital, the first output terminal of the digital processing unit Digital is connected to the input terminal of the first current-steering digital-to-analog converter IDAC_R, the output terminal of the first current-steering digital-to-analog converter IDAC_R is connected to the second control terminal of the first programmable gain amplifier PGA_R, the second output terminal of the digital processing unit Digital is connected to the first control terminal of the first programmable gain amplifier PGA_R, and the third output terminal of the digital processing unit Digital is connected to the input terminal of the current signal output module IOUT.

[0019] The second signal chain includes a second differential difference amplifier DDA_L, a second programmable gain amplifier PGA_L, a second analog-to-digital converter ADC_L, a digital processing unit Digital, a second current steering digital-to-analog converter IDAC_L and a current signal output module IOUT, a first input end of the second differential difference amplifier DDA_L is connected to the output signal VL-, a second input end of the second differential difference amplifier DDA_L is connected to the output signal VL+, a third input end of the second differential difference amplifier DDA_L is connected to the output signal VC-, a fourth input end of the second differential difference amplifier DDA_L is connected to the output signal VC+, a first output end of the second differential difference amplifier DDA_L is connected to the first input end of the second programmable gain amplifier PGA_L, and a second output end of the second differential difference amplifier DDA_L is connected to the second programmable gain amplifier PGA_L. L, the first output end of the second programmable gain amplifier PGA_L is connected to the first input end of the second analog-to-digital converter ADC_L, the second output end of the second programmable gain amplifier PGA_L is connected to the second input end of the second analog-to-digital converter ADC_L, the output end of the second analog-to-digital converter ADC_L is connected to the second input end of the digital processing unit Digital, the fourth output end of the digital processing unit Digital is connected to the input end of the second current-steering digital-to-analog converter IDAC_L, the output end of the second current-steering digital-to-analog converter IDAC_L is connected to the second control end of the second programmable gain amplifier PGA_L, the fifth output end of the digital processing unit Digital is connected to the first control end of the second programmable gain amplifier PGA_L, and the third output end of the digital processing unit Digital is connected to the input end of the current signal output module IOUT.

[0020] A coil L_R is arranged on the outside of the Hall disk Hall_R, one end of the coil L_R is connected to the detection signal ITEST_R, and the other end of the coil L_R is grounded. A coil L_C is arranged on the outside of the Hall disk Hall_C, one end of the coil L_C is connected to the detection signal ITEST_C, and the other end of the coil L_C is grounded. A coil L_L is arranged on the outside of the Hall disk Hall_L, one end of the coil L_L is connected to the detection signal ITEST_L, and the other end of the coil L_L is grounded.

[0021] A test method for a Hall plate sensitivity test circuit applied to a wheel speed sensor comprises the following steps: In the normal working mode, switch S1, switch S2, switch S3, switch S4, switch S5, switch S6 and switch S7 are all turned off, no current flows through coil L_R, coil L_C and coil L_L, and coil L_R, coil L_C and coil L_L will not affect the normal working of the wheel speed sensor chip.

[0022] After entering the test mode, firstly, the switches S2, S4, S5, S6 and S7 are closed through the timing control, and the switches S1 and S3 remain turned off. At this time, the differential output signal of the Hall disk Hall_C is short-circuited, the coil L_C does not inject current, the coil L_R and the coil L_L inject current I, and the current I generates a fixed DC magnetic field M on the coil L_R and the coil L_L; the Hall disk Hall_C has no magnetic field, and the differential output signal of the Hall disk Hall_C is short-circuited, and the signal size of the Hall disk Hall_C input to the first differential difference amplifier DDA_R is zero.

[0023] The differential output signal sensed by the Hall disk Hall_R is input into the first differential difference amplifier DDA_R with an amplification factor of Gain_DDA_R in the first signal chain, and the differential output signal sensed by the Hall disk Hall_R is preliminarily amplified. The differential output signal amplified by the first differential difference amplifier DDA_R is input into the first programmable gain amplifier PGA_R with an amplification factor of Gain_PGA_R for further amplification; the differential output signal of the first programmable gain amplifier PGA_R outputs a detection signal VP_R and a detection signal VN_R through switches S4 and S5; then the sensitivity SR of the Hall disk Hall_R is expressed as: SR=(VP_R-VN_R) / (Gain_DDA_R*Gain_PGA_R*M).

[0024] The differential output signal sensed by the Hall disk Hall_L is input into the second differential difference amplifier DDA_L with an amplification factor of Gain_DDA_L in the second signal chain, and the differential output signal sensed by the Hall disk Hall_L is preliminarily amplified. The differential output signal amplified by the second differential difference amplifier DDA_L is input into the second programmable gain amplifier PGA_L with an amplification factor of Gain_PGA_L for further amplification; the differential output signal of the second programmable gain amplifier PGA_L outputs a detection signal VP_L and a detection signal VN_L through switches S6 and S7; then the sensitivity SL of the Hall disk Hall_L is expressed as: SL=-(VP_L-VN_L) / (Gain_DDA_L*Gain_PGA_L*M).

[0025] The timing control closes switches S1, S3, S4, S5, S6 and S7, and switches S2 is turned off. At this time, the differential output signals of the Hall disk Hall_R and the Hall disk Hall_L are short-circuited, no current is injected into the coil L_R and the coil L_L, and the current I is injected into the coil L_C. The current I generates a fixed DC magnetic field M on the coil L_C; the differential output signal induced by the Hall disk Hall_C is input into the second differential difference amplifier DDA_L with an amplification factor of Gain_DDA_L in the second signal chain, and the differential output signal induced by the Hall disk Hall_C is preliminarily amplified; the differential output signal amplified by the second differential difference amplifier DDA_L is input into the second programmable gain amplifier PGA_L with an amplification factor of Gain_PGA_L for further amplification; the differential output signal of the second programmable gain amplifier PGA_L outputs a detection signal VP_L and a detection signal VN_L through switches S6 and S7; then the sensitivity SC of the Hall disk Hall_C is expressed as: SC=(VP_C-VN_C) / (Gain_DDA_L*Gain_PGA_L*M).

[0026] After measuring the sensitivities of the Hall plates Hall_R, Hall_C and Hall_L under different temperatures and process conditions, the sensitivity of the Hall plates is compensated by adjusting the injected current of the Hall plates to avoid large differences in the sensitivity of the Hall plates of different wheel speed sensor chips.

[0027] The present invention provides a Hall disk sensitivity test circuit and method for a wheel speed sensor. The circuit of the present invention does not require major changes to a traditional signal processing circuit for a wheel speed sensor. Only a small number of switches need to be added to implement the Hall disk sensitivity test, and the modification cost is low. In addition, the present invention performs a Hall disk sensitivity test by injecting current into a coil to generate a fixed DC magnetic field, and the test method is simple.

[0028] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A Hall plate sensitivity test circuit for a wheel speed sensor, characterized in that: The device comprises a Hall plate Hall_R, a Hall plate Hall_C, a Hall plate Hall_L, a first signal chain, a second signal chain, a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6 and a switch S7. The differential output signal of the Hall plate Hall_R and the Hall plate Hall_C is input to the first signal chain, the differential output signal of the Hall plate Hall_C and the Hall plate Hall_L is input to the second signal chain, the two ends of the switch S1 are respectively connected to the differential output signal of the Hall plate Hall_R, the two ends of the switch S2 are respectively connected to the differential output signal of the Hall plate Hall_C, the two ends of the switch S3 are respectively connected to the differential output signal of the Hall plate Hall_L. Output signal, one end of the switch S4 is connected to the first output end of the first programmable gain amplifier PGA_R in the first signal chain, and the other end of the switch S4 is connected to the detection signal VP_R, one end of the switch S5 is connected to the second output end of the first programmable gain amplifier PGA_R in the first signal chain, and the other end of the switch S5 is connected to the detection signal VN_R, one end of the switch S6 is connected to the second output end of the second programmable gain amplifier PGA_R in the second signal chain, and the other end of the switch S6 is connected to the detection signal VP_L, one end of the switch S7 is connected to the first output end of the second programmable gain amplifier PGA_R in the second signal chain, and the other end of the switch S7 is connected to the detection signal VN_L.

2. The Hall plate sensitivity test circuit for a wheel speed sensor according to claim 1, characterized in that: The first output end of the Hall disk Hall_R generates an output signal VR+, the second output end of the Hall disk Hall_R generates an output signal VR-, the output signal VR+ and the output signal VR- constitute the differential output signal of the Hall disk Hall_R, the first output end of the Hall disk Hall_C generates an output signal VC+, the second output end of the Hall disk Hall_C generates an output signal VC-, the output signal VC+ and the output signal VC- constitute the differential output signal of the Hall disk Hall_C, the first output end of the Hall disk Hall_L generates an output signal VL+, the second output end of the Hall disk Hall_L generates an output signal VL-, the output signal VL+ and the output signal VL- constitute the differential output signal of the Hall disk Hall_L.

3. The Hall plate sensitivity test circuit for a wheel speed sensor according to claim 2, characterized in that: The first signal chain includes a first differential difference amplifier DDA_R, a first programmable gain amplifier PGA_R, a first analog-to-digital converter ADC_R, a digital processing unit Digital, a first current steering digital-to-analog converter IDAC_R and a current signal output module IOUT, a first input end of the first differential difference amplifier DDA_R is connected to an output signal VR+, a second input end of the first differential difference amplifier DDA_R is connected to an output signal VR-, a third input end of the first differential difference amplifier DDA_R is connected to an output signal VC+, a fourth input end of the first differential difference amplifier DDA_R is connected to an output signal VC-, a first output end of the first differential difference amplifier DDA_R is connected to a first input end of the first programmable gain amplifier PGA_R, and a second output end of the first differential difference amplifier DDA_R is connected to a first programmable gain amplifier PGA_R. _R, the first output end of the first programmable gain amplifier PGA_R is connected to the first input end of the first analog-to-digital converter ADC_R, the second output end of the first programmable gain amplifier PGA_R is connected to the second input end of the first analog-to-digital converter ADC_R, the output end of the first analog-to-digital converter ADC_R is connected to the first input end of the digital processing unit Digital, the first output end of the digital processing unit Digital is connected to the input end of the first current-steering digital-to-analog converter IDAC_R, the output end of the first current-steering digital-to-analog converter IDAC_R is connected to the second control end of the first programmable gain amplifier PGA_R, the second output end of the digital processing unit Digital is connected to the first control end of the first programmable gain amplifier PGA_R, and the third output end of the digital processing unit Digital is connected to the input end of the current signal output module IOUT.

4. The Hall plate sensitivity test circuit for a wheel speed sensor according to claim 2, characterized in that: The second signal chain includes a second differential difference amplifier DDA_L, a second programmable gain amplifier PGA_L, a second analog-to-digital converter ADC_L, a digital processing unit Digital, a second current steering digital-to-analog converter IDAC_L and a current signal output module IOUT, a first input end of the second differential difference amplifier DDA_L is connected to the output signal VL-, a second input end of the second differential difference amplifier DDA_L is connected to the output signal VL+, a third input end of the second differential difference amplifier DDA_L is connected to the output signal VC-, a fourth input end of the second differential difference amplifier DDA_L is connected to the output signal VC+, a first output end of the second differential difference amplifier DDA_L is connected to the first input end of the second programmable gain amplifier PGA_L, and a second output end of the second differential difference amplifier DDA_L is connected to the second programmable gain amplifier PGA_L. _L, the first output end of the second programmable gain amplifier PGA_L is connected to the first input end of the second analog-to-digital converter ADC_L, the second output end of the second programmable gain amplifier PGA_L is connected to the second input end of the second analog-to-digital converter ADC_L, the output end of the second analog-to-digital converter ADC_L is connected to the second input end of the digital processing unit Digital, the fourth output end of the digital processing unit Digital is connected to the input end of the second current-steering digital-to-analog converter IDAC_L, the output end of the second current-steering digital-to-analog converter IDAC_L is connected to the second control end of the second programmable gain amplifier PGA_L, the fifth output end of the digital processing unit Digital is connected to the first control end of the second programmable gain amplifier PGA_L, and the third output end of the digital processing unit Digital is connected to the input end of the current signal output module IOUT.

5. The Hall plate sensitivity test circuit for a wheel speed sensor according to claim 2, characterized in that: A coil L_R is arranged on the outside of the Hall disk Hall_R, one end of the coil L_R is connected to the detection signal ITEST_R, and the other end of the coil L_R is grounded. A coil L_C is arranged on the outside of the Hall disk Hall_C, one end of the coil L_C is connected to the detection signal ITEST_C, and the other end of the coil L_C is grounded. A coil L_L is arranged on the outside of the Hall disk Hall_L, one end of the coil L_L is connected to the detection signal ITEST_L, and the other end of the coil L_L is grounded.

6. A method for testing a Hall plate sensitivity test circuit for a wheel speed sensor according to any one of claims 1 to 5, characterized in that The following steps are involved: In the normal working mode, the switches S1, S2, S3, S4, S5, S6 and S7 are all turned off, and no current flows through the coils L_R, L_C and L_L, and the coils L_R, L_C and L_L will not affect the normal working of the wheel speed sensor chip; After entering the test mode, firstly, the switches S2, S4, S5, S6 and S7 are closed through the timing control, and the switches S1 and S3 are kept off. At this time, the differential output signal of the Hall disk Hall_C is short-circuited, the coil L_C does not inject current, and the coil L_R and the coil L_L inject current I. The current I generates a fixed DC magnetic field M on the coil L_R and the coil L_L. The Hall disk Hall_C has no magnetic field, and the differential output signal of the Hall disk Hall_C is short-circuited, and the signal input from the Hall disk Hall_C to the first differential amplifier DDA_R is zero; The differential output signal sensed by the Hall disk Hall_R is input into the first differential difference amplifier DDA_R with an amplification factor of Gain_DDA_R in the first signal chain, and the differential output signal sensed by the Hall disk Hall_R is preliminarily amplified. The differential output signal amplified by the first differential difference amplifier DDA_R is input into the first programmable gain amplifier PGA_R with an amplification factor of Gain_PGA_R for further amplification; the differential output signal of the first programmable gain amplifier PGA_R outputs a detection signal VP_R and a detection signal VN_R through switches S4 and S5; then the sensitivity SR of the Hall disk Hall_R is expressed as: SR=(VP_R-VN_R) / (Gain_DDA_R*Gain_PGA_R*M); The differential output signal sensed by the Hall disk Hall_L is input into the second differential amplifier DDA_L with an amplification factor of Gain_DDA_L in the second signal chain, and the differential output signal sensed by the Hall disk Hall_L is preliminarily amplified. The differential output signal amplified by the second differential amplifier DDA_L is input into the second programmable gain amplifier PGA_L with an amplification factor of Gain_PGA_L for further amplification. The differential output signal of the second programmable gain amplifier PGA_L outputs the detection signal VP_L and the detection signal VN_L through the switch S6 and the switch S7; then the sensitivity SL of the Hall plate Hall_L is expressed as: SL=-(VP_L-VN_L) / (Gain_DDA_L*Gain_PGA_L*M); The timing control closes the switches S1, S3, S4, S5, S6 and S7, and turns off the switch S2. At this time, the differential output signals of the Hall disk Hall_R and the Hall disk Hall_L are short-circuited, no current is injected into the coil L_R and the coil L_L, and the current I is injected into the coil L_C. The current I generates a fixed DC magnetic field M on the coil L_C; the differential output signal induced by the Hall disk Hall_C is input into the second differential difference amplifier DDA_L with an amplification factor of Gain_DDA_L in the second signal chain, and the differential output signal induced by the Hall disk Hall_C is preliminarily amplified; the differential output signal amplified by the second differential difference amplifier DDA_L is input into the second programmable gain amplifier PGA_L with an amplification factor of Gain_PGA_L for further amplification; The differential output signal of the second programmable gain amplifier PGA_L outputs the detection signal VP_L and the detection signal VN_L through the switch S6 and the switch S7; then the sensitivity SC of the Hall plate Hall_C is expressed as: SC=(VP_C-VN_C) / (Gain_DDA_L*Gain_PGA_L*M); After measuring the sensitivities of the Hall plates Hall_R, Hall_C and Hall_L under different temperatures and process conditions, the sensitivity of the Hall plates is compensated by adjusting the injected current of the Hall plates to avoid large differences in the sensitivity of the Hall plates of different wheel speed sensor chips.

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