Linear voltage regulator and phase-locked loop circuit

Abstract

The invention relates to the technical field of integrated circuits, and discloses a linear voltage regulator comprising an error amplifier, a first input end of which is connected with a reference voltage and a second input end of which is connected with an output voltage of a load; the comparator is used for comparing reference voltage with output voltage to generate first feedback voltage; the power transistor is connected with a power supply, is connected with the output end of the error amplifier and is used for adjusting the output voltage of the load according to the first feedback voltage; the buffer is connected with the error amplifier and the power transistor and used for driving the power transistor; and the power supply ripple feed-forward path is connected with the output end of the buffer and the power transistor, and is used for extracting ripples from the power supply and copying the ripples to the power transistor. The linear voltage regulator introduces a power supply ripple feed-forward path. Ripples are extracted from a power supply through a power supply wave feedforward path, and the ripples are copied to a grid electrode of a power transistor, so that the power supply rejection ratio of the linear voltage regulator is increased. The invention also discloses a phase-locked loop circuit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, for example, to a linear regulator and a phase-locked loop circuit. Background Art

[0002] With the development of communication electronic products, the requirements for power supply systems are getting higher and higher. The power supply system should have the characteristics of low power consumption and high efficiency to save energy and extend battery life. The power supply system with the above characteristics is also accompanied by higher system noise, which is unacceptable for high-quality clock systems. For example, in a phase-locked loop, the phase noise index of the voltage-controlled oscillator (VCO) determines the noise performance of the phase-locked loop circuit, and the introduction of power supply system noise will seriously deteriorate the phase noise of the voltage-controlled oscillator.

[0003] To solve the noise problem, a linear regulator (LDO) with a high power supply rejection ratio (PSRR) is usually used to provide a "clean" power supply for the voltage-controlled oscillator. The design methods of a high power supply rejection ratio linear regulator include: Method 1: Design a high-precision error amplifier with a very wide bandwidth to enhance high-frequency negative feedback. Method 2: Stack more power transistors to enhance the isolation between the power system and the linear regulator output.

[0004] The above method will increase the difficulty of circuit design or occupy a larger chip area, thereby increasing the cost.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide a linear regulator and a phase-locked loop circuit to provide a linear regulator with a simple structure and a high power supply rejection ratio.

[0008] In some embodiments, the linear regulator includes: an error amplifier, a first input terminal connected to a reference voltage, and a second input terminal connected to the output voltage of a load; used to compare the reference voltage and the output voltage to generate a first feedback voltage; a power transistor, connected to a power supply and connected to the output terminal of the error amplifier, and used to adjust the output voltage of the load according to the first feedback voltage; a buffer, connected to the error amplifier and the power transistor, and used to drive the power transistor; a power supply ripple feedforward path, connected to the output terminal of the buffer and the power transistor, and used to extract ripple from the power supply and copy the ripple to the power transistor.

[0009] In some embodiments, the phase-locked loop circuit includes: a voltage-controlled oscillator; and a linear regulator such as the aforementioned, connected to the voltage-controlled oscillator to provide power to the voltage-controlled oscillator.

[0010] The linear voltage regulator and phase-locked loop circuit for a voltage-controlled oscillator provided in the embodiments of the present disclosure can achieve the following technical effects:

[0011] In the disclosed example, a power ripple feed-forward path is introduced to extract ripples from the power supply and copy the ripples to the gate of the power transistor to improve the power supply rejection ratio of the linear regulator.

[0012] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0014] Figure 1 is a schematic diagram of the structure of a linear regulator provided by an embodiment of the present disclosure;

[0015] Figure 2 is a complete circuit structure diagram of a linear regulator provided by an embodiment of the present disclosure;

[0016] Figure 3 is a complete circuit structure diagram of another linear regulator provided by an embodiment of the present disclosure;

[0017] Figure 4 It is a schematic diagram of the structure of a phase-locked loop circuit provided in an embodiment of the present disclosure.

[0018] Reference numerals:

[0019] 10: power supply ripple feed-forward path; 20: buffer; EA: error amplifier; MP: power transistor; PM1: first PMOS tube; PM2: second PMOS tube; NM1: first NMOS tube; R1: first resistor; R2: second resistor; CL: load capacitor; Cc: Miller compensation capacitor; Vref: reference voltage; Ibias: bias current source; LPF: low-pass filter; VCO: voltage-controlled oscillator. DETAILED DESCRIPTION

[0020] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0021] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0022] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0023] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0024] Unless otherwise stated, the term "plurality" means two or more.

[0025] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0026] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0027] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0028] At present, linear regulators (LDOs) with high power supply rejection ratio (PSRR) are usually used to provide "clean" power for voltage-controlled oscillators. The design methods of high power supply rejection ratio linear regulators include: Method 1: Design a high-precision error amplifier with a very wide bandwidth to enhance high-frequency negative feedback. Method 2: Stack more power transistors to enhance the isolation between the power system and the linear regulator output. These methods will increase the difficulty of circuit design or occupy a larger chip area, increasing costs.

[0029] Combination Figure 1 , 2 As shown, the embodiment of the present disclosure provides a linear regulator including: an error amplifier EA, a power transistor MP, a buffer 20 and a power ripple feed-forward path 10. Among them, the error amplifier EA has a first input terminal connected to a reference voltage Vref, and a second input terminal connected to the output voltage VOUT of the load; it is used to compare the reference voltage Vref and the output voltage VOUT to generate a first feedback voltage. The power transistor MP is connected to the output terminal of the error amplifier EA, and is used to adjust the output voltage of the load according to the first feedback voltage. The buffer 20 is connected to the error amplifier EA and the power transistor MP, and is used to drive the power transistor MP. The power ripple feed-forward path 10 is connected to the output terminal of the buffer 20 and the power transistor MP, and is used to extract ripples from the power supply VDD and copy the ripples to the power transistor MP. The power supply VDD supplies power to the error amplifier EA, the power transistor MP, the buffer 20 and the power ripple feed-forward path 10.

[0030] Here, the two input terminals of the error amplifier EA are respectively connected to the output voltage of the linear regulator and the reference voltage Vref (also called the reference voltage) to compare the two and output the first feedback voltage. The output terminal of the error amplifier EA is connected to the input terminal of the power transistor MP to control the conduction degree of the power transistor MP based on the first feedback voltage. Specifically, if the output voltage is less than the reference voltage, the error amplifier EA controls to increase the conduction degree of the power transistor MP and increase the output voltage. If the output voltage is greater than the reference voltage, the error amplifier EA reduces the conduction degree of the power transistor MP and reduces the output voltage to ensure the stability of the linear regulator output. In the disclosed embodiment, the in-phase input terminal of the error amplifier EA is connected to the output voltage, and the inverting input terminal is connected to the reference voltage Vref; the power transistor MP is a PMOS tube. When the output voltage is less than the reference voltage, the first feedback voltage output by the error amplifier EA is a negative voltage signal. The gate-source voltage difference of the power transistor MP becomes larger, so that the current of the power transistor MP becomes larger, and the output voltage is increased. When the output voltage is greater than the reference voltage, the first feedback voltage output by the error amplifier EA is a positive voltage signal. The gate-source voltage difference of the power transistor MP becomes smaller, so that the current of the power transistor MP becomes smaller, thereby reducing the output voltage.

[0031] The buffer 20 is located between the error amplifier EA and the power transistor MP, and is used to enhance the driving capability and move the pole located at the gate of the power transistor MP to a higher frequency. The power ripple feed-forward path 10 is connected to the output end of the buffer 20 and the power transistor MP. The power ripple feed-forward path 10 is mainly composed of a MOS tube and an amplifier. The power ripple feed-forward path can be used to extract ripples from the power supply and copy the ripples to the power transistor MP.

[0032] The linear regulator provided by the embodiment of the present disclosure is used to introduce a power ripple feed-forward path. The power ripple feed-forward path is used to extract ripples from the power supply and copy the ripples to the gate of the power transistor MP to improve the power supply rejection ratio of the linear regulator. The power ripple feed-forward path does not require additional on-chip resistors and capacitors for filtering, which greatly saves circuit area.

[0033] Optionally, the buffer 20 includes a first PMOS transistor PM1 and a second PMOS transistor PM2. The first PMOS transistor PM1 has a source connected to the power supply, and a gate connected to a component of the power ripple feed-forward path. The second PMOS transistor PM2 has a source connected to the drain of the first PMOS transistor PM1, a gate connected to the output end of the error amplifier EA and a load, and a drain connected to ground.

[0034] Here, the second PMOS tube PM2 is controlled by the output signal of the error amplifier EA and can be turned on or off quickly; that is, the second PMOS tube PM2 is mainly used as a switch. Specifically, when the first feedback voltage output by the error amplifier EA is a negative voltage signal, the conduction degree of the second PMOS tube PM2 increases, providing a current path from the power supply to the output, and the current is sufficient to drive the gate of the power transistor MP to discharge. And the on-resistance of the second PMOS tube PM2 is low, and a larger output current can be achieved. When the first feedback voltage output by the error amplifier EA is a positive voltage signal, the conduction degree of the second PMOS tube PM2 decreases, and the gate of the power transistor MP obtains charge from the power supply through the buffer, that is, the power transistor MP is charged. The on-resistance of the second PMOS tube PM2 is high, and a smaller output current can be achieved. In this way, the second PMOS tube PM2 can quickly change the voltage of the output node and enhance the driving capability.

[0035] In addition, the buffer 20 reduces the interaction with the load by providing a low impedance output, thereby reducing the pole in the circuit. This is because the low impedance output can reduce the impact of the load and move the pole to a higher frequency. In addition, the first PMOS tube is controlled by the components of the power ripple feed-forward path, and its main function is amplification.

[0036] Optionally, the power ripple feed-forward path 10 includes: a first NMOS tube NM1, an operational amplifier AMP and a first PMOS tube PM1. Among them, the first NMOS tube NM1 has a source connected to a bias current source and a drain connected to ground. The operational amplifier AMP has an input terminal connected to an input current and a gate of the first NMOS tube NM1, and another input terminal connected to an output terminal. The first PMOS tube PM1 has a drain connected to a power supply, a gate connected to an output terminal of the operational amplifier AMP, and a source connected to a component of a buffer. The first PMOS tube PM1 is a component shared by the power ripple feed-forward path 10 and the buffer 20.

[0037] Here, the power ripple feed-forward path reuses the first PMOS tube PM1 of the buffer. The first NMOS tube NM1 of the power ripple feed-forward path has a source connected to the bias current source Ibias, a drain connected to the ground, and a gate connected to the non-inverting input terminal of the operational amplifier AMP. Under the action of the bias current source Ibias, the first NMOS tube NM1 is turned on, and its voltage VB is not affected by the power supply voltage. This is because the first NMOS tube NM1 is equivalent to a diode in the disclosed embodiment. The non-inverting input terminal of the operational amplifier AMP is connected to the gate of the first NMOS tube NM1, and the inverting input terminal is connected to the output terminal of the operational amplifier AMP. When there is a voltage difference between the two input terminal signals, the operational amplifier AMP amplifies the voltage difference. The output terminal of the operational amplifier AMP is connected to the gate of the first PMOS tube PM1, so the gate voltage of the first PMOS tube PM1 and the gate of the first PMOS tube PM1 convert the voltage change into a current change. By calculating the impedance and current, the change in the gate voltage of the power transistor MP can be obtained. Then adjust the transconductance of the two PMOS tubes of the buffer to keep the Vgs of the power transistor MP unchanged. In this way, the output voltage of the linear regulator is guaranteed not to change, thereby effectively improving the power supply rejection ratio performance of the linear regulator.

[0038] In addition, the first PMOS tube PM1 of the power ripple feedforward path multiplexes the buffer, and no additional static power consumption is required. The power ripple feedforward path does not require additional on-chip resistors and capacitors for filtering, and is easy to integrate, greatly saving chip area.

[0039] Optionally, the operational amplifier AMP is a unit gain amplifier, and is used to copy the gate voltage of the first NMOS transistor NM1 to the gate of the first PMOS transistor PM1.

[0040] Here, the unity gain amplifier refers to an amplifier with a fixed gain of 1, which means that the amplitude of the output signal of the operational amplifier AMP is the same as the amplitude of the input signal. In this way, the output signal of the operational amplifier AMP is only related to the in-phase input signal, that is, when the input signal changes, the operational amplifier AMP will adjust its output to ensure that the voltage at the inverting input terminal is equal to the voltage at the in-phase input terminal. This ensures that the output voltage will follow the change of the input voltage, that is, the gate voltage of the first PMOS tube PM1 is only affected by the gate voltage of the first NMOS tube NM1, and is not affected by the power supply.

[0041] Optionally, when the power supply changes, the gate voltage change ΔU of the power transistor MP mp for:

[0042] △U mp =(gm mp1 ×ΔVDD) / gm mp2

[0043] Among them, gm mp1 is the transconductance of the first PMOS tube PM1, gm mp2 is the transconductance of the second PMOS transistor PM2, and ΔVDD is the voltage variation of the power supply.

[0044] As mentioned above, the gate voltage of the first PMOS transistor PM1 is not affected by the power supply. Therefore, when the power supply changes, the voltage change can be converted into a current change through the first PMOS transistor PM1. Specifically, the feedforward current value of the branch where the first PMOS transistor PM1 is located is gm mp1 × VDD. Since the second PMOS transistor PM2 is controlled by the error amplifier EA and is equivalent to a switch, its influence on the current value of the branch is very small and can be ignored. Then, based on the feedforward current value and the impedance of the second PMOS transistor PM2 (i.e., 1 / gm mp2 ), the gate voltage gm of the power transistor MP can be obtained mp1 ×VDD / gm mp2 In this way, when the power supply changes, the gate voltage change ΔU of the power transistor MP can be obtained. mp Among them, gm mp1 is the transconductance of the first PMOS tube PM1, gm mp2 is the transconductance of the second PMOS transistor PM2, and ΔVDD is the voltage variation of the power supply. Thus, after determining the gate voltage variation of the power transistor MP, in order to ensure that the output voltage of the linear regulator does not change, it is necessary to make the gate voltage variation follow the voltage variation of the power supply. That is, the voltage variation of the power supply is equal to the gate voltage variation of the power transistor MP, thereby ensuring the stability of the output voltage of the linear regulator.

[0045] Optionally, by adjusting the transconductance of the first PMOS transistor PM1 and the transconductance of the second PMOS transistor PM2 , the gate voltage variation of the power transistor MP is made equal to the power supply variation.

[0046] Here, it can be seen from the above formula that when the power supply changes, the gate voltage change is only related to the transconductance of the first PMOS tube PM1 and the transconductance of the second PMOS tube PM2. Therefore, by adjusting the transconductance of the first PMOS tube PM1 and the transconductance of the second PMOS tube PM2, the gate voltage change of the power transistor MP is equal to the change of the power supply. In this way, the gate voltage and source voltage changes of the power transistor MP are equal, thereby ensuring that the gate-source voltage of the power transistor MP remains unchanged. Therefore, the output voltage of the linear regulator does not change, thereby effectively improving the power supply rejection ratio performance of the linear regulator.

[0047] Optionally, the linear regulator further includes a Miller compensation capacitor Cc. The Miller compensation capacitor Cc is connected to the output end of the error amplifier EA and the load.

[0048] Here, due to the Miller effect, when the Miller compensation capacitor Cc is located between the input and output of the error amplifier EA, the equivalent capacitance value generated by the capacitor in the circuit will be larger than the actual capacitance value, thereby improving the stability and frequency response of the amplifier. In addition, the Miller capacitor will move the first pole of the error amplifier EA toward the low frequency direction and generate a new pole at a higher frequency. This can improve the phase margin of the error amplifier EA and keep it stable at a higher frequency.

[0049] Optionally, the linear voltage regulator further includes a low-pass filter LPF. The low-pass filter LPF is connected to the output end of the error amplifier EA to filter the output voltage.

[0050] Here, the load output voltage of the linear regulator may contain some ripples, which are mainly caused by the fluctuation of the input voltage or the internal switching action of the regulator. The high-frequency ripples are filtered out by the low-pass filter, so that the linear regulator outputs a clean power supply. In addition, the low-pass filter can also suppress the high-frequency noise in the circuit and protect the load circuit from interference.

[0051] Optionally, the linear regulator further includes a voltage divider resistor. The voltage divider resistor is connected in series at both ends of the load, including a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is connected to the drain of the power transistor MP, the second end is connected to the first end of the second resistor R2, the second end of the second resistor R2 is grounded; and the first end of the second resistor R2 is connected to the second input end of the error amplifier EA.

[0052] Here, the voltage divider resistor is used to provide a feedback signal, that is, to generate an output voltage. The error amplifier compares the reference voltage Vref and the output voltage. If the output voltage deviates from the reference voltage Vref, the gate voltage of the power transistor MP is controlled to adjust the output voltage so that the output voltage returns to the vicinity of the reference voltage Vref. In addition, the voltage divider resistor can correspond to load changes and input voltage fluctuations to ensure the stability of the output voltage.

[0053] In the above-mentioned embodiment, the linear regulator, during actual operation, determines the appropriate transconductance of the first PMOS transistor PM1 and the transconductance of the second PMOS transistor PM2 based on the voltage change of the power supply system in the usage scenario, thereby obtaining the linear regulator in the current usage scenario.

[0054] Combination Figure 3, the overall circuit structure of the linear regulator includes: the first NMOS tube NM1, the operational amplifier AMP and the first PMOS tube PM1 constitute a power ripple feed-forward path; the first PMOS tube PM1 and the second PMOS tube PM2 constitute a buffer Buffer, an error amplifier EA, a power transistor MP, a voltage divider resistor, a load capacitor CL and a Miller compensation capacitor Cc. In detail, the gate and drain of the first NMOS tube are connected to the bias current source, and the source and the substrate are grounded. The gate of the first NMOS tube NM1 is connected to the non-inverting input terminal of the operational amplifier AMP, and the inverting input terminal and the output terminal of the operational amplifier AMP are connected. The output terminal of the operational amplifier AMP is connected to the gate of the first PMOS tube PM1, the source of the first PMOS tube PM1 is connected to the power supply, the drain is connected to the source of the second PMOS tube PM2, and the drain is also connected to the gate of the power transistor. The source of the power transistor MP is connected to the power supply VDD, and the drain is connected to the voltage divider resistor and the load capacitor CL connected in parallel with the voltage divider resistor. The voltage-dividing resistor includes a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is connected to the drain of the power transistor MP, the second end is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded. The gate of the second PMOS tube PM2 is connected to the power supply, and the gate is connected to the output end of the error amplifier EA. The inverting input end of the error amplifier EA is connected to the reference voltage, and the non-inverting input end is connected to the first end of the second resistor R2. A Miller compensation capacitor Cc is provided between the output end of the error amplifier EA and the first end of the load capacitor CL, and the first end of the load capacitor CL is also connected to a low-pass filter LPF, so that the output voltage is supplied to devices such as a voltage-controlled oscillator.

[0055] During operation, the linear regulator provides a bias current source for the power supply ripple feed-forward path. Under the action of the bias current source, the first NMOS tube NM1 is turned on, and the generated voltage value VB is input into the non-inverting input terminal of the operational amplifier AMP. Since the operational amplifier AMP is a unit gain amplifier, the output voltage of the operational amplifier AMP is still VB. The gate voltage of the first PMOS tube PM1 is VB, and the source voltage is VDD. VDD>VB, so the first PMOS tube PM1 is turned on. After the first PMOS tube PM1 is turned on, it provides a voltage drop for the gate of the power transistor. The power transistor is turned on to provide current to the load, thereby outputting a voltage. The error amplifier compares the output voltage with the reference voltage. If the output voltage is less than the reference voltage, the first feedback voltage output by the error amplifier EA is a negative voltage signal. The second PMOS tube PM2 has a higher degree of conduction and a lower on-resistance, providing a current path from VDD to the output, which is sufficient to drive the gate of the power transistor MP to discharge. The gate-source voltage difference of the power transistor MP increases, which increases the current of the power transistor MP and increases the output voltage. When the output voltage is greater than the reference voltage, the first feedback voltage output by the error amplifier EA is a positive voltage signal. The conduction degree of the second PMOS tube PM2 is reduced and the on-resistance is high. The gate of the power transistor MP obtains charge from the power supply through the buffer, that is, the power transistor MP is charged. The gate-source voltage difference of the power transistor MP becomes smaller, so that the current of the power transistor MP becomes smaller, and the output voltage is reduced. In this way, the output voltage is stabilized near the reference voltage.

[0056] During operation, if the power supply changes, the fluctuation of the power supply is copied to the gate of the power transistor through the power ripple feed-forward path because the transconductance of the first PMOS tube PM1 and the transconductance of the second PMOS tube PM2 are selected to adapt. That is, the voltage change of the power supply is equal to the voltage change of the gate of the power transistor MP, thereby ensuring the stability of the output voltage of the linear regulator.

[0057] Combination Figure 4 As shown, an embodiment of the present disclosure provides a phase-locked loop circuit including: a voltage-controlled oscillator; and a linear regulator as described above, connected to the voltage-controlled oscillator VCO, for providing power to the voltage-controlled oscillator VCO.

[0058] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A linear regulator, characterized in that: include: An error amplifier, a first input terminal connected to a reference voltage, and a second input terminal connected to an output voltage of a load; Used to compare the reference voltage and the output voltage to generate a first feedback voltage; A power transistor connected to the output end of the error amplifier and used to adjust the output voltage of the load according to the first feedback voltage; A buffer is connected between the error amplifier and the power transistor and is used to drive the power transistor; The power supply ripple feed-forward path is connected to the output end of the buffer and the power transistor, and is used for extracting the ripple from the power supply and copying the ripple to the power transistor.

2. The linear regulator according to claim 1, characterized in that: The buffer comprises: A first PMOS tube, a source electrode of which is connected to a power supply, and a gate electrode of which is connected to a component of a power supply ripple feed-forward path; The second PMOS tube has a source connected to the drain of the first PMOS tube, a gate connected to the output end of the error amplifier and the load, and a drain grounded.

3. The linear regulator according to claim 1, characterized in that: The power supply ripple feed-forward path comprises: The first NMOS tube has a drain and a gate connected to a bias current source and a source grounded; An operational amplifier, one input end of which is connected to a bias current source and a gate of the first NMOS tube, and the other input end of which is connected to an output end; A first PMOS tube, with a source connected to a power supply, a gate connected to an output end of an operational amplifier, and a drain connected to components of a buffer; The first PMOS tube is a component shared by the power ripple feed-forward path and the buffer.

4. The linear regulator according to claim 3, characterized in that: The operational amplifier is a unit gain amplifier, and is used to copy the gate voltage of the first NMOS tube to the gate of the first PMOS tube.

5. The linear regulator according to claim 3, characterized in that: When the power supply changes, the gate voltage of the power transistor changes by ΔU mp for: ΔU mp =(g mp1 ×ΔVDD) / gm mp2 Among them, gm mp1 is the transconductance of the first PMOS tube, gm mp2 is the transconductance of the second PMOS tube, and ΔVDD is the change of the power supply.

6. The linear regulator according to claim 5, characterized in that: By adjusting the transconductance of the first PMOS tube and the transconductance of the second PMOS tube, the change in the gate voltage of the power transistor is equal to the change in the power supply.

7. The linear regulator according to any one of claims 1 to 6, characterized in that: Also includes: Miller compensation capacitor, connected between the output of the error amplifier and the load.

8. The linear regulator according to any one of claims 1 to 6, characterized in that: Also includes: The low-pass filter is connected to the output end of the error amplifier to filter the output voltage.

9. The linear regulator according to any one of claims 1 to 6, characterized in that: Also includes: The voltage-dividing resistor is connected in series at both ends of the load, and includes a first resistor and a second resistor; the first end of the first resistor is connected to the drain of the power transistor, the second end is connected to the first end of the second resistor, and the second end of the second resistor is grounded; and the first end of the second resistor is connected to the second input end of the error amplifier.

10. A phase-locked loop circuit, characterized in that: include: Voltage controlled oscillator; The linear regulator according to any one of claims 1 to 9, connected to a voltage controlled oscillator, for providing power to the voltage controlled oscillator.

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