Data recording methods, data recording devices, system-on-a-chip (SoC) and smart devices

Abstract

This application relates to the field of data processing technology and provides a data recording method, a data recording device, a system-on-a-chip (SoC), and a smart device. The data recording method includes: determining an update cycle for at least one target data set; periodically reading the target data set from a corresponding partition via shared memory, using the update cycle of each target data set as the cycle; and saving the read target data set to a second memory of a first processor; the storage space of the second memory is larger than the storage space of the first memory. This application enables efficient long-term recording of large amounts of collected data.

Description

Technical Field

[0001] This application belongs to the field of data processing technology, and in particular relates to a data recording method, a data recording device, a system-on-a-chip, and a smart device. Background Technology

[0002] To investigate the cause of an electronic control unit (ECU) malfunction, it is necessary to reconstruct the fault scene, including environmental data around the vehicle, diagnostic values, and ECU operating status. This data significantly improves problem analysis efficiency; the more data collected and the longer the time frame, the more efficient the problem localization will be.

[0003] However, microcontroller units (MCUs) have limited storage space, making it impossible to record large amounts of data or record data for extended periods. Furthermore, under certain abnormal operating conditions, MCUs are prone to losing their data recording capabilities, and some MCU data is difficult to record using the MCU itself. Therefore, how to efficiently achieve long-term recording of large amounts of acquired data is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This application provides a data recording method, a data recording device, a system-on-a-chip, and a smart device, which can efficiently achieve long-term recording of large amounts of collected data.

[0005] In a first aspect, embodiments of this application provide a data recording method, the data recording method comprising:

[0006] The update cycle of at least one target acquisition data is determined; at least one target acquisition data is stored in one or more partitions of the first memory of the system-on-a-chip, and the acquisition data located in the same partition has the same update cycle, wherein the first memory is the memory in the first processor of the system-on-a-chip;

[0007] The target data is periodically read from the corresponding partition via shared memory, based on the update cycle of the target data.

[0008] The collected data from each target is saved to a second memory; the storage space of the second memory is larger than that of the first memory, and the second memory is the memory in the second processor of the system-on-a-chip.

[0009] In the embodiments of this application, by determining the update cycle of at least one target acquisition data, the target acquisition data in the corresponding partition can be read periodically through shared memory with the update cycle of each target acquisition data as the cycle, thereby achieving lossless acquisition of each target acquisition data and no data loss, improving the reading efficiency of the target acquisition data. On this basis, the read target acquisition data is saved to a second memory with a larger storage space, which can efficiently realize long-term recording of a large amount of acquisition data.

[0010] Secondly, embodiments of this application provide a data recording method, the data recording method comprising:

[0011] Acquire one or more data points;

[0012] According to the update cycle of each of the collected data, each of the collected data is allocated to one or more partitions of the first memory; the collected data in the same partition have the same update cycle, and the first memory is the memory in the first processor of the system-on-a-chip.

[0013] The data update cycle is used to trigger the second processor of the system-on-a-chip to periodically read the data from the corresponding partition through shared memory and save the read data to the second memory. The storage space of the second memory is larger than that of the first memory, and the second memory is the memory in the second processor.

[0014] In this embodiment, by acquiring one or more data sets, each data set can be allocated to one or more partitions of the first memory according to its update cycle. Data sets in the same partition have the same update cycle. Based on this, the second processor of the system-on-a-chip can be triggered to periodically read the data set in the corresponding partition through shared memory and save the read data set to the second memory. The storage space of the second memory is larger than that of the first memory, thereby efficiently realizing long-term recording of a large amount of data set.

[0015] Thirdly, embodiments of this application provide a data recording device, which can be a device applied in a second processor of a system-on-a-chip or can serve as a second processor. The data recording device includes:

[0016] A period determination module is used to determine the update period of at least one target acquisition data; at least one target acquisition data is stored in one or more partitions of the first memory of the system-on-a-chip, and the acquisition data located in the same partition has the same update period; the first memory is the memory in the first processor of the system-on-a-chip.

[0017] The data reading module is used to periodically read the target data collected from the corresponding partition through shared memory, based on the update cycle of the target data collected.

[0018] A storage module is used to save the read target acquisition data into a second memory; the storage space of the second memory is larger than the storage space of the first memory, and the second memory is the memory in the second processor of the system-on-a-chip.

[0019] Fourthly, embodiments of this application provide a data recording device, which can be a device applied in a first processor of a system-on-a-chip or can serve as a first processor. The data recording device includes:

[0020] The data acquisition module is used to acquire one or more data sets.

[0021] The data allocation module is used to allocate each of the collected data to one or more partitions of the first memory according to the update cycle of each of the collected data; the update cycle of the collected data in the same partition is the same, and the first memory is the memory in the first processor of the system-on-a-chip;

[0022] The data update cycle is used to trigger the second processor of the system-on-a-chip to periodically read the data from the corresponding partition through shared memory and save the read data to the second memory. The storage space of the second memory is larger than that of the first memory, and the second memory is the memory in the second processor.

[0023] Fifthly, embodiments of this application provide a system-on-a-chip (SoC) comprising a first processor and a second processor, wherein the first processor is configured to execute the data recording method as described in the second aspect above, and the second processor is configured to execute the data recording method as described in the first aspect above.

[0024] Sixthly, embodiments of this application provide a smart device, the smart device including a system-on-a-chip as described in the fifth aspect above, or the smart device including a first processor and a second processor, the first processor being configured to execute the data recording method as described in the second aspect above, and the second processor being configured to execute the data recording method as described in the first aspect above.

[0025] In a seventh aspect, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a computer, implements the data recording method as described in the first aspect or the second aspect above.

[0026] Eighthly, embodiments of this application provide a computer program product, including a computer program, which, when run, causes the data recording method as described in the first or second aspect above to be executed.

[0027] It is understood that the beneficial effects of the third to eighth aspects mentioned above can be found in the relevant descriptions in the first and second aspects mentioned above, and will not be repeated here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is an example diagram of a data recording scenario;

[0030] Figure 2 This is a flowchart illustrating a data recording method provided in an embodiment of this application;

[0031] Figure 3 This is an example diagram of data that needs to be written to the file system, provided in an embodiment of this application.

[0032] Figure 4 This is a flowchart illustrating another data recording method provided in an embodiment of this application;

[0033] Figure 5 This is an example diagram of the collected data and partitions provided in the embodiments of this application;

[0034] Figure 6 This is an example architecture diagram of the data recording system provided in the embodiments of this application;

[0035] Figure 7 This is a schematic diagram of the structure of a data recording device provided in an embodiment of this application;

[0036] Figure 8 This is a schematic diagram of the structure of another data recording device provided in an embodiment of this application;

[0037] Figure 9 This is a schematic diagram of the structure of the system-on-a-chip provided in the embodiments of this application. Detailed Implementation

[0038] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0039] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0040] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0041] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0042] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0043] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0044] As an example rather than a limitation, such as Figure 1The diagram shows an example of a data recording scenario. The MCU monitors that the camera power supply is less than 9V (normal is 9-16V) and reports an undervoltage fault. Therefore, it's necessary to record multiple system voltages, power supply unit statuses, and the camera power supply voltage before and after the fault to investigate whether the undervoltage is the cause. If only sampling point 3 data is recorded, the failure location cannot be determined because an abnormality in the enable pin of power supply unit 1 or power supply unit 2 would cause an abnormal voltage at sampling point 3.

[0045] In the following scenarios, the MCU may have difficulty meeting the following requirements:

[0046] 1. Need to record large amounts of data or data for a long time: For complex central controllers or domain controllers, there may be hundreds or thousands of data points to be recorded, and the recording time may be several seconds or minutes. The MCU in the system on chip (SoC) of the central controller or domain controller is difficult to record large amounts of data or data for a long time.

[0047] 2. Under certain abnormal operating conditions, the MCU loses its data recording capability: When a core in a multi-core MCU experiences an abnormal interruption or a severe scheduling timeout, the MCU itself malfunctions and loses its normal data recording capability.

[0048] 3. Some MCU data is difficult to collect and save through the MCU itself: Direct access to sensitive data such as the stack by the MCU through business programs may cause system anomalies, while indirect access will generate additional complexity and data consistency risks.

[0049] To address the aforementioned technical problems, this application provides a data recording method. The second processor of the system-on-a-chip determines the update cycle of at least one target acquisition data and periodically reads the target acquisition data from the corresponding partition through shared memory, based on the update cycle of each target acquisition data. This achieves lossless acquisition of each target acquisition data and prevents data loss, thereby improving the reading efficiency of the target acquisition data. Furthermore, the read target acquisition data is saved to a second memory with a larger storage space, which can efficiently achieve long-term recording of a large amount of acquisition data.

[0050] Please see Figure 2 , Figure 2The illustration shows a flowchart of a data recording method provided in an embodiment of this application. This is an example and not a limitation. The method can be applied to smart devices (e.g., smart devices may include driving devices, smart cars, robots, etc.) or to a system-on-a-chip (SoC) within a smart device. Specifically, it can be applied to a second processor within a SoC. The method is described below using a second processor within a SoC as an example. Specifically, the method includes the following steps:

[0051] Step 201: The second processor in the system-on-a-chip determines the update cycle of at least one target acquisition data.

[0052] The target data collected refers to the data that needs to be recorded (i.e., the data that the second processor needs to collect or read from the first processor). The data collected from each target is stored in one or more partitions of the first memory of the system-on-a-chip (SoC). Data collected in the same partition has the same update cycle. The first memory is the memory within the first processor of the SoC. The update cycle of the collected data can refer to the update cycle of the collected data in the second processor. The aforementioned collected data can refer to data stored in partitions of the first memory, such as vehicle diagnostic data.

[0053] The first memory mentioned above can be any memory in the first processor, and this application does not limit the type of the first memory. By way of example and not limitation, the first memory can be random access memory (RAM) or static random access memory (SRAM).

[0054] It should be understood that, based on the fact that the storage space of the second memory of the second processor is larger than the storage space of the first memory, this application does not limit the type of the second memory, the type of the second processor, or the type of the second processor. By way of example and not limitation, the second memory can be Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), the second processor can be an Advanced Reduced Instruction Set Computer (ARM) in a system-on-a-chip, and the first processor can be an MCU in a system-on-a-chip.

[0055] A data recording module is deployed on the second processor, which can be set to start automatically upon system boot and run continuously. Accordingly, step 201 in this embodiment can be triggered by the second processor in the system-on-a-chip to determine the update cycle of at least one target acquisition data. Step 202 in this embodiment, described later, can be triggered by the second processor to periodically read the target acquisition data from the corresponding partition via shared memory, using the update cycle of each target acquisition data as the period. Step 203 in this embodiment, described later, can be triggered by the second processor to save the read target acquisition data to the second memory.

[0056] As an example rather than a limitation, the system-on-a-chip (SoC) is deployed on the vehicle terminal. After the vehicle terminal is powered on, the SoC powers on, and in this case, the data recording module on the second processor starts and runs continuously.

[0057] In one embodiment, the second processor can trigger the data recording module to load a configuration file upon startup, identifying the update cycle of each target data acquisition from the configuration file. The configuration file records information about each target data acquisition and the partition where each target data acquisition resides. For any target data acquisition, the information includes, but is not limited to, the name of the data acquisition, the address of the partition in the second processor, the type of data acquisition, the update cycle of the data acquisition in the second processor, the length of time the data should be retained before the trigger flag is triggered, the length of time the data should continue to be recorded after the trigger flag is triggered, the description of the data acquisition, and whether data acquisition needs to be enabled. Whether acquisition needs to be enabled can refer to whether the first processor is allowed to acquire data from the second processor. For any partition, the partition information includes, but is not limited to, the partition name, the partition start address, the partition end address, and the partition update cycle (i.e., the update cycle of the target data acquisition in the partition).

[0058] As an example and not a limitation, the first processor is the MCU in the system-on-a-chip, and the first memory is RAM. The partitions that the MCU divides in RAM can be called RAM partitions. In the configuration file, the information for each RAM partition can include the following four attributes: name, i.e., the name of the RAM partition; start_address, i.e., the starting address of the RAM partition; end_address, i.e., the ending address of the RAM partition; and period, i.e., the update period of the RAM partition. Each acquired data entry can include the following nine attributes: variable_name (name of the acquired data); address (address of the acquired data in the MCU's RAM partition); data_type (data type, including u8 / int8, u16 / int16, u32 / int32, u64 / int64, float); flag_name (trigger flag variable corresponding to the acquired data; if flag_name is "NA", it indicates that it is a trigger flag variable); period (update cycle of the acquired data in the MCU); pre_windows (length of time the data should be retained before the trigger flag variable is triggered); post_windows (length of time the data should continue to be recorded after the trigger flag variable is triggered); description (description of the acquired data); and enabled (whether acquisition needs to be enabled; if false, the second processor is not allowed to acquire this data from the first processor).

[0059] Step 202: The second processor periodically reads the target acquisition data from the corresponding partition through shared memory, based on the update cycle of the target acquisition data.

[0060] The second processor, through shared memory technology, is able to read the target acquisition data from the partition of the first processor.

[0061] For any target acquisition data, the second processor periodically reads the target acquisition data from the corresponding partition through shared memory, based on the update cycle of the target acquisition data. This ensures that the cycle in which the second processor reads the target acquisition data from the first processor is the same as the update cycle of the target acquisition data in the first processor. On this basis, it can be guaranteed that the target acquisition data read by the second processor from the first processor each time is the latest updated data (i.e., full reading of the target acquisition data is achieved), thereby realizing lossless reading of the target acquisition data by the second processor and ensuring that no data is lost, thus improving the reading efficiency of the target acquisition data.

[0062] As an example, and not a limitation, the target acquisition data is updated every 10 milliseconds in the first processor. To achieve full reading of the target acquisition data, the second processor needs to periodically read the target acquisition data from the corresponding partition of the first processor via shared memory every 10 milliseconds. If the second processor uses a 100-millisecond cycle, the target acquisition data in the first processor will be updated 10 times before the second processor reads the target acquisition data from the first processor only once, resulting in 9 updates of target acquisition data not being read by the second processor.

[0063] In one possible implementation, the second processor can read the target acquisition data in the following two ways.

[0064] Method 1: The second processor determines the number of update cycles for each target's collected data; based on the number of update cycles for each target's collected data, it creates a corresponding number of first threads or first processes; and it controls each first thread or first process to periodically read the target collected data from the corresponding partition through shared memory, with the update cycle of the corresponding target's collected data as the cycle.

[0065] The number of update cycles for each target data acquisition item can refer to the number of different update cycles for each target data acquisition item. As an example, and not a limitation, the number of target data acquisition items is four: target data acquisition 1, target data acquisition 2, target data acquisition 3, and target data acquisition 4. If the update cycles of these four target data acquisition items are all different, then the number of update cycles for these four target data acquisition items is four. If the update cycles of target data acquisition 1 and target data acquisition 2 are the same, but different from the update cycles of target data acquisition 3 and target data acquisition 4, and the update cycles of target data acquisition 3 and target data acquisition 4 are also different, then the number of update cycles for these four target data acquisition items is three.

[0066] In the first method described above, the second processor creates a corresponding number of first threads or first processes based on the number of update cycles for each target data acquisition cycle. This allows the processor to read target data acquisition cycles with different threads or processes, thereby improving the efficiency of reading target data acquisition.

[0067] In one embodiment, where a partition in the first processor is mapped to the address space of the second processor, and the access attribute of the mapped address space is read-only, the aforementioned control of each first thread or first process to periodically read the target acquisition data in the corresponding partition through shared memory based on the update cycle of the corresponding target acquisition data includes:

[0068] Each first thread or first process is controlled to read target data periodically from the mapped address space based on the update cycle of the target data and the address of the target data in the corresponding partition.

[0069] The second processor can identify the address of the target data in the corresponding partition from the configuration file.

[0070] A partition may contain multiple data collections, each with a different address within the partition. Therefore, based on the address of any target data collection in the corresponding partition, the mapped address space corresponding to that partition's address can be accurately located, allowing the target data collection to be accurately read from the mapped address space.

[0071] Method 2: The second processor can determine the number of partitions where each target data is located; based on the number of partitions where each target data is located, it creates a corresponding number of second threads or second processes; it controls each second thread or second process to periodically read the data from the corresponding partition through shared memory, taking the update cycle of the target data in the corresponding partition as the cycle, and to determine the target data from the data in the corresponding partition based on the address of the target data in the corresponding partition.

[0072] The number of partitions where the target data is located can refer to the number of different partitions where each target data is located. As an example, and not a limitation, the number of target data is four, namely target data 1, target data 2, target data 3, and target data 4. If these four target data are located in four different partitions, then the number of partitions where these four target data are located can be determined to be four. If target data 1 and target data 2 are located in the same partition, but in a different partition from target data 3 and target data 4, and target data 3 and target data 4 are also in a different partition, then the number of partitions where these four target data are located can be determined to be three.

[0073] In the second method described above, the second processor creates a corresponding number of second threads or second processes based on the number of partitions where the target acquisition data is located. This allows the processor to read the target acquisition data located in different partitions through different threads or processes, thereby improving the efficiency of reading the target acquisition data.

[0074] In one embodiment, when a partition in the first processor is mapped to the address space of the second processor, and the access attribute of the mapped address space is read-only, the above-mentioned control of each second thread or second process to periodically read the target acquisition data in the corresponding partition through the shared memory region based on the update cycle of the target acquisition data in the corresponding partition includes:

[0075] Each second thread or process is controlled to periodically read the collected data of the corresponding partition from the mapped address space based on the update cycle of the target collected data in the corresponding partition.

[0076] The second processor can identify the address of the partition where the target data is located from the configuration file.

[0077] Based on the address of the partition where any target acquisition data is located, the second processor can accurately find the mapped address space corresponding to the address of the partition, and thus accurately read the acquisition data in the partition from the mapped address space. The acquisition data in the partition includes the target acquisition data.

[0078] In both methods described above, the second processor can achieve shared memory between the first and second processors by mapping partitions in the first processor to its own address space. This allows the second processor to access the first processor, and applications in the second processor can directly read data from the partitions in the first processor. By setting the access attribute of the mapped address space to read-only, the second processor can prevent itself from interfering with the operation of the first processor.

[0079] Before mapping the partitions in the first processor to the address space, the second processor needs to obtain the partition information in the first processor. Only on this basis can the partition mapping be realized. Optionally, the partition information can be manually input into the second processor, sent by the first processor to the second processor, or identified by the second processor from a configuration file. This application does not limit the source of the partition information.

[0080] Step 203: The second processor saves the collected data from each target into the second memory.

[0081] The second memory has a larger storage space than the first memory. The second memory is the memory within the second processor.

[0082] It should be understood that although the storage space of the second memory is larger than that of the first memory, the storage space of the second memory is also limited. Therefore, in order to ensure that the latest target acquisition data is stored in the second memory, the second processor can save historical acquisition data for a certain period of time in the second memory in real time. When the historical acquisition data exceeds the set time, the historical acquisition data is discarded so that the latest target acquisition data can be saved in the second memory.

[0083] In one possible implementation, after saving the read target acquisition data to the second memory, the method further includes:

[0084] For any target acquisition data, monitor the state of the trigger flag variable of the target acquisition data; when the state of the trigger flag variable is switched to the trigger state, write the target acquisition data that meets the requirements stored in the second memory to the file system. The target acquisition data that meets the requirements refers to the target acquisition data stored in the second memory within the first time period before the switching time and the second time period after the switching time. The switching time is the moment when the state of the trigger flag variable is switched to the trigger state.

[0085] The trigger flag variable indicates whether to write the corresponding target acquisition data from the second memory to a file. The trigger state indicates whether to write the corresponding target acquisition data from the second memory to the local file system of the second processor. Compared to the second memory, the file system can be called external memory. External memory has a larger storage space, so saving the target acquisition data to external memory (i.e., sending the target acquisition data externally) can record more acquisition data and data for a longer period of time. Furthermore, it eliminates the need for external devices when sending target acquisition data externally.

[0086] In one embodiment, the configuration file may also record trigger flag variables for the target data acquisition. The second processor can identify the trigger flag variables for the target data acquisition from the configuration file, and based on this, monitor the status of the trigger flag variables for the target data acquisition.

[0087] It should be noted that the second processor has higher computing and data processing performance than the first processor (this is an example, not a limitation; the first processor is an MCU, which typically runs operating systems like AUTOSAR CP and FreeRTOS, unlike Windows and Linux systems which have strong connectivity; the development and iteration of these operating systems are very slow, resulting in lower computing and data processing performance; the second processor is RAM, which typically runs operating systems like Windows and Linux, which are easier to develop and have higher computing and data processing performance). Furthermore, the second processor has a file system, allowing it to write data to disk without needing to develop a dedicated transmission protocol to send data from the first processor. This reduces development and adaptation costs when requirements change. While sending large amounts of data outwards might affect the first processor's real-time performance, in this embodiment, sending large amounts of data outwards via the second processor does not affect the first processor's real-time performance. Moreover, the second processor's large data transmission does not depend on the first processor's operating system; therefore, even if the first processor's operating system malfunctions, it will not affect the second processor's data transmission.

[0088] Optionally, a first duration and a second duration can be set according to the needs of the scenario. For example, the first duration can be 10 seconds, and the second duration can be 5 seconds. Figure 3 The image shown is an example of data that needs to be written to the file system. Figure 3 The historical 10-second data in the data refers to the target acquisition data within the first time period before the switching time, and the next 5-second data refers to the target acquisition data within the second time period after the switching time.

[0089] In real-world scenarios, much of the target acquisition data stored in the second memory may be useless. Therefore, when a specific event occurs (in which case, the state of the trigger flag variable corresponding to the target acquisition data for that specific event switches to the trigger state), the target acquisition data for a period of time before and after the specific event can be written to the file system. This means writing useful data to the file system, thereby enabling long-term recording of useful data from a large number of different events. Once the writing to disk is complete, the acquisition and writing of data for a specific scenario is finished.

[0090] Optionally, when writing the target acquisition data to the file system, the file generated when writing the target acquisition data to the disk can be named based on the trigger flag variable and the current time. For example, the trigger flag variable + the current time can be used as the file name.

[0091] In one embodiment, the second processor can transmit the files created on the disk to the cloud for data analysis by after-sales analysts.

[0092] In this embodiment, the second processor of the system-on-a-chip determines the update cycle of at least one target acquisition data. It can periodically read the target acquisition data in the corresponding partition through shared memory based on the update cycle of each target acquisition data, thereby achieving lossless acquisition of each target acquisition data and preventing data loss, thus improving the reading efficiency of the target acquisition data. On this basis, the read target acquisition data is saved to a second memory with a larger storage space, which can efficiently realize long-term recording of a large amount of acquisition data.

[0093] Please see Figure 4 , Figure 4 This illustration shows a flowchart of another data recording method provided in an embodiment of this application. It is provided as an example and not as a limitation. This method can be applied to smart devices (e.g., smart devices may include driving devices, smart cars, robots, etc.) or to a system-on-a-chip (SoC) within a smart device. Specifically, it can be applied to a first processor within a SoC. The method is described below using a first processor within a SoC as an example. Specifically, the method includes the following steps:

[0094] Step 401: The first processor in the system-on-a-chip acquires one or more data sets.

[0095] It should be understood that this application does not limit the type of data collected. As an example and not a limitation, the aforementioned collected data may be environmental data surrounding the vehicle, or ECU operating status data, etc.

[0096] Step 402: The first processor allocates each collected data to one or more partitions of the first memory according to the update cycle of each collected data.

[0097] The data update cycle is used to trigger the second processor of the system-on-a-chip to periodically read the data collected in the corresponding partition through shared memory and save the read data to the second memory. The storage space of the second memory is larger than that of the first memory, and the second memory is the memory in the second processor.

[0098] The first processor can divide the first memory into at least two partitions and allocate the collected data to these pre-divided partitions. Collected data with different update cycles are allocated to different partitions, and the collected data within the same partition has the same update cycle. Of course, different collected data with the same update cycle can also be allocated to different partitions, and this application does not limit this.

[0099] It should be understood that spatial contiguousness between partitions is not required, but any collected data must be entirely contained within the same partition to ensure that collected data can be quickly read from the same partition.

[0100] like Figure 5 The diagram shown is an example of the data collection and partitioning provided in an embodiment of this application. Figure 5 The first processor divides the RAM into m RAM partitions, each RAM partition being allocated multiple data acquisitions. The 10 seconds in RAM partition 1 represents the duration of the data acquisition stored in RAM partition 1, meaning RAM partition 1 stores 10 seconds of data acquisition. The 20 seconds in RAM partitions 2 and n represent the duration of the data acquisition stored in RAM partitions 2 and n, meaning RAM partitions 2 and n store 20 seconds of data acquisition. 0x1000 0000 is the starting address of RAM partition 1, 0x1100 0000 is the starting address of RAM partition 2, 0x1900 0000 is the starting address of RAM partition n, and 0x2200 0000 is the starting address of RAM partition m.

[0101] In one possible implementation, each piece of collected data has a trigger flag variable;

[0102] When the first processor detects an event that the target data in one or more data sets is written to disk, it switches the state of the trigger flag variable corresponding to the target data to the trigger state.

[0103] The trigger state is used to trigger the second processor to write the target acquisition data that meets the requirements stored in the second memory to the file system. The target acquisition data that meets the requirements refers to the target acquisition data stored in the second memory within the first time period before the switching time and the second time period after the switching time. The switching time is the moment when the state of the trigger flag variable is switched to the trigger state.

[0104] After the first processor has partitioned the system and allocated the collected data to different partitions, the information of the data to be recorded (i.e., the target data) and the corresponding partition information can be saved to a configuration file. The configuration file also records a trigger flag variable for each target data. Based on this, the second processor can record the target data according to the configuration file. Optionally, the configuration file can be manually set.

[0105] The first processor notifies the second processor to write data to disk by updating the state of the trigger flag variable, thus enabling precise data capture.

[0106] Optionally, the aforementioned chassis-dropping events include, but are not limited to, specific events such as malfunction events or entering a scenario requiring data recording. As an example, and not a limitation, for a scenario where the user wants to record the chassis system's performance during emergency braking, a trigger flag variable can be created. This trigger flag variable is used to monitor the vehicle's emergency braking. When an emergency braking event is detected, the first processor switches the trigger flag variable to the triggered state. At this time, the second processor records data such as the chassis system's cylinder pressure, wheel speed, and motor speed.

[0107] like Figure 6 The diagram shown is an example of the architecture of the data recording system provided in this application embodiment. Figure 6 The first processor in the system-on-a-chip divides the RAM into multiple partitions and allocates the collected data from different update cycles to different partitions. Based on this, the second processor in the system-on-a-chip can trigger the data recording module to periodically read the data in each partition through shared memory technology, and when a specific event occurs, write the collected data before and after the specific event to the local file system of the second processor, and transfer the file formed by writing to the disk to the cloud for after-sales analysts to perform data analysis.

[0108] In this embodiment, the first processor in the system-on-a-chip acquires one or more data sets and stores each data set in one or more partitions of the first memory according to the update cycle of each data set. The data sets in the same partition have the same update cycle. Based on this, the second processor of the system-on-a-chip can be triggered to periodically read the data set in the corresponding partition through shared memory and save the read data set to the second memory. The storage space of the second memory is larger than that of the first memory, thereby efficiently realizing long-term recording of a large amount of data set.

[0109] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0110] Corresponding to the data recording method described in the above embodiments, Figure 7 A schematic diagram of a data recording device provided in an embodiment of this application is shown. The data recording device can be a device applied in a second processor of a system-on-a-chip or the data recording device can be used as a second processor. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0111] Reference Figure 7 The device includes:

[0112] The period determination module 701 is used to determine the update period of at least one target acquisition data; at least one target acquisition data is stored in one or more partitions of the first memory of the system-on-a-chip, and the acquisition data located in the same partition have the same update period; the first memory is the memory in the first processor of the system-on-a-chip.

[0113] The data reading module 702 is used to periodically read the target data collected from the corresponding partition through shared memory, based on the update cycle of each target data collection period.

[0114] A storage module is used to save the read target acquisition data to a second memory; the storage space of the second memory is larger than the storage space of the first memory, and the second memory is the memory in the second processor of the system-on-a-chip.

[0115] Optionally, the above-mentioned device further includes:

[0116] The first determining module is used to determine the number of update cycles for the data collected from each target.

[0117] The aforementioned data reading module 702 includes:

[0118] The first creation unit is used to create a corresponding number of first threads or first processes based on the number of update cycles of the data collected from each target.

[0119] The first control unit is used to control each of the first threads or the first process to periodically read the target acquisition data in the corresponding partition through shared memory, based on the update cycle of the target acquisition data.

[0120] Optionally, when a partition in the first processor is mapped to the address space of the second processor, and the access attribute of the mapped address space is read-only, the aforementioned first control unit is specifically used for:

[0121] Each of the first threads or the first processes is controlled to periodically read the target data from the mapped address space based on the address of the target data in the corresponding partition, with the update cycle of the target data as the corresponding update cycle.

[0122] Optionally, the above-mentioned device further includes:

[0123] The second determining module is used to determine the number of partitions where the target data is located;

[0124] Optionally, the data reading module 702 mentioned above includes:

[0125] The second creation unit is used to create a corresponding number of second threads or second processes based on the number of partitions where the target data is located;

[0126] The second control unit is used to control each of the second threads or the second process to periodically read the acquisition data of the corresponding partition through shared memory, based on the update cycle of the target acquisition data in the corresponding partition, and to determine the target acquisition data from the acquisition data of the corresponding partition based on the address of the target acquisition data in the corresponding partition.

[0127] Optionally, when a partition in the first processor is mapped to the address space of the second processor, and the access attribute of the mapped address space is read-only, the second control unit is specifically used for:

[0128] Each of the second threads or the second processes is controlled to periodically read the collected data of the corresponding partition from the mapped address space, based on the update cycle of the target collected data in the corresponding partition and the address of the partition where the target collected data is located.

[0129] Optionally, the above-mentioned device further includes:

[0130] The status monitoring module is used to monitor the status of the trigger flag variable of any of the target data collection data.

[0131] The disk-to-disk module is used to write the target acquisition data that meets the requirements stored in the second memory to the file system when the state of the trigger flag variable is switched to the trigger state. The target acquisition data that meets the requirements refers to the target acquisition data stored in the second memory within a first time period before the switching time and a second time period after the switching time. The switching time is the moment when the state of the trigger flag variable is switched to the trigger state.

[0132] Corresponding to the data recording method described in the above embodiments, Figure 8 A schematic diagram of another data recording device provided in an embodiment of this application is shown. The data recording device can be a device applied in a first processor of a system-on-a-chip or the data recording device can be used as a first processor. For ease of explanation, only the parts related to the embodiments of this application are shown.

[0133] Reference Figure 8 The device includes:

[0134] Data acquisition module 801 is used to acquire one or more data points.

[0135] The data allocation module 802 is used to allocate each of the collected data to one or more partitions of the first memory according to the update cycle of each of the collected data; the update cycle of the collected data in the same partition is the same, and the first memory is the memory in the first processor of the system-on-a-chip;

[0136] The data update cycle is used to trigger the second processor of the system-on-a-chip to periodically read the data from the corresponding partition through shared memory and save the read data to the second memory. The storage space of the second memory is larger than that of the first memory, and the second memory is the memory in the second processor.

[0137] Optionally, any of the acquired data has a trigger flag variable; the above-mentioned device further includes:

[0138] The state switching module is used to switch the state of the trigger flag variable corresponding to the target data to the trigger state when an event for disk placement of target data in one or more of the collected data is detected.

[0139] The trigger state is used to trigger the second processor to write the target acquisition data that meets the requirements stored in the second memory to a file. The target acquisition data that meets the requirements refers to the target acquisition data stored in the second memory within a first time period before the switching time and a second time period after the switching time. The switching time is the time when the state of the trigger flag variable is switched to the trigger state.

[0140] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0141] Figure 9 This is a schematic diagram of the structure of a system-on-a-chip provided in an embodiment of this application. Figure 9 As shown, the system-on-a-chip 9 in this embodiment includes: a first processor 901 and a second processor 902. The first processor 901 is used to perform the above-described... Figure 4 In the method embodiment shown, the second processor 902 is used to perform the steps as follows: Figure 2 The steps in the method embodiment shown.

[0142] This system-on-a-chip may include, but is not limited to, a first processor 901 and a second processor 902. Those skilled in the art will understand that... Figure 9 This is merely an example of a system-on-a-chip (SoC) and does not constitute a limitation on SoCs. It may include more or fewer components than shown, or combine certain components, or use different components.

[0143] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0144] This application embodiment also provides a smart device, the smart device including the features described above. Figure 9The system-on-a-chip, or the smart device, includes a first processor and a second processor, wherein the first processor is used to perform the above-described... Figure 4 The data recording method described above, wherein the second processor is used to execute the above-described data recording method. Figure 2 The data recording method described above.

[0145] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / electronic device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0146] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0147] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0148] In the embodiments provided in this application, it should be understood that the disclosed device / system-on-a-chip and method can be implemented in other ways. For example, the device / system-on-a-chip embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0149] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0150] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A data recording method characterized by, The data recording method comprises: determining an update period of at least one target acquisition data; the at least one target acquisition data is stored in one or more partitions of a first memory of a system on chip, and the update periods of the acquisition data in the same partition are the same; the first memory is a memory in a first processor of the system on chip; periodically reading the target acquisition data in the corresponding partition through shared memory with the update period of each target acquisition data as a period; saving each target acquisition data read in a second memory; the storage space of the second memory is larger than that of the first memory, and the second memory is a memory in a second processor of the system on chip; before the periodically reading the target acquisition data in the corresponding partition through shared memory with the update period of each target acquisition data as a period, further comprising: determining the number of update periods of each target acquisition data; the periodically reading the target acquisition data in the corresponding partition through shared memory with the update period of each target acquisition data as a period, comprising: creating a corresponding number of first threads or first processes based on the number of update periods of each target acquisition data; controlling each first thread or first process to periodically read the target acquisition data in the corresponding partition through shared memory with the update period of the corresponding target acquisition data as a period; or, before the periodically reading the target acquisition data in the corresponding partition through shared memory with the update period of each target acquisition data as a period, further comprising: determining the number of partitions in which each target acquisition data is located; the periodically reading the target acquisition data in the corresponding partition through shared memory with the update period of each target acquisition data as a period, comprising: creating a corresponding number of second threads or second processes based on the number of partitions in which each target acquisition data is located; controlling each second thread or second process to periodically read the acquisition data in the corresponding partition through shared memory with the update period of the target acquisition data in the corresponding partition as a period, and determining the target acquisition data from the acquisition data in the corresponding partition based on the address of the target acquisition data in the corresponding partition.

2. The data recording method according to claim 1, characterized by, in the case where the partition in the first processor is mapped to the address space of the second processor, and the access attribute of the mapped address space is a read-only attribute, the controlling each first thread or first process to periodically read the target acquisition data in the corresponding partition through shared memory with the update period of the corresponding target acquisition data as a period, comprising: controlling each first thread or first process to periodically read the target acquisition data from the mapped address space based on the address of the target acquisition data in the corresponding partition with the update period of the corresponding target acquisition data as a period.

3. The data recording method according to claim 1, wherein In the case that the partition in the first processor is mapped to the address space of the second processor, and the access attribute of the mapped address space is a read-only attribute, the control is periodically performed on each of the second threads or the second processes with the update period of the target acquisition data in the corresponding partition as a period, and the acquisition data in the corresponding partition is read through the shared memory, including: The control is periodically performed on each of the second threads or the second processes with the update period of the target acquisition data in the corresponding partition as a period, and the acquisition data in the corresponding partition is read from the mapped address space based on the address of the partition in which the target acquisition data is located.

4. The data recording method according to any one of claims 1 to 3, characterized by, After the reading of each of the target acquisition data is saved to the second memory, the method further includes: For any target acquisition data, the state of a trigger flag variable of the target acquisition data is monitored; In the case that the state of the trigger flag variable is switched to a trigger state, the target acquisition data meeting the requirement saved in the second memory is flushed to the file system, the target acquisition data meeting the requirement refers to the target acquisition data stored in the second memory within a first time length before a switching time and within a second time length after the switching time, and the switching time is the time when the state of the trigger flag variable is switched to the trigger state.

5. A data recording method characterized by, The data recording method includes: one or more acquisition data are acquired; each of the acquisition data is allocated to one or more partitions of a first memory according to the update period of each of the acquisition data, the update period of the acquisition data in the same partition is the same, and the first memory is a memory in a first processor of a system on chip; The update period of the acquisition data is used to trigger a second processor of the system on chip to periodically read the acquisition data in the corresponding partition through the shared memory and save the read acquisition data to a second memory, the storage space of the second memory is greater than that of the first memory, the second memory is a memory in the second processor; any of the acquisition data has a trigger flag variable, and the data recording method further includes: In the case that a flushing event for target acquisition data in the one or more acquisition data is detected, the state of the trigger flag variable corresponding to the target acquisition data is switched to a trigger state; The trigger state is used to trigger the second processor to flush the target acquisition data meeting the requirement saved in the second memory to the file system, the target acquisition data meeting the requirement refers to the target acquisition data stored in the second memory within a first time length before a switching time and within a second time length after the switching time, and the switching time is the time when the state of the trigger flag variable is switched to the trigger state.

6. A data recording apparatus, characterized by comprising: The data recording device includes: a period determination module configured to determine an update period of at least one target collection data; the at least one target collection data is stored in one or more partitions of a first memory of a system on chip, and collection data in a same partition has a same update period; the first memory is a memory in a first processor of the system on chip; a data reading module configured to periodically read the target collection data in a corresponding partition through a shared memory with a period of the update period of each target collection data; a storage module configured to save each read target collection data into a second memory; a storage space of the second memory is larger than a storage space of the first memory; the second memory is a memory in a second processor of the system on chip; the data recording apparatus further comprises: a first determination module configured to determine a number of the update periods of each target collection data; the data reading module comprises: a first creation unit configured to create a corresponding number of first threads or first processes based on the number of the update periods of each target collection data; a first control unit configured to control each first thread or first process to periodically read the target collection data in a corresponding partition through a shared memory with a period of the update period of the corresponding target collection data; alternatively, the data recording apparatus further comprises: a second determination module configured to determine a number of partitions in which each target collection data is located; the data reading module comprises: a second creation unit configured to create a corresponding number of second threads or second processes based on the number of the partitions in which each target collection data is located; a second control unit configured to control each second thread or second process to periodically read collection data in a corresponding partition through a shared memory with a period of the update period of the target collection data in the corresponding partition, and determine the target collection data from the collection data in the corresponding partition based on an address of the target collection data in the corresponding partition.

7. A data recording apparatus, characterized by comprising: the data recording apparatus comprises: a data acquisition module configured to acquire one or more collection data; a data distribution module configured to distribute each collection data to one or more partitions of a first memory according to an update period of each collection data; the collection data in a same partition has a same update period; the first memory is a memory in a first processor of a system on chip; wherein the update period of the collection data is used to trigger a second processor of the system on chip to periodically read the collection data in a corresponding partition through a shared memory, and save each read collection data into a second memory; a storage space of the second memory is larger than a storage space of the first memory; the second memory is a memory in the second processor; any collection data has a trigger flag variable; the data recording apparatus further comprises: a state switching module configured to switch a state of the trigger flag variable corresponding to a target collection data to a trigger state when a discarding event of the target collection data is detected from one or more collection data. The trigger state is used to trigger the second processor to write the target acquisition data meeting the requirement saved in the second memory to a file system, the target acquisition data meeting the requirement refers to target acquisition data stored in the second memory within a first time length before a switching time and within a second time length after the switching time, and the switching time is a time when the state of the trigger flag variable is switched to the trigger state.

8. A system on chip, comprising: The system on chip includes a first processor configured to perform the data recording method of claim 5, and a second processor configured to perform the data recording method of any one of claims 1 to 4.

9. A smart device, comprising: The smart device includes the system on chip of claim 8, or the smart device includes a first processor configured to perform the data recording method of claim 5, and a second processor configured to perform the data recording method of any one of claims 1 to 4.

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