Resource configuration method, apparatus, device, and storage medium

Abstract

According to embodiments of the present disclosure, a method, an apparatus, a device and a storage medium for resource configuration are provided. The method comprises obtaining an indication of a number of nodes for NUMA nodes of a processor socket; dividing, based on the number of nodes, an acceleration resource of an accelerator into at least one acceleration resource queue; and causing a plurality of processor cores divided to a corresponding NUMA node to use the at least one acceleration resource queue based on an association of the at least one acceleration resource queue to the corresponding NUMA node comprised by the processor socket. In this way, the availability of the accelerator can be improved.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein relate generally to the field of computers, and more particularly to resource allocation methods, apparatus, devices, and computer-readable storage media. Background Technology

[0002] Accelerators are currently widely used in computing devices. They enable a wide variety of functions, such as artificial intelligence (AI) inference and encryption / decryption tasks. Compared to processor cores, accelerators often process specific tasks more efficiently, while also offering significant advantages in power consumption and area. Accelerators in computing devices can be scheduled in the following way: applications run on the processor cores of the computing device, and the processor cores invoke accelerators to accelerate various tasks or operations within those applications. Therefore, how the processor cores schedule the acceleration resources provided by accelerators to improve the processing performance of the computing device is of great interest. Summary of the Invention

[0003] In a first aspect of this disclosure, a resource allocation method is provided. The method includes: obtaining an indication of the number of Non-Uniform Memory Access (NUMA) nodes for a processor socket; dividing acceleration resources of an accelerator into at least one acceleration resource queue based on the number of nodes; and enabling multiple processor cores assigned to the corresponding NUMA nodes to use the at least one acceleration resource queue based on the association by associating the at least one acceleration resource queue with a corresponding NUMA node contained in the processor socket.

[0004] In a second aspect of this disclosure, a resource allocation apparatus is provided. The apparatus includes: an acquisition module configured to acquire an indication of the number of NUMA nodes for non-uniform memory access to a processor socket; a partitioning module configured to partition acceleration resources of an accelerator into at least one acceleration resource queue based on the number of nodes; and an invocation module configured to associate the at least one acceleration resource queue with a corresponding NUMA node contained in the processor socket, such that multiple processor cores partitioned to the corresponding NUMA node use the at least one acceleration resource queue based on the association.

[0005] In a third aspect of this disclosure, an electronic device is provided. The device includes at least one processing unit; and at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit. When executed by the at least one processing unit, the instructions cause the device to perform the method of the first aspect.

[0006] In a fourth aspect of this disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program that can be executed by a processor to implement the method of the first aspect.

[0007] It should be understood that the content described in this content section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0008] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0009] Figure 1 A schematic diagram of an example environment in which embodiments of the present disclosure can be implemented is shown;

[0010] Figure 2 A schematic diagram illustrating the process of a resource allocation method according to some embodiments of the present disclosure is shown;

[0011] Figure 3 A schematic diagram illustrating the association between NUMA nodes and acceleration resource queues according to some embodiments of the present disclosure is shown;

[0012] Figure 4 A schematic diagram illustrating the process of an application invoking acceleration resources according to some embodiments of the present disclosure is shown;

[0013] Figure 5 A block diagram of a resource configuration apparatus according to some embodiments of the present disclosure is shown; and

[0014] Figure 6 A block diagram of an apparatus capable of implementing several embodiments of the present disclosure is shown. Detailed Implementation

[0015] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0016] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0017] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0018] As briefly mentioned earlier, accelerators are widely used in computing devices. How processor cores schedule the acceleration resources provided by accelerators to improve the processing performance of computing devices is a key concern. Currently, processors typically employ a Non-uniform memory access (NUMA) architecture. In this architecture, different memory devices and processor cores belong to different NUMA nodes. Each NUMA node contains one or more processor cores, and each NUMA node has its own Integrated Memory Controller (IMC). With advancements in semiconductor manufacturing processes and the widespread application of chiplet technology, the number of NUMA nodes that need to be split on a single processor socket is increasing. That is, multiple processor cores on a single processor socket are split into multiple different NUMA nodes. In this scenario, how accelerators are used by the processor cores within NUMA nodes warrants discussion.

[0019] When accelerators access memory across NUMA nodes, significant latency issues arise due to interconnection limitations between processor sockets or dies. Here, a socket or die refers to the packaged unit of a processor core. Typically, a socket can contain multiple dies, and each die can package multiple processor cores.

[0020] To avoid this problem, the common practice in current computing devices is to configure accelerators with corresponding NUMA nodes and restrict the processor cores using the accelerators to be within the same NUMA node. In this approach, an accelerator can only be used by processor cores within its own NUMA node and cannot be used by processor cores in other NUMA nodes. Therefore, this approach suffers from the problem of restricted accelerator usage.

[0021] For example, multiple processor cores in a processor socket are divided into four NUMA nodes: NUMA0, NUMA1, NUMA2, and NUMA3, and the corresponding NUMA node configured for the accelerator is NUMA1. Therefore, only the processor cores in NUMA1 can use the accelerator, while the processor cores in other NUMA nodes cannot.

[0022] To address the issue of limited accelerator usage, another approach involves adjusting NUMA configurations through accelerator software and then allocating accelerator usage so that processor cores across multiple NUMA nodes can utilize the accelerators. This approach requires configuring complex software logic. Furthermore, the software needs to dynamically check the current NUMA configuration of the computing device and dynamically allocate accelerator usage based on that configuration. This further increases the complexity of the software configuration.

[0023] To at least partially address the problems existing in current solutions, this solution proposes a resource allocation scheme. In this scheme, the computing device obtains an indication of the number of NUMA nodes for a processor socket. Based on this number of nodes, the accelerator's acceleration resources are divided into at least one acceleration resource queue. Then, by associating the at least one acceleration resource queue with a corresponding NUMA node, multiple processor cores assigned to that NUMA node can use the at least one acceleration resource queue based on this association. In this way, multiple NUMA nodes can use the corresponding acceleration resource queue. This improves the availability of the accelerator. Furthermore, in this embodiment, the above resource allocation can be completed through firmware, thereby reducing the development difficulty of the accelerator software.

[0024] Figure 1A schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented is shown. In environment 100, one or more applications 120 may be installed on computing device 110. Applications 120 may be, for example, applications for file decompression, applications for graphics processing, etc. Embodiments of the present disclosure do not limit the type and number of applications. Applications 120 run on the processor cores of computing device 110. In embodiments of the present disclosure, the processor architecture of computing device 110 may adopt the NUMA architecture mentioned above, that is, multiple processor cores in the processor socket are divided into multiple NUMA nodes.

[0025] In some cases, application 120 needs to perform tasks such as AI inference and encryption / decryption. The processor core running this application can use an accelerator to perform these tasks. In this embodiment, the number of accelerators can be one or more. Furthermore, accelerators can include those that manipulate data, such as vector accelerators and AI accelerators. Accelerators can also include those that execute specific algorithms on dedicated hardware, such as encryption accelerators, compression accelerators, and graphics accelerators. This embodiment does not limit the type or number of accelerators.

[0026] In some embodiments of this disclosure, an accelerator may be presented as a platform device comprising multiple acceleration resources. The multiple acceleration resources in an accelerator may be divided into multiple acceleration resource queues.

[0027] The computing device 110 may also display an interface 140. The user 130 can perform interactive operations through this interface 140, such as operating the application 120.

[0028] In some embodiments of this disclosure, user 130 can also configure the number of NUMA nodes based on the interface 140 presented by computing device 110. Then, computing device 110 can divide the accelerator's acceleration resources into multiple acceleration resource queues based on the number of NUMA nodes, and establish associations between NUMA nodes and acceleration resource queues so that NUMA nodes can use the corresponding acceleration resource queues. The specific implementation is detailed below.

[0029] In environment 100, computing device 110 can be any type of computing-capable device, including computing devices or server devices. Computing devices can be any type of mobile terminal, fixed terminal, or portable terminal, including mobile phones, desktop computers, laptop computers, notebook computers, netbook computers, tablet computers, media computers, multimedia tablets, personal communication system (PCS) devices, personal navigation devices, personal digital assistants (PDAs), audio / video players, digital cameras / camcorders, positioning devices, television receivers, radio receivers, e-book devices, gaming devices, or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof. Server devices may include, for example, computing systems / servers, such as mainframes, edge computing nodes, computing devices in cloud environments, and so on.

[0030] It should be understood that the structure and function of environment 100 are described for illustrative purposes only and do not imply any limitation on the scope of this disclosure.

[0031] The following description will continue with reference to the accompanying drawings, which will provide some exemplary embodiments of this disclosure.

[0032] Figure 2 A flowchart of a resource configuration process 200 according to some embodiments of the present disclosure is shown. Process 200 may be implemented at computing device 110. Reference is made below. Figure 1 Describe the process 200.

[0033] In box 210, computing device 110 obtains an indication of the number of NUMA nodes for the processor socket.

[0034] As mentioned earlier, processors can employ a NUMA architecture. In this architecture, multiple processor cores in a processor socket can be divided into multiple NUMA nodes. A NUMA node can include one or more processor cores.

[0035] In some embodiments, the computing device 110 may present an entry point for setting the number of NUMA nodes. This entry point may be, for example, a configuration item or configuration menu presented by the computing device. The user can use this entry point to instruct the user to configure the number of NUMA nodes. Accordingly, the computing device 110 can obtain the number of NUMA nodes indicated by the user through this entry point.

[0036] In some embodiments, the computing device 110 can obtain an indication of the number of NUMA nodes through an entry provided by the firmware. For example, a preset configuration item can be presented in the firmware's boot menu, which the user can configure to indicate the number of NUMA nodes.

[0037] As an example, the firmware boot mode in this embodiment can be the Unified Extensible Firmware Interface (UEFI) mode. Firmware in this mode can also be referred to as UEFI firmware. It is understood that UEFI is merely an example, and the firmware boot mode can also be other modes, such as BIOS mode. This embodiment does not limit the scope of the invention.

[0038] As an example, the boot menu of the UEFI firmware defines an option for how many NUMA nodes (PS) each socket contains. Users can manually select the number of NUMA nodes per socket, i.e., set the number of NUMA nodes that can be allocated to each socket. Furthermore, the configuration of this (NUMA Per Socket) option, i.e., the number of NUMA nodes, can be stored in the Advanced Configuration and Power Interface (ACPI) table.

[0039] In some embodiments, the computing device 110 may also divide multiple processor cores associated with processor sockets into corresponding NUMA nodes based on the number of nodes.

[0040] For example, in response to the NUMA Per Socket option being set to M, where M is a positive integer, the multiple processor cores in the processor socket are divided into M NUMA nodes. The specific process of dividing the processor cores based on the number of NUMA nodes can be, for example, an average division method, where each NUMA node contains an equal number of processor cores. This disclosure does not limit the specific configuration implementation of the NUMA nodes.

[0041] In this embodiment of the disclosure, the number of nodes obtained by the computing device 110, in addition to being used to partition NUMA nodes, can also be used to partition acceleration resources provided by the accelerator and establish the association between the partitioned acceleration resource queue and the NUMA nodes. See the following description of boxes 220 and 230 for details.

[0042] In box 220, computing device 110 divides the accelerator's acceleration resources into at least one acceleration resource queue based on the number of nodes.

[0043] Accelerators typically use queues as an interface for application interaction, with each queue having corresponding registers for application operation. In this embodiment, firmware can be used to present these queues as independent devices.

[0044] In other words, as mentioned earlier, an accelerator can be presented as a platform device containing multiple acceleration resources. These multiple acceleration resources within an accelerator can be divided into multiple acceleration resource queues and presented as independent devices. That is, an accelerator can be further subdivided into smaller granularities.

[0045] In some embodiments, in response to dividing the processor cores in the processor socket into M NUMA nodes, the acceleration resources provided by an accelerator can be divided into N acceleration resource queues. Both M and N are positive integers. The value of N can be equal to M. That is, when the number of NUMA nodes is M, the number of acceleration resource queues can also be M. Of course, in some cases, the number of acceleration resource queues N may not be equal to M, for example, N may be greater than M or less than M.

[0046] In some embodiments, the number of acceleration resources in each of the divided acceleration resource queues can be the same or different. For example, if the number of processor cores in each NUMA node is the same, then the number of acceleration resources in each acceleration resource queue can also be the same. Alternatively, if the number of processor cores in each NUMA node is different, the acceleration resource queues can be divided according to the number of processor cores in different NUMA nodes. Specifically, the number of acceleration resources in an acceleration resource queue can be proportional to the number of processor cores in the associated corresponding NUMA node. Thus, some acceleration resource queues may have more acceleration resources, and an association can be established between that acceleration resource queue and the NUMA node with a larger number of processor cores. The acceleration resources in that acceleration resource queue can be used by the processor cores in that NUMA node. This disclosure does not limit the strategy for dividing acceleration resources in acceleration resource queues.

[0047] In some embodiments, acceleration resources within an accelerator are identified by different numbers. For example, see [reference]. Figure 3 The acceleration resource queue 0-11 indicates that the acceleration resource queue contains acceleration resources numbered 0-11. Similarly, Figure 3 The additional resources included in other acceleration resource queues can be deduced similarly, and will not be listed in this embodiment.

[0048] Next, by presenting the accelerator as an acceleration resource queue, compatibility with different NUMA configurations can be achieved. See box 230 for details.

[0049] In block 230, computing device 110 enables multiple processor cores assigned to a corresponding NUMA node to use the at least one acceleration resource queue based on the association by associating at least one acceleration resource queue with the corresponding NUMA node contained in the processor socket.

[0050] By associating the acceleration resource queue with NUMA nodes, compatibility with different NUMA configurations can be achieved. For example, a single socket can be configured to include one NUMA node, two NUMA nodes, or four NUMA nodes. Under each NUMA configuration, the acceleration resource queue can be associated with the corresponding NUMA node, ensuring that the accelerator can be used by all NUMA nodes in each configuration.

[0051] In some embodiments, the relationship between acceleration resource queues and NUMA nodes can be one-to-one. That is, the number of acceleration resource queues is the same as the number of NUMA nodes. An acceleration resource queue can be associated with a NUMA node and used by the processor cores within that NUMA node.

[0052] For example, see reference. Figure 3 Box 310 in the diagram. When the NPS value is 1, it means the processor socket contains only one NUMA node, NUMA0. Acceleration resources in the accelerator are identified by numbers 0-23. An acceleration resource queue 0-23 is also allocated, which can be used by the processor cores in NUMA0. (See reference...) Figure 3 Box 320 in the diagram. When the NPS value is 2, it means the processor socket contains two NUMA nodes, NUMA0 and NUMA1. Correspondingly, the accelerator is also divided into two acceleration resource queues (acceleration resource queues 0-11 and 12-23). ​​Acceleration resource queues 0-11 can be used by the processor cores of NUMA0, and acceleration resource queues 12-23 can be used by the processor cores of NUMA1. (See reference...) Figure 3 Box 330 in the diagram. When the NPS value is 4, it means the processor socket contains four NUMA nodes: NUMA0, NUMA1, NUMA2, and NUMA3. Correspondingly, the accelerator is also divided into four acceleration resource queues (acceleration resource queues 0-5, 6-11, 12-17, and 18-23). ​​Acceleration resource queues 0-5 can be used by the processor cores of NUMA0, acceleration resource queues 6-11 can be used by the processor cores of NUMA1, acceleration resource queues 12-17 can be used by the processor cores of NUMA2, and acceleration resource queues 18-23 can be used by the processor cores of NUMA3.

[0053] Understandably, in Figure 3In the example, with multiple NUMA nodes, each NUMA node contains the same number of processor cores. Correspondingly, the amount of acceleration resources allocated to each NUMA node is the same. This is merely one example of partitioning NUMA nodes and allocating acceleration resource queues. In other examples, the number of processor cores in different NUMA nodes can differ, and consequently, the number of acceleration resources in the acceleration resource queues allocated to different NUMA nodes can also differ. For example, a NUMA node with a larger number of processor cores can have a larger acceleration resource queue. Furthermore, the correspondence between NUMA node identifiers and acceleration resource queue identifiers is not limited. In other examples, such as for NPS=4, the acceleration resource queue allocated to NUMA0 could also be an acceleration resource queue consisting of acceleration resources 6-11.

[0054] In some embodiments, the relationship between acceleration resource queues and NUMA nodes is not necessarily one-to-one. For example, a NUMA node with a large number of processor cores may be allocated two acceleration resource queues. Conversely, some NUMA nodes with fewer processor cores may share the same acceleration resource queue. Of course, these NUMA nodes sharing the same acceleration resource queue may also need to meet other conditions, such as the access latency of the accelerator when accessing memory from different NUMA nodes needing to meet a certain threshold.

[0055] In some embodiments, the computing device 110 may also generate a description of the established associations based on the association between at least one acceleration resource queue and its corresponding NUMA node. This description at least indicates the corresponding identifier of the at least one acceleration resource queue associated with the corresponding NUMA node. Thus, if at least one core within a NUMA node (also referred to as a first node) is to use an accelerator, the description can be used to determine the first acceleration resource queue allocated to that first node, and the at least one core can then utilize the acceleration resources in that first acceleration resource queue for acceleration.

[0056] As an example, the ACPI table mentioned earlier includes the Differentiated System Description Table (DSDT). NUMA node information can be configured in the ACPI table, and the firmware will then configure the association between the acceleration resource queue identifier and the NUMA node identifier in the DSDT table. This allows software processes running on different NUMA nodes to use the corresponding acceleration resource queues. For example, with NPS set to 1 by default, accelerators are assigned to the current NUMA node, and a description of the association between the accelerator and that NUMA node is generated in the DSDT.

[0057] In some cases, the number of NUMA nodes can be adjusted. For example, a user might change the NPS value based on actual needs. In response to this change in the number of NUMA nodes, the association between at least one acceleration resource queue and the corresponding NUMA node is automatically adjusted, and the description is updated based on the adjusted association. In other words, this association is configured in tandem with the number of NUMA nodes. If the number of NUMA nodes is adjusted, the association between the acceleration resource queue identifier and the NUMA node is automatically adjusted without user configuration.

[0058] Continuing with the previous example, when the value of NPS is changed, update the association between the identifiers of NUMA nodes and acceleration resource queues in the DSDT table.

[0059] In some embodiments of this disclosure, the aforementioned linkage configuration can be accomplished through firmware. The firmware can dynamically adjust the association between the accelerator and the NUMA node based on the NUMA configuration of the processor core, offering high flexibility. Furthermore, no changes are required to the accelerator software. In addition, by shielding the operating system / accelerator software from hardware details and configuration changes, the accelerator can be used by the appropriate NUMA node's processor core without any modifications, contributing to improved device utilization and overall system performance.

[0060] The following describes the process by which the processor core uses the accelerator based on the configured association.

[0061] In some embodiments of this disclosure, during the initialization phase of each hardware device in the computing device, device hardware configuration information is obtained by loading the driver. Based on this device hardware configuration information, the descriptions mentioned above that indicate acceleration resource queue identifiers and NUMA node identifiers can be obtained. For example, the associations recorded in the DSDT table mentioned above. This description is exposed to the application. Thus, if an application wants to use the accelerator, it needs to invoke the accelerator through the processor core running the application, and can invoke the accelerator based on the associations between NUMA nodes and acceleration resources obtained from the exposed description.

[0062] Figure 4 The process of the processor core running the application using the accelerator is described. This process includes a device initialization process 410 and an accelerator invocation process 420.

[0063] refer to Figure 4 The device initialization process 410 is as follows.

[0064] In box 411, during device initialization, device configuration information is obtained. This includes, for example, the ACPI table and DSDT table mentioned earlier. This configuration information can be obtained through a predefined function (e.g., the probe function). In box 412, the association between acceleration resource queues and NUMA nodes is exposed to the application. For example, the association between acceleration resource queue identifiers and NUMA node identifiers in the ACPI and DSDT tables is exposed to the application.

[0065] For applications that require acceleration resources, the accelerator is invoked in process 420 as follows.

[0066] In box 421, the application requests access to the target acceleration resource queue. The target acceleration resource queue can be an acceleration resource determined by the application based on the task to be performed, such as acceleration resources for AI inference. In box 422, the application determines the identifier of the NUMA node to which the current processor core belongs. In box 423, it determines whether the target NUMA node corresponding to the target acceleration resource queue matches the NUMA node to which the current processor core belongs. In box 424, if they match, the application is allowed to access the target acceleration resource queue. If the identifier of the target NUMA node does not match the NUMA node to which the current processor core belongs, the acceleration resource queue associated with the NUMA node to which the current processor core belongs is accessed.

[0067] Figure 5A schematic structural block diagram of a resource configuration apparatus 500 according to certain embodiments of the present disclosure is shown. Apparatus 500 may be implemented as or included in computing device 110. Various modules / components in apparatus 500 may be implemented by hardware, software, firmware, or any combination thereof.

[0068] like Figure 5 As shown, the apparatus 500 includes an acquisition module 510 configured to acquire an indication of the number of NUMA nodes for a processor socket; the apparatus 500 also includes a partitioning module 520 configured to partition the acceleration resources of the accelerator into at least one acceleration resource queue based on the number of nodes; the apparatus 500 also includes an invocation module 530 configured to associate the at least one acceleration resource queue with the corresponding NUMA node contained in the processor socket, so that multiple processor cores partitioned to the corresponding NUMA node can use the at least one acceleration resource queue based on the association.

[0069] In some embodiments, the acquisition module 510 is further configured to present an entry for setting the number of nodes; and to acquire an instruction through the entry.

[0070] In some embodiments, the partitioning module 520 is further configured to partition multiple processor cores associated with a processor socket into corresponding NUMA nodes based on the number of nodes.

[0071] In some embodiments, the apparatus 500 further includes a generation module configured to generate a description of the association between at least one acceleration resource queue and a corresponding NUMA node, the description indicating at least one identifier of the at least one acceleration resource queue associated with the corresponding NUMA node.

[0072] In some embodiments, the calling module 530 is further configured to, in response to at least one core in a first node of a corresponding NUMA node being to use an accelerator, determine, based on a description, a first acceleration resource queue allocated to the first node in at least one acceleration resource queue; and cause the at least one core to utilize the acceleration resources in the first acceleration resource queue for acceleration.

[0073] In some embodiments, the generation module is further configured to adjust the association between at least one acceleration resource queue and the corresponding NUMA node in response to a change in the number of nodes; and to update the above description based on the adjusted association.

[0074] Figure 6 A block diagram is shown illustrating an electronic device 600 in which one or more embodiments of the present disclosure may be implemented. It should be understood that... Figure 6 The electronic device 600 shown is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein. Figure 6The electronic device 600 shown can be used to achieve Figure 1 Electronic devices 110.

[0075] like Figure 6 As shown, electronic device 600 is in the form of a general-purpose electronic device. Components of electronic device 600 may include, but are not limited to, one or more processors or processing units 610, memory 620, storage device 630, one or more communication units 640, one or more input devices 650, and one or more output devices 660. Processing unit 610 may be a physical or virtual processor and is capable of performing various processes according to programs stored in memory 620. In a multiprocessor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing capability of electronic device 600.

[0076] Electronic device 600 typically includes multiple computer storage media. Such media can be any accessible media that is accessible to electronic device 600, including but not limited to volatile and non-volatile media, removable and non-removable media. Memory 620 can be volatile memory (e.g., registers, cache, random access memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 630 can be removable or non-removable media and can include machine-readable media, such as flash drives, disks, or any other media that can be used to store information and / or data and can be accessed within electronic device 600.

[0077] Electronic device 600 may further include additional removable / non-removable, volatile / non-volatile storage media. Although not explicitly stated... Figure 6 As shown, disk drives for reading from or writing to removable, non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable, non-volatile optical disks can be provided. In these cases, each drive can be connected to a bus (not shown) via one or more data media interfaces. Memory 620 may include computer program product 625 having one or more program modules configured to perform various methods or actions of various embodiments of this disclosure.

[0078] The communication unit 640 enables communication with other electronic devices via a communication medium. Additionally, the functionality of the components of the electronic device 600 can be implemented using a single computing cluster or multiple computing machines capable of communicating via communication connections. Therefore, the electronic device 600 can operate in a networked environment using logical connections to one or more other servers, network personal computers (PCs), or another network node.

[0079] Input device 650 can be one or more input devices, such as a mouse, keyboard, trackball, etc. Output device 660 can be one or more output devices, such as a monitor, speaker, printer, etc. Electronic device 600 can also communicate with one or more external devices (not shown) via communication unit 640 as needed. These external devices include storage devices, display devices, etc., and can communicate with one or more devices that enable user interaction with electronic device 600, or with any device that enables electronic device 600 to communicate with one or more other electronic devices (e.g., network card, modem, etc.). Such communication can be performed via input / output (I / O) interface (not shown).

[0080] According to an exemplary implementation of this disclosure, a computer-readable storage medium is provided that stores computer-executable instructions thereon, wherein the computer-executable instructions are executed by a processor to implement the methods described above. According to an exemplary implementation of this disclosure, a computer program product is also provided, which is tangibly stored on a non-transitory computer-readable medium and includes computer-executable instructions, which are executed by a processor to implement the methods described above.

[0081] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, devices, and computer program products implemented according to this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0082] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0083] Computer-readable program instructions can be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0084] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0085] Various implementations of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed implementations. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described implementations. The terminology used herein is chosen to best explain the principles, practical applications, or improvements to technology in the market, or to enable others skilled in the art to understand the various implementations disclosed herein.

Claims

1. A resource allocation method, comprising: Obtain an indication of the number of nodes for non-uniform memory access NUMA nodes for the processor socket via a user-configurable firmware interface; Based on the number of nodes, the acceleration resources of the accelerator are divided into at least one acceleration resource queue. By associating the at least one acceleration resource queue with a corresponding NUMA node contained in the processor socket, multiple processor cores allocated to the corresponding NUMA node can use the at least one acceleration resource queue based on the association; and In response to a change in the number of nodes, the association between the at least one acceleration resource queue and the corresponding NUMA node is dynamically adjusted.

2. The method of claim 1, wherein obtaining the instruction comprises: An entry point for setting the number of nodes is provided; as well as The instruction is obtained through the aforementioned entry point.

3. The method according to claim 1, further comprising: Based on the number of nodes, the plurality of processor cores associated with the processor socket are assigned to the corresponding NUMA nodes.

4. The method according to any one of claims 1 to 3, further comprising: A description of the association between the at least one acceleration resource queue and the corresponding NUMA node is generated, the description indicating at least the corresponding identifier of the at least one acceleration resource queue associated with the corresponding NUMA node, and the description is stored in the Advanced Configuration and Power Interface (ACPI) table.

5. The method according to claim 4, further comprising: In response to the fact that at least one core in the first node of the corresponding NUMA node is going to use the accelerator, the first acceleration resource queue allocated to the first node in the at least one acceleration resource queue is determined based on the description. as well as The at least one core is accelerated by utilizing the acceleration resources in the first acceleration resource queue.

6. The method of claim 4, further comprising: In response to a change in the number of nodes, the association between the at least one acceleration resource queue and the corresponding NUMA node is adjusted; as well as The description is updated based on the adjusted association, and the description is stored in the ACPI table.

7. A resource allocation device, comprising: The acquisition module is configured to obtain an indication of the number of nodes for non-uniform memory access NUMA nodes for the processor socket via a user-configurable firmware interface. The partitioning module is configured to partition the accelerator's acceleration resources into at least one acceleration resource queue based on the number of nodes. The calling module is configured to enable multiple processor cores assigned to the respective NUMA nodes to use the at least one acceleration resource queue based on the association by associating the at least one acceleration resource queue with the respective NUMA node contained in the processor socket. as well as The adjustment module is configured to dynamically adjust the association between the at least one acceleration resource queue and the corresponding NUMA node in response to a change in the number of nodes.

8. An electronic device, comprising: At least one processing unit; as well as At least one memory, coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, which, when executed by the at least one processing unit, cause the electronic device to perform the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, the computer program being executable by a processor to implement the method according to any one of claims 1 to 6.

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