Queue command processing method and device, equipment, storage medium and program product

Abstract

The invention relates to a queue command processing method and device, equipment, a storage medium and a program product. The method comprises the following steps: obtaining type information of a to-be-transmitted submission queue SQ command and / or configuration information of the SQ command; according to the type information of the SQ command and / or the configuration information of the SQ command, a queue entry corresponding to the SQ command is generated in a circular array structure of a submission queue corresponding to the SQ command, and a pointer of the queue entry is refreshed; generating doorbell information of the SQ command according to the pointer of the queue entry; doorbell information of the SQ command is sent to a controller in the data processor, so that the controller obtains a queue entry corresponding to the SQ command from a circular array structure of a submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command; and after the interrupt information is received, obtaining a queue entry corresponding to the completion queue CQ command. By adopting the method, the simulation verification speed of the drive of the NVMe can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a queue command processing method, device, equipment, storage medium and program product. Background Art

[0002] With the rapid development of the cloud computing industry, the requirements for hard disk performance are getting higher and higher. The non-volatile memory express (NVMe) protocol is used to define hardware interfaces and transmission protocols. The emergence of the NVMe protocol has greatly improved the performance of hard disks, so data processing units (DPUs) generally support the NVMe protocol.

[0003] In the related art, when simulating the NVMe driver, the simulation verification platform mainly simulates the NVMe driver and the behavior of the host device side to generate various input / output (I / O) requests. NVMe usually uses a queue to implement the transmission of I / O requests.

[0004] However, since the DPU supports thousands of queue pairs (QPs), the number of QPs corresponding to various scenarios when simulating and verifying the NVMe driver is huge. Currently, it is not possible to effectively manage multiple QPs, which reduces the simulation and verification speed of the NVMe driver. Summary of the invention

[0005] Based on this, it is necessary to provide a queue command processing method, device, equipment, storage medium and program product that can improve the simulation verification speed of NVMe drivers in response to the above technical problems.

[0006] In a first aspect, the present application provides a method for processing a queue command. The method comprises:

[0007] Obtaining type information of a submission queue SQ command to be transmitted and / or configuration information of the SQ command;

[0008] Generate a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command according to the type information of the SQ command and / or the configuration information of the SQ command, and refresh a pointer to the queue entry;

[0009] generating doorbell information of the SQ command according to the pointer of the queue entry;

[0010] Sending doorbell information of the SQ command to a controller, so that the controller obtains a queue entry corresponding to the SQ command from a circular array structure of a submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command;

[0011] After receiving the interruption information, a queue entry corresponding to the completion queue CQ command is obtained, and the queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0012] In one embodiment, after obtaining the queue entry corresponding to the completion queue CQ command, the method further includes:

[0013] According to the queue entry corresponding to the CQ command, the resources of the submission queue corresponding to the SQ command are released.

[0014] In one embodiment, releasing resources of a submission queue corresponding to the SQ command according to a queue entry corresponding to the CQ command includes:

[0015] Determine the submission queue corresponding to the SQ command according to the submission queue identifier in the queue entry corresponding to the CQ command;

[0016] Determine the queue entry corresponding to the SQ command according to the submission queue corresponding to the SQ command and the head pointer information in the queue entry corresponding to the CQ command;

[0017] According to the information added in the queue entry corresponding to the SQ command, the resources of the submission queue corresponding to the SQ command are released.

[0018] In one of the embodiments, the resources of the submission queue include at least one of the following: a cache space, a message list of a memory descriptor, and a queue entry corresponding to the SQ command.

[0019] In one embodiment, generating a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command according to the type information and / or configuration information of the SQ command includes:

[0020] If the type information of the SQ command indicates that the SQ command is a management command, the control information corresponding to the SQ command is added to the first initial queue entry to generate a queue entry corresponding to the SQ command. The first initial queue entry is located in the space of the circular array structure of the first submission queue corresponding to the management command.

[0021] In one embodiment, generating a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command according to the type information and / or configuration information of the SQ command includes:

[0022] If the type information of the SQ command indicates that the SQ command is an input / output command, generating at least one memory descriptor structure corresponding to the SQ command according to the configuration information of the SQ command;

[0023] Filling the at least one memory descriptor structure into a cache space of a second submission queue corresponding to the SQ command, the second submission queue being a submission queue corresponding to the input / output command;

[0024] Adding sequence information in the message list space of the memory descriptor according to the number of generated memory descriptor structures, wherein the sequence information is used to characterize the sequence of memory addresses of each memory descriptor structure in the cache space of the second submission queue;

[0025] The memory addresses of the respective memory descriptor structures in the cache space of the second submission queue and / or the memory addresses of the message list space of the memory descriptors are added to a second initial queue entry to generate a queue entry corresponding to the SQ command, and the second initial queue entry is located in the space of the circular array structure of the second submission queue.

[0026] In one embodiment, after receiving the interrupt information, obtaining the queue entry corresponding to the completion queue CQ command includes:

[0027] After receiving the interruption information, determine the identification information of the queue entry corresponding to the CQ command by querying the local index;

[0028] The queue entry corresponding to the CQ command is acquired according to the identification information of the queue entry corresponding to the CQ command.

[0029] In one of the embodiments, after obtaining the type information and configuration information of the submission queue SQ command to be transmitted, the method further includes:

[0030] Obtain configuration information of a non-volatile memory NVMe queue, wherein the configuration information includes configuration information of a data processor DPU and in-queue configuration information of each queue;

[0031] Allocate a memory address range for each queue in the NVMe queue according to the configuration information of the DPU;

[0032] The memory address range of the internal resources in each queue is determined according to the memory address range allocated to each queue, the queue configuration information of each queue and the type information of each queue.

[0033] In one of the embodiments, the internal resource includes at least one of the following: doorbell information, queue entries, message lists of memory descriptors, cache space, and interrupt information.

[0034] In one of the embodiments, after obtaining the queue entry corresponding to the completion queue CQ command, the method further includes:

[0035] Perform a validity check on the queue entry corresponding to the CQ command and determine a validity check result.

[0036] In a second aspect, the present application also provides a queue command processing device. The device comprises:

[0037] An acquisition module, used to acquire type information of a submission queue SQ command to be transmitted and / or configuration information of the SQ command;

[0038] a processing module, configured to generate a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command according to the type information of the SQ command and / or the configuration information of the SQ command, and refresh a pointer of the queue entry; and generate doorbell information of the SQ command according to the pointer of the queue entry;

[0039] a sending module, configured to send the doorbell information of the SQ command to a controller in the data processor, so that the controller obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command;

[0040] The receiving module is used to obtain the queue entry corresponding to the completion queue CQ command after receiving the interrupt information, and the queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0041] In one of the embodiments, the processing module is further used to release the resources of the submission queue corresponding to the SQ command according to the queue entry corresponding to the CQ command.

[0042] In one of the embodiments, the processing module is specifically used to determine the submission queue corresponding to the SQ command based on the submission queue identifier in the queue entry corresponding to the CQ command; determine the queue entry corresponding to the SQ command based on the submission queue corresponding to the SQ command and the head pointer information in the queue entry corresponding to the CQ command; and release the resources of the submission queue corresponding to the SQ command based on the information added in the queue entry corresponding to the SQ command.

[0043] In one of the embodiments, the resources of the submission queue include at least one of the following: a cache space, a message list of a memory descriptor, and a queue entry corresponding to the SQ command.

[0044] In one of the embodiments, the processing module is specifically used to add the control information corresponding to the SQ command to a first initial queue entry to generate a queue entry corresponding to the SQ command if the type information of the SQ command indicates that the SQ command is a management command. The first initial queue entry is located in the space of the circular array structure of the first submission queue corresponding to the management command.

[0045] In one of the embodiments, the processing module is specifically used to generate at least one memory descriptor structure corresponding to the SQ command according to the configuration information of the SQ command if the type information of the SQ command indicates that the SQ command is an input / output command; fill the at least one memory descriptor structure into the cache space of the second submission queue corresponding to the SQ command, the second submission queue is the submission queue corresponding to the input / output command; add sequence information in the message list space of the memory descriptor according to the number of generated memory descriptor structures, the sequence information is used to characterize the order of memory addresses of each memory descriptor structure in the cache space of the second submission queue; add the memory address of each memory descriptor structure in the cache space of the second submission queue and / or the memory address of the message list space of the memory descriptor to the second initial queue entry to generate a queue entry corresponding to the SQ command, the second initial queue entry is located in the space of the circular array structure of the second submission queue.

[0046] In one of the embodiments, the receiving module is specifically used to determine the identification information of the queue entry corresponding to the CQ command by querying the local index after receiving the interrupt information; and obtain the queue entry corresponding to the CQ command according to the identification information of the queue entry corresponding to the CQ command.

[0047] In one embodiment, the queue command processing device further includes:

[0048] A configuration module is used to obtain configuration information of a non-volatile memory NVMe queue, wherein the configuration information includes configuration information of a data processor DPU and queue configuration information of each queue; a memory address range is allocated to each queue in the NVMe queue according to the configuration information of the DPU; and a memory address range of internal resources in each queue is determined according to the memory address range allocated to each queue, the queue configuration information of each queue, and the type information of each queue.

[0049] In one of the embodiments, the internal resource includes at least one of the following: doorbell information, queue entries, message lists of memory descriptors, cache space, and interrupt information.

[0050] In one of the embodiments, the processing module is further used to perform a validity check on the queue entry corresponding to the CQ command and determine a validity check result.

[0051] In a third aspect, the present application further provides a computer device, wherein the computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the queue command processing method described in the first aspect.

[0052] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, and the computer program is executed by a processor to implement the queue command processing method described in the first aspect.

[0053] In a fifth aspect, the present application further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the method for processing queue commands described in the first aspect is implemented.

[0054] The above-mentioned queue command processing method, device, equipment, storage medium and program product first obtain the type information of the submission queue SQ command to be transmitted and / or the configuration information of the SQ command. Secondly, based on the type information of the SQ command and / or the configuration information of the SQ command, a queue entry corresponding to the SQ command is generated in the circular array structure of the submission queue corresponding to the SQ command, and the pointer of the queue entry is refreshed. Thirdly, based on the pointer of the queue entry, the doorbell information of the SQ command is generated, and the doorbell information of the SQ command is sent to the controller in the data processor, so that the controller obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command. Finally, after receiving the interrupt information, the queue entry corresponding to the completion queue CQ command is obtained, and the queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command. In this way, a queue entry corresponding to the SQ command is generated according to the type information and / or configuration information of the SQ command, and the doorbell information of the SQ command is generated according to the pointer of the queue entry, so that the controller obtains the queue entry corresponding to the SQ command according to the doorbell information, and generates a queue entry corresponding to the CQ command, thereby realizing the incentive of the QP composed of SQ and CQ in different scenarios, effectively managing the queue resources of the I / O data corresponding to the QP, and improving the simulation verification speed of the NVMe driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic diagram of a DPU implementing an NVMe controller in the related art;

[0056] Figure 2 A schematic diagram of SQ and CQ in the related art;

[0057] Figure 3 is a schematic diagram of another SQ and CQ in the related art;

[0058] Figure 4 An application environment of a queue command processing method provided in an embodiment of the present application;

[0059] Figure 5 A flowchart of a method for processing a queue command provided in an embodiment of the present application;

[0060] Figure 6 A schematic diagram of an Admin SQ generating a control request provided in an embodiment of the present application;

[0061] Figure 7 A schematic diagram of an I / O SQ generating an I / O request provided in an embodiment of the present application;

[0062] Figure 8A flowchart of another method for processing a queue command provided in an embodiment of the present application;

[0063] Fig. 9 A schematic diagram of the division of the memory address range provided in the embodiment of the present application;

[0064] Fig.10 A flowchart of another method for processing a queue command provided in an embodiment of the present application;

[0065] Fig.11 A flowchart of another method for processing a queue command provided in an embodiment of the present application;

[0066] Fig.12 A structural block diagram of a queue command processing device provided in an embodiment of the present application;

[0067] Fig.13 An internal structure diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0069] The following first describes the NVMe protocol.

[0070] Currently, almost all common operating systems support the NVMe protocol. Figure 1 FIG. 1 is a schematic diagram of a DPU implementing an NVMe controller in the related art. Figure 1 As shown in the figure, the DPU is connected to the host device and the storage device respectively. The host device is integrated with an NVMe driver, the DPU is provided with an NVMe controller, and the storage device is provided with a Flash Translation Layer (FTL) and a NAND Flash storage medium. The DPU is connected to the host device through a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIe). The PCIe bus is divided into three layers, including the physical layer, the data link layer, and the processing layer, and forwards data through packets. The content defined by the NVMe protocol is equivalent to the upper application layer of PCIe. At the application layer, the DPU is equivalent to a PCIe end device.

[0071] NVMe uses queues to implement the transmission of I / O requests. The QP used to carry NVMe commands consists of a submission queue (SQ) and a completion queue (CQ). There are two types of QPs, namely Admin QP and I / O QP. Admin QP is used to carry admin commands, and I / O QP is used to carry I / O commands. I / O QP is also called data queue. The host device (host) submits NVMe commands to the NVMe controller on the DPU through SQ, and the NVMe controller submits the completion status to CQ.

[0072] It should be noted that usually SQ and CQ are in the host's double data rate (DDR) synchronous dynamic random access memory. The host sends an SQ command, which actually fills the command into the SQ queue and then notifies the NVMe controller to fetch the command from the DDR.

[0073] Among them, Admin QP is mainly used to place Admin commands, which are used for host device management and control I / O QP, and I / O QP is mainly used to transmit data commands, which are used for data transmission between host device and DPU. For example, Admin commands execute some solid state disk (SSD) management operations, such as namespace management and firmware upgrade.

[0074] It should be noted that there is only one pair of Admin SQ and Admin CQ in the system, but there can be multiple pairs of I / O SQ and I / OCQ. Figure 2 and Figure 3 The following example shows the deployment of Admin QP and I / O QP on the host side. Figure 2 As shown, the I / O SQ and CQ are deployed one-to-one, such as Figure 3 As shown, the I / O SQ and CQ are deployed in a many-to-one manner.

[0075] The following is an explanation of the data interaction process between the host device and the DPU through the queue in the related art. The data interaction process includes S101-S108:

[0076] S101. The host device submits a new command.

[0077] In some embodiments, when the host device issues a new command, it is placed in the SQ in the host device memory.

[0078] S102: The host device notifies the controller of the DPU to extract a new command.

[0079] In some embodiments, after the host device writes a new command into SQ, the driver does not know the new command. Therefore, the host device needs to send a notification message to the controller to notify the controller. This process is completed by updating the SQ Tail Doorbell register inside the controller. The notification message can be, for example, "I submitted a new command request, please help me process it as soon as possible!".

[0080] S103, the controller extracts new commands from the SQ. After taking the new command, the position of the queue head needs to be updated in the SQ Head Pointer register inside the controller. If NVMe does not specify the execution order of new commands stored in the queue, the controller can take out multiple new commands at a time for batch processing.

[0081] S104. The controller executes the new command extracted from the SQ.

[0082] It should be understood that the order in which new commands in a queue are executed is not fixed, which may result in earlier requests being processed later. When executing a new read or write command, this process will also transfer data with the host device memory.

[0083] S105: The controller writes the completion status of the new command into CQ. At this time, the controller needs to update the CQ Tail Pointer register.

[0084] S106, the controller notifies the host device to check the completion status of the new command. The controller notifies the host device by sending an interrupt message. Exemplarily, the interrupt message may be, for example, "I have completed the execution of the new command you submitted, please check the result!".

[0085] S107. The host device checks the completion status of the new command in the CQ.

[0086] S108, the host device notifies the controller that the processing has been completed. At this time, the host device updates the CQ Head Doorbell register inside the controller and sends a notification message to the controller. Exemplarily, the notification message may be, for example, "I have processed the new command execution result you sent back, thank you very much!".

[0087] In the related technology, when simulating the NVMe driver, the simulation verification platform mainly simulates the NVMe driver and the behavior of the host device side to generate various input / output (I / O) requests. NVMe usually uses queues to implement the transmission of I / O requests. However, since the DPU supports thousands of queue combinations (QueuePair, QP), the number of QPs corresponding to various scenarios when simulating and verifying the NVMe driver is huge. At present, it is still impossible to effectively manage multiple QPs, which reduces the simulation verification speed of the NVMe driver.

[0088] To solve the above technical problems, the embodiments of the present application provide a queue command processing method, apparatus, device, storage medium and program product, which generates a queue entry corresponding to the SQ command according to the type information and / or configuration information of the SQ command, and generates the doorbell information of the SQ command according to the pointer of the queue entry, so that the controller obtains the queue entry corresponding to the SQ command according to the doorbell information, and generates a queue entry corresponding to the CQ command, thereby realizing the incentive of QP in different scenarios, effectively managing the queue resources of I / O data corresponding to QP, and improving the simulation verification speed of the NVMe driver.

[0089] The queue command processing method provided in the embodiment of the present application can be applied to Figure 4 In the application environment shown. Among them, the host device 202 is connected to the DPU204 via PCIe. The host device 202 obtains the type information of the submission queue SQ command to be transmitted and / or the configuration information of the SQ command. Secondly, the host device 202 generates a queue entry corresponding to the SQ command in the circular array structure of the submission queue corresponding to the SQ command according to the type information of the SQ command and / or the configuration information of the SQ command, and refreshes the pointer of the queue entry. Thirdly, the host device 202 generates the doorbell information of the SQ command according to the pointer of the queue entry. Finally, the host device 202 sends the doorbell information of the SQ command to the controller in the DPU204. According to the doorbell information of the SQ command, the DPU204 obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command, and executes the SQ command according to the queue entry corresponding to the SQ command. Subsequently, the DPU204 generates a queue entry corresponding to the CQ command. After receiving the interruption information, the host device 202 obtains the queue entry corresponding to the completion queue CQ command, and the queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0090] The host device 202 may be, but is not limited to, various personal computers, network devices, laptops, smart phones, tablet computers, IoT devices, and portable wearable devices. The network device may be a smart network card, etc. The IoT device may be a smart speaker, smart TV, smart air conditioner, smart car-mounted device, etc. The portable wearable device may be a smart watch, smart bracelet, head-mounted device, etc.

[0091] In one embodiment, Figure 5 As shown, a method for processing queue commands is provided, and the method is applied to Figure 4 The host device in is used as an example to illustrate, including S301-S305:

[0092] S301. Obtain type information of a submission queue SQ command to be transmitted and / or configuration information of the SQ command.

[0093] In the present application, when the host device generates an SQ command, type information of the SQ command to be transmitted and / or configuration information of the SQ command can be obtained.

[0094] The type information of the SQ command may be used to indicate the type of the SQ command. The types of the SQ command include management commands and input / output commands. The input / output commands may also be data commands.

[0095] In some embodiments, if the type information of the SQ command indicates that the type of the SQ command is a management command, the host device does not need to obtain the configuration information of the SQ command, and can directly generate a queue entry corresponding to the SQ command based on the type information of the SQ command.

[0096] In other embodiments, if the type information of the SQ command indicates that the type of the SQ command is an input / output command, the host device needs to further obtain configuration information of the SQ command, and generate a queue entry corresponding to the SQ command based on the type information of the SQ command and the configuration information of the SQ command.

[0097] It should be understood that the embodiments of the present application do not limit the configuration information of the SQ command. In some embodiments, the configuration information of the SQ command may include the number of I / Os, the total packet length of each I / O, the chain length of the message list of the memory descriptor, the address offset, I / O data, etc.

[0098] S302: Generate a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command according to the type information of the SQ command and / or the configuration information of the SQ command, and refresh a pointer to the queue entry.

[0099] In the present application, for different type information of SQ commands, different methods may be used to generate queue entries corresponding to the SQ commands.

[0100] In some embodiments, if the type information of the SQ command indicates that the SQ command is a management command, the control information corresponding to the SQ command is added to the first initial queue entry to generate a queue entry corresponding to the SQ command. The first initial queue entry is located in the space of the circular array structure of the first submission queue corresponding to the management command.

[0101] For example, Figure 6 A schematic diagram of an Admin SQ generating a control request provided in an embodiment of the present application. Figure 6 As shown, the first submission queue is Admin SQ, the circular array structure may be a ring space, which includes a plurality of initial queue entries, and the first initial queue entry may be any initial queue entry in the ring space.

[0102] Exemplarily, the initial queue entries in the space of the circular array structure of the first submission queue may be submission queue entries (SQE), and each SQE corresponds to a control request.

[0103] It should be understood that the above control information corresponds to different control requests through encoding, and by adding the control information to the first initial queue entry, a queue entry corresponding to the SQ command is generated, and the relevant control request can be transmitted to the DPU. After the filling is completed, the pointer of the SQE is refreshed to generate the doorbell information of the SQ command.

[0104] In other embodiments, if the type information of the SQ command indicates that the SQ command is an input / output command, the host device may first generate at least one memory descriptor structure corresponding to the SQ command according to the configuration information of the SQ command. Secondly, the host device fills at least one memory descriptor structure into the cache space of the second submission queue corresponding to the SQ command. Thirdly, the host device adds sequence information to the message list space of the memory descriptor according to the number of memory descriptor structures generated. Finally, the host device adds the memory address of each memory descriptor structure in the cache space of the second submission queue and / or the memory address of the message list space of the memory descriptor to the second initial queue entry to generate a queue entry corresponding to the SQ command.

[0105] For example, Figure 7 A schematic diagram of an I / O SQ generating an I / O request provided in an embodiment of the present application. Figure 7 As shown, the second submission queue is the I / O SQ corresponding to the I / O command. The order information is used to characterize the order of the memory addresses of each memory descriptor structure in the cache space of the second submission queue. The second initial queue entry is located in the space of the circular array structure of the second submission queue.

[0106] It should be understood that the embodiments of the present application do not limit how to generate at least one memory descriptor structure corresponding to an SQ command based on the configuration information of the SQ command. In some embodiments, the host device can slice the I / O data according to the configuration information of the SQ command to generate at least one memory descriptor structure.

[0107] Exemplarily, the above-mentioned memory descriptor structure may be a physical region page (PRP) structure, which may be sliced ​​to generate a single PRP, two PRPs, multiple PRPs, and the like.

[0108] It should be understood that the embodiments of the present application do not limit how to add sequence information in the message list space of the memory descriptor according to the number of memory descriptor structures generated. In some embodiments, if the number of memory descriptor structures generated is less than a threshold, there is no need to add sequence information in the message list space of the memory descriptor. If the number of memory descriptor structures generated is greater than or equal to, then the sequence information is added in the message list space of the memory descriptor.

[0109] The threshold can be set according to actual conditions, for example, 3. That is, when there are 3 or more memory descriptor structures, the sequence information is added to the message list space of the memory descriptor. When there are less than 3 memory descriptor structures, there is no need to add the sequence information to the message list space of the memory descriptor.

[0110] Correspondingly, if the message list space of the memory descriptor has sequence information added, the memory address of each memory descriptor structure in the cache space of the second submission queue and the memory address of the message list space of the memory descriptor can be added to the second initial queue entry to generate a queue entry corresponding to the SQ command. If the message list space of the memory descriptor has not been added with sequence information, the memory address of each memory descriptor structure in the cache space of the second submission queue can be directly added to the second initial queue entry to generate a queue entry corresponding to the SQ command.

[0111] It should be noted that the processing of multiple queues is consistent with the single queue processing flow, and this embodiment of the present application will not be repeated here.

[0112] S303: Generate doorbell information of the SQ command according to the pointer of the queue entry.

[0113] In this step, after refreshing the pointer of the queue entry, the host device can generate the doorbell information of the SQ command according to the pointer of the queue entry.

[0114] It should be understood that the embodiments of the present application do not limit how to generate the doorbell information of the SQ command. In some embodiments, the host device can write the index of the pointer of the updated queue entry into the address of the doorbell information of the SQ command, thereby generating the doorbell information of the SQ command.

[0115] Different doorbell information addresses may be used for different types of SQ commands. For example, if the SQ command is an Adimn command, the index of the pointer of the updated queue entry is written into the doorbell address of the Adimn SQ. If the SQ command is an I / O command, the index of the pointer of the updated queue entry is written into the doorbell address of the I / O SQ.

[0116] S304. Send the doorbell information of the SQ command to the controller in the data processor, so that the controller obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command.

[0117] In this step, the host device may send doorbell information of the SQ command to the controller in the DPU, so that the controller may obtain the queue entry corresponding to the SQ command and execute the SQ command according to the queue entry corresponding to the SQ command.

[0118] It should be understood that the process in which the host device can send doorbell information to the controller can be completed through the SQ Tail Doorbell inside the controller.

[0119] In some embodiments, after the controller obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command, it can take away the information written in the queue entry corresponding to the SQ command to obtain the SQ command, and then update the position of the Head in the SQ Head Pointer register inside the Controller.

[0120] In some embodiments, after obtaining the SQ command, the controller may execute the SQ command, and the execution order of the SQ command may be determined based on the order of the queue entries corresponding to the SQ command in the submission queue. In addition, when the controller executes the read and write SQ command, the process also transfers data with the memory of the host device.

[0121] In some embodiments, after executing the SQ command, the controller may generate a queue entry corresponding to the CQ command, write the completion status of the SQ command into the CQ, and send an interrupt message to the host device to inform the host device that the controller has completed the execution of the SQ command.

[0122] S305. After receiving the interruption information, obtain a queue entry corresponding to the completion queue CQ command, where the queue entry corresponding to the CQ command contains completion status information corresponding to the SQ command.

[0123] It should be understood that the embodiments of the present application do not limit how to obtain the queue entry corresponding to the completion queue CQ command. In some embodiments, the host device can determine the identification information of the queue entry corresponding to the CQ command by querying the local index after receiving the interrupt information. Subsequently, the host device obtains the queue entry corresponding to the CQ command according to the identification information of the queue entry corresponding to the CQ command.

[0124] In some embodiments, after querying the identification information of the queue entry, the host device may update the identification information of the queue entry. Exemplarily, if the queried identification information of the queue entry is CQE index, the host device may update the identification information to index+1.

[0125] In some embodiments, when the host device obtains the queue entry corresponding to the completion queue CQ command, it can also perform a legitimacy check on the queue entry corresponding to the CQ command and determine the legitimacy check result. It should be understood that the embodiments of the present application do not limit the method of legitimacy check. In some embodiments, the completion status information written in the queue entry corresponding to the CQ command can be checked to determine whether the completion status information meets the preset data content and data format requirements. If the detection result indicates that it is correct, the host device can also inform the controller that the queue entry corresponding to the CQ command has been processed.

[0126] In some embodiments, after the host device obtains the queue entry corresponding to the completion queue CQ command, it can also release the resources of the submission queue corresponding to the SQ command according to the queue entry corresponding to the CQ command.

[0127] It should be understood that the embodiments of the present application do not limit how to release the resources of the submission queue corresponding to the SQ command. In some embodiments, the host device may first determine the submission queue corresponding to the SQ command based on the submission queue identifier in the queue entry corresponding to the CQ command, and then the host device may determine the queue entry corresponding to the SQ command based on the submission queue corresponding to the SQ command and the head pointer information in the queue entry corresponding to the CQ command. Finally, the host device may release the resources of the submission queue corresponding to the SQ command based on the information added in the queue entry corresponding to the SQ command.

[0128] The resources of the submission queue include at least one of the following: a cache space, a message list of a memory descriptor, and a queue entry corresponding to an SQ command.

[0129] In this application, when the interrupt information is received, it can be determined that the transmission of the SQ command has been completed, and the resources of the submission queue can be released accordingly. When a new SQ command is generated, the resources of the submission queue may be empty or insufficient. At this time, the resources of the submission queue can be released before the transmission of the queue command. In this way, priority management and timely reuse of the resources of the submission queue can be achieved, greatly improving the verification efficiency and quality.

[0130] An embodiment of the present application provides a method for processing queue commands, which generates a queue entry corresponding to an SQ command according to type information and / or configuration information of the SQ command, and generates doorbell information of the SQ command according to a pointer to the queue entry, so that a controller obtains a queue entry corresponding to the SQ command according to the doorbell information, and generates a queue entry corresponding to a CQ command, thereby realizing incentives for QP in different scenarios, effectively managing and controlling queue resources for I / O data corresponding to QP, and improving the simulation verification speed of the NVMe driver.

[0131] The following describes how to divide memory before processing queue commands. Figure 8 A flowchart of another method for processing a queue command provided in an embodiment of the present application. Figure 8 As shown, the method for processing the queue command includes S401-S408:

[0132] S401. Obtain configuration information of a non-volatile memory NVMe queue, where the configuration information includes configuration information of a data processor DPU and in-queue configuration information of each queue.

[0133] The configuration information of the DPU includes: the number of supported NVMe devices, the number of queues supported in each NVMe device, and the correspondence between SQ and CQ of input and output types.

[0134] Among them, the queue configuration information of each queue includes: NVMe's stride field (nvme_stride), packet size (page_size) field, queue size, etc.

[0135] S402. Allocate a memory address range for each queue in the NVMe queue according to the configuration information of the DPU.

[0136] In some embodiments, the host device can determine the memory space required for each queue based on the configuration information of the DPU, such as the number of NVMe devices, the number of queues supported by each NVMe device, and the correspondence between SQ and CQ of the input and output types. Then, based on the memory space required by each queue, the memory is sliced ​​to allocate a memory address range for each queue in the NVMe queue.

[0137] S403: Determine the memory address range of internal resources in each queue according to the memory address range allocated to each queue, the queue configuration information of each queue, and the type information of each queue.

[0138] The internal resource includes at least one of the following: doorbell information, queue entries, a message list of a memory descriptor, a cache space, and interrupt information.

[0139] For example, Fig. 9 A schematic diagram of the division of the memory address range provided in the embodiment of the present application, such as Fig. 9 As shown in the figure, the total address space is the memory address space that can be represented by m+n+64 bits, where the high n bits are used to distinguish different NVMe devices, and the second highest m bits are used to distinguish the queues supported by the same NVMe device. Correspondingly, m is determined by the maximum number of NVMe devices supported by the DPU, and n is determined by the number of queues supported by each NVMe device. Therefore, the memory address range of each queue will be uniquely allocated during initialization. The lowest 64 bits are used to distinguish the memory addresses to be used under each queue. When installing different types of queues, different memory address ranges of internal resources can be allocated in their own memory address spaces.

[0140] Exemplarily, Admin SQ includes the memory address range of the doorbell and the memory address range of the SQE. AdminCQ includes the memory address range of the doorbell and the memory address range of the CQE. I / O SQ includes the memory address range of the doorbell, the memory address range of the SQE, the memory address range of the address space of the message list of the memory descriptor, and the memory address range of the cache space. I / O CQ includes the memory address range of the doorbell, the memory address range of the CQE, and the memory address range of the interrupt information.

[0141] Exemplarily, the memory address range of the doorbell is determined by the offset of the queue identifier plus the power of the configuration value of the stride field of NVMe. The memory address range of SQE and CQE is determined by the queue size. The memory address range of the cache space is determined according to the protocol and the maximum supported packet length for transmission.

[0142] It should be understood that the above-mentioned cache space may include a first-level cache space and a second-level cache space. The first-level cache space is a buffer located in the memory space of the host device; the second-level cache space is a buffer located in the memory space of the DPU.

[0143] In some embodiments, after completing the allocation of the memory address range of each queue in the NVMe queue and the memory address range of the internal resources in each queue, the allocated memory address range can be recorded and sent to the DPU.

[0144] It should be noted that unless the NVMe device or queue is deleted or rebuilt, the allocated memory address range will not change.

[0145] S404: Obtain type information of the submission queue SQ command to be transmitted and / or configuration information of the SQ command.

[0146] S405: Generate a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command according to the type information of the SQ command and / or the configuration information of the SQ command, and refresh a pointer to the queue entry.

[0147] S406: Generate doorbell information of the SQ command according to the pointer of the queue entry.

[0148] S407. Send the doorbell information of the SQ command to the controller in the data processor, so that the controller obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command.

[0149] S408. After receiving the interruption information, obtain a queue entry corresponding to the completion queue CQ command, where the queue entry corresponding to the CQ command contains completion status information corresponding to the SQ command.

[0150] In this application, by allocating the memory address range in advance, memory space overlap is avoided, which facilitates use and maintenance and greatly improves verification efficiency and quality.

[0151] The following describes how to recycle the resources of the submission queue. Fig.10 A flowchart of another method for processing a queue command provided in an embodiment of the present application is shown below. Fig.10 As shown, the method for processing the queue command includes S501-S508:

[0152] S501: Obtain type information of a submission queue SQ command to be transmitted and / or configuration information of the SQ command.

[0153] S502: Generate a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command according to the type information of the SQ command and / or the configuration information of the SQ command, and refresh a pointer to the queue entry.

[0154] S503: Generate doorbell information of the SQ command according to the pointer of the queue entry.

[0155] S504. Send the doorbell information of the SQ command to the controller in the data processor, so that the controller obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command.

[0156] S505 . After receiving the interruption information, obtain a queue entry corresponding to the completion queue CQ command, where the queue entry corresponding to the CQ command contains completion status information corresponding to the SQ command.

[0157] S506: Determine the submission queue corresponding to the SQ command according to the submission queue identifier in the queue entry corresponding to the CQ command.

[0158] In some embodiments, the submission queue identifier may be an SQ identifier field in the CQE. The host device extracts the SQ identifier field in the CQE, and then matches the SQ identifier field to determine the SQ corresponding to the SQ command.

[0159] S507: Determine the queue entry corresponding to the SQ command according to the submission queue corresponding to the SQ command and the head pointer information in the queue entry corresponding to the CQ command.

[0160] In some embodiments, the head pointer information may be a head pointer field in the CQE. Through the head pointer field, the host device may further determine the identifier of the related SQE in the determined SQ through the head pointer field.

[0161] S508. Release resources of the submission queue corresponding to the SQ command according to the information added in the queue entry corresponding to the SQ command.

[0162] It should be understood that the embodiments of the present application do not provide for how to release the resources of the submission queue corresponding to the SQ command. In some embodiments, the information added in the queue entry corresponding to the SQ command can be used to determine the address of the resources of the related submission queue. Accordingly, the resources of the related submission queue can be released through the information added in the queue entry.

[0163] Exemplarily, according to the information added in the SQE, the cache space resources and the message list resources of the memory descriptor used by it are released, and the SQE can also be released to the SQE resource pool. In addition, the host device can also release the circular array structure resources.

[0164] In some embodiments, when transmitting the next SQ command, it can be checked whether there are sufficient SQEs in the SQE resource pool for use. If not, wait; if sufficient, fill the SQE with relevant information, including the address of the memory space, data length and other information.

[0165] In this application, when the interrupt information is received, it can be determined that the transmission of the SQ command has been completed, and the resources of the submission queue can be released accordingly. When a new SQ command is generated, the resources of the submission queue may be empty or insufficient. At this time, the resources of the submission queue can be released before the transmission of the queue command. In this way, priority management and timely reuse of the resources of the submission queue can be achieved, greatly improving the verification efficiency and quality.

[0166] Fig.11 A flowchart of another method for processing a queue command provided in an embodiment of the present application is shown below. Fig.11 As shown, the method for processing the queue command includes S501-S508:

[0167] S601. Obtain configuration information of a non-volatile memory NVMe queue, where the configuration information includes configuration information of a data processor DPU and configuration information within each queue;

[0168] S602. Allocate a memory address range for each queue in the NVMe queue according to the configuration information of the DPU;

[0169] S603: Determine the memory address range of internal resources in each queue according to the memory address range allocated to each queue, the queue configuration information of each queue, and the type information of each queue.

[0170] S604: Obtain type information of the submission queue SQ command to be transmitted and / or configuration information of the SQ command.

[0171] S605: Generate a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command according to the type information of the SQ command and / or the configuration information of the SQ command, and refresh a pointer to the queue entry.

[0172] S606: Generate doorbell information of the SQ command according to the pointer of the queue entry.

[0173] S607. Send the doorbell information of the SQ command to the controller in the data processor, so that the controller obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command.

[0174] S608. After receiving the interruption information, obtain the queue entry corresponding to the completion queue CQ command, and the queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0175] S609: Release the resources of the submission queue corresponding to the SQ command according to the queue entry corresponding to the CQ command.

[0176] S610: Determine whether there are any SQ commands that have not been completed.

[0177] If yes, execute S604; if yes, execute S612.

[0178] S611: Determine that the processing of the queue command is completed.

[0179] The queue command processing method provided in the embodiment of the present application first obtains the type information of the submission queue SQ command to be transmitted and / or the configuration information of the SQ command. Secondly, based on the type information of the SQ command and / or the configuration information of the SQ command, a queue entry corresponding to the SQ command is generated in the circular array structure of the submission queue corresponding to the SQ command, and the pointer of the queue entry is refreshed. Thirdly, based on the pointer of the queue entry, the doorbell information of the SQ command is generated, and the doorbell information of the SQ command is sent to the controller in the data processor, so that the controller obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command. Finally, after receiving the interrupt information, the queue entry corresponding to the completion queue CQ command is obtained, and the queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command. In this way, a queue entry corresponding to the SQ command is generated according to the type information and / or configuration information of the SQ command, and the doorbell information of the SQ command is generated according to the pointer of the queue entry, so that the controller obtains the queue entry corresponding to the SQ command according to the doorbell information, and generates a queue entry corresponding to the CQ command, thereby realizing the incentive of QP in different scenarios, effectively managing the queue resources of I / O data corresponding to QP, and improving the simulation verification speed of the NVMe driver.

[0180] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0181] Based on the same inventive concept, the embodiment of the present application also provides a queue command processing device for implementing the queue command processing method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiment of the one or more queue command processing devices provided below can refer to the limitations of the queue command processing method above, and will not be repeated here.

[0182] In one embodiment, Fig.12 As shown, a queue command processing device 700 is provided, comprising: an acquisition module 701, a processing module 702, a sending module 703, a receiving module 704 and a configuration module 705, wherein:

[0183] The acquisition module 701 is used to acquire type information of a submission queue SQ command to be transmitted and / or configuration information of the SQ command.

[0184] Processing module 702 is used to generate a queue entry corresponding to the SQ command in the circular array structure of the submission queue corresponding to the SQ command according to the type information of the SQ command and / or the configuration information of the SQ command, and refresh the pointer of the queue entry; generate doorbell information of the SQ command according to the pointer of the queue entry.

[0185] The sending module 703 is used to send the doorbell information of the SQ command to the controller in the data processor, so that the controller obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command.

[0186] The receiving module 704 is used to obtain the queue entry corresponding to the completion queue CQ command after receiving the interrupt information. The queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0187] In one embodiment, the processing module 702 is further configured to release resources of a submission queue corresponding to the SQ command according to a queue entry corresponding to the CQ command.

[0188] In one embodiment, the processing module 702 is specifically used to determine the submission queue corresponding to the SQ command based on the submission queue identifier in the queue entry corresponding to the CQ command; determine the queue entry corresponding to the SQ command based on the submission queue corresponding to the SQ command and the head pointer information in the queue entry corresponding to the CQ command; and release the resources of the submission queue corresponding to the SQ command based on the information added in the queue entry corresponding to the SQ command.

[0189] In one of the embodiments, the resources of the submission queue include at least one of the following: a cache space, a message list of a memory descriptor, and a queue entry corresponding to an SQ command.

[0190] In one embodiment, the processing module 702 is specifically used to add the control information corresponding to the SQ command to the first initial queue entry if the type information of the SQ command indicates that the SQ command is a management command, and generate a queue entry corresponding to the SQ command. The first initial queue entry is located in the space of the circular array structure of the first submission queue corresponding to the management command.

[0191] In one of the embodiments, the processing module 702 is specifically used to generate at least one memory descriptor structure corresponding to the SQ command according to the configuration information of the SQ command if the type information of the SQ command indicates that the SQ command is an input / output command; fill the at least one memory descriptor structure into the cache space of the second submission queue corresponding to the SQ command, the second submission queue is the submission queue corresponding to the input / output command; add sequence information in the message list space of the memory descriptor according to the number of memory descriptor structures generated, the sequence information is used to characterize the order of memory addresses of each memory descriptor structure in the cache space of the second submission queue; add the memory address of each memory descriptor structure in the cache space of the second submission queue and / or the memory address of the message list space of the memory descriptor to the second initial queue entry, and generate a queue entry corresponding to the SQ command, the second initial queue entry is located in the space of the circular array structure of the second submission queue.

[0192] In one embodiment, the receiving module 704 is specifically used to determine the identification information of the queue entry corresponding to the CQ command by querying the local index after receiving the interrupt information; and obtain the queue entry corresponding to the CQ command according to the identification information of the queue entry corresponding to the CQ command.

[0193] In one embodiment, the queue command processing device further includes:

[0194] The configuration module 705 is used to obtain the configuration information of the non-volatile memory NVMe queue, where the configuration information includes the configuration information of the data processor DPU and the queue configuration information of each queue; according to the configuration information of the DPU, a memory address range is allocated to each queue in the NVMe queue; according to the memory address range allocated to each queue, the queue configuration information of each queue and the type information of each queue, the memory address range of the internal resources in each queue is determined.

[0195] In one of the embodiments, the internal resource includes at least one of the following: doorbell information, queue entries, message lists of memory descriptors, cache space, and interrupt information.

[0196] In one embodiment, the processing module 702 is further configured to perform a validity check on the queue entry corresponding to the CQ command and determine a validity check result.

[0197] Each module in the above-mentioned queue command processing device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module above.

[0198] In one embodiment, a computer device is provided. The computer device may be a host device, and its internal structure diagram may be as follows: Fig.13 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a method for processing a queue command is implemented.

[0199] Those skilled in the art will understand that Fig.13The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0200] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the above-mentioned queue command processing method when executing the computer program.

[0201] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned queue command processing method is implemented.

[0202] In one embodiment, a computer program product is provided, including a computer program, which implements the above-mentioned queue command processing method when executed by a processor.

[0203] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0204] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0205] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for processing a queue command, characterized in that: The method comprises: Obtaining type information of a submission queue SQ command to be transmitted and / or configuration information of the SQ command; Generate a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command according to the type information of the SQ command and / or the configuration information of the SQ command, and refresh a pointer to the queue entry; generating doorbell information of the SQ command according to the pointer of the queue entry; Sending doorbell information of the SQ command to a controller in the data processor, so that the controller obtains a queue entry corresponding to the SQ command from a circular array structure of a submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command; After receiving the interruption information, a queue entry corresponding to the completion queue CQ command is obtained, and the queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

2. The method according to claim 1, characterized in that After obtaining the queue entry corresponding to the completion queue CQ command, the method further includes: According to the queue entry corresponding to the CQ command, the resources of the submission queue corresponding to the SQ command are released.

3. The method according to claim 2, characterized in that The releasing the resources of the submission queue corresponding to the SQ command according to the queue entry corresponding to the CQ command includes: Determine the submission queue corresponding to the SQ command according to the submission queue identifier in the queue entry corresponding to the CQ command; Determine the queue entry corresponding to the SQ command according to the submission queue corresponding to the SQ command and the head pointer information in the queue entry corresponding to the CQ command; According to the information added in the queue entry corresponding to the SQ command, the resources of the submission queue corresponding to the SQ command are released.

4. The method according to claim 3, characterized in that The resources of the submission queue include at least one of the following: a cache space, a message list of a memory descriptor, and a queue entry corresponding to the SQ command.

5. The method according to claim 1, characterized in that Generating, according to the type information and / or configuration information of the SQ command, a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command, comprises: If the type information of the SQ command indicates that the SQ command is a management command, the control information corresponding to the SQ command is added to the first initial queue entry to generate a queue entry corresponding to the SQ command. The first initial queue entry is located in the space of the circular array structure of the first submission queue corresponding to the management command.

6. The method according to claim 1, characterized in that Generating, according to the type information and / or configuration information of the SQ command, a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command, comprises: If the type information of the SQ command indicates that the SQ command is an input / output command, generating at least one memory descriptor structure corresponding to the SQ command according to the configuration information of the SQ command; Filling the at least one memory descriptor structure into a cache space of a second submission queue corresponding to the SQ command, the second submission queue being a submission queue corresponding to the input / output command; Adding sequence information in the message list space of the memory descriptor according to the number of generated memory descriptor structures, wherein the sequence information is used to characterize the sequence of memory addresses of each memory descriptor structure in the cache space of the second submission queue; The memory addresses of the respective memory descriptor structures in the cache space of the second submission queue and / or the memory addresses of the message list space of the memory descriptors are added to a second initial queue entry to generate a queue entry corresponding to the SQ command, and the second initial queue entry is located in the space of the circular array structure of the second submission queue.

7. The method according to claim 1, characterized in that After receiving the interrupt information, obtaining the queue entry corresponding to the completion queue CQ command includes: After receiving the interrupt information, determine the identification information of the queue entry corresponding to the CQ command by querying the local index; The queue entry corresponding to the CQ command is acquired according to the identification information of the queue entry corresponding to the CQ command.

8. The method according to claim 1, characterized in that Before obtaining the type information and configuration information of the submission queue SQ command to be transmitted, the method further includes: Obtain configuration information of a non-volatile memory NVMe queue, wherein the configuration information includes configuration information of a data processor DPU and in-queue configuration information of each queue; Allocate a memory address range for each queue in the NVMe queue according to the configuration information of the DPU; The memory address range of the internal resources in each queue is determined according to the memory address range allocated to each queue, the queue configuration information of each queue and the type information of each queue.

9. The method according to claim 8, characterized in that The internal resource includes at least one of the following: doorbell information, queue entries, a message list of a memory descriptor, a cache space, and interrupt information.

10. The method according to claim 1, characterized in that After obtaining the queue entry corresponding to the completion queue CQ command, the method further includes: Perform a validity check on the queue entry corresponding to the CQ command and determine a validity check result.

11. A queue command processing device, characterized in that: The device comprises: An acquisition module, used to acquire type information of a submission queue SQ command to be transmitted and / or configuration information of the SQ command; a processing module, configured to generate a queue entry corresponding to the SQ command in a circular array structure of a submission queue corresponding to the SQ command according to the type information of the SQ command and / or the configuration information of the SQ command, and refresh a pointer of the queue entry; and generate doorbell information of the SQ command according to the pointer of the queue entry; a sending module, configured to send the doorbell information of the SQ command to a controller in the data processor, so that the controller obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command; The receiving module is used to obtain the queue entry corresponding to the completion queue CQ command after receiving the interrupt information, and the queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 10 are implemented.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

Images