Top structure based on GPU multi-core processor and Cache consistency processing method

Abstract

The invention is suitable for the technical field of GPUs, and provides a top layer structure based on a GPU multi-core processor and a Cache consistency processing method. According to the technical scheme, on the basis of a catalog type, information exchange and transmission between a catalog type total catalog controller and all Caches are simplified in combination with monitoring type transmission and management states, six states of an MESIPB protocol are designed, and the consistency of the Caches is improved. According to the method and the system, switching between Cache Line states is realized, the access times of a video memory are effectively reduced, the GPU structure is clear, the expansibility is good, the problem of Cache consistency during GPU multi-core processing can be solved with relatively low resource overhead, the GPU processing speed and the core utilization rate are well improved, and bus bandwidth, storage bandwidth and overhead caused by data access are effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the field of GPU technology, and in particular relates to a top-level structure based on a GPU multi-core processor and a cache consistency processing method. Background Art

[0002] In recent years, domestic and foreign GPU (Graphics Processing Unit) chip manufacturers have been committed to improving their computing power and graphics rendering capabilities, thereby achieving high data throughput and high-quality, ultra-smooth visual experience. Currently, GPU has been updated and iterated to become a high-performance computing platform for multi-core processors. However, with the continuous expansion of computing cores and the continuous increase in operating frequency, the speed of accessing video memory data has become a new performance bottleneck.

[0003] As the functions and performance of graphics processors are continuously optimized and improved, the number of processor cores used for unified rendering (i.e., vertex shading, fragment shading, tessellation shading (programmable part) and geometric shading, etc. are all completed by the same circuit logic) is also increasing. The more processor cores there are, the stronger the parallel computing capability is. However, how to cache data at multiple stages in the graphics pipeline, how to work together between multiple processors, how to write parallel calculated data into the video memory, how to ensure the consistency of multi-core access to the cache and how to reduce the number of accesses to the video memory, how to improve the bus bandwidth and storage bandwidth, etc. will all become the focus of GPU architecture design. The unified rendering processor needs to access data (such as vertex data, normal vectors, texture coordinates or other user-defined attributes, etc.) when performing vertex, fragment, tessellation and geometric shading, and the data is generally cached in the cache. When multiple processors read and write to the cache, it will inevitably cause cache consistency issues.

[0004] Based on this, it is necessary to consider load balancing in all aspects, organize and manage the numerous computing cores and caches reasonably and effectively, and be able to efficiently handle cache consistency issues, which not only improves the parallel processing capabilities and computing core utilization of the processor, but also reduces the GPU storage access bandwidth. In order to achieve this goal, some patent technologies are currently open.

[0005] For example, patent application number 201410017448.4 discloses "a directory cache consistency method that combines a limited directory with a fully mapped directory". Based on the use of memory, a dual-protocol two-level directory storage structure is set up to solve the problems of excessive storage overhead of the fully mapped directory, the limited directory being limited by directory item overflow, and the low time validity of the chain directory. However, the two-level directory structure using a limited directory at the memory layer and a fully mapped directory at the memory cache layer inevitably reduces the access speed of the storage structure. At the same time, the directory may overflow when the number of data copies in the cache is not limited.

[0006] Another example is the patent application number 201410235258.X, which discloses "a dual-core cache consistency system circuit structure based on the MSI protocol". The patent uses three states (M modification state, S sharing state and I invalid state) to mark the state of data. When the cache line is in the modification state, the local processor can read and write at will, and when other processors access it, the state needs to be converted to a shared state or an invalid state, and the modified data is written back to the main memory, so that only one processor has a modified state in the same cache line, and the other processors are in an invalid state. The shared state can exist in different cache lines at the same time, and the processor only has read permission for the shared state, so it will not cause data consistency problems. This method can effectively maintain data consistency in some embedded occasions, especially in multi-core applications with high requirements for power consumption and chip area. However, as GPU processors continue to expand and application scenarios become more complex, it is difficult to significantly improve the processing performance of the GPU when data inconsistency occurs by maintaining cache consistency based on the MSI protocol.

[0007] For another example, application number 201510314083.6 discloses "A multi-core processor system and cache consistency processing method". In this patent, the cache lines in the multi-core processor system have M, E, K, I, and F states. The first processor core is used to send a first request message to the second processor core requesting a read operation. The second processor core is used to change the state of the first cache line from the M state to the K state, and then ignore the operation of writing the data in the first cache line into the memory. This invention solves the problem that when the multi-core processor system performs cache consistency processing, the performance of the multi-core processor system is poor due to the participation of memory in the processing. Although this method solves the problem that data in the S-state cache line in the MESI protocol cannot be forwarded and reduces the number of memory accesses, it cannot avoid or delay unnecessary write-back operations.

[0008] Therefore, various technical solutions currently have various problems and cannot effectively solve the cache consistency problem caused by GPU multi-core processing. Summary of the invention

[0009] In view of the above problems, the purpose of the present invention is to provide a top-level structure and cache consistency processing method based on a GPU multi-core processor, aiming to solve the above technical problems.

[0010] The present invention adopts the following technical solution:

[0011] On the one hand, the top-level structure based on the GPU multi-core processor includes a video memory and multiple GPU blocks connected to the video memory data. The GPU block includes a general directory controller and multiple clusters. Each cluster includes a fixed function module, a unified rendering processor and a storage controller. The unified rendering processor includes a cluster control / manager, a Shader processor, an instruction cache and a general storage cache. The Shader processor includes multiple computing cores CU. Different numbers of CUs are started in the cluster to perform work according to the number of tasks. The general directory controller is used to monitor the status information of the general storage cache in each cluster and store all directory information to manage and update the status of the cache lines in the general storage cache.

[0012] Furthermore, the GPU blocks process in parallel, each GPU completes the rendering of one display frame, and after the current display frame is processed, other display frames are rendered alternately, or each GPU block renders one block of a display frame.

[0013] On the other hand, the cache consistency processing method based on GPU multi-core processor is implemented based on the top-level structure, wherein the main directory controller adopts the MESIPB protocol to maintain cache consistency. The MESIPB protocol defines six states, namely I invalid state, E exclusive state, M modified state, S shared state, B to be written back state and P partial rewrite state.

[0014] Further, the process of the method is as follows: after the GPU block is started, the initial state of all cache lines in the general storage cache in each cluster is the I invalid state, and according to the operation request of local access or remote access, the state is switched in six states according to the MESIPB protocol. The specific process of the state switching of the general storage cache is as follows:

[0015] In the I invalid state, if a local read request is received, the general storage cache in the cluster activates the cache line and reads the cache line data corresponding to the request from the video memory, and monitors the remote state of the current cache line at the same time. If there is a miss at the remote end, the current cache line state switches to the E exclusive state; if there is a hit at the remote end, the current cache line state switches to the S shared state; if a local write miss is detected, the current cache line state switches to the P partial rewrite state;

[0016] In the E exclusive state, if a remote read request is detected, the state switches to the S shared state; if a remote write request is detected, the cache line data is copied to the remote cache line, and the current cache line state switches to the I invalid state; if a local write miss is detected, the current cache line state switches to the M modified state;

[0017] In the M modification state, if a remote write request is detected, the cache line data is copied to the remote cache line so that the remote cache line is modified based on the current data, and then the current cache line state is switched to the I invalid state; if a remote read request is detected, the cache line data is copied to the remote cache line, and the current cache line state is switched to the B pending write-back state; if a local refresh operation is received, the current cache line data is written back to the video memory, and the current cache line state is switched to the E exclusive state;

[0018] In the S sharing state, if a remote write request is detected, the cache line data is copied to the remote cache line, and the current cache line state is switched to the I invalid state;

[0019] When in the B write-back state, if a remote write request is detected, the current cache line data is copied to the remote cache line, and then the current cache line state is switched to the I invalid state; if a local refresh operation is received, the current cache line data is written back to the video memory and the current cache line state is switched to the S shared state;

[0020] When in the P partial rewrite state, if a remote read request is detected, the modified data will be filled and copied to the remote Cache Line, the current Cache Line state will be switched to the B pending write-back state, and the remote Cache Line will be switched to the S shared state; if a remote write request is detected, the modified data will be filled and copied to the remote Cache Line, and the current Cache Line state will be switched to the I invalid state.

[0021] Furthermore, in the S shared state and the B pending write-back state, if a local write hit is detected, the current cache line state is switched to the M modified state.

[0022] The beneficial effects of the present invention are as follows: the present invention designs a top-level structure based on a GPU multi-core processor, and also provides a cache consistency processing method based on the structure; the technical solution of the present invention is based on the directory type, combined with the monitoring transmission and management status, simplifies the information exchange and transmission between the directory type general directory controller and each cache, designs six states of the MESIPB protocol, realizes the switching between cache line states, effectively reduces the number of video memory accesses, the GPU structure is clear, the scalability is good, and the cache consistency problem during GPU multi-core processing can be solved with a small resource overhead, which greatly improves the GPU processing speed and core utilization, and effectively reduces the bus bandwidth, storage bandwidth and data access overhead.

[0023] In particular, the structure of the present invention adopts a reasonable and effective organization method of GPU blocks, clusters, and computing cores CU, so that the host computer software can more flexibly split, reorganize and optimize rendering tasks, truly realizing the parallel execution of multiple tasks and multiple rendering pipelines, improving the precise management of the software, and greatly improving the overall rendering performance of the GPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the top-level structure based on the GPU multi-core processor;

[0025] Figure 2 is a schematic diagram of alternating frame rendering provided by an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of block rendering provided by an embodiment of the present invention;

[0027] Figure 4 is a specific internal structure diagram of a cluster provided by an embodiment of the present invention;

[0028] Figure 5 is a schematic diagram of a GPU block structure provided by an embodiment of the present invention;

[0029] Figure 6 It is the state switching diagram of the MESIPB protocol. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0031] GPU is a multi-core multi-threaded parallel computing structure. When unified shading is performed, the cache needs to quickly provide data to the processor and may also exchange data with the processor. When the processor reads the original data required for calculation and starts to calculate, the intermediate results after calculation may be used by other processors. Therefore, how to organize and manage multiple processors, how to deal with the cache consistency problem (Cache consistency: It is the process and mechanism to ensure that the data in the cache Cache is the same as that in the main memory. It is a key concept in computer systems, especially in computing systems involving hierarchical storage systems), and how to avoid frequent access to the video memory due to intermediate data as much as possible is crucial. In response to this problem, the present invention considers the GPU rendering process and designs a top-level structure based on a GPU multi-core processor. The structure can balance the load of each part, improve the calculation speed and core utilization of the processor, and solve the cache consistency problem caused by GPU multi-core processing, so that the entire GPU system runs smoothly and the load is balanced.

[0032] In order to illustrate the technical solution of the present invention, a specific embodiment is provided below for illustration.

[0033] like Figure 1 As shown, this embodiment provides a top-level structure based on a GPU multi-core processor, which is designed to be managed in three levels, including video memory and multiple GPU blocks connected to the video memory data, GPU0-GPUM in the figure, a total of M+1 GPU blocks; each GPU block is divided into multiple clusters Cluster, Cluster0-ClusterN in the figure, a total of N+1 clusters; each cluster is divided into multiple computing core CU arrays. Therefore, the top-level structure of the embodiment is divided into three levels: block-cluster-computing core. The present invention mainly designs the GPU top-level structure from the perspective of GPU performance, and improves the utilization rate of the computing core and quickly responds to the consistency problem caused by multiple processing cores accessing the Cache through the hierarchical structure. Due to the large number of GPU computing cores, it is also difficult for the host computer software to accurately assign tasks to each specific computing core, so the three-layer structure design organizes and effectively manages the computing cores.

[0034] When executing an action, the host computer software splits, reorganizes and sends the rendering task or computing task according to the processing capacity of the cluster. When the GPU block receives the rendering task, the task scheduler allocates the task to each cluster according to the allocation strategy. Different numbers of computing cores CU are started in the cluster to execute the work according to the number of tasks.

[0035] Multiple GPU blocks can process in parallel, and the processing method is also more flexible. For example, when rendering a multi-frame scene, one method is to render the frames alternately, such as Figure 2 As shown, each GPU completes the rendering of a display frame, and after the current display frame is processed, other display frames are rendered alternately; another method is block rendering, such as Figure 3 As shown, each GPU block renders one block of a display frame.

[0036] The GPU block uses a standard AXI4 interface for external interfaces, which is easy to expand. It is difficult to truly improve the core utilization of the processor by only expanding the GPU block. The present invention achieves refined organization and management through hierarchical design. Clusters are considered from the perspective of graphics rendering relationships. As a specific structure of clusters, such as Figure 4 As shown, each cluster includes a fixed function module (FixedFunction module), a unified rendering processor and a storage controller. The unified rendering processor includes a cluster control / manager, a Shader processor (shading processor), an instruction Cache and a universal storage Cache (US Cache). The Shader processor includes multiple computing cores CU. It can be seen that each cluster is a complete graphics pipeline that can independently complete graphics rendering tasks.

[0037] Cache is a high-speed buffer memory that can provide instructions and data to the processor at high speed, thereby accelerating the execution of the program. Generally, the instruction cache and data cache are separated in the processor design, and the cache size, association method, replacement strategy, etc. may also be different.

[0038] Specifically in operation, when the GPU block receives a rendering task, the task scheduler allocates the task to each cluster according to the allocation strategy. When the cluster receives the configuration information of the rendering task, it sends a request to read the instruction from the instruction cache, decodes and executes the instruction. During execution, it is necessary to obtain the original data, which is read from the US Cache. When the processing is completed, the intermediate results are also temporarily stored in the US Cache. After the unified rendering processor executes a complete Shader program, it will start the fixed-function module to complete specific dedicated graphics acceleration processing. The fixed-function module generally completes processing that is not convenient for general programming, cannot be processed in parallel, and has fixed functions, such as primitive assembly, plane clipping, three-dimensional clipping, Raster rasterization scanning, fragment blending, testing and other functions.

[0039] The unified rendering processors in the cluster need to access their own instruction cache and US cache, but the instruction cache is read-only, so there is no cache consistency problem. The US cache is a data cache and must be readable and writable, so cache consistency problems are inevitable. There are two ways to deal with the cache consistency problem: the directory structure and the monitoring structure. Both methods have disadvantages. In the application scenario of GPU, there are many processor cores and data read and write operations are frequent. If the local data is inconsistent with the video memory data, the data is directly written back, which will cause the bus to be very busy. The high demand for the bus by the monitoring structure will not be well adapted to the GPU application scenario. The information exchange between the central controller of the directory structure and each cache is large, which has a direct impact on performance.

[0040] The present invention is based on the directory method and combined with the monitoring method to solve the cache consistency problem. Figure 5 As shown, each GPU block is designed with a master directory controller, which is used to monitor the status information of the US Cache in each cluster and store all directory information in the master directory memory to manage and update the status of the Cache Line in the US Cache (the cache line is a fixed-size data block, and its size is based on the size of the burst read or burst write cycle) so that the GPU block can respond to processing more quickly.

[0041] Based on the above structure, this embodiment also provides a cache consistency processing method based on a GPU multi-core processor, wherein the master directory controller uses the MESIPB protocol to maintain cache consistency. The MESIPB protocol defines six states, namely, I invalid state, E exclusive state, M modified state, S shared state, B pending write-back state, and P partial rewrite state. The states of the MESIPB protocol are shown in Table 1 below:

[0042] Table 1 MESIPB status table

[0043]

[0044] The process of the method is as follows: after the GPU block is started, the initial state of all cache lines in the general storage cache in each cluster is invalid state I, and the state is switched in six states according to the MESIPB protocol based on the operation request of local access or remote access. In this embodiment, local refers to the current cluster only, and remote refers to other clusters under the same GPU block. Local access refers to the access of the processor corresponding to the US Cache in the cluster, and remote access refers to the access of the processor not corresponding to the US Cache in the cluster. Figure 6 As shown in the figure, the specific process of state switching of the general storage cache is as follows:

[0045] (1) In the I invalid state, if a local read request is received, the general storage cache in the cluster activates the cache line and reads the cache line data corresponding to the request from the video memory, while monitoring the remote state of the current cache line. If there is a miss at the remote end, the current cache line state switches to the E exclusive state; if there is a hit at the remote end, the current cache line state switches to the S shared state; if a local write miss is detected, the current cache line state switches to the P partial rewrite state. The P partial rewrite state is mainly applicable to write operations.

[0046] The initial state of all cache lines in the US Cache is marked as the I invalid state. When receiving a local read request, the US Cache will activate the cache line and read the cache line data corresponding to the request from the video memory, and then determine whether the current cache line is switched to the E exclusive state or the S shared state based on whether there is a hit in the remote state. The premise for switching from the I invalid state to the E exclusive state or the S shared state is that the cache line data corresponding to the current local read request does not hit in the local US Cache, that is, the corresponding cache line data does not exist locally, so the cache line data corresponding to the request needs to be read from the video memory.

[0047] In addition, whether the I invalid state switches to the E exclusive state or the S shared state depends on whether the Cache Line hits at the remote end, that is, whether the current Cache Line data exists at the remote end. If so, it is a hit, otherwise it is a miss.

[0048] (2) In the E exclusive state, if a remote read request is detected, that is, the remote end wants to read the current cache line, it is necessary to switch from the E exclusive state to the S shared state; if a remote write request is detected, the cache line data is copied to the remote cache line, and the current cache line state is switched to the I invalid state; if a local write miss is detected, the current cache line state is switched to the M modified state.

[0049] (3) In the M modification state, if a remote write request is detected, the cache line data is copied to the remote cache line so that the remote cache line is modified based on the current data, and then the current cache line state is switched to the I invalid state; if a remote read request is detected, the cache line data is copied to the remote cache line, and the current cache line state is switched to the B pending write-back state; if a local refresh operation is received, the current cache line data is written back to the video memory, and the current cache line state is switched to the E exclusive state.

[0050] (4) In the S sharing state, if a remote write request is detected, the cache line data is copied to the remote cache line, and the current cache line state is switched to the I invalid state; if a local write hit is detected, the current cache line state is switched to the M modified state.

[0051] (5) When in the B write-back state, if a remote write request is detected, the current cache line data is copied to the remote cache line, and then the current cache line state is switched to the I invalid state; if a local refresh operation is received, the current cache line data is written back to the video memory and the current cache line state is switched to the S shared state. If a local write hit is detected, the current cache line state is switched to the M modified state.

[0052] (6) When the P part is rewritten, if a remote read request is detected, the modified data is filled and copied to the remote Cache Line, the current Cache Line state is switched to the B pending write-back state, and the remote Cache Line is switched to the S shared state; if a remote write request is detected, the modified data is filled and copied to the remote Cache Line, and the current Cache Line state is switched to the I invalid state.

[0053] In summary, the technical solution of the present invention is based on the directory type, combined with monitoring transmission and management status, simplifies the information exchange and transmission between the directory type main directory controller and each Cache, designs six states of the MESIPB protocol, realizes the switching between CacheLine states, effectively reduces the number of video memory accesses, has a clear GPU structure and good scalability, and can solve the cache consistency problem during GPU multi-core processing with a small resource overhead, greatly improves the GPU processing speed and core utilization, and effectively reduces the bus bandwidth, storage bandwidth and data access overhead, so that the entire GPU system runs smoothly and load is balanced.

[0054] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A top-level structure based on a GPU multi-core processor, characterized in that: The top-level structure includes a video memory and multiple GPU blocks connected to the video memory data. The GPU block includes a general directory controller and multiple clusters. Each cluster includes a fixed function module, a unified rendering processor and a storage controller. The unified rendering processor includes a cluster control / manager, a shader processor, an instruction cache and a general storage cache. The shader processor includes multiple computing cores CU. Different numbers of CUs are started in the cluster to perform work according to the number of tasks. The general directory controller is used to monitor the status information of the general storage cache in each cluster and store all directory information to manage and update the status of the cache lines in the general storage cache.

2. The top-level structure based on a GPU multi-core processor as claimed in claim 1, characterized in that: The GPU blocks are processed in parallel, and each GPU completes the rendering of one display frame. After the current display frame is processed, other display frames are rendered alternately, or each GPU block renders one of the blocks of a display frame.

3. A cache consistency processing method based on a GPU multi-core processor, characterized in that: The method is implemented based on the top-level structure described in claim 1 or 2, wherein the master directory controller adopts the MESIPB protocol to maintain cache consistency, and the MESIPB protocol defines six states, namely, I invalid state, E exclusive state, M modified state, S shared state, B pending write-back state and P partial rewrite state.

4. The cache consistency processing method based on a GPU multi-core processor as claimed in claim 3, characterized in that: The process of the method is as follows: after the GPU block is started, all cache lines in the general storage cache of each cluster are initially in the invalid state. According to the operation request of local access or remote access, the state is switched in six states according to the MESIPB protocol. The specific process of the state switching of the general storage cache is as follows: In the I invalid state, if a local read request is received, the general storage cache in the cluster activates the cache line and reads the cache line data corresponding to the request from the video memory, and monitors the remote state of the current cache line. If there is a miss at the remote end, the current cache line state switches to the E exclusive state; if there is a hit at the remote end, the current cache line state switches to the S shared state; if a local write miss is detected, the current cache line state switches to the P partial rewrite state; In the E exclusive state, if a remote read request is detected, it switches to the S shared state; If a remote write request is detected, the cache line data is copied to the remote cache line, and the current cache line state is switched to the I invalid state; if a local write miss is detected, the current cache line state is switched to the M modified state; In the M modification state, if a remote write request is detected, the cache line data is copied to the remote cache line so that the remote cache line is modified based on the current data, and then the current cache line state is switched to the I invalid state; If a remote read request is detected, the cache line data is copied to the remote cache line, and the current cache line state is switched to the B pending write-back state; if a local refresh operation is received, the current cache line data is written back to the video memory, and the current cache line state is switched to the E exclusive state; In the S sharing state, if a remote write request is detected, the cache line data is copied to the remote cache line, and the current cache line state is switched to the I invalid state; When in the B write-back state, if a remote write request is detected, the current cache line data is copied to the remote cache line, and then the current cache line state is switched to the I invalid state; if a local refresh operation is received, the current cache line data is written back to the video memory and the current cache line state is switched to the S shared state; When the P part is in the rewrite state, if a remote read request is detected, the modified data is filled and copied to the remote cache line, the current cache line state is switched to the B pending write-back state, and the remote cache line is switched to the S shared state; If a remote write request is detected, the modified data is filled and copied to the remote Cache Line, and the current Cache Line state is switched to the I invalid state.

5. The cache consistency processing method based on a GPU multi-core processor as claimed in claim 4, characterized in that: In the S shared state and the B pending write-back state, if a local write hit is detected, the current cache line state is switched to the M modified state.

Images