Crosstalk-aware quantum program compiling framework system

Abstract

The invention discloses a crosstalk perception quantum program compiling framework system, which comprises a parameter optimization module, a crosstalk perception mapping module and a quantum logic gate scheduling module which are in communication connection, and is characterized in that the parameter optimization module is used for optimizing parameters of a quantum logic gate in a quantum program to be executed; the crosstalk perception mapping module is used for receiving a parameter optimization result of the parameter optimization module and determining an optimal mapping scheme of a to-be-executed quantum program by constructing a cost function, and the quantum logic gate scheduling module is used for scheduling a to-be-executed quantum program according to the optimal mapping scheme. The maximum independent set between quantum bits in a quantum program to be executed and a parallel quantum logic gate scheduling scheme of the maximum independent set are determined, compiling of the quantum program to be executed is achieved, and the quantum program to be executed is compiled by providing a quantum program compiling framework system based on crosstalk perception and comprehensively optimizing a quantum circuit mapping scheme according to perceived crosstalk noise. The accuracy and high efficiency of the quantum program compiling process are realized.

Description

Technical Field

[0001] The present invention belongs to the field of quantum computing technology, and in particular to a crosstalk-aware quantum program compilation framework system. Background Art

[0002] Quantum computing is currently believed to have the potential to catch up with or even surpass classical computing in areas such as quantum chemistry, artificial intelligence, and factorization. At present, quantum computing has entered the era of noisy intermediate-scale quantum (NISQ) chips. Quantum computing simulation is a simulation that uses numerical computing and computer science to simulate calculations that follow the laws of quantum mechanics. As a simulation program, it uses the high-speed computing power of NISQ computers based on the basic laws of quantum mechanics to depict the spatiotemporal evolution of quantum states.

[0003] At present, although existing technologies have confirmed the superiority of quantum computing, in order to fully utilize the acceleration capabilities of NISQ computers to solve practical problems, in addition to continuing to improve the performance of quantum hardware, the small number of quantum bits, low operational depth of quantum circuits, and susceptibility to noise (for example, crosstalk is an important source of noise in quantum computing) are all difficulties that must be overcome. Due to the insufficient number of quantum bit hardware, fault-tolerant quantum computing cannot be supported and it is easily affected by noise. Therefore, how to solve problems such as crosstalk under the current reality of limited NISQ computer resources is a key issue that needs to be solved in verifying the effectiveness of various quantum algorithms for NISQ computers and moving towards practical application. Summary of the invention

[0004] The purpose of the present invention is to provide a crosstalk-aware quantum program compilation framework system to address the deficiencies in the prior art. It proposes a quantum program compilation framework system based on crosstalk awareness, perceives crosstalk noise, and comprehensively optimizes the quantum circuit mapping scheme to achieve accurate and efficient quantum program compilation process, thereby effectively promoting the development of quantum computing technology.

[0005] An embodiment of the present application provides a crosstalk-aware quantum program compilation framework system, the system comprising: a communication connection parameter optimization module, a crosstalk-aware mapping module, and a quantum logic gate scheduling module, wherein:

[0006] The parameter optimization module is used to optimize the parameters of the quantum logic gates in the quantum program to be executed;

[0007] The crosstalk perception mapping module is used to receive the parameter optimization result of the parameter optimization module and determine the optimal mapping scheme of the quantum program to be executed by constructing a cost function;

[0008] The quantum logic gate scheduling module is used to determine the maximum independent set between quantum bits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme of the maximum independent set according to the optimal mapping scheme, so as to realize the compilation of the quantum program to be executed.

[0009] Optionally, the parameter optimization module includes:

[0010] A dual quantum logic gate initial parameter optimization unit and a dual quantum logic gate parallel parameter optimization unit, wherein:

[0011] The dual quantum logic gate initial parameter optimization unit is used to determine the optimal dual quantum logic gate frequency and the discrete degree parameter of the dual quantum logic gate frequency distribution in the quantum program to be executed;

[0012] The dual quantum logic gate parallel parameter optimization unit is used to optimize the coupler pulse frequency parameters of adjacent dual quantum logic gates.

[0013] Optionally, the dual quantum logic gate initial parameter optimization unit optimizes the parameters of the dual quantum logic gate in the quantum program to be executed by the following formula:

[0014]

[0015] Where W(t) represents the frequency of the optimized dual quantum logic gate at time t, W off represents the idle frequency of the coupler and qubit, W on represents the resonant frequency value of the quantum logic gate, erf represents the error function, σ represents the amplitude of the frequency waveform controlling the dual quantum logic gate, t gate represents the execution time of a quantum logic gate.

[0016] Optionally, the crosstalk perception mapping module includes:

[0017] A conversion unit, used for converting the quantum program to be executed into a directed acyclic graph;

[0018] A determination unit is used to determine the optimal mapping scheme of the quantum program to be executed by combining the parameter optimization results and traversing the directed acyclic graph.

[0019] Optionally, the determining unit includes:

[0020] A pre-gate determination subunit, used to determine a set of pre-quantum logic gates that cannot be directly executed in the topological sequence corresponding to the directed acyclic graph according to the topological order of the directed acyclic graph and the execution time of the quantum logic gates;

[0021] The mapping determination subunit is used to traverse each dual quantum logic gate in the preceding quantum logic gate set in turn, construct a tree search structure based on the SWAP gate, generate all mapping schemes inserted into the SWAP gate, and determine the optimal mapping scheme of the quantum program to be executed through a cost function.

[0022] Optionally, the cost function includes:

[0023]

[0024] Where D represents the cost function, d represents the distance cost of each SWAP gate, g represents the dual quantum logic gate that needs to be inserted into the SWAP gate, F represents the set of pre-quantum logic gates, and π l+1 For the mapping π l The sub-terms of l The new mapping π obtained after inserting the SWAP gate l+1 , and They represent the two quantum bits that need to be inserted into the SWAP gate.

[0025] Optionally, the quantum logic gate scheduling module includes:

[0026] A crosstalk map determination unit, used to generate a quantum logic gate crosstalk map;

[0027] A crosstalk subgraph determining unit, used to determine a crosstalk subgraph of the quantum logic gate crosstalk graph;

[0028] The maximum independent set determination unit is used to obtain the maximum independent set of all the crosstalk subgraphs.

[0029] Another embodiment of the present application provides a quantum computer operating system, which includes the crosstalk-aware quantum program compilation framework system described above.

[0030] Another embodiment of the present application provides a quantum computer, comprising:

[0031] A first quantum computing hardware device, wherein the crosstalk-aware quantum program compilation framework system described above is set on the first quantum computing hardware device; and

[0032] A second quantum computing hardware device in communication with the first quantum computing hardware device comprises a quantum chip, wherein the communication module of the crosstalk-aware quantum program compilation framework system sends the quantum program to be executed to the second quantum computing hardware device for executing the compilation of the quantum program.

[0033] Another embodiment of the present application provides a quantum computer-readable storage medium, wherein the storage medium stores one or more quantum computer-executable instructions. When the quantum computer-executable instructions are executed by a quantum computer, the above-mentioned crosstalk-aware quantum program compilation framework system is implemented.

[0034] Compared with the prior art, the crosstalk-aware quantum program compilation framework system disclosed in the present invention includes a communication-connected parameter optimization module, a crosstalk-aware mapping module, and a quantum logic gate scheduling module, wherein the parameter optimization module is used to optimize the parameters of the quantum logic gates in the quantum program to be executed, the crosstalk-aware mapping module is used to receive the parameter optimization results of the parameter optimization module, and determine the optimal mapping scheme of the quantum program to be executed by constructing a cost function, and the quantum logic gate scheduling module is used to determine the maximum independent set between quantum bits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme of the maximum independent set according to the optimal mapping scheme, so as to realize the compilation of the quantum program to be executed. It proposes a quantum program compilation framework system based on crosstalk perception, perceives crosstalk noise, and comprehensively optimizes the quantum circuit mapping scheme to realize the accuracy and efficiency of the quantum program compilation process, and effectively promotes the development of quantum computing technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a structural block diagram of a quantum computer provided by an embodiment of the present invention;

[0036] Figure 2 It is a schematic architecture block diagram of a crosstalk-aware quantum program compilation framework system provided by an embodiment of the present invention;

[0037] Figure 3 is a schematic diagram of a quantum chip provided by an embodiment of the present invention;

[0038] Figure 4 It is a schematic architecture block diagram of another crosstalk-aware quantum program compilation framework system provided by an embodiment of the present invention.

[0039] Description of reference numerals:

[0040] 10- The first quantum computing hardware device,

[0041] 11- Processor,

[0042] 12-Memory,

[0043] 100-Quantum Computer Operating System,

[0044] 20- Second quantum computing hardware device,

[0045] 21- Quantum chip,

[0046] 200-Crosstalk-aware quantum program compilation framework system,

[0047] 201- parameter optimization module,

[0048] 202-crosstalk perception mapping module,

[0049] 203-Quantum logic gate scheduling module,

[0050] 204-Quantum Programming Framework Module. DETAILED DESCRIPTION

[0051] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but should not be construed as limiting the present invention.

[0052] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, but should not be construed as limiting the present invention.

[0053] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0054] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0055] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0056] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0057] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0058] Figure 1 is a block diagram of a quantum computer provided by an embodiment of the present invention, such as Figure 1As shown, the quantum computer includes a first quantum computing hardware device 10 and a second quantum computing hardware device 20. A quantum computer operating system 100 is set on the first quantum computing hardware device 10. The first quantum computing hardware device 10 may include a processor 11, and may also include a memory 12. The quantum computer operating system 100 may be implemented by the processor 11 and the memory 12. The second quantum computing hardware device 20 communicates with the first quantum computing hardware device 10. The second quantum computing hardware device 20 includes a quantum chip 21.

[0059] The quantum computer operating system 100 may include a crosstalk-aware quantum program compilation framework system. The quantum computer operating system 100 generates a quantum program to be executed or a quantum computing task. The communication module sends the quantum program to be executed to the second quantum computing hardware device 20 for executing the compilation of the quantum program.

[0060] The crosstalk-aware quantum program compilation framework system 200 in the embodiment of the present application can be applied to a quantum computer operating system 100, which is a computer program that manages quantum computing software and hardware resources. Figure 2 Describe the relevant modules of each embodiment.

[0061] Figure 2 is a schematic block diagram of a crosstalk-aware quantum program compilation framework system provided by an embodiment of the present invention. Figure 2 As shown, the crosstalk-aware quantum program compilation framework system 200 may include: a communication-connected parameter optimization module 201, a crosstalk-aware mapping module 202, and a quantum logic gate scheduling module 203, wherein the parameter optimization module 201 is used to optimize the parameters of the quantum logic gates in the quantum program to be executed; the crosstalk-aware mapping module 202 is used to receive the parameter optimization result of the parameter optimization module, and determine the optimal mapping scheme of the quantum program to be executed by constructing a cost function; the quantum logic gate scheduling module 203 is used to determine the maximum independent set between quantum bits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme of the maximum independent set according to the optimal mapping scheme, so as to realize the compilation of the quantum program to be executed.

[0062] Specifically, the quantum program to be executed may include a quantum circuit. A quantum program as a whole is a total quantum circuit, which can be understood as follows: a quantum program can be composed of a quantum circuit, measurement operations on quantum bits in the quantum circuit, registers that store measurement results, and control flow nodes (jump instructions). A quantum circuit can contain dozens, hundreds, or even thousands of quantum logic gate operations. The execution process of a quantum program is the process of executing all quantum logic gates in a certain sequence, which is the time sequence in which a single quantum logic gate is executed.

[0063] In an optional implementation, the parameter optimization module 201 may include: a dual quantum logic gate initial parameter optimization unit and a dual quantum logic gate parallel parameter optimization unit, wherein the dual quantum logic gate initial parameter optimization unit is used to determine the optimal dual quantum logic gate frequency and the discrete degree parameter of the dual quantum logic gate frequency distribution in the quantum program to be executed, and the parameters optimized by the dual quantum logic gate initial parameter optimization unit may also include the pulse parameters of the quantum bit, the pulse parameters of the quantum logic gate coupler, and the pulse parameters of the coupler between the quantum bit and the adjacent quantum bit, etc.

[0064] Exemplarily, the dual quantum logic gate initial parameter optimization unit can optimize the parameters of the dual quantum logic gate in the quantum program to be executed by the following formula:

[0065]

[0066] Where W(t) represents the frequency of the optimized dual quantum logic gate at time t, W off represents the idle frequency of the coupler and qubit, W on represents the resonant frequency value of the quantum logic gate, erf represents the error function, σ represents the amplitude of the frequency waveform controlling the dual quantum logic gate, t gate represents the execution time of a quantum logic gate.

[0067] It should be noted that optimizing the parameters of dual quantum logic gates usually involves optimizing more parameters, and because the optimal parameters obtained through optimization are inconsistent when adjacent quantum bits are at different frequencies, during the specific chip initial parameter optimization process, for each quantum bit-coupler-quantum bit combination, it is necessary to obtain the parameters of the adjacent quantum bits when they are at the idle operating frequency.

[0068] Specifically, the dual quantum logic gate parallel parameter optimization unit can be used to optimize the coupler pulse frequency parameters of adjacent dual quantum logic gates. When the quantum chip is initialized, the initial parameters of each dual quantum logic gate are optimized. During the optimization process, the adjacent quantum bit frequencies can be first set to the idle frequency. Because when two adjacent dual quantum logic gates are performing quantum computing tasks, the quantum bit states are in a mixed state, they are not at the idle frequency, and the detuning between the quantum bits has changed. This means that the initial crosstalk blocking between the two dual quantum logic gates is invalid, so the parameters of the dual quantum logic gates need to be re-optimized. For example, the coupler pulse frequency parameter can be changed to the minimum value with the lowest crosstalk intensity.

[0069] In an alternative embodiment, the crosstalk-aware mapping module 202 may include: a conversion unit configured to convert a quantum program to be executed into a directed acyclic graph; a determination unit configured to determine an optimal mapping scheme for the quantum program to be executed by combining the parameter optimization result and traversing the directed acyclic graph. The determination unit may include: a pre-gate determination subunit configured to determine a set of pre-quantum logic gates that cannot be directly executed in the corresponding topological sequence of the directed acyclic graph according to the topological order of the directed acyclic graph and the execution time of the quantum logic gates; a mapping determination subunit configured to sequentially traverse each two-qubit logic gate in the set of pre-quantum logic gates, construct a tree search structure based on SWAP gates, generate all mapping schemes with inserted SWAP gates, and determine the optimal mapping scheme for the quantum program to be executed through a cost function.

[0070] Exemplarily, first, the conversion unit converts the quantum program to be executed into a directed acyclic graph. Then, according to the topological order of the directed acyclic graph and the execution time of the quantum logic gates, a set of pre-quantum logic gates that cannot be directly executed in the corresponding topological sequence of the directed acyclic graph is determined, that is, the gates that cannot be executed in the frontmost layer are selected and defined as the set of pre-quantum logic gates (front_layer). Then, based on the mapping determination subunit, each two-qubit logic gate in the set of pre-quantum logic gates is sequentially traversed. If the current frontmost quantum logic gate cannot be directly executed under the current mapping, a SWAP gate is inserted. It should be noted that the SWAP gate needs to be inserted between qubits connected by a coupler. For example, before the SWAP gate S ij , the mapping is π l : q i →Q i q j →Q j . After inserting the SWAP gate, the mapping arrangement changes to π l+1 : q i →Q j q j →Q i .

[0071] To find a more suitable mapping, a tree search structure based on SWAP gates is constructed, and all mapping schemes with inserted SWAP gates are listed. Among them, the nodes of the tree represent the mapping states, the edges represent the SWAP gates that change the mapping, and the root node of the tree is the current mapping state π l . During the construction process, specific values of M and L are set according to the performance of the current hardware computing device; the look-ahead degree of subsequent tree search is controlled by the tree depth L, and the breadth of the tree search is controlled by the number of child nodes M of each node; to reduce the complexity, M < S is also set, where S represents the number of all selectable SWAP gates.

[0072] Specifically, the tree search structure process based on the SWAP gate is an iterative process, with the initial mapping π l Take this as an example. First, obtain the quantum logic gates that cannot be directly executed and their corresponding mappings. Then, insert the SWAP gate operation into the two qubits of all quantum logic gates to be executed to obtain the new mapping (π l+1，1 , π l+1，2 ,…,π l+1，M ); then iterate the second step until the (L-1) layer mapping is obtained. For each SWAP gate S in the tree search structure based on the SWAP gate ij , insert it into the quantum program to be executed, and calculate S ij Distance cost The above cost function may include:

[0073]

[0074] Where D represents the cost function, d represents the distance cost of each SWAP gate, g represents the dual quantum logic gate that needs to be inserted into the SWAP gate, F represents the set of pre-quantum logic gates, and π l+1 For the mapping π l The sub-terms of l The new mapping π obtained after inserting the SWAP gate l+1 , and They represent the two quantum bits that need to be inserted into the SWAP gate.

[0075] In another optional implementation, after obtaining the first M nodes with the smallest distance according to the above cost function, after performing the exchange operation Sij on the current mapping, M child nodes are obtained. Finally, after obtaining the L×M search tree, we start from the last child node and evaluate the quality of the current mapping. The evaluation criteria can be determined by the following formula:

[0076]

[0077] Among them, C l，p Represents the evaluation function of the current mapping quality, C l+1，m C l，p The child of G l，p , βP l，p represents the gain and parallel parameter overhead of the two-bit quantum logic gate at node l, G represents the mapping π l，p The number of pre-quantum logic gates that can be executed under the mapping π l，pThe number of parameters that need to be re-optimized due to the parallel execution of the first two quantum logic gates is given below, β is the weight coefficient of the number of parameters that need to be re-optimized in the mapping quality, γ is the sub-item weight coefficient of the current mapping, and γ∈(0,1).

[0078] Finally, when we go back to the step of converting the quantum program to be executed into a directed acyclic graph, we can choose the maximum C l+1，p The corresponding SWAP gate, after inserting the SWAP gate p, obtains a new mapping π l，p Repeat the above steps until all quantum logic gates that cannot be directly executed are remapped, and the mapping schemes for all inserted SWAP gates can be obtained, and the optimal mapping scheme for the quantum program to be executed can be determined through the above cost function.

[0079] Specifically, the quantum logic gate scheduling module 203 is used to determine the maximum independent set between quantum bits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme of the maximum independent set according to the optimal mapping scheme, so as to realize the compilation of the quantum program to be executed.

[0080] In an optional implementation, the quantum logic gate scheduling module 203 may include: a crosstalk graph determination unit, used to generate a quantum logic gate crosstalk graph; a crosstalk subgraph determination unit, used to determine a crosstalk subgraph of the quantum logic gate crosstalk graph; and a maximum independent set determination unit, used to obtain the maximum independent set of all the crosstalk subgraphs.

[0081] The crosstalk graph determination unit is used to generate a quantum logic gate crosstalk graph G(V g , E g ), where node V g represents a qubit-coupler-qubit set that can directly execute a dual quantum logic gate, E g represents the parallel crosstalk effect between the quantum bit-coupler-quantum bit set; the weight of the edge represents the number of parameters that need to be re-optimized for the two quantum logic gates corresponding to the edge when executed in parallel.

[0082] See also Figure 3 , Figure 3 This is a schematic diagram of a quantum chip provided by an embodiment of the present invention, in which V is constructed. g，9，10 The crosstalk diagram is based on V g，9，10 represents a qubit-coupler-qubit combination, where the weight of the two-qubit gate with parallel crosstalk to other nodes adjacent to it is 2, because only one coupler frequency needs to reoptimize its parameters. g，9，10，g，14，15 、E g，9，10，g，4，5 The weight is 4, which means that the frequency parameters of two couplers need to be re-optimized.

[0083] Secondly, the crosstalk subgraph determination unit is used to obtain the crosstalk subgraph corresponding to the quantum program to be executed. First, the quantum program after mapping is converted into a directed acyclic graph, and then the DAG topological order of the quantum logic gate and the execution time t g Determine the start execution time gτ and end execution time gτ+t of each quantum logic gate g ; Then determine all the parallel quantum logic gates in the quantum program; if the execution time of the quantum logic gate satisfies the equation Then there is a time overlap, that is, the above quantum logic gate maps π to the current quantum bit. l Under parallel execution, all quantum logic gates executed in parallel are selected and a crosstalk subgraph is formed. The edges of the crosstalk subgraph represent the parallel crosstalk of the quantum logic gates, and the weight of the edge is the number of coupler parameters that need to be optimized for the parallel execution of the quantum logic gates. Then, the maximum independent set of the crosstalk subgraph is obtained using the maximum independent set determination unit. If there are no interconnected edges between the executing quantum logic gates in the crosstalk subgraph, it means that there is no parallel crosstalk, that is, the executing quantum logic gates are independent of each other and can be in the same set. The corresponding nodes are deleted one by one, and the maximum independent set is found in the remaining crosstalk graph until the crosstalk subgraph is completely disconnected.

[0084] It should be noted that in order to reduce the execution time of the quantum program, if the number of maximum independent sets is too large, the length of the quantum program will be extended and the decoherence noise will become significant. To avoid this, the number of sets in the maximum independent set should be small. In the specific process of obtaining independent sets, start from the number of maximum independent sets N, where the initial value of N is 2, and perform the following steps:

[0085] 1) Search for the maximum independent set. If the number of sets in the maximum independent set is less than or equal to N, stop;

[0086] 2) Otherwise, let K be the maximum number of re-optimization parameters allowed in the quantum chip control system, select nodes from large to small according to their degrees, and put them into N different sets;

[0087] 3) For each set, calculate the number of re-optimized parameters of the crosstalk subgraphs corresponding to these nodes. If they are all less than K, then end; otherwise, the number of sets in the maximum independent set is updated to N+1 and the above steps are repeated. Finally, the quantum logic gates in different independent sets are determined and executed.

[0088] It can be seen that by implementing a scheduling scheme for quantum logic gates based on a quantum logic gate scheduling module, the parallel crosstalk relationship between quantum logic gates can be abstracted into a crosstalk graph model, and simplified to solving the maximum independent set problem to select the largest set of quantum logic gates without parallel crosstalk. By parallelizing as many dual quantum logic gates as possible through the above method, the execution time of the quantum program can be shortened while avoiding crosstalk.

[0089] Figure 4 is a schematic block diagram of another crosstalk-aware quantum program compilation framework system provided by an embodiment of the present invention. Figure 4 As shown, the crosstalk-aware quantum program compilation framework system 200 may further include: a quantum programming framework module 204, wherein the quantum programming framework module 204 is used to provide a quantum / classical hybrid programming language, a visual programming IDE, and generate a quantum program to be executed.

[0090] Exemplarily, the quantum programming framework module 204 may include a quantum programming framework unit and a quantum classical hybrid compilation framework unit, wherein the quantum programming framework unit may be used to provide programming languages ​​and simulation computing interfaces, and users may write quantum programs based on the programming languages ​​provided by the programming framework, and perform simulation computing of quantum algorithms according to the simulation computing interfaces provided by the programming framework. At the same time, the quantum programming framework unit may also provide a variety of quantum circuit operation interfaces, such as quantum circuit printing, equivalent quantum circuit comparison, quantum circuit flipping, and conversion to other quantum programming languages. The quantum classical hybrid compilation framework unit is used to compile and optimize the quantum classical hybrid program written by the user, and adjust the timing relationship between quantum computing and classical computing, etc., to improve the execution efficiency of the quantum classical hybrid algorithm.

[0091] In another optional embodiment, the crosstalk-aware quantum program compilation framework system shown above can be installed in Figure 1 In the quantum computer shown.

[0092] It can be seen that the crosstalk-aware quantum program compilation framework system disclosed in the present invention includes a communication-connected parameter optimization module, a crosstalk-aware mapping module, and a quantum logic gate scheduling module, wherein the parameter optimization module is used to optimize the parameters of the quantum logic gates in the quantum program to be executed, the crosstalk-aware mapping module is used to receive the parameter optimization results of the parameter optimization module, and determine the optimal mapping scheme of the quantum program to be executed by constructing a cost function, and the quantum logic gate scheduling module is used to determine the maximum independent set between quantum bits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme of the maximum independent set according to the optimal mapping scheme, so as to realize the compilation of the quantum program to be executed. It proposes a quantum program compilation framework system based on crosstalk perception, based on the perception of crosstalk noise, and comprehensively optimizes the quantum circuit mapping scheme to realize the accuracy and efficiency of the quantum program compilation process, and effectively promote the development of quantum computing technology.

[0093] An embodiment of the present invention further provides a quantum computer-readable storage medium, wherein one or more quantum computer-executable instructions are stored in the storage medium. When the quantum computer-executable instructions are executed by a quantum computer, the above-mentioned crosstalk-aware quantum program compilation framework system is implemented.

[0094] Therefore, the embodiments disclosed herein may include a crosstalk-aware quantum program compilation framework system, a quantum computer operating system, a quantum computer, and / or a quantum computer program product. The quantum computer program product may include a computer-readable storage medium having executable commands of a quantum computer operating system stored thereon.

[0095] A quantum computer readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A quantum computer readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of quantum computer readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing.

[0096] The executable instructions of the quantum computer described herein can be downloaded from the quantum computer readable storage medium to each quantum computing / processing device, or downloaded to an external quantum computer or external storage device through a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each quantum computing / processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0097] The executable instructions for implementing the quantum computer operating system may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code, intermediate code, or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as C or similar programming languages. The executable instructions may be executed entirely on the quantum computer, partially on the quantum computer, as a separate software package, partially on the local quantum computer and partially on the remote quantum computer, or entirely on the remote quantum computer or server. In the case of a remote quantum computer, the remote quantum computer may be connected to the local quantum computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external quantum computer (e.g., via the Internet using an Internet service provider). In some embodiments, the various embodiments herein are implemented by utilizing state information of executable instructions of a quantum computer to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), which can execute the executable instructions of a quantum computer.

[0098] Various aspects of the present invention are described herein with reference to block diagrams of a crosstalk-aware quantum program compilation framework system, a quantum computer operating system, a quantum computer, and a computer program product according to embodiments herein. It should be understood that each block of the block diagram and the combination of blocks can be implemented by executable instructions of a quantum computer.

[0099] These quantum computer executable instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, thereby producing a quantum computing machine, so that when these instructions are executed by the processor of the quantum computer or other programmable data processing device, a device that implements the functions / actions specified in one or more blocks in the block diagram is generated. These executable instructions can also be stored in a quantum computer readable storage medium, and these instructions make the quantum computer, programmable data processing device and / or other equipment work in a specific way, so that the quantum computer readable medium storing the instructions includes a product, which includes instructions for implementing various aspects of the functions / processing specified in one or more blocks in the block diagram.

[0100] Quantum computer-readable program instructions may also be loaded onto a quantum computer, other programmable quantum data processing apparatus, or other quantum device, so that a series of processing is performed on the quantum computer, other programmable quantum data processing apparatus, or other quantum device to produce a process implemented by the quantum computer, thereby causing the instructions executed on the quantum computer, other programmable quantum data processing apparatus, or other quantum device to implement the functions / processing specified in one or more blocks in the block diagram.

[0101] The block diagrams in the accompanying drawings show the possible architecture, functions and processing of quantum computer operating systems, quantum computers and computer program products according to multiple embodiments of the present invention. In this regard, each box in the block diagram can represent a module, a program segment or a part of an instruction, and the module, a program segment or a part of an instruction contains one or more quantum computer executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and the combination of boxes can be implemented with a dedicated hardware-based quantum system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and quantum computer instructions. It is well known to those skilled in the art that implementation by hardware, implementation by software, and implementation by a combination of software and hardware are all equivalent.

[0102] The above describes in detail the structure, features and effects of the present invention based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the drawings. Any changes made according to the concept of the present invention, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the protection scope of the present invention.

Claims

1. A crosstalk-aware quantum program compilation framework system, characterized in that: The system includes: a communication connection parameter optimization module, a crosstalk perception mapping module and a quantum logic gate scheduling module, wherein: The parameter optimization module is used to optimize the parameters of the quantum logic gates in the quantum program to be executed; The crosstalk perception mapping module is used to receive the parameter optimization result of the parameter optimization module and determine the optimal mapping scheme of the quantum program to be executed by constructing a cost function; The quantum logic gate scheduling module is used to determine the maximum independent set between quantum bits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme of the maximum independent set according to the optimal mapping scheme, so as to realize the compilation of the quantum program to be executed.

2. The system according to claim 1, characterized in that The parameter optimization module comprises: A dual quantum logic gate initial parameter optimization unit and a dual quantum logic gate parallel parameter optimization unit, wherein: The dual quantum logic gate initial parameter optimization unit is used to determine the optimal dual quantum logic gate frequency and the discrete degree parameter of the dual quantum logic gate frequency distribution in the quantum program to be executed; The dual quantum logic gate parallel parameter optimization unit is used to optimize the coupler pulse frequency parameters of adjacent dual quantum logic gates.

3. The system according to claim 2, characterized in that The dual quantum logic gate initial parameter optimization unit optimizes the parameters of the dual quantum logic gate in the quantum program to be executed by the following formula: Where W(t) represents the frequency of the optimized dual quantum logic gate at time t, W off represents the idle frequency of the coupler and qubit, W on represents the resonant frequency value of the quantum logic gate, erf represents the error function, σ represents the amplitude of the frequency waveform controlling the dual quantum logic gate, t gate represents the execution time of a quantum logic gate.

4. The system according to claim 1, characterized in that The crosstalk perception mapping module includes: A conversion unit, used for converting the quantum program to be executed into a directed acyclic graph; A determination unit is used to determine the optimal mapping scheme of the quantum program to be executed by combining the parameter optimization results and traversing the directed acyclic graph.

5. The system according to claim 4, characterized in that The determining unit comprises: A pre-gate determination subunit, used to determine a set of pre-quantum logic gates that cannot be directly executed in the topological sequence corresponding to the directed acyclic graph according to the topological order of the directed acyclic graph and the execution time of the quantum logic gates; The mapping determination subunit is used to traverse each dual quantum logic gate in the preceding quantum logic gate set in turn, construct a tree search structure based on the SWAP gate, generate all mapping schemes inserted into the SWAP gate, and determine the optimal mapping scheme of the quantum program to be executed through a cost function.

6. The system according to claim 5, characterized in that The cost function includes: Where D represents the cost function, d represents the distance cost of each SWAP gate, g represents the dual quantum logic gate that needs to be inserted into the SWAP gate, F represents the set of pre-quantum logic gates, and π 1+1 For the mapping π l The sub-item is represented by the new mapping π obtained by inserting the SWAP gate into the mapping π1 l+1 , g qi and g qj They represent the two quantum bits that need to be inserted into the SWAP gate.

7. The system according to claim 1, characterized in that The quantum logic gate scheduling module comprises: A crosstalk map determination unit, used to generate a quantum logic gate crosstalk map; A crosstalk subgraph determining unit, used to determine a crosstalk subgraph of the quantum logic gate crosstalk graph; The maximum independent set determination unit is used to obtain the maximum independent set of all the crosstalk subgraphs.

8. A quantum computer operating system, characterized in that: The quantum computer operating system comprises a crosstalk-aware quantum program compilation framework system according to any one of claims 1 to 7.

9. A quantum computer, characterized in that: include: A first quantum computing hardware device, wherein the crosstalk-aware quantum program compilation framework system according to any one of claims 1 to 7 is arranged on the first quantum computing hardware device; and A second quantum computing hardware device in communication with the first quantum computing hardware device comprises a quantum chip, wherein the communication module of the crosstalk-aware quantum program compilation framework system sends the quantum program to be executed to the second quantum computing hardware device for executing the compilation of the quantum program.

10. A quantum computer readable storage medium, characterized in that: The storage medium stores one or more quantum computer executable instructions. When the quantum computer executable instructions are executed by a quantum computer, the crosstalk-aware quantum program compilation framework system according to any one of claims 1 to 7 is implemented.

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