Frequency hopping channelized transmit-receive system based on FPGA
By implementing a parity-even serial digital channelization technology on FPGA, adapting to a multi-frequency frequency hopping communication system, and coupling with a high-speed serial interface, the problem of high resource consumption of frequency synthesizers in the prior art is solved, and efficient frequency hopping communication and resource utilization are achieved.
Patent Information
- Application Number
- CN202411927671.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-03-28
AI Technical Summary
When the prior art realizes the transmission and reception of broadband frequency hopping signals, there are problems such as high resource consumption of frequency synthesizers, inability to cover all frequency points, and low resource utilization.
The frequency hopping channelized transceiver and reception system based on FPGA is adopted, and the frequency hopping communication system with multiple frequency points is adapted to the frequency hopping communication system that is effective at the same time, and is coupled with the high-speed serial interface to improve the working speed and resource utilization of the FPGA chip.
It realizes efficient work of the frequency hopping communication system under multi-frequency point situation, improves the working speed and resource utilization of the FPGA chip, and solves the problem of large resource consumption of frequency synthesizers and the inability to cover the full frequency point.
Smart Images
Figure CN119727780A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of communications, and in particular to a frequency hopping channelized transceiver system based on FPGA. Background Art
[0002] At present, the main implementation schemes for sending and receiving broadband frequency hopping signals are as follows: At the transmitting end, a direct frequency synthesizer + mixer is used to move the baseband signal to a specific frequency point. At the receiving end, the frequency hopping signal needs to be synchronized first, and normal communication can only be established after obtaining the current frequency hopping pattern. In order to improve the receiver's ability to capture synchronization information at different frequencies, the receiver often adopts a multi-channel parallel reception mechanism.
[0003] However, for the transmitter, the use of direct digital frequency synthesis technology to achieve frequency switching is only applicable to the situation where the number of effective frequency points at the same time is small. When the number of effective frequency points is large, the demand for frequency synthesizers increases linearly, and resource consumption increases. On the other hand, when the full bandwidth increases, it is difficult for the output of the digital frequency synthesizer to achieve full frequency coverage. In addition, the traditional channelization circuit based on polyphase filtering, whether transmitting or receiving, its filter group module and FFT module operate at a speed of fs / M, where fs is the signal sampling rate and M is the number of frequency points. When M is large, the operating speed of the entire FPGA is low, resulting in low resource utilization. Summary of the invention
[0004] The present disclosure proposes a frequency hopping channelized transceiver system based on FPGA, which can solve the technical problems such as the inability to cover all frequency points and low resource utilization in frequency modulation communication to a certain extent.
[0005] In a first aspect, the present disclosure provides a frequency hopping channelized transceiver system based on FPGA, comprising:
[0006] A sending data mapping module, used for receiving target data and mapping the target data into a first odd-path transmission sequence and a first even-path transmission sequence based on a frequency hopping sequence;
[0007] A first conversion module, connected to the transmission data mapping module, used for converting the first odd-path transmission sequence and the first even-path transmission sequence into first conversion data;
[0008] The first filter group module is connected to the first transformation module and is used to perform serial filtering on the first transformation data to obtain a transmission signal related to the target data.
[0009] In a second aspect of the present disclosure, a frequency hopping channelized transceiver system based on FPGA is provided, comprising:
[0010] A second filter bank module, configured to receive a transmission signal related to target data and filter the transmission signal to obtain second transformed data;
[0011] A second transformation module, connected to the second filter bank module, for transforming the second transformation data to obtain a second odd-path transmission sequence and a second even-path transmission sequence;
[0012] A receiving data mapping module is connected to the second transformation module and is used to map the second odd-path transmission sequence and the second even-path transmission sequence into the target data based on a frequency hopping sequence.
[0013] From the above description, it can be seen that the present invention provides an FPGA-based frequency hopping channelized transceiver system, which can adapt to a frequency hopping communication system that is effective at multiple frequencies at the same time by adopting odd and even serial digital channelization, and is coupled with a high-speed serial interface to improve the operating speed of the FPGA chip, thereby improving resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0015] Figure 1 This is a structural block diagram of a channelized receiver with M frequency points.
[0016] Figure 2 This is a structural block diagram of a channelized transmitter with M frequency points.
[0017] Figure 3 The structure diagram of the frequency hopping channelized transceiver system based on FPGA according to the embodiment of the present disclosure is shown.
[0018] Figure 4 The structure diagram of the frequency hopping channelized transceiver system based on FPGA according to the embodiment of the present disclosure is shown.
[0019] Figure 5 It is a schematic diagram of a sending data mapping module according to an embodiment of the present disclosure.
[0020] Figure 6 Schematic diagram of a serial low-pass filter group module according to an embodiment of the present disclosure.
[0021] Figure 7 It is a schematic diagram of a receiving data mapping module according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0022] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0023] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0024] With the rapid development of communication technology, the reliability requirements of communication systems are getting higher and higher, while the conventional fixed-frequency communication mode has weak anti-interference ability and the signal is easily intercepted. In order to further improve the reliability of the communication system, a frequency hopping communication mechanism is proposed. The frequency hopping communication mechanism can resist wideband blocking interference by increasing the bandwidth and the number of frequency hopping points, and increasing the frequency hopping rate can resist tracking interference to a certain extent. At the same time, frequency hopping communication also has strong confidentiality. The transmitter and receiver stipulate the change law of the frequency hopping point, that is, the frequency hopping pattern. As long as the interfering party does not know the pre-specified hopping rules, it is impossible to intercept the information. In related technologies, DSP (digital signal processing chip), FPGA (field programmable gate array) or other digital processing chips can be used to meet the needs of real-time processing. Among them, FPGA has greater advantages in development cycle, flexibility, real-time operation, etc., so high-speed ADC (analog-to-digital converter) sampling and high-performance FPGA can be used to implement frequency hopping communication system. At the transmitting end, the baseband signal can be moved to a specific frequency point by direct frequency synthesizer and mixer. Specifically, the local frequency hopping sequence generator outputs the frequency hopping sequence according to predetermined rules, controls the frequency synthesizer to output IQ signals of different frequencies, mixes the baseband signal with the frequency synthesizer output signal, and finally sends it to the DAC (digital-to-analog converter) to convert it into an analog signal for transmission.
[0025] At the receiving end, the frequency hopping signal needs to be synchronized first, and normal communication can only be established after obtaining the current frequency hopping pattern. In order to improve the receiver's ability to capture synchronization information of different frequencies, the receiver often adopts a multi-channel parallel receiving mechanism. Among them, a channelized receiver can be realized based on the principle of multi-phase filtering, such as Figure 1 As shown, Figure 1 This is the block diagram of a channelized receiver with M frequencies, where M = 2 n The receiver divides the broadband signal into several parallel output sub-band signals by means of a polyphase filter bank and FFT transformation. The subsequent modules can select the effective frequency point signal according to the frequency hopping sequence obtained by frequency hopping synchronization.
[0026] Then, for the sender, Figure 2 As shown, Figure 2 This is a block diagram of a channelized transmitter with M frequencies. Direct digital frequency synthesis technology is used to achieve frequency switching, which is only applicable to the case where there are fewer valid frequencies at the same time. When there are more valid frequencies, the demand for frequency synthesizers increases linearly, and resource consumption increases. On the other hand, when the full bandwidth increases, it is difficult for the output of the digital frequency synthesizer to cover all frequencies. In addition, the traditional channelized circuit based on polyphase filtering, whether transmitting or receiving, its filter bank module and FFT module work at f s / M speed, where f s is the signal sampling rate, and M is the frequency point number. When M is large, the working speed of the entire FPGA is low and the resource utilization is low. Therefore, how to improve the working speed and resource utilization of FPGA has become a technical problem that needs to be solved urgently.
[0027] In view of this, the embodiments of the present disclosure provide a frequency hopping channelized transceiver system based on FPGA. By adopting odd and even serial digital channelization, it can adapt to a frequency hopping communication system with multiple frequencies simultaneously effective, and is coupled with a high-speed serial interface to improve the working speed of the FPGA chip, thereby improving resource utilization.
[0028] The RF agile transceiver model ADRV9009 can be selected as the AD / DA (analog-to-digital conversion / digital-to-analog conversion) chip. The sampling bandwidth range of this chip in the observation reception mode is -245.76 to +245.76 MHZ, and the full bandwidth is 491.52 MHZ. The data interface can transmit 2 16-bit IQ sampling data in one clock cycle.
[0029] The full bandwidth can be divided into several sub-channels according to the number of frequencies of the frequency hopping system. For example, taking 32 frequencies as an example, the bandwidth of 491.52MHZ is divided into 32 segments in steps of 15.36MHZ. Each segment is a sub-channel, and the center of each sub-channel is a frequency hopping frequency. If the channels are divided according to positive and negative symmetry, the positive and negative frequency bands should be divided into 16 sub-channels each. At this time, the center frequency of channel 0 should be at +7.68MHZ. However, this division method will introduce secondary up / down conversion during channelized transmission and reception, consuming additional DSP (digital signal processing unit) resources. From a resource perspective, an asymmetric channel division method is adopted. At this time, the calculation formula for the kth center frequency is as follows:
[0030]
[0031] According to the above-mentioned divided channels, a low-pass filter is designed. The passband of the low-pass filter should be 0-7.68 MHZ, but the actual filter has a transition band, so the actual filter index is designed as a passband of 0-6 MHZ and a transition band of 6-9.36 MHZ. In this way, there is inevitably some aliasing between two adjacent channels. The order of the filter is set to 256, which is conducive to the subsequent multi-phase decomposition of the low-pass filter.
[0032] Assume that the baseband signal loaded to the kth frequency point is m k (n), the D-fold interpolated signal is m′ k (n), then:
[0033]
[0034] The final transmitter output is:
[0035]
[0036] Among them, h lp (n) is the prototype low-pass filter designed in step S3, and polyphase decomposition is performed on it, setting n = 32*n+p, p∈[0,31], and ω k Substituting in:
[0037] Y p (n) = IFFT[m k (n)]*k p (n).
[0038] In the formula, h p (n) is h lp (n) After the polyphase decomposition, the p-th sub-filter can realize the synchronous loading of multiple data channels onto 0 to 31 sub-channels through channelized transmission.
[0039] Channelized reception and channelized transmission are a pair of dual operations. Channelized reception can synchronously receive 32 sub-channel data and pass them to the subsequent processing module. Suppose the received signal is S(n), then the output of the kth sub-channel is:
[0040]
[0041] The results after multiphase decomposition are:
[0042] y k (m) = IFFT(S p (m)*h p (m)).
[0043] Among them, S p (m) is the result after delayed extraction of the S(n) signal.
[0044] The JESD204B interface of the ADRV9009 chip transmits 2 IQ sampling data in one clock cycle, with a full bandwidth of 491.52 MHZ. The input data rate of the FPGA is 245.76 MHZ, divided into two odd and even inputs. In order to couple the FPGA circuit with the JESD204B interface and to improve resource utilization through serialization, the channelized transmission circuit can be designed as Figure 3 The structure shown in the figure, the channelized receiving circuit is designed as Figure 4 The structure shown.
[0045] See also Figure 3 , Figure 3 A schematic structural diagram of a frequency hopping communication system based on FPGA according to an embodiment of the present disclosure is shown. Figure 3 In the embodiment, a frequency hopping communication system based on FPGA may further include:
[0046] A sending data mapping module, used for receiving target data and mapping the target data into a first odd-path transmission sequence and a first even-path transmission sequence based on a frequency hopping sequence;
[0047] A first conversion module, connected to the transmission data mapping module, used for converting the first odd-path transmission sequence and the first even-path transmission sequence into first conversion data;
[0048] The first filter group module is connected to the first transformation module and is used to perform serial filtering on the first transformation data to obtain a transmission signal related to the target data.
[0049] The first transformation module may include a first Fourier transformation module or a first inverse Fourier transformation module, which is used to perform Fourier transformation or inverse Fourier transformation on the first odd-path transmission sequence and the first even-path transmission sequence to obtain corresponding first transformation data.
[0050] In some embodiments, the sending data mapping module includes:
[0051] A first odd-path memory, used for acquiring first odd-path data from the target data based on the frequency hopping sequence;
[0052] A first odd-path data selector, connected to the first odd-path memory, configured to map the first odd-path data to the first odd-path transmission sequence based on the frequency hopping sequence;
[0053] a first even-path memory, configured to obtain first even-path data from the target data based on the frequency hopping sequence;
[0054] The first even-path data selector is connected to the first even-path memory and is used for mapping the first even-path data into the first even-path transmission sequence based on the frequency hopping sequence.
[0055] Specifically, to achieve the serial channel transmission of odd and even channels, the multiple baseband signals can be reordered according to the frequency hopping sequence. The data transmission order after mapping is the frequency point arrangement order. Assuming the frequency hopping sequence is 0, 4, 8, 7, it means that the 4 baseband data should be mapped to the 4 frequencies 0, 4, 8, and 7 respectively. The mapping result should be: Even channel: D00D40D800000000000; Odd channel: 000D7000000000000. The data transmission order is from left to right, D i Indicates the data of the i-th frequency point. When a frequency point does not load data, it is filled with 0.
[0056] The transmission data mapping is implemented by multi-port RAM and data selector, where the depth of the multi-port RAM is 32, with one write port and two read ports. Multi-channel baseband data is written into two multi-port RAMs in two groups of odd and even using the frequency hopping sequence as the write address, and two groups of data are read out from the two odd and even RAMs in sequence. In order to meet the continuous reading and writing of data, ping-pong operation is required, so the depth of the multi-port RAM should be doubled to 64. The read data uses the frequency hopping sequence as the selection signal. When the read address of the odd RAM is equal to the frequency hopping sequence, it indicates that the current data is valid and the read data of the odd RAM is output; when the read address of the even RAM is equal to the frequency hopping sequence, it indicates that the current data is valid and the read data of the even RAM is output, otherwise all zeros are output. Its structure is as follows Figure 5 shown.
[0057] In some embodiments, the first transformation module includes:
[0058] The multi-stage operation module is used to perform multi-stage butterfly operations on the first odd-path transmission sequence and the first even-path transmission sequence in sequence to obtain the first transformed data.
[0059] Among them, the butterfly operation divides the data into two parts, odd and even, and then performs FFT transformation (Fourier transform) or IFFT transformation (Inverse Fourier transform) on the two parts respectively, and finally combines the results of the two parts according to certain rules.
[0060] Specifically, the multi-channel baseband signal is mapped into a serial odd and even signal. The two signals need to be transformed by 32-point FFT or IFFT. The 32-point FFT or 32-point IFFT can be divided into five-level butterfly operations. Since the data is continuously input and output, the five-level butterfly operation should be designed as a parallel pipeline structure. The first four levels of odd and even are executed separately, which is equivalent to 16-point transformation of the two channels. The fifth level combines the odd and even channels into one level for butterfly operation and output.
[0061] In some embodiments, the multi-stage operation module includes a five-stage butterfly operation module, including:
[0062] A first-level operation module performs a first-level butterfly operation on the first odd-path transmission sequence and the first even-path transmission sequence to obtain a first-level operation result;
[0063] A second-level operation module, connected to the first-level operation module, for performing a second-level butterfly operation on the first-level operation result to obtain a second-level operation result;
[0064] A third-level operation module, connected to the second-level operation module, for performing a third-level butterfly operation on the second-level operation result to obtain a third-level operation result;
[0065] A fourth-level operation module, connected to the third-level operation module, and configured to perform a fourth-level butterfly operation on the third-level operation result to obtain a fourth-level operation result;
[0066] The fifth-level operation module is connected to the fourth-level operation module and is used to perform a fifth-level butterfly operation on the fourth-level operation result, and merge the fourth operation results according to the butterfly operation rule to obtain the first transformed data.
[0067] Specifically, taking 32-point FFT as an example, the five-level butterfly operation may include: dividing the 32-point data into two groups of odd and even data, each with 16 points. Then, the first two levels of butterfly operation of 16-point FFT are performed on the two groups of data respectively (i.e., regarded as two independent 16-point FFT). The third level of butterfly operation is continued to be performed on the two groups of odd and even data respectively, and each group of data becomes 8 points. The fourth level of butterfly operation can be continued to be performed on the two groups of odd and even data respectively, and each group of data becomes 4 points. The fifth level of butterfly operation can be continued to be performed on the two groups of odd and even data respectively, and each group of data becomes 2 points. However, it should be noted that in the complete five-level operation of 32-point FFT, the fourth level is not the final merging step, but further decomposes the data into smaller units for more efficient calculation. Finally, the 2-point results of the two groups of odd and even data are merged according to the rules of butterfly operation to obtain the final result of 32-point FFT.
[0068] In some embodiments, the first filter group module includes multiple groups of first sub-filters connected in series; wherein, the sub-filter data output by each group of first sub-filters is used as the input of the next group of first sub-filters, and the transmission output by the first filter group module is obtained based on the outputs of all the first sub-filters.
[0069] Specifically, the sub-filter may include a buffer and a FIR filter, wherein the input end of the FIR filter is connected to the buffer. The filter bank module is implemented using a FIFO (first in, first out) buffer and a fully parallel FIR filter, and is suitable for applications that require simultaneous processing of multiple signal channels and have high real-time requirements. Among them, since the calculation of the FIR filter usually requires multiple input samples (i.e., the order of the filter), and the input signal may arrive continuously in the form of a stream, the buffer can be used to store enough input samples for the filter to use. The FIFO buffer can store and output data in the order of the input data to ensure that the filter can correctly obtain the required input samples. In multi-channel signal processing, the data of each channel may not be completely synchronized. The FIFO buffer can help adjust the data arrival time between different channels so that they can keep synchronized during filter processing to maintain signal consistency and avoid phase distortion.
[0070] A fully parallel FIR filter is one in which all the coefficients and input samples of the filter are calculated simultaneously, so that the entire filtering operation is completed within one clock cycle. Since all calculations are performed in parallel, a fully parallel FIR filter can process input signals at very high speeds. Since each input sample is immediately used to calculate the output, the latency of a fully parallel FIR filter is very low. By adjusting the coefficients of the filter, the frequency response of the filter can be easily changed. This allows a fully parallel FIR filter to flexibly adapt to different signal processing requirements.
[0071] Specifically, the low-pass filter group is derived from the multi-phase decomposition of the low-pass filter. The low-pass filter is 256-order and has 32 frequency points. Therefore, the 256-order filter is decomposed into 32 groups of 8-order sub-filters. These 32 sub-filters constitute a filter group. The filter group module is implemented using FIFO buffering and fully parallel FIR filters. The coefficients of the 32 groups of sub-filters are divided into two odd and even paths, 16 groups in each path, and each path multiplexes an 8-order fully parallel FIR filter. Each input terminal of the filter is connected to a synchronous FIFO with a depth of 16 as a buffer. The output of a group of sub-filters is calculated in each clock cycle. 16 clock cycles can complete a round of filtering of a total of 16 sub-filters. The serial filter group module can be realized by repeating the cycle. Its structure is as follows: Figure 6 shown.
[0072] See also Figure 4 , Figure 4 A schematic structural diagram of a frequency hopping channelized transceiver system based on FPGA according to an embodiment of the present disclosure is shown. Figure 4 In the embodiment, a frequency hopping channelized transceiver system based on FPGA may further include:
[0073] A second filter bank module, configured to receive a transmission signal related to target data and filter the transmission signal to obtain second transformed data;
[0074] A second transformation module, connected to the second filter bank module, for transforming the second transformation data to obtain a second odd-path transmission sequence and a second even-path transmission sequence;
[0075] A receiving data mapping module is connected to the second transformation module and is used to map the second odd-path transmission sequence and the second even-path transmission sequence into the target data based on a frequency hopping sequence.
[0076] In some embodiments, the second filter group module includes multiple groups of second sub-filters connected in series; wherein, the second sub-filter data output by each group of second sub-filters is used as the input of the next group of second sub-filters, and the transmission output by the second filter group module is obtained based on the outputs of all the second sub-filters.
[0077] In some embodiments, the second transformation module includes:
[0078] A multi-stage operation module is used to convert the second transformed data into the second odd-path transmission sequence and the second even-path transmission sequence.
[0079] The second transformation module may include a second Fourier transformation module or a second inverse Fourier transformation module, which is used to convert the second transformation data into a second odd-path transmission sequence and a second even-path transmission sequence. Specifically, the second transformation module may perform a five-level butterfly operation, which may be the same as the five-level butterfly operation of the first transformation module.
[0080] In some embodiments, the receiving data mapping module includes:
[0081] A second odd path memory, used for acquiring second odd path data from a second odd path transmission sequence based on the frequency hopping sequence;
[0082] A second odd-way data selector, connected to the second odd-way memory, for mapping the second odd-way data to the odd-way data in the target data based on the frequency hopping sequence;
[0083] a second even-path memory, used for acquiring second even-path data from the target data based on the frequency hopping sequence;
[0084] The second even-path data selector is connected to the second even-path memory and is used for mapping the second even-path data to the even-path data in the target data based on the frequency hopping sequence.
[0085] Specifically, the receiving data mapping module and the sending data mapping module are a set of dual operations. The sending data mapping module maps multi-channel parallel data into odd and even channels according to the frequency hopping sequence, and the receiving data mapping module takes out the corresponding data one by one according to the frequency hopping sequence.
[0086] The receiving data mapping module is similar to the sending data mapping module, and is implemented by multi-port RAM and data selector. The RAM depth is 16. As in step S6, ping-pong operation is used, so the depth is doubled to 32, with one write port and two read ports. The even and odd input data are written into the even and odd RAMs in sequence. The high 4 bits of the frequency hopping sequence are used as the read address to read out groups of data from the two RAMs at a time. The read data uses the lowest bit of the frequency hopping sequence as the selection signal. When the lowest bit of the frequency hopping sequence is 0, the data corresponding to the even RAM is output, and when it is 1, the data corresponding to the odd RAM is output. Its structure is as follows: Figure 7 shown.
[0087] It can be seen that the FPGA-based frequency hopping channelized transceiver system according to the embodiment of the present disclosure can adapt to the frequency hopping communication system with multiple frequency points simultaneously and effectively, and is coupled with the JESD204B interface. At the same time, the working speed of the FPGA chip is improved through serialization processing, thereby improving resource utilization. It can be used for the transmission data mapping circuit and the reception data mapping circuit of any frequency point number and any frequency point position.
[0088] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.
[0089] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present disclosure difficult to understand, the known power / ground connections to the integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present disclosure difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present disclosure will be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it is apparent to those skilled in the art that the embodiments of the present disclosure can be implemented without these specific details or with changes in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.
[0090] Although the present disclosure has been described in conjunction with specific embodiments of the present disclosure, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
[0091] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.
Claims
1. A frequency hopping channelized transceiver system based on FPGA, comprising: A sending data mapping module, used for receiving target data and mapping the target data into a first odd-path transmission sequence and a first even-path transmission sequence based on a frequency hopping sequence; A first conversion module, connected to the transmission data mapping module, used for converting the first odd-path transmission sequence and the first even-path transmission sequence into first conversion data; The first filter group module is connected to the first transformation module and is used to perform serial filtering on the first transformation data to obtain a transmission signal related to the target data.
2. The system according to claim 1, wherein: The sending data mapping module includes: A first odd-path memory, used for acquiring first odd-path data from the target data based on the frequency hopping sequence; A first odd-path data selector, connected to the first odd-path memory, configured to map the first odd-path data to the first odd-path transmission sequence based on the frequency hopping sequence; a first even-path memory, configured to obtain first even-path data from the target data based on the frequency hopping sequence; The first even-path data selector is connected to the first even-path memory and is used for mapping the first even-path data into the first even-path transmission sequence based on the frequency hopping sequence.
3. The system according to claim 1, wherein: The first transformation module includes: The multi-stage operation module is used to perform multi-stage butterfly operations on the first odd-path transmission sequence and the first even-path transmission sequence in sequence to obtain the first transformed data.
4. The system according to claim 3, wherein: The multi-level operation module includes a five-level butterfly operation module, including: A first-level operation module performs a first-level butterfly operation on the first odd-path transmission sequence and the first even-path transmission sequence to obtain a first-level operation result; A second-level operation module, connected to the first-level operation module, for performing a second-level butterfly operation on the first-level operation result to obtain a second-level operation result; A third-level operation module, connected to the second-level operation module, for performing a third-level butterfly operation on the second-level operation result to obtain a third-level operation result; A fourth-level operation module, connected to the third-level operation module, and configured to perform a fourth-level butterfly operation on the third-level operation result to obtain a fourth-level operation result; The fifth-level operation module is connected to the fourth-level operation module and is used to perform a fifth-level butterfly operation on the fourth-level operation result, and merge the fourth operation results according to the butterfly operation rule to obtain the first transformed data.
5. The system according to claim 1, wherein: The first filter group module includes multiple groups of first sub-filters connected in series; wherein the sub-filter data output by each group of first sub-filters is used as the input of the next group of first sub-filters, and the transmission output by the first filter group module is obtained based on the outputs of all the first sub-filters.
6. A frequency hopping channelized transceiver system based on FPGA, comprising: A second filter bank module, configured to receive a transmission signal related to target data and filter the transmission signal to obtain second transformed data; A second transformation module, connected to the second filter bank module, for transforming the second transformation data to obtain a second odd-path transmission sequence and a second even-path transmission sequence; A receiving data mapping module is connected to the second transformation module and is used to map the second odd-path transmission sequence and the second even-path transmission sequence into the target data based on a frequency hopping sequence.
7. The system according to claim 6, wherein: The receiving data mapping module includes: A second odd-path memory, configured to obtain second odd-path data from a second odd-path transmission sequence based on the frequency hopping sequence; A second odd-way data selector, connected to the second odd-way memory, for mapping the second odd-way data to the odd-way data in the target data based on the frequency hopping sequence; a second even-path memory, used for acquiring second even-path data from the target data based on the frequency hopping sequence; The second even-path data selector is connected to the second even-path memory and is used for mapping the second even-path data to the even-path data in the target data based on the frequency hopping sequence.
8. The system according to claim 6, wherein: The second filter group module includes multiple groups of second sub-filters connected in series; wherein, the second sub-filter data output by each group of second sub-filters is used as the input of the next group of second sub-filters, and the transmission output by the second filter group module is obtained based on the outputs of all the second sub-filters.
9. The system according to claim 6, wherein: The second transformation module includes: A multi-stage operation module is used to convert the second transformed data into the second odd-path transmission sequence and the second even-path transmission sequence.
10. The system according to claim 9, wherein: The second transformation module includes a second Fourier transformation module or a second inverse Fourier transformation module, which is used to perform a five-level butterfly operation.