DDR interface arbitration control method suitable for video processing

Abstract

The invention provides a DDR (Double Data Rate) interface arbitration control method suitable for video processing, which relates to the technical field of embedded computer video processing, and comprises the following steps of: respectively setting a data volume fixed length for a plurality of mutually independent video storage control channels; performing arbitration control on the current state through a DDR interface arbitration controller, if the write operation is operated, judging whether the current to-be-written cache amount of the video storage control channel reaches the data volume fixed length of the channel, and if the read operation state is operated, performing arbitration control on the current state; and if not, judging whether the current to-be-read cache amount of the video storage control channel reaches the data volume fixed length of the channel. According to the DDR interface arbitration control method, the abnormal condition that null data FIFO is read can be avoided, and the reliability is high; the channel switching frequency is reduced, and the data access efficiency is improved; frequent change of multiple addresses is avoided, the stability is high, and the stability and reliability requirements of multi-channel image data processing and image display of an embedded computer are better met.

Description

Technical Field

[0001] The invention relates to the technical field of embedded computer video processing, and in particular to a DDR interface arbitration control method suitable for video processing. Background Art

[0002] With the development of embedded computer technology and video image technology, integrated display technology has become increasingly complex, and the requirements for display integration have become increasingly higher. In the integrated computer display system, it is necessary to collect and display video images sent by multiple external visual acquisition devices. At present, embedded computers with integrated display functions use the logic operation processing of FPGA (field programmable gate array) to realize functions such as video switching and superimposed display. Among them, for video switching and superimposed display from different sources, the logic control of the FPGA in the computer is usually used to enter the DDR memory to splice into a complete picture. According to the final display requirements, the pictures of different data sources are read from the DDR memory and controlled for display.

[0003] The DDR controller in FPGA consists of two parts: the lower-layer FPGA official IP core MIS (Memory Interface Solutions) and the upper-layer DDR interface arbitration controller. MIS uses the internal resources of FPGA to implement the physical layer for DDR memory interface, directly connects to the external DDR memory chip, and provides the user-available APP (application) interface (MIS-APP interface).

[0004] The DDR interface arbitration controller has developed a multi-channel storage controller based on a dual FIFO interface for the MIS-APP interface. Figure 1 As shown in the figure, the arbitrator provides multiple independent storage control channels to the upper layer. Each channel contains two FIFO interfaces, one for the instruction FIFO interface and the other for the data FIFO interface. The arbitrator performs priority arbitration on the read and write requests sent by each channel, and selects a channel to exclusively use the MIS-APP interface for DDR read and write operations. The bonding logic completes the interaction between the dual FIFO interface and the MIS-APP interface. During the write operation, the instruction FIFO and the data FIFO are read, and the data FIFO is written into the MIS-APP interface (that is, into the DDR); during the read operation, the instruction FIFO is read, and the read data of the MIS-APP interface is written into the data FIFO.

[0005] All logic circuits inside the DDR interface arbitration controller in the FPGA run in the same clock domain. Only the interface of the bonding logic has signals introduced into the non-clock domain. The DDR interface arbitration controller uses asynchronous FIFOs (instruction FIFOs and data FIFOs) to isolate the clock domains of the application layer and the MIS-APP interface. The asynchronous FIFO is the source of cross-clock domain signals. The data and control signals of the asynchronous FIFO in the DDR controller are cross-clock domain signals, which will cause a certain delay due to the frequency of the previous and next clock domains and the internal processing mechanism. The state machine jump mode of the DDR interface arbitration controller needs to fully consider eliminating the abnormal situation of being read when the asynchronous FIFO is empty, otherwise there will be errors in writing data to the DDR memory, which will appear as a chaotic display screen.

[0006] If only the command FIFO is judged to be "not empty" but the data FIFO is not judged to be "not empty", the command FIFO may be "not empty" but the data FIFO may be empty (the command FIFO is valid earlier than the data FIFO). Because the clock domain is switched inside the asynchronous FIFO, the data is not written when the "empty" FIFO is read, which will eventually cause data errors in the DDR3 memory. Therefore, only when the data FIFO is judged to be "not empty" can the internally stored data be read reliably. Summary of the invention

[0007] In view of this, in order to fully solve the abnormal error of reading when the asynchronous FIFO in the DDR controller is empty during video data processing, the embodiment of the present application provides a DDR interface arbitration control method suitable for video processing to ensure that there is no abnormal operation due to the data FIFO being "empty" during the read / write operation, thereby meeting the stability and reliability requirements of multi-channel image data processing and image display of embedded computers.

[0008] The embodiment of the present application provides the following technical solution: a DDR interface arbitration control method suitable for video processing, comprising:

[0009] The data volume and fixed length are respectively set for multiple independent video storage control channels; wherein the video storage control channel is a storage control channel based on a dual FIFO interface, and the dual FIFO interface includes an instruction FIFO interface and a data FIFO interface;

[0010] Perform arbitration control of the current state through the DDR interface arbitration controller. If the write operation state is in operation, determine whether the current cache amount to be written of the video storage control channel reaches the fixed length of the data amount of the channel. If so, issue a write request through the instruction FIFO interface, read the image data through the data FIFO interface and write it to the MIS-APP interface, determine whether the image data amount written to the MIS-APP interface reaches the fixed length of the data amount of the channel, and if so, jump to the waiting arbitration control state;

[0011] If the read operation state is in progress, determine whether the current cache amount to be read of the video storage control channel reaches the data length of the channel. If so, issue a read request through the instruction FIFO interface, read the image data through the MIS-APP interface and write it to the data FIFO interface, determine whether the image data amount read from the MIS-APP interface reaches the data length of the channel, and if so, jump to the waiting arbitration control state.

[0012] According to an embodiment of the present application, the fixed length of the data volume of the channel is calculated according to the image resolution of the video storage control channel.

[0013] According to an embodiment of the present application, the data volume fixed length of the channel is calculated according to the image resolution of the video storage control channel, including:

[0014] According to the image resolution of the video storage control channel, the maximum pixel value and the pixel value transmitted per unit time of the channel are determined, and the ratio of the maximum pixel value to the pixel value transmitted per unit time is used as the data volume fixed length of the channel.

[0015] According to an embodiment of the present application, the MIS-APP interface is connected to an external DDR memory to write and read image data to the DDR memory.

[0016] According to an embodiment of the present application, the DDR memory stitches the written image data into a complete picture, and reads different data source pictures from the DDR memory for control display according to display requirements.

[0017] According to an embodiment of the present application, the instruction FIFO interface caches instruction types and memory addresses, and the data FIFO interface caches image data.

[0018] Compared with the prior art, at least one of the above-mentioned technical solutions adopted in the embodiments of this specification can achieve the following beneficial effects at least: the embodiments of the present invention add a fixed-length burst jump mechanism, which can be specifically configured according to actual conditions and is flexible to control; it avoids the abnormal situation of reading an empty data FIFO and has high reliability; it reduces the channel switching frequency and improves data access efficiency; it avoids frequent changes in multiple addresses and has high stability, which better meets the stability and reliability requirements of multi-channel image data processing and image display of embedded computers. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 It is a schematic diagram of the upper and lower functional blocks of the DDR3 controller;

[0021] Figure 2 1 is a schematic diagram of an internal state machine of a DDR interface arbitration controller of a burst mechanism with fixed data length in an embodiment of the present invention;

[0022] Figure 3 It is a functional block diagram of a DDR3 controller in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0024] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0025] like Figure 2-Figure 3 As shown, an embodiment of the present invention provides a DDR interface arbitration control method suitable for video processing, comprising:

[0026] The data volume and fixed length are respectively set for multiple independent video storage control channels; wherein the video storage control channel is a storage control channel based on a dual FIFO interface, and the dual FIFO interface includes an instruction FIFO interface and a data FIFO interface; wherein the instruction FIFO interface caches instruction types and memory addresses, and the data FIFO interface caches image data;

[0027] The arbitration control of the current state is performed through the DDR interface arbitration controller. If the write operation state is running, it is determined whether the current cache amount to be written of the video storage control channel reaches the data amount fixed length of the channel. If so, a write request is issued through the instruction FIFO interface, the image data is read through the data FIFO interface and written to the MIS-APP interface, and it is determined whether the image data amount written to the MIS-APP interface reaches the data amount fixed length of the channel. If so, it jumps to the waiting arbitration control state; if the read operation state is running, it is determined whether the current cache amount to be read of the video storage control channel reaches the data amount fixed length of the channel. If so, a read request is issued through the instruction FIFO interface, the image data is read through the MIS-APP interface and written to the data FIFO interface, and it is determined whether the image data amount read from the MIS-APP interface reaches the data amount fixed length of the channel. If so, it jumps to the waiting arbitration control state.

[0028] The MIS-APP interface is connected to an external DDR memory to write and read image data to the DDR memory. The DDR memory splices the written image data into a complete picture, and reads different data source pictures from the DDR memory for control display according to display requirements.

[0029] The method of the embodiment of the present invention is an improved state machine jump mode of a DDR interface arbitration controller, in which the jump mode of the state machine is a burst mode with a fixed data length, wherein the burst length of the data can be calculated according to the resolution of different channel images. In this mode, the data cache and jump strategy of the channel is changed from a random jump mode in which data is processed as long as there is data to a burst jump mode in which a fixed-length value is continuously processed after a certain amount of data is cached. It is ensured that there is no abnormal operation due to "empty" data FIFO during the read / write operation.

[0030] In a specific implementation manner of the embodiment of the present invention, the fixed length of the data volume of the channel is calculated according to the image resolution of the video storage control channel.

[0031] Specifically, the data volume fixed length of the channel is calculated according to the image resolution of the video storage control channel, including: determining the maximum pixel value and the pixel value transmitted per unit time of the channel according to the image resolution of the video storage control channel, and taking the ratio of the maximum pixel value and the pixel value transmitted per unit time as the data volume fixed length of the channel.

[0032] like Figure 2 As shown, in the internal state machine of the embodiment of the present invention, no read and write operations are performed in the IDLE state, write operations are performed in the WRITE state, and read operations are performed in the READ state. The data amount fixed length judgment mechanism of the embodiment of the present invention is compared with the traditional simple instruction FIFO "non-empty" judgment mechanism, and its changes are shown in Table 1.

[0033] Table 1 Change comparison table

[0034]

[0035] For example, an embedded computer needs to complete various overlay display functions of 1 analog PAL video and 2 digital DVI videos. The internal working principle of the product is to decode the analog PAL video and DVI digital video and convert them into RGB signals. The signal data enters the DDR3 memory through the control of FPGA to splice into a complete picture. According to the final display requirements, the pictures of different data sources are read from the DDR3 memory and controlled for display. The specific functional block diagram is as follows Figure 3 shown.

[0036] The embedded computer has the following video interfaces:

[0037] a. 1-channel analog differential PAL video interface, denoted as PAL;

[0038] b. 2-way digital DVI video input interface; one from external video equipment, denoted as EDVI; the other from internal graphics drawing interface, denoted as GDVI;

[0039] c. 3-way digital DVI video output interface, denoted as DISDVI1, DISDVI2, DISDVI3.

[0040] One of the complex video switching overlay display function modes is: PAL, EDVI and GDVI overlay display;

[0041] Corresponding to the display mode, the three-channel videos of PAL, EDVI and GDVI are buffered in DDR after format conversion. The video switching and overlay function block takes out the required video data from the buffer of DDR according to the bus instruction to perform video overlay processing.

[0042] In this display mode, the usage of the DDR controller is as follows:

[0043] a. Write channel 1: PAL amplification before entering the cache;

[0044] b. Write channel 2: PAL is amplified and put into cache to be read in superposition;

[0045] c. Write channel 3: EDVI is put into cache and waits for superposition reading;

[0046] d. Write channel 4: GDVI is put into cache and waits for overlay reading;

[0047] e. Read channel 1: read before PAL amplification and do amplification;

[0048] f. Read channel 2: read and amplify PAL for superposition;

[0049] g. Read channel 3: read EDVI for superposition;

[0050] h. Read channel 4: read GDVI for overlay;

[0051] The specific implementation method of the method of the embodiment of the present invention is as follows:

[0052] 1. The resolution of the video channel in the example of the embodiment of the present invention is: 720x576 before PAL amplification, 800x600 after PAL amplification, and 1600x1200 for the other 3 DVIs. The video data transmission architecture in the example uses 4 DDR3 memories, each with 16 bits, and uses 8-burst mode (i.e., 8 bits of data are continuously transmitted per unit time). The total bit width per unit time can be calculated as 4*16*8=512 bits. The size of each pixel is set to 16 bits (higher image quality scenario), and the number of pixels transmitted per unit time is 32 (512÷16=32).

[0053] 2. Calculate the burst length according to the resolution of images in different channels, the maximum pixel value ÷ pixel transmitted per unit time = fixed length; for PAL video with a resolution of 720x576, the burst fixed length depth is 720÷32=20 based on the row pixel value of 720; for PAL video with a resolution of 800x600, the burst fixed length depth is 800÷32=25 based on the row pixel value of 800; for DVI video with a resolution of 1600x1200, the burst fixed length depth is 1600÷32=50 based on the row pixel value of 1600; corresponding to 1 PAL video of 720x576 or 800x600, the burst lengths of 3 DVI video channels of 1600x1200 are set to 20, 25, 50, 50, 50 respectively.

[0054] 3. When the read operation is in progress, when the amount of buffer to be read from the channel reaches the fixed-length burst depth, the instruction FIFO interface sends a read request, waiting for data to be read from the MIS-APP interface (i.e., DDR3 memory) and written to the data FIFO. It will jump to wait for the next arbitration until the data read from the MIS-APP interface reaches the fixed-length burst depth.

[0055] 4. When the write operation is in progress, when the amount of buffer to be written to the channel reaches the fixed-length burst depth, the instruction FIFO interface sends a write request, waiting to read data from the data FIFO interface and write it to the MIS-APP interface. It will jump to wait for the next arbitration until the data written to the MIS-APP interface reaches the fixed-length burst depth.

[0056] Since the minimum data volume is 20-burst, even if the two asynchronous FIFOs, the command and data FIFOs, are written at different times, it is guaranteed that there will be at least 19 data and they will not be empty. This completely eliminates the possibility of reading an empty FIFO and ensures stable image display.

[0057] The data fixed-length jump mechanism of the embodiment of the present invention can be specifically configured according to actual conditions, and the control is flexible; it can avoid the abnormal situation of reading an empty data FIFO, and has high reliability; it reduces the channel switching frequency and improves data access efficiency; it avoids frequent changes in multiple addresses, and has high stability, which better meets the stability and reliability requirements of multi-channel image data processing and image display of embedded computers.

[0058] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A DDR interface arbitration control method suitable for video processing, characterized in that: include: The data volume and fixed length are respectively set for multiple independent video storage control channels; wherein the video storage control channel is a storage control channel based on a dual FIFO interface, and the dual FIFO interface includes an instruction FIFO interface and a data FIFO interface; Perform arbitration control of the current state through the DDR interface arbitration controller. If the write operation state is in operation, determine whether the current cache amount to be written of the video storage control channel reaches the fixed length of the data amount of the channel. If so, issue a write request through the instruction FIFO interface, read the image data through the data FIFO interface and write it to the MIS-APP interface, determine whether the image data amount written to the MIS-APP interface reaches the fixed length of the data amount of the channel, and if so, jump to the waiting arbitration control state; If the read operation state is in progress, determine whether the current cache amount to be read of the video storage control channel reaches the data length of the channel. If so, issue a read request through the instruction FIFO interface, read the image data through the MIS-APP interface and write it to the data FIFO interface, determine whether the image data amount read from the MIS-APP interface reaches the data length of the channel, and if so, jump to the waiting arbitration control state.

2. The DDR interface arbitration control method suitable for video processing according to claim 1, characterized in that: The data volume fixed length of the channel is calculated according to the image resolution of the video storage control channel.

3. The DDR interface arbitration control method suitable for video processing according to claim 2, characterized in that: Calculating the fixed length of the data volume of the channel according to the image resolution of the video storage control channel respectively, including: According to the image resolution of the video storage control channel, the maximum pixel value and the pixel value transmitted per unit time of the channel are determined, and the ratio of the maximum pixel value to the pixel value transmitted per unit time is used as the data volume fixed length of the channel.

4. The DDR interface arbitration control method suitable for video processing according to claim 1, characterized in that: The MIS-APP interface is connected to an external DDR memory to write and read image data into the DDR memory.

5. The DDR interface arbitration control method suitable for video processing according to claim 4, characterized in that: The DDR memory splices the written image data into a complete picture, and reads pictures of different data sources from the DDR memory according to display requirements and controls the display.

6. The DDR interface arbitration control method suitable for video processing according to claim 1, characterized in that: The instruction FIFO interface caches instruction types and memory addresses, and the data FIFO interface caches image data.

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