Scheduler, integrated circuit, and image sensing device

Abstract

The present application provides a scheduler, an integrated circuit, and an image sensing device, relating to the field of image processing technology. The scheduler is used in an integrated circuit, the integrated circuit being configured to process a sequence of image frames, the sequence of image frames including a first image frame, and the integrated circuit including several image processing modules; the scheduler is configured to activate the first image processing module so that the first image processing module performs a first processing on the first image frame, the several image processing modules including the first image processing module; the scheduler is further configured to set the first image processing module to a standby state based on the state of a target signal, the first image processing module modifying the state of the target signal after completing the first processing; wherein, when the first image processing module is in an activated state, the scheduler sets the image processing modules in the integrated circuit other than the first image processing module to a standby state. The scheduler can reduce the power consumption of the integrated circuit in which it is located during use.

Description

Technical Field

[0001] The present application relates to the field of image processing technology, and in particular to a scheduler, an integrated circuit, and an image sensing device. Background Art

[0002] In existing application scenarios, media processing pathways comprise multiple modules, such as image processing, video encoding and decoding, and signal transmission. Each module performs a specific function within the pathway. These modules remain operational until all tasks are completed, and even when no tasks are being processed or the load is very low, they still consume a certain amount of power. The combined power consumption of each module contributes to the overall power consumption of the entire integrated circuit, such as a system-on-chip (SOC). Therefore, if all modules remain operational, the total power consumption of the integrated circuit will be high.

[0003] Therefore, how to reduce the power consumption of integrated circuits during use is an urgent problem to be solved. Summary of the Invention

[0004] In view of this, the present application discloses a scheduler, an integrated circuit, and an image sensing device to reduce the power consumption of the integrated circuit during use.

[0005] In a first aspect, the present application discloses a scheduler for an integrated circuit, the integrated circuit being configured to process an image frame sequence, the image frame sequence including a first image frame, and the integrated circuit including several image processing modules; the scheduler is configured to activate the first image processing module so that the first image processing module performs a first processing on the first image frame, and the several image processing modules include the first image processing module; the scheduler is also configured to set the first image processing module to a standby state based on the state of a target signal, and the first image processing module modifies the state of the target signal after completing the first processing; wherein, when the first image processing module is in an activated state, the scheduler sets the image processing modules other than the first image processing module in the integrated circuit to a standby state.

[0006] Optionally, the plurality of image processing modules further include a second image processing module; when the scheduler sets the second image processing module to standby state, it performs at least one of the following operations: cutting off the power supply of the second image processing module or shutting down the clock source of the second image processing module.

[0007] Optionally, after the first image processing module is switched from the active state to the standby state, the scheduler is configured to set the second image processing module to the active state based on the state of the target signal.

[0008] Optionally, the scheduler is configured to set the processing order of several image processing modules on the first image frame, and the first image frame passes through the first image processing module and the second image processing module successively; the second image processing module performs the second processing on the first image frame when it is activated.

[0009] Optionally, when the scheduler sets the second image processing module to standby mode, it reads the properties of the power supply and clock source of the first image processing module and the second image processing module, determines whether the power supply of the first image processing module and the second image processing module is a shared power supply and whether the clock source of the first image processing module and the second image processing module is a shared clock source, and performs at least one of the following operations based on the judgment result: cutting off the power supply of the second image processing module or turning off the clock source of the second image processing module.

[0010] Optionally, when the power supply of the first image processing module and the second image processing module is a shared power supply, the scheduler turns off the clock source of the second image processing module; when the clock source of the first image processing module and the second image processing module is a shared clock source, the scheduler cuts off the power supply of the second image processing module; when the power supply of the first image processing module and the second image processing module is not a shared power supply and the clock source of the first image processing module and the second image processing module is not a shared clock source, the scheduler performs at least one of the following operations: cuts off the power supply of the second image processing module or turns off the clock source of the second image processing module.

[0011] Optionally, the image frame sequence includes a second image frame; after the first image frame passes through several image processing modules in sequence, the scheduler activates the first image processing module to enable the first image processing module to perform the first processing on the second image frame.

[0012] Optionally, the integrated circuit also includes a counting module, which is configured to start counting after the first image frame passes through several image processing modules in sequence; the scheduler reads the counting result of the counting module, and activates the first image processing module when the counting result exceeds a preset time so that the first image processing module performs the first processing on the second image frame.

[0013] In a second aspect, the present application discloses an integrated circuit, comprising the scheduler disclosed in the first aspect above.

[0014] In a third aspect, the present application discloses an image sensing device, comprising the integrated circuit disclosed in the second aspect above.

[0015] To sum up, the scheduler, integrated circuit and image sensing device disclosed in the present application have at least the following beneficial effects: only the scheduled image processing modules perform business processing, so that the unscheduled image processing modules are powered off or clock-off by default, so as to save the power consumption of the integrated circuit; when the performance requirements are not high, the use of the scheduler of the present application can improve the on-machine time of the system equipment and save the cost of battery equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following is a brief introduction to the drawings used in describing the embodiments of this application:

[0017] Figure 1 This is a schematic diagram of an image processing chip in the prior art processing an image frame.

[0018] Figure 2 This is an example diagram of the structure of an integrated circuit provided in an embodiment of the present application.

[0019] Figure 3 This is an example diagram of the structure of another integrated circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. The drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative work. Adjustments and improvements made without departing from the concept of the present application are all within the scope of protection of the present application.

[0021] To simplify the drawings, only the parts related to the corresponding embodiments are schematically shown in each figure. They do not represent the actual structure of the product. In addition, to simplify the drawings and facilitate understanding, in some figures, only a portion of the components with the same structure or function are schematically depicted. In reality, more or fewer components with the same structure or function may exist.

[0022] In this application, unless otherwise expressly specified and limited, ordinal numbers such as "first", "second", etc. are only used to distinguish and describe associated objects, and cannot be understood as indicating or implying the relative importance or order between associated objects; in addition, they do not represent the number of associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between associated objects, which indicates the "or" relationship between associated objects. "And / or" is used to describe the relationship between associated objects, which includes any combination relationship between associated objects, for example, "a and / or b" includes: "alone a", "alone b", or "a and b". "One or more" or "at least one" in multiple objects refers to any object or any combination of multiple objects, for example, "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "alone a1", "alone a2", "alone a3", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0023] In today's multimedia applications, multiple functional modules often form a complex media processing pipeline. This pipeline includes modules such as image processing, video encoding and decoding, audio processing, and signal transmission. Each module plays a specific role, working together to complete a series of processing steps, including media data acquisition, conversion, encoding, and transmission. In some practical applications, to improve the system's responsiveness to user operations and task requests, these modules can be set to remain operational until all tasks are completed. This prevents them from fully entering a dormant or shutting down state even during idle periods when no tasks are being processed or when the system load is very low, inevitably consuming a certain amount of power. This normal power consumption may be small for a single module, but at the system level, especially for an entire integrated circuit, the combined power consumption of each module can become significant, resulting in higher total power consumption for the entire integrated circuit. An image processing chip can essentially be an integrated circuit that integrates several image processing modules. In this application, the terms "integrated circuit" and "image processing chip" are used interchangeably. This is described below with reference to the accompanying figures.

[0024] Figure 1 This is a schematic diagram of an image processing chip processing an image frame in the prior art. Figure 1 ,In the integrated circuit, several image processing modules are included, e.g. Figure 1The image signal processor (ISP), video post-processor (VPP), digital signal processor (DSP), neural processing unit (NPU), application central processing unit (ACPU) and video encoder (VENC) shown in the figure are shown in the figure. The above image processing modules process the image frame sequence in sequence, where the image frame sequence is used to represent an ordered sequence composed of several image frames. Figure 1 In the example, the image frame sequence includes a first image frame Frame1, a second image frame Frame2, a third image frame Frame3, a fourth image frame Frame4, a fifth image frame Frame5, a sixth image frame Frame6 and a seventh image frame Frame7, and these image frames have the following characteristics: Figure 1The order of priority is shown. In the image processing modules described above, the ISP is primarily responsible for processing raw image data captured by image sensors (such as CMOS or CCD), including operations such as denoising, white balance adjustment, color correction, gamma correction, sharpening, and automatic exposure adjustment. Its function is to convert the raw image data (such as RAW format) output by the sensor into clear, color-accurate images for use by subsequent processing modules. The VPP is responsible for performing various optimization tasks during the post-processing of video data, such as resolution scaling, frame rate conversion, color space conversion, sharpening, and brightness adjustment. It primarily improves video display quality and ensures that the video output is suitable for the target display device (such as adjusting to the resolution and color format of a specific screen). The DSP is a specialized processor designed to perform efficient mathematical calculations and is suitable for image and video processing. It accelerates complex signal processing tasks such as filtering, convolution, and Fourier transforms. It can be used in image and video decoding, encoding, and enhancement, and is particularly suitable for real-time audio and video processing scenarios. The NPU is designed specifically to accelerate the inference of neural network models and is a hardware accelerator for machine learning, image recognition, object detection, and other AI-related processing tasks. It can be used in image processing systems for artificial intelligence functions such as face recognition, object classification, and motion detection, giving devices more intelligent image processing capabilities. The ACPU is a processing unit used to run high-level applications and can be a multi-core general-purpose processor (such as the ARM Cortex-A series). During image processing, the ACPU is primarily responsible for non-real-time, non-urgent processing tasks, including high-level application logic control and algorithm scheduling. It also collaborates with other processing units to perform image enhancement and post-processing effects. The VENC is responsible for compressing and encoding raw video data into standard video formats (such as H.264 and H.265) for storage or transmission. The encoder compresses video data to reduce video file size while minimizing image quality. It is suitable for scenarios such as video recording and streaming. Its function is to convert processed video frames into an encoded format for easy network transmission or storage.

[0025] During image processing, the integrated circuit uses the ISP to process Frame 1 during a first time period (i.e., the time period represented by 0-T1 in the figure). During a second time period (i.e., the time period represented by T1-T2 in the figure), the integrated circuit uses the VPP to process Frame 1 and uses the ISP to process Frame 2. During a third time period (i.e., the time period represented by T2-T3 in the figure), the integrated circuit uses the DSP to process Frame 1, uses the VPP to process Frame 2, and uses the ISP to process Frame 3. During a fourth time period (i.e., the time period represented by T3-T4 in the figure), the integrated circuit uses the NPU to process Frame 1, uses the DSP to process Frame 2, uses the VPP to process Frame 3, and uses the ISP to process Frame 4. During a fifth time period (i.e., the time period represented by T4-T5 in the figure), the integrated circuit uses the ACPU to process Frame 1, uses the NPU to process Frame 2, uses the DSP to process Frame 3, uses the VPP to process Frame 4, and uses the ISP to process Frame 5. During the sixth time period (i.e., the time period indicated by T5-T6 in the figure), the integrated circuit uses VENC to process Frame1, uses ACPU to process Frame2, uses NPU to process Frame3, uses DSP to process Frame4, uses VPP to process Frame5, and uses ISP to process Frame6. After time T6, the integrated circuit completes all processing operations on Frame1, and Frame1 is transmitted to the subsequent memory or processor, which stores Frame1 or further processes Frame1. During the seventh time period (i.e., the time period after time T6 in the figure), the integrated circuit uses VENC to process Frame2, uses ACPU to process Frame3, uses NPU to process Frame4, uses DSP to process Frame5, uses VPP to process Frame6, and uses ISP to process Frame7. In other words, Frame7 and subsequent image frames will also be processed in sequence by the various image processing modules in the integrated circuit.

[0026] Figure 1The integrated circuit shown includes six image processing modules for illustrative purposes only. In actual applications, the type and number of image processing modules can be customized based on actual needs. During the image processing process described above, all image processing modules are active, including the VPP, DSP, NPU, ACPU, and VENC modules during the first time period. Although these modules are not directly operational during the first time period, they are still active and consume a certain amount of power. Active status indicates that the module is powered on or that the corresponding clock is running.

[0027] The way the image processing chip disclosed above processes image frames will result in a large overall power consumption in the integrated circuit, and reducing power consumption is one of the important links in integrated circuit design. If the integrated circuit is in a high power consumption state for a long time, it is not conducive to application scenarios that are sensitive to power consumption (such as mobile devices and battery-powered systems). In this case, optimizing the working state of each module, reasonably managing its power consumption, or using dynamic power management strategies to allow modules with no tasks or low loads to enter low power consumption or sleep mode, will become key measures to reduce the overall power consumption of the integrated circuit. In other words, for low-power scenarios, such as when there are fewer image frames to be processed or when the processing speed requirements are low, the power consumption of the integrated circuit during use can be reduced by setting the status of each image management module in the integrated circuit and setting the image frame processing method. In this way, the service life of the integrated circuit can be extended, the user experience can be improved, and heat can be reduced, thereby improving the reliability of the image sensing device in which the integrated circuit is located.

[0028] Figure 2 This is a structural example diagram of an integrated circuit provided in an embodiment of the present application. Please refer to Figure 2 The present application discloses a scheduler 201 for an integrated circuit 200, wherein the integrated circuit 200 is configured to process an image frame sequence, the image frame sequence including a first image frame (in Figure 2 In the figure, the integrated circuit 200 includes an image processing module group 210, which includes several image processing modules (several image processing modules are in Figure 2 In the figure, the first image processing module 211, the second image processing module 212, the third image processing module 213, the fourth image processing module 214 and the fifth image processing module 215 are represented. It should be noted that the number of image processing modules in the image processing module group 210 is not limited to Figure 2The scheduler 201 is configured to activate the first image processing module 211 so that the first image processing module 211 performs a first processing on the first image frame, and the plurality of image processing modules include the first image processing module 211; the scheduler 201 is further configured to set the first image processing module 211 to a standby state based on the state of the target signal, and the first image processing module 211 modifies the state of the target signal after completing the first processing; wherein, when the first image processing module 211 is in an activated state, the scheduler 201 sets the image processing modules other than the first image processing module 211 in the integrated circuit 200 to a standby state.

[0029] For example, the first image processing module 211 may be the image signal processor ISP mentioned above, the second image processing module 212 may be the video post-processor VPP mentioned above, the third image processing module 213 may be the digital signal processor DSP mentioned above, the fourth image processing module 214 may be the neural network processor NPU mentioned above, and the fifth image processing module 215 may be the video encoder VENC mentioned above. The image frame sequence may include, for example, N image frames, namely, the first image frame, the second image frame (in Figure 2 In the figure, it is represented as a square grid, and the inside of the grid is marked as 2) ... the Nth image frame (in Figure 2 ( is represented by a square grid, with the inside of the grid labeled N). An image frame refers to a single static image in a video or continuous image sequence. In video processing, a frame is a still image presented continuously at a certain frequency, each frame recording the complete scene information at a specific moment. The continuous playback of multiple image frames creates a dynamic visual effect. One form of image frame sequence is video, which is essentially a series of image frames played back in rapid succession, creating a continuous motion effect for the human eye.

[0030] When the integrated circuit 200 begins operation, the scheduler 201 first activates the first image processing module 211, causing it to perform a first process on the first image frame. For example, if the first image processing module 211 is an ISP, the first process may include one or more operations such as denoising, white balance adjustment, color correction, gamma correction, sharpening, and automatic exposure adjustment. After the first image processing module 211 completes the first process on the first image frame, it modifies the state of a target signal in the scheduler 201. For example, the target signal may be a flag bit dedicated to the first image processing module 211. When the first image processing module 211 is in the active state, the flag bit has a value of 1. After the first image processing module 211 completes the first process, the flag bit is modified to 0. When the scheduler 201 detects that the flag bit has a value of 0, it places the first image processing module 211 in a standby state to conserve power consumption, thereby reducing the power consumption of the integrated circuit 200. An image processing module in the standby state consumes almost no power. For another example, the target signal can be a count value stored in a register. When the first image processing module 211 is in an activated state, the count value is 1; after the first image processing module 211 completes the first processing, the count value is modified to 2. When the scheduler 201 detects that the value of the flag is 2, the first image processing module 211 is set to a standby state, and the second image processing module 212 can be immediately activated to process the first image frame, or the second image processing module 212 can be activated to process the first image frame after a certain delay. By setting a certain delay between adjacent image processing modules, such as a millisecond delay, the flexibility of scheduling in the integrated circuit 200 can be improved, and the purpose of power saving can be further achieved. In the above examples, the specific values ​​of the flags and the count values ​​in the registers are only examples, and this application does not limit them.

[0031] In some embodiments of the present application, the scheduler 201 can be implemented by software or by hardware, and the number of schedulers 201 is greater than or equal to one. For example, the scheduler 201 can be implemented by an ACPU. In this case, the ACPU can run a scheduling algorithm to control the activation and standby of each image processing module. When the scheduler 201 is implemented by software, it can be determined whether the corresponding image processing module has completed the corresponding processing by judging whether the value of the flag bit has changed. When the scheduler 201 is implemented by hardware, it can be determined whether the corresponding image processing module has completed the corresponding processing by the level state of a detection signal. For example, when the detection signal is in a high level state, the scheduler 201 determines that the image processing module has completed the corresponding processing. The number of schedulers 201 can be set according to user needs. For example, a scheduler can be assigned to each image processing module, or one scheduler can control multiple image processing modules.

[0032] Furthermore, when the first image processing module 211 is in the active state, the scheduler 201 sets the image processing modules in the integrated circuit 200 other than the first image processing module 211 to the standby state. That is, when the first image processing module 211 is in the active state, the second image processing module 212, the third image processing module 213, the fourth image processing module 214, and the fifth image processing module 215 are all in the standby state, thereby achieving the purpose of saving power consumption.

[0033] Through the above technical means, only the scheduled image processing modules perform business processing, while the unscheduled image processing modules are powered off or clock-off by default to save power consumption of the integrated circuit; when performance requirements are not high, the use of the scheduler of this application can improve the on-machine time of the system equipment and save the cost of battery equipment.

[0034] In some embodiments of the present application, when the first image frame is processed by any image processing module in the integrated circuit 200, all image frames except the first image frame are in a waiting state; that is, at any moment, only one image frame is processed by the image processing module, thereby achieving the purpose of saving power consumption.

[0035] In some embodiments of the present application, the plurality of image processing modules further includes a second image processing module 212. When the scheduler 201 sets the second image processing module 212 to the standby state, the scheduler 201 performs at least one of the following operations: cutting off the power supply to the second image processing module 212 or shutting down the clock source of the second image processing module 212. In other words, the scheduler 201 sets any image processing module to the standby state by controlling the power supply and clock source corresponding to the image processing module, thereby shutting off the power signal or clock signal to the image processing module, thereby causing the image processing module to enter the standby state and reduce power consumption.

[0036] Figure 3 This is an example diagram of the structure of another integrated circuit provided in the embodiment of the present application. Figure 3 When the scheduler 301 sets the second image processing module 312 to the standby state, it reads the properties of the power supply and clock source of the first image processing module 311 and the second image processing module 312, determines whether the power supply of the first image processing module 311 and the second image processing module 312 is a shared power supply and whether the clock source of the first image processing module 311 and the second image processing module 312 is a shared clock source, and performs at least one of the following operations based on the result of the judgment: cutting off the power supply of the second image processing module 312 or turning off the clock source of the second image processing module 312.

[0037] In some embodiments of the present application, when the power supply of the first image processing module 311 and the second image processing module 312 is a shared power supply, the scheduler 301 turns off the clock source of the second image processing module 312; when the clock source of the first image processing module 311 and the second image processing module 312 is a shared clock source, the scheduler 301 cuts off the power supply of the second image processing module 312; when the power supply of the first image processing module 311 and the second image processing module 312 is not a shared power supply and the clock source of the first image processing module 311 and the second image processing module 312 is not a shared clock source, the scheduler 301 performs at least one of the following operations: cuts off the power supply of the second image processing module 312 or turns off the clock source of the second image processing module 312.

[0038] exist Figure 3In the embodiment, the first image processing module 311 and the second image processing module 312 share a power supply 330, that is, the two are in the same power domain. However, the two are not in the same clock domain. The clock source 300 divides the clock signal c into a first clock signal c1 and a second clock signal c2 through a first frequency divider 310 and a second frequency divider 320. When the first image processing module 311 performs the first processing on the first image frame, the scheduler sets the second image processing module 312 to a standby state by turning off the second frequency divider 320. Since the first image processing module 311 and the second image processing module 312 share a power supply 330, if it is turned off, the normal operation of the first image processing module 311 may be affected. The scheduler 301 can determine whether to turn off the power supply or the clock source based on the properties of the power supply and clock source of the first image processing module 311 and the second image processing module 312. When the first image frame is processed by the first image processing module 311, the scheduler 301 can turn off the first frequency divider 310 and set the first image processing module 311 to a standby state by eliminating the first clock signal c1; and the scheduler 301 can turn on the second frequency divider 320, so that the second frequency divider 320 transmits the second clock signal c2 to the second image processing module 312, thereby activating the second image processing module 312. After the second image processing module 312 processes the first image frame, the scheduler 301 turns off the second frequency divider 320 and determines the next third image processing module ( Figure 3 The scheduler 301 determines whether the power supply 330 is used together with the first image processing module 311 and the second image processing module 312 (not shown). If the power supply 330 is not used to supply power to the third image processing module, the scheduler 301 turns off the power supply 330 to save power consumption. Considering that each image processing module consumes power even when it is not performing image processing operations, turning off the power supply corresponding to these image processing modules can effectively solve this problem. The leakage power consumption of the module still consumes a small amount of electricity when the module is not working, which is mainly due to the leakage current inside the semiconductor device. In low-power design, it is particularly important to reduce the leakage power consumption of the non-working module. For businesses with low performance requirements, using the above design can not only maintain work efficiency but also reduce the power consumption of the integrated circuit.

[0039] In some embodiments of the present application, after the first image processing module transitions from an active state to a standby state, the scheduler is configured to set the second image processing module to an active state based on the state of the target signal. For example, after the first image processing module completes processing the first image frame, it modifies a flag in the scheduler. The scheduler detects the flag modification and sets the first image processing module to a standby state and the second image processing module to an active state, thereby enabling the second image processing module to further process the first image frame.

[0040] In some embodiments of the present application, the scheduler is configured to set the order in which several image processing modules process a first image frame, and the first image frame passes through the first image processing module and the second image processing module in sequence; when the second image processing module is activated, the second image processing module performs the second processing on the first image frame. Each image processing module processes the image frame in a certain order. For example, the first image frame may be processed by the first image processing module, the second image processing module, the third image processing module, the fourth image processing module, and the fifth image processing module in sequence, and each image processing module processes the image frame in a different manner.

[0041] In some embodiments of this application, please continue to refer to Figure 2 The image frame sequence includes a second image frame. After the first image frame passes through the plurality of image processing modules, the scheduler 201 activates the first image processing module 211, causing the first image processing module 211 to perform the first processing on the second image frame. That is, after the first image frame has been processed by each image processing module in the image processing module group 210, the scheduler 201 sets the fifth image processing module 215 to a standby state and reactivates the first image processing module 211, causing the first image processing module 211 to perform the first processing on the second image frame, thus starting a new cycle. This cycle repeats until all image frames in the image frame sequence have been processed by the integrated circuit 200, marking the end of this transaction.

[0042] In some embodiments of this application, please continue to refer to Figure 2 Integrated circuit 200 further includes a counting module 220, which is configured to start counting after a first image frame passes through a plurality of image processing modules in sequence. Scheduler 201 reads the counting result of counting module 220 and, when the counting result exceeds a preset time, activates first image processing module 211 to cause first image processing module 211 to perform the first processing on the second image frame. Exemplarily, the preset time may be 10 ms. After integrated circuit 200 completes processing of the first image frame, counting module 220 begins counting. When the counting result exceeds 10 ms, scheduler 201 activates first image processing module 211 to begin processing the second image frame.

[0043] Based on similar technical concepts, the present application discloses an integrated circuit, including the scheduler disclosed in the above embodiments.

[0044] Based on similar technical concepts, the present application discloses an image sensing device, including the integrated circuit disclosed in the above embodiments. The image sensing device can be, for example, various cameras (CCD cameras, CMOS cameras, infrared thermal imaging cameras, etc.) or a laser radar.

[0045] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A scheduler, characterized in that: An integrated circuit configured to process a sequence of image frames, the sequence of image frames including a first image frame, the integrated circuit including a plurality of image processing modules, the plurality of image processing modules sequentially processing the first image frame; The scheduler is configured to activate a first image processing module so that the first image processing module performs a first process on the first image frame, the plurality of image processing modules including the first image processing module; The scheduler is further configured to set the first image processing module to a standby state based on a state of a target signal, the first image processing module modifying the state of the target signal after completing the first processing; Wherein, when the first image processing module is in the active state, the scheduler sets the image processing modules other than the first image processing module in the integrated circuit to the standby state.

2. The scheduler according to claim 1, wherein: The plurality of image processing modules further include a second image processing module; When the scheduler sets the second image processing module to the standby state, the scheduler performs at least one of the following operations: cutting off the power supply of the second image processing module or shutting down the clock source of the second image processing module.

3. The scheduler according to claim 2, wherein: After the first image processing module is switched from the active state to the standby state, the scheduler is configured to set the second image processing module to the active state based on a state of the target signal.

4. The scheduler according to claim 3, wherein: The scheduler is configured to set a processing order of the plurality of image processing modules on the first image frame, and the first image frame passes through the first image processing module and the second image processing module in sequence; The second image processing module performs a second process on the first image frame in the activated state.

5. The scheduler according to claim 2, wherein: When the scheduler sets the second image processing module to the standby state, it reads the properties of the power supply and clock source of the first image processing module and the second image processing module, determines whether the power supply of the first image processing module and the second image processing module is a shared power supply and whether the clock source of the first image processing module and the second image processing module is a shared clock source, and performs at least one of the following operations based on the result of the judgment: cutting off the power supply of the second image processing module or turning off the clock source of the second image processing module. The scheduler according to claim 5, characterized in that When the power supplies of the first image processing module and the second image processing module are shared, the scheduler turns off the clock source of the second image processing module; When the clock sources of the first image processing module and the second image processing module are a shared clock source, the scheduler cuts off the power supply of the second image processing module; When the power supply of the first image processing module and the second image processing module is not a shared power supply and the clock source of the first image processing module and the second image processing module is not a shared clock source, the scheduler performs at least one of the following operations: cutting off the power supply of the second image processing module or turning off the clock source of the second image processing module.

7. The scheduler according to claim 1, wherein: The sequence of image frames includes a second image frame; After the first image frame passes through the plurality of image processing modules in sequence, the scheduler activates the first image processing module to enable the first image processing module to perform the first processing on the second image frame.

8. The scheduler according to claim 7, characterized in that The integrated circuit further includes a counting module, wherein the counting module is configured to start counting after the first image frame passes through the plurality of image processing modules in sequence; The scheduler reads a counting result of the counting module, and activates the first image processing module when the counting result exceeds a preset time so that the first image processing module performs the first processing on the second image frame.

9. An integrated circuit, characterized in that: Comprising a scheduler as described in any one of claims 1-8.

10. An image sensing device, characterized in that: comprising the integrated circuit of claim 9.

Images