Image sensor, image sensing circuit and image processing method

Abstract

The invention provides an image sensor, an image sensing circuit and an image processing method. The image sensor includes: a plurality of pixel rows disposed in a first direction, each of the pixel rows including a plurality of pixels disposed in a second direction intersecting the first direction; the plurality of pixel rows are configured to count received photons to obtain a count value in a counting mode; in a transfer mode, multiple transfer operations are carried out, so that the count value of each pixel line is transferred line by line and output; wherein in each transfer operation, the count value of each of the other pixel rows except the last pixel row is transferred to the next pixel row, and the count value of the last pixel row is output. And the count value of each of the other pixel rows except the first pixel row is replaced by the count value from the previous pixel row.

Description

Technical Field

[0001] The present disclosure relates to the field of image processing technology, and in particular to an image sensor, an image sensing circuit, and an image processing method. Background Art

[0002] With the development of SPAD (single photon avalanche diode) device manufacturing technology and integrated circuits, SPAD-based PCI (single photon counting imaging) technology has been applied. In PCI image sensors, each pixel unit has an independent SPAD and counting circuit, which replicates and expands the pixel unit into a pixel array. At the same time, components such as readout circuits and control circuits are connected outside the pixel array to form a PCI image sensor that can capture the target optical image. Frame rate (the number of images output per unit time) is one of the important performance indicators of image sensors, and improving the frame rate of image sensors is a key technical issue in this field. Summary of the invention

[0003] Embodiments of the present disclosure provide an image sensor, an image sensing circuit, and an image processing method.

[0004] In a first aspect, an embodiment of the present disclosure provides an image sensor, comprising: a plurality of pixel rows arranged in a first direction, each of the pixel rows comprising a plurality of pixels arranged in a second direction intersecting the first direction; the plurality of pixel rows are configured as follows:

[0005] In the counting mode, the received photons are counted to obtain the count value;

[0006] In the transfer mode, multiple transfer operations are performed so that the count value of each pixel row is transferred and output row by row; wherein, in each transfer operation, the count value of each pixel row except the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each pixel row except the first pixel row is replaced by the count value from the previous pixel row.

[0007] In a second aspect, an embodiment of the present disclosure provides an image sensing circuit, which is applied to an image sensor, wherein the image sensor includes a plurality of pixel rows arranged in a first direction, each of the pixel rows including a plurality of pixels arranged in a second direction intersecting the first direction;

[0008] The image sensor has a counting mode and a transfer mode, and the image sensing circuit includes a counting circuit and a transfer circuit;

[0009] When the image sensor is in a counting mode, the plurality of pixel rows count received photons through the counting circuit to obtain count values;

[0010] When the image sensor is in the transfer mode, the multiple pixel rows perform multiple transfer operations through the transfer circuit, so that the count value of each pixel row is transferred and output row by row; wherein, in each transfer operation, the count value of each pixel row except the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each pixel row except the first pixel row is replaced by the count value from the previous pixel row.

[0011] In a third aspect, an embodiment of the present disclosure provides an image processing method of an image sensor, wherein the image sensor includes a plurality of pixel rows arranged in a first direction, each of the pixel rows includes a plurality of pixels arranged in a second direction intersecting the first direction; the processing method includes:

[0012] In the counting mode, the plurality of pixel rows count received photons to obtain count values;

[0013] In the transfer mode, the multiple pixel rows perform multiple transfer operations so that the count value of each pixel row is transferred and output row by row; wherein, in each transfer operation, the count value of each pixel row except the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each pixel row except the first pixel row is replaced by the count value from the previous pixel row.

[0014] In the disclosed embodiment, during one imaging process, multiple pixel rows are exposed simultaneously, and the count value of each pixel in the multiple pixel arrays reflects the light intensity information of a single point, and the count values ​​of the multiple pixel rows can feed back the light intensity information of multiple rows of images, and depict the digital images corresponding to the multiple rows of images. After the multiple pixel rows complete the exposure at one time, multiple transfer operations begin to be performed synchronously. In each transfer operation, the count value of each pixel row is transferred to the next pixel row, and each pixel row receives the count value from the previous pixel row. In this way, through N transfer operations, the count values ​​of N pixel rows are transferred out row by row, and the light intensity information of N rows of images can be obtained. Compared with the prior art, in order to obtain the light intensity information of N rows of images, it is necessary The solution of the embodiment of the present disclosure can greatly reduce the number of transfer operations, thereby shortening the readout time, improving the frame rate of the image sensor, and providing users with a better visual experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of an image sensor including a pixel array and a readout circuit provided for an embodiment of the present disclosure.

[0016] Figure 2 for Figure 1 A partial enlarged view of the pixel array.

[0017] Figure 3 Schematic diagram of an image sensor provided in an embodiment of the present disclosure Figure 1 .

[0018] Figure 4 Schematic diagram of an image sensor provided in an embodiment of the present disclosure Figure 2 .

[0019] Figure 5 Schematic diagram of an image sensor provided in an embodiment of the present disclosure Figure 3 .

[0020] Figure 6 A logical relationship table between the first control signal, the counting indication signal and the control counting signal provided in the embodiment of the present disclosure.

[0021] Figure 7 A schematic diagram of an overflow feedback circuit provided in an embodiment of the present disclosure.

[0022] Figure 8 A table of logical relationships among counting indication signals, counting pulse signals and counting trigger signals provided in an embodiment of the present disclosure.

[0023] Fig. 9 A schematic diagram of a counting feedback circuit provided in an embodiment of the present disclosure.

[0024] Fig.10 Schematic diagram of an image sensor provided in an embodiment of the present disclosure Figure 4 .

[0025] Fig.11 A schematic diagram of an asynchronous counting structure of an image sensor provided in an embodiment of the present disclosure.

[0026] Fig.12 A schematic diagram of the synchronous transfer structure of the image sensor provided in an embodiment of the present disclosure.

[0027] Fig.13 This is a working timing diagram of the image sensor provided in an embodiment of the present disclosure.

[0028] Fig.14 A flowchart of an image processing method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0030] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0031] In the drawings, like reference numerals refer to like elements throughout.

[0032] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] In a PCI image sensor, each pixel unit has an independent SPAD and counting circuit, which replicates and expands the pixel unit into a pixel array (also called a photosensitive area array). At the same time, components such as readout circuits and control circuits are connected outside the pixel array to form a PCI image sensor that can capture the target optical image.

[0035] Figure 1 A schematic diagram of an image sensor including a pixel array and a readout circuit provided for an embodiment of the present disclosure. Figure 2 for Figure 1 A partial enlarged view of the pixel array in Figure 2. Figure 1 As shown, the image sensor includes a pixel array and a readout circuit. The pixel array includes a plurality of pixel rows ROW1, ...ROW n-1 、ROW n 、ROW n+1 and a plurality of pixel columns COL1, ...COL n-1 , COL n , COL n+1 The readout circuit includes a row selection module 10 and a shift register module 20. In the prior art, the row selection module 10 controls a row of pixels 30 to perform exposure and count value transfer by controlling the row selection signal corresponding to the pixel row. For example, when exposure ROW is required n Row pixels or request to transfer ROW n When the count value in the row pixel is n The row select signal corresponding to the row.

[0036] In the pixel array, adjacent pixels 30 in the same column have a cascade relationship to realize the transfer of count values, and the cascade relationship can be realized by a selector. Specifically, Figure 2 As shown, the output end of each pixel 30 in the pixel array is connected to the input end of a selector 40. In each column, the output end of the selector 40 corresponding to the previous pixel 30 is connected to the input end of the selector 40 corresponding to the next pixel 30. n After the row is selected, the n , COL n ] will be transferred to the pixel at [ROW n-1 , COL n ] in the pixel at the position; then ROW n-1 The row is selected and the count value is taken from the n-1 , COL n ] is transferred to the pixel at [ROW n-2 , COL n ] position. In this way, it is transferred to the pixel at [ROW1, COL n] position and is eventually sampled by the downstream shift register module.

[0037] During the transfer process, ROW n The row count value is transferred to ROW n-1 The delay of the line is D mux , which is the transmission delay of the selector. n The row count value finally needs to be transferred out of the pixel array after n transfers, so ROW n The delay for transferring the row count value out of the pixel array is n*D mux +D sel , where D sel Enable delay for row select signals.

[0038] By analogy, the readout delay to complete the transfer of an N-line image is Take a 1080P resolution image as an example, N = 1080, assuming D mux 0.5ns, D sel If D is 5ns, the readout delay is about 300us. mux and D sel The delay may be even greater, and as the application requirements for image resolution develop, the value of N will increase by 3 to 5 times, further increasing the image readout delay.

[0039] Frame rate is one of the important performance indicators of image sensors. Frame rate can generally be expressed as Where T E is the exposure time, T readout is the readout time, also known as the readout delay, T output Is the output time. If the readout time is too high, the frame rate of the image sensor will be seriously reduced, affecting the user's visual experience.

[0040] In view of this, an embodiment of the present disclosure provides an image sensor for shortening the image readout time. Figure 3 Schematic diagram of an image sensor provided in an embodiment of the present disclosure Figure 1 ,like Figure 3 As shown, the image sensor includes a pixel array, and the pixel array includes: a plurality of pixel rows Row and a plurality of pixel columns Col, the plurality of pixel rows Row are sequentially arranged in a first direction D1, and the plurality of pixel columns Col are sequentially arranged in a second direction D2 intersecting the first direction D1. Each pixel row Row includes a plurality of pixels 100 arranged along the second direction D2, each pixel column Col includes a plurality of pixels 100 arranged along the first direction D1, and in each pixel column Col, two adjacent pixels 100 are connected to each other.

[0041] Multiple pixel rows Row are configured as follows: in counting mode, the received photons are counted to obtain count values; in transfer mode, multiple transfer operations are performed so that the count values ​​of each pixel row are transferred and output row by row; wherein, in each transfer operation, the count values ​​of each pixel row except the last pixel row are transferred to the next pixel row, the count value of the last pixel row is output, and the count values ​​of each pixel row except the first pixel row are replaced by the count values ​​from the previous pixel row.

[0042] Figure 3 Three adjacent rows of pixels are shown. n-1 、Row n 、Row n+1 and three adjacent pixel columns Col n-1 、Col n 、Col n+1 The connection relationship and function of the pixels in other pixel rows and other pixel columns can be deduced from these three pixel rows and three pixel columns. Figure 3 The pixel array shown is used as an example to illustrate the solution of the present disclosure in detail.

[0043] The imaging process includes an exposure phase and a transfer phase after the exposure phase. The pixels have a counting mode in the exposure phase and a transfer mode in the transfer phase. In the exposure phase, a plurality of pixel rows are n-1 、Row n 、Row n+1 The pixels 100 in the image sensor are exposed simultaneously, so that each pixel 100 counts the received photons and obtains a count value.

[0044] In the transfer stage, multiple pixel rows synchronously perform multiple transfer operations. Specifically, in each transfer operation, the count value of the last pixel row is output, and the count value of each pixel in each pixel row other than the last pixel row is correspondingly transferred to the pixel in the same column in the next pixel row; and each pixel in each pixel row other than the first pixel row correspondingly receives the count value from the pixel in the same column in the previous pixel row.

[0045] Here, the last pixel row refers to the pixel row where the count value is output first, and the first pixel row refers to the pixel row where the count value is output last. In one example, the last pixel row is the pixel row closest to the shift register (not shown in the figure) in the readout circuit, and the first pixel row is the pixel row farthest from the shift register. Figure 3 In the embodiment shown, Row n-1 Row is the last pixel row, Row n+1 row is the first pixel row.

[0046] In the first transfer operation, Row n-1 The row count value is output to the shift register, Row n The row count value is transferred to Row n-1 OK n+1 The row count value is transferred to Row n OK. Specifically, Row n-1 The count value of each pixel in the row is output to the shift register. n In the row is located [Row n , Col n-1 The count value of the pixel at position ] is transferred to [Row n-1 , Col n-1 ], located in [Row n , Col n The count value of the pixel at position ] is transferred to [Row n-1 , Col n ], located in [Row n , Col n+1 The count value of the pixel at position ] is transferred to [Row n-1 , Col n+1 ] pixels. Similarly, Row n+1 In the row is located [Row n+1 , Col n-1 ]、[Row n+1 , Col n ]、[Row n+1 , Col n+1 ] position pixel count values ​​are transferred to [Row n , Col n-1 ]、[Row n , Col n ]、[Row n , Col n+1 ] pixels. After the first transfer operation is completed, Row n-1 The row pixels save the original Row n Row pixel count, Row n The pixels of the row are saved in the original Row n+1 The count value of the row pixel, the original Row n-1 The count value in the row of pixels is output.

[0047] In the second transfer operation, Row n-1 The original Row saved by the row n The count value of the row pixel is output to the shift register, Row n The original Row saved in the row n+1 The count value of the row is further transferred to Row n-1The specific steps are the same as the first transfer operation, that is, the count value of the pixel in the previous row is transferred to the pixel in the same column in the next row. n-1 The row pixels save the original Row n+1 The count value of the row pixel, the original Row n-1 Row and original Row n The count value in the row of pixels is output.

[0048] In the third transfer operation, Row n-1 The original Row saved by the row n+1 The count values ​​of the pixels in the row are output to the shift register. That is, after three transfer operations, the count values ​​of the three pixel rows are all output to the shift register. Similarly, N pixel rows need to undergo N transfer operations to output all the count values.

[0049] As mentioned above, in the prior art, when imaging an imaging target, N pixel rows need In the present embodiment, only N transfer operations are required, which greatly reduces the number of transfer operations and can shorten the read time.

[0050] In the disclosed embodiment, during one imaging process, multiple pixel rows are exposed simultaneously, and the count value of each pixel in the multiple pixel arrays reflects the light intensity information of a single point, and the count values ​​of the multiple pixel rows can feed back the light intensity information of multiple rows of images, and depict the digital images corresponding to the multiple rows of images. After the multiple pixel rows complete the exposure at one time, multiple transfer operations begin to be performed synchronously. In each transfer operation, the count value of each pixel row is transferred to the next pixel row, and each pixel row receives the count value from the previous pixel row. In this way, through N transfer operations, the count values ​​of N pixel rows are transferred out row by row, and the light intensity information of N rows of images can be obtained. Compared with the prior art, in order to obtain the light intensity information of N rows of images, it is necessary The solution of the embodiment of the present disclosure can greatly reduce the number of transfer operations, thereby shortening the readout time, improving the frame rate of the image sensor, and providing users with a better visual experience.

[0051] In some embodiments, the plurality of pixel rows are configured to: enter a counting mode in synchronous response to the first control signal being in a first level state; and enter a transfer mode in synchronous response to the first control signal being in a second level state.

[0052] The first control signal expo_en is generated by a control circuit outside the pixel array. The first control signal expo_en is an exposure enable signal, which is used to control the pixel to switch between the counting mode and the transfer mode. The first control signal expo_en can switch between a first level state and a second level state, that is, the exposure enable signal switches between a valid state and an invalid state. The first level is higher than the second level, or the first level is lower than the second level, and the present disclosure does not limit this. For ease of understanding, the disclosed embodiments in the present application are all described by taking the first control signal expo_en in the first level state as exposure enable valid, and in the second level state as exposure enable invalid as an example.

[0053] like Figure 3 As shown, each pixel in a plurality of pixel rows receives a first control signal expo_en, and the first control signal expo_en received by each pixel switches synchronously between a first level state and a second level state. When the first control signal expo_en received by each pixel switches synchronously to the first level state, all pixels in the plurality of pixel rows are simultaneously in an exposure state and enter a counting mode. When the first control signal expo_en received by each pixel switches synchronously from the first level state to the second level state, all pixels in the plurality of pixel rows are simultaneously in a non-exposure state and enter a transfer mode from a counting mode.

[0054] In some embodiments, Figure 4 As shown, each pixel in the plurality of pixel rows can be coupled to the same signal source and receive the same first control signal expo_en. In this way, it is easier to control the mode switching of the plurality of pixel rows at the same time by using the same first control signal, and it can also improve the consistency of the steps of different pixels when switching modes, avoid abnormal transfer operation caused by inconsistent switching steps, and improve the reliability of the transfer operation.

[0055] In some embodiments, multiple pixel rows are configured to: in a transfer mode, synchronously respond to a second control signal to transfer count values; wherein the second control signal is a transfer clock signal including multiple periodic clock pulses, and the multiple pixel rows perform a transfer operation in response to one clock pulse.

[0056] like Figure 3 As shown, each pixel in a plurality of pixel rows receives a transfer clock signal clk_shift. The transfer clock signal clk_shift is generated by a control circuit outside the pixel array. The transfer clock signal clk_shift includes a plurality of periodic clock pulses. Each pixel of the pixel array synchronously responds to the transfer clock signal, which means that the rising edges of the clock pulses received by each pixel are aligned with each other, and the falling edges are aligned with each other.

[0057] Multiple pixel rows perform multiple transfer operations in response to multiple clock pulses. Multiple pixel rows may perform a transfer operation once at the rising edge of each clock pulse, or may perform a transfer operation once at the falling edge of each clock pulse. The present disclosure does not limit this. When N transfer operations are required, at least N clock pulses are required.

[0058] Here, it should be noted that the pixel can receive the transfer clock signal in the transfer mode to transfer the count value according to the transfer clock signal, but this does not mean that the transfer clock signal can only be transmitted to the pixel when the pixel is in the transfer mode. In one embodiment, the control circuit can associate the first control signal with the transfer clock signal so that the control circuit transmits the transfer clock signal to the pixel only when the pixel enters the transfer mode. In another embodiment, the control circuit may transmit the transfer clock signal to the pixel when the pixel is in the counting mode and the transfer mode, but the pixel only responds to the transfer clock signal in the transfer mode. In the first embodiment, the control circuit transmits the transfer clock signal to the pixel only in the transfer mode, which can reduce the signal interference to the pixel and also reduce the power consumption of the pixel. The second embodiment can simplify the design of the control circuit. In practical applications, any one of the schemes can be adopted according to specific design requirements, and the present disclosure does not limit this.

[0059] In some embodiments, Figure 4 As shown, each pixel in the pixel array can be coupled to the same clock source and receive the same clock transfer signal clk_shift, so as to synchronously perform each transfer operation under the control of the same clock transfer signal clk_shift. In this embodiment, the use of the same transfer clock signal clk_shift makes it easier to control multiple pixel rows to perform transfer operations synchronously, thereby avoiding the delay of the transfer operation of individual pixel rows causing abnormality in the entire transfer process, that is, improving the reliability of the transfer operation.

[0060] Figure 5 Schematic diagram of an image sensor provided in an embodiment of the present disclosure Figure 3 . Figure 5 The structure of any three adjacent pixels in a certain pixel column is shown. The three pixels are located in Row n-1 Row n Row and Row n+1 In some embodiments, Figure 5As shown, each pixel 100 includes: a pixel unit 110 and a counter 120, wherein the first input terminal in1 of the counter 120 is coupled to the output terminal of the pixel unit 110, and the second input terminal in2 of the counter 120 is used to receive the first control signal expo_en. The pixel unit 110 generates a counting pulse signal photon pulse based on the received photons. The counter 120 enters a counting mode in response to the first control signal expo_en being in a first level state, counts the received counting pulse signal photon pulse to generate a counting value; and enters a transfer mode in response to the first control signal expo_en being in a second level state, and performs a transfer operation in response to the second control signal (i.e., the transfer clock signal clk_shift).

[0061] For example, the pixel unit 110 includes a single-photon avalanche diode SPAD and a quenching circuit connected to the SPAD. When the pixel unit is exposed, the SPAD in the waiting state is excited by light, generates photogenerated electrons, and triggers an avalanche event. After the avalanche event occurs, the quenching circuit works to extinguish the avalanche, and then the quenching circuit recharges the SPAD to restore it to the waiting state. In this process, the quenching circuit generates a digital signal pulse (ie, a counting pulse) to the downstream counter. During the exposure phase, the SPAD repeatedly undergoes avalanche events, thereby generating a series of counting pulses, causing the count value of the counter to continue to increase.

[0062] The counter 120 has two functional structures, one is an asynchronous counting structure, and the other is a synchronous transfer structure. The counter is controlled by the first control signal expo_en to switch between the counting mode and the transfer mode, that is, to select between the asynchronous counting structure and the synchronous transfer structure. Specifically, when the first control signal is in the first level state, the counter selects the asynchronous counting structure and enters the counting mode. When the second control signal is in the second level state, the counter selects the synchronous transfer structure and enters the transfer mode. Here, synchronous transfer means that all pixel rows have data transfer actions in one transfer operation, that is, the count value in the counter of the previous pixel row in two adjacent pixel rows is transferred to the counter of the next pixel row.

[0063] In some embodiments, Figure 5As shown, in each pixel row except the first pixel row, the third input terminal in3 of the counter 120 is coupled to the first output terminal out1 of the corresponding counter 120 in the previous pixel row; in each pixel row except the last pixel row, the first output terminal out1 of the counter 120 is coupled to the third input terminal in3 of the corresponding counter 120 in the next pixel row. In the transfer mode, all the counters 120 of the plurality of pixel rows perform multiple transfer operations; wherein, in each transfer operation, the counters 120 of each pixel row except the last pixel row transfer the count value to the corresponding counter 120 in the next pixel row, and the counter 120 of the last pixel row outputs the count value; the count value of the counter 120 of each pixel row except the first pixel row is replaced by the count value transferred by the corresponding counter 120 in the previous pixel row.

[0064] by Figure 5 For example, the three pixel rows in Row n+1 The first output terminal out1 of the row counter is coupled to Row n The third input terminal in3 of the counter in the same column in the row. n The first output terminal out1 of the row counter is coupled to Row n-1 The third input terminal in3 of the counter in the same column in the row. n-1 The first output terminal out1 of the row counter is coupled to the shift register.

[0065] In the transfer mode, only the counter in the pixel participates in the count value transfer, and all the counters in multiple pixel rows use the synchronous transfer structure and perform the count value transfer operation synchronously. Figure 5 For example, in the first transfer operation, Row n-1 The counter in the row outputs the count value. n The counter in the row transfers the count value to Row n-1 OK n+1 The counter in the row transfers the count value to Row n After the first transfer operation is completed, Row n-1 The row counter stores the original Row n The count value in the row counter, Row n The counter in the row stores the original Row n+1 The count value in the row counter, the original Row n-1 The count value in the counter of the row is output.

[0066] In the second transfer operation, Row n-1 The row counter outputs the count value. nThe row counter transfers the count value to Row n-1 After the second transfer operation is completed, Row n-1 The row counter stores the original Row n+1 The count value in the row counter, the original Row n Row n-1 The count value in the counter of the row is output.

[0067] In the third transfer operation, Row n-1 The row counter outputs the count value. n+1 Row n Row n-1 All count values ​​in the row counters are output.

[0068] In some embodiments, when performing a transfer operation, the third input terminal in3 of the counter 120 of the first pixel row is used to receive a reset value. The reset value is used to restore the first output terminal out1 of the counter 120 of the first pixel row to a default value. For example, the reset value can be a fixed value of 0, so that the first output terminal out1 of the counter is reset to 0, that is, the state when the counter is not counting. In the transfer mode, through multiple transfer operations, the reset value 0 can be transferred from the counter of the first pixel row to the counter of the last pixel row row by row, so that the counter array of the entire pixel array can be automatically reset. It should be noted that the reset value can also be other values ​​input at the third input terminal in3, and the specific value can be set according to the measurement needs. For example, when the environment is dark, the reflectivity of the imaging target is small, or the imaging target is far away, the reset value can be a value greater than 0, so as to improve the counting base of the pixel array as a whole, so that the imaging is brighter and clearer. In contrast, when the environment is bright, the reflectivity of the imaging target is large, or the imaging target is close, the reset value can be a value less than 0, so as to reduce the counting base of the pixel array as a whole, so that the imaging is not easily distorted due to overexposure.

[0069] In the embodiment of the present disclosure, the reset value received by the third input terminal in3 of the counter of the first pixel row is 0 as an example, that is, the default value of the first output terminal out1 of the counter of the first pixel row is 0. Figure 5 , in the first transfer operation above, Row n+1 The third input terminal in3 of the row counter receives the reset value 0, so that Row n+1 The row counter is reset to 0, that is, it stores the value 0. n+1 The row counter will be transferred to Row with a value of 0 n Row, so that Row n The row counter is reset to 0, and the Row n+1The third input terminal in3 of the row counter continues to receive the reset value 0, so that Row n+1 The row counter remains at 0. In the third transfer operation, Row n The row counter will be transferred to Row with a value of 0 n-1 OK n+1 The row counter will be transferred to Row with a value of 0 n OK n+1 The third input terminal in3 of the row counter continues to receive the reset value 0, so that Row n+1 The row counter remains at 0. n+1 Row n Row n-1 All count values ​​in the row counter are output, and Row n+1 Row n Row n-1 All row counters are reset to 0.

[0070] In this embodiment, by inputting a reset value at the third input terminal in3 of the counter of the first pixel row, the count value transfer operation and the counter reset operation are performed simultaneously. When the transfer operation is completed, the counters of multiple pixel rows are reset synchronously without the need for additional time to achieve the reset, which can shorten the operation time of the image sensor. In addition, the counter can be reset automatically without the need to set an additional reset structure, which is beneficial to reducing the area of ​​the image sensor and saving costs.

[0071] For example, the third input terminal in3 of the counter of the first pixel row can be fixed to receive the reset value, that is, the third input terminal in3 is connected to a fixed voltage. For example, the third input terminal in3 is grounded. In this way, no additional reset signal is required, which can simplify circuit control.

[0072] In some embodiments, Figure 5 As shown, each pixel further includes: an overflow feedback circuit 310 coupled to the second output terminal out2 of the counter 120 and the control terminal of the pixel unit; the overflow feedback circuit 310 is configured to: generate a control count signal qch_en in response to the first control signal expo_en and the count indication signal OF outputted from the second output terminal out2 of the counter 120, and output it to the pixel unit 110. The pixel unit 110 is configured to: generate a count pulse signal based on the received photons in response to the control count signal qch_en being in a first level state; or, stop generating the count pulse signal in response to the control count signal qch_en being in a second level state.

[0073] The count indication signal OF is used to indicate whether the count value of the counter is saturated. For example, the count indication signal OF also has a first level state and a second level state, one of which is used to indicate that the count is saturated, and the other is used to indicate that the count is not saturated. Here, it should be noted that the count value saturation of the counter means that the count value reaches a preset target value, which does not mean that the count value must reach the maximum value of the counter.

[0074] It should be noted that in this application, "first level state" and "second level state" are only used to represent two voltage states of different magnitudes, rather than limiting a specific voltage value. In other words, the first level state and the second level state of the first control signal, the counting control signal and the counting indication signal are independent of each other and do not affect each other.

[0075] For example, in response to the first control signal expo_en being in the first level state (i.e., the pixel is in the counting mode), and the count indication signal OF being in the first level state indicating that the count is not saturated, the overflow feedback circuit 310 controls the count signal qch_en to be in the first level state, allowing the pixel unit to generate a count pulse signal. In other cases, the pixel unit is prohibited from generating a count pulse signal.

[0076] For example, the overflow feedback circuit 310 responds to the count indication signal OF being in the second level state indicating count saturation, so that the control count signal qch_en is in the second level state, and the pixel unit is prohibited from generating a count pulse signal. The overflow feedback circuit 310 responds to the first control signal expo_en being in the second level state (that is, the pixel is in the transfer mode), so that the control count signal qch_en is in the second level state to prohibit the pixel unit from generating a count pulse signal. That is, when the count indication signal OF indicates count saturation or the pixel is in the transfer mode, the control count signal qcn_en prohibits the pixel unit from generating a count pulse signal.

[0077] It can also be understood that when the pixel is in the counting mode, if the count is saturated, the pixel unit is prohibited from generating a counting pulse, and if the count is not saturated, the pixel unit is allowed to generate a counting pulse; when the pixel is in the transfer mode, no matter whether the counter is saturated or not, the pixel unit is prohibited from generating a counting pulse. Or it can be understood that when the count is not saturated, the pixel unit is allowed to generate a counting pulse in the counting mode, and the pixel unit is prohibited from generating a counting pulse in the transfer mode; when the count is saturated, no matter which mode the pixel is in, the pixel unit is prohibited from generating a counting pulse.

[0078] On the premise of satisfying the above-mentioned logical relationship between the first control signal expo_en, the counting indication signal OF and the control counting signal qch_en, since each of the three signals has two polarities (the first level state and the second level state), according to the different response modes of the pixel unit (high level response, low level response, rising edge response or falling edge response), the polarity of the control counting signal qch_en that enables the pixel unit to generate a counting pulse signal is also different, and the polarity of qch_en is directly determined by the circuit structure of the overflow feedback circuit 310, the polarity of the first control signal expo_en and the counting indication signal OF, therefore, the specific circuit structure of the overflow feedback circuit 310 can be multiple. Figure 6 The following is a logical relationship table between the first control signal expo_en, the count indication signal OF and the control count signal qch_en provided in the embodiment of the present disclosure. Figure 6 Several overflow feedback circuits are provided, wherein the overflow feedback circuits can be determined based on a logical relationship.

[0079] Before providing the overflow feedback circuit, it is explained that when the first control signal expo_en is valid, the pixel is allowed to enter the counting mode, and when expo_en is invalid, the pixel is prohibited from entering the counting mode and the pixel enters the transfer mode. When the count indication signal OF is valid, the pixel unit is prohibited from outputting the counting pulse signal, and when OF is invalid, the pixel unit is allowed to output the counting pulse signal. When the control count signal qch_en is valid, the pixel unit is allowed to output the counting pulse, and when qch_en is invalid, the pixel unit is prohibited from outputting the counting pulse.

[0080] It should be noted that, in some other embodiments, the pixel unit is allowed to output a counting pulse signal when the counting indication signal OF is valid, and is prohibited from outputting a counting pulse signal when OF is invalid. In this case, it is necessary to adjust the logical relationship table between the first control signal expo_en, the counting indication signal OF and the control counting signal qch_en accordingly, and the specific structure of the overflow feedback circuit can also be determined based on the adjusted logical relationship table.

[0081] In Example 1, Figure 6 and Figure 7As shown, the first control signal expo_en is configured to be low level effective, the count indication signal OF is high level effective, and the control count signal qch_en is high level effective, then the logic expression between the three signals is: qch_en = ~ (expo_en | OF), then the overflow feedback circuit 310 can include a NOR gate, the first input end of the NOR gate receives expo_en, the second input end is coupled to the second output end out2 of the counter 120, for receiving OF, and the output end of the NOR gate is coupled to the control end of the pixel unit 110, for outputting qch_en to the control end of the pixel unit. The NOR gate is configured to: in response to expo_en being low level (effective) and OF being low level (ineffective), qch_en is high level (effective); in response to OF being high level (effective), qch_en is low level (ineffective); in response to expo_en being high level (ineffective), qch_en is low level (ineffective).

[0082] In Example 2, compared with Example 1, the counting indication signal OF is modified to be valid at a low level, then the logical expression between the three signals is: qch_en = (~expo_en) & OF, then the overflow feedback circuit may include a NOT gate and an AND gate, the input end of the NOT gate receives expo_en, the output end of the NOT gate is coupled to the first input end of the AND gate, the second input end of the AND gate receives OF, and the output end of the AND gate outputs qch_en. Among them, the NOT gate outputs a high level in response to expo_en being a low level (valid), and the AND gate responds to the high level of the NOT gate output and OF being a high level (invalid), so that qch_en is a high level (valid). The AND gate responds to OF being a low level (valid), so that qch_en is a low level (invalid). The NOT gate outputs a low level in response to expo_en being a high level (invalid), and the AND gate responds to the low level of the NOT gate output, so that qch_en is a low level (invalid).

[0083] In Example 4, compared with Example 2, the first control signal expo_en is modified to be high level valid, then the logical expression between the three signals is: qch_en=expo_en&OF, then the overflow feedback circuit may include an AND gate, the first input of the AND gate receives expo_en, the second input receives OF, and the output outputs qch_en. The AND gate is configured to: in response to expo_en being high level (valid) and OF being high level (invalid), qch_en is high level (valid); in response to OF being low level (valid), qch_en is low level (invalid); in response to expo_en being low level (invalid), qch_en is low level (invalid).

[0084] In Example 5, compared with Example 1, the control count signal qch_en is modified to be low level valid, then the logical expression between the three signals is: qch_en = expo_en | OF, then the overflow feedback circuit may include an OR gate, the first input of the OR gate receives expo_en, the second input receives OF, and the output outputs qch_en. The OR gate is configured to: in response to expo_en being low level (valid) and OF being low level (invalid), qch_en is low level (valid); in response to OF being high level (valid), qch_en is high level (invalid); in response to expo_en being high level (invalid), qch_en is high level (invalid).

[0085] In Example 8, compared with Example 1, the first control signal expo_en is modified to be high level valid, the count indication signal OF is modified to be low level valid, and the control count signal qch_en is modified to be low level valid. Then the logical expression between the three signals is: qch_en = ~ (expo_en | OF), then the overflow feedback circuit may include a NAND gate, the first input of the NAND gate receives expo_en, the second input receives OF, and the output outputs qch_en. The NAND gate is configured to: in response to expo_en being high level (valid) and OF being high level (invalid), qch_en is low level (valid); in response to OF being low level (valid), qch_en is high level (invalid); in response to expo_en being low level (invalid), the control count signal qch_en is high level (invalid).

[0086] Based on similar analysis, it can be known that in Example 3, the overflow feedback circuit may include a NOT gate and an AND gate, the input end of the NOT gate receives OF, the output end of the NOT gate is coupled to the first input end of the AND gate, the second input end of the AND gate receives expo_en, and the output end of the AND gate outputs qch_en. In Example 6, the overflow feedback circuit may include a NOT gate and an OR gate, the input end of the NOT gate receives OF, the output end of the NOT gate is coupled to the first input end of the OR gate, the second input end of the OR gate receives expo_en, and the output end of the OR gate outputs qch_en. In Example 7, the overflow feedback circuit may include a NOT gate and an OR gate, the input end of the NOT gate receives expo_en, the output end of the NOT gate is coupled to the first input end of the OR gate, the second input end of the OR gate receives OF, and the output end of the OR gate outputs qch_en. Examples 1 to 8 of the overflow feedback circuit provided above in the present disclosure are only examples and do not constitute a limitation on the overflow feedback circuit of the present disclosure. It should be understood that circuits that can replace the logic gates in Examples 1 to 8 are also within the scope of protection of the present disclosure. For example, the AND gate can be used to replace the NAND gate and the NOT gate.

[0087] For example, the overflow feedback circuit 310 is coupled to the quenching circuit in the pixel unit 110. The overflow feedback circuit turns off the quenching circuit after counting saturation, and the quenching circuit no longer works, so the pixel unit no longer generates counting pulses.

[0088] The overflow feedback circuit in the embodiment of the present disclosure can control the pixel unit to stop generating counting pulses when the counter counts saturated or the pixel enters the transfer mode, thereby reducing the power consumption of the pixel unit.

[0089] In some embodiments, Figure 5 As shown, each pixel also includes: a counting feedback circuit 320, a first input terminal of the counting feedback circuit 320 is coupled to the second output terminal out2 of the counter, a second input terminal of the counting feedback circuit 320 is coupled to the output terminal of the pixel unit, and an output terminal of the counting feedback circuit 320 is coupled to the first input terminal in1 of the counter; the counting feedback circuit 320 is configured to: in response to the counting indication signal OF indicating that the counting is not saturated, allow the counting pulse signal photonpulse to enter the first input terminal in1 of the counter 120; in response to the counting indication signal OF indicating that the counting is saturated (that is, the OF signal is valid), prohibit the counting pulse signal photon pulse from entering the first input terminal in1 of the counter 120.

[0090] By way of example, the counting feedback circuit 120 is specifically configured to generate a counting trigger signal dlsb_ck based on the counting indication signal OF and the counting pulse signal photon pulse and output it to the first input terminal of the counter. When the counting indication signal OF is in a first level state indicating that the counting is not saturated, the counting feedback circuit 320 receives the counting pulse signal photon pulse and generates a counting trigger signal dlsb_ck. Specifically, the counting feedback circuit 320 outputs a pulse (i.e., the counting trigger signal dlsb_ck) for each counting pulse signal received. When the counting indication signal OF is in a second level state indicating that the counting is saturated, the counting feedback circuit 320 shields the counting pulse signal photon pulse and no longer outputs a pulse.

[0091] On the premise that the counting feedback circuit 320 meets the above requirements, since the counting indication signal OF, the counting pulse signal photon pulse and the counting trigger signal dlsb_ck all have two polarities, the specific circuit structure of the counting feedback circuit 320 can be various. Figure 8 The logical relationship table between the counting indication signal OF, the counting pulse signal photonpulse and the counting trigger signal dlsb_ck provided in the embodiment of the present disclosure is as follows. Figure 8 Several counting feedback circuits are provided, wherein the counting feedback circuits can be determined based on a logical relationship.

[0092] Before describing the embodiments in detail, the present disclosure first makes the following definitions. For example, if the counting pulse signal photonpulse (hereinafter referred to as pulse) is set to a high level by default, when it switches from a high level to a low level and returns to a high level again, a counting pulse is formed, then the counting pulse signal is called a low level valid, and the formed counting pulse is a negative pulse. Correspondingly, if the counting pulse signal pulse is set to a low level by default, when it switches from a low level to a high level and returns to a low level again, a counting pulse is formed, then this counting pulse signal is called a high level valid, and the formed counting pulse is a positive pulse.

[0093] Similarly, the count trigger signal dlsb_ck may also be low level active, with a negative pulse, or high level active, with a positive pulse.

[0094] In Example 9, Figure 8 and Fig. 9 As shown, the counting pulse signal pulse is valid at a low level, the counting indication signal OF is valid at a high level, and the counting trigger signal dlsb_ck is valid at a high level, then the logic expression is: dlsb_ck = ~(pulse|OF). In this configuration, the counting feedback circuit 320 includes a NOR gate, wherein the first input terminal of the NOR gate is coupled to the second output terminal out2 of the counter 120 for receiving OF; the second input terminal of the NOR gate is coupled to the output terminal of the pixel unit 110 for receiving pulse; the output terminal of the NOR gate is coupled to the first input terminal in1 of the counter 120 for outputting dlsb_ck. The NOR gate is configured as follows: in response to OF being low level (invalid), the counting pulse signal pulse has a negative pulse, then the counting trigger signal dlsb_ck has a positive pulse; in response to OF being high level (invalid), no pulse is output.

[0095] In Example 10, compared with Example 9, the count indication signal OF is modified to be valid at a low level, and the logical expression is: dlsb_ck = (~pulse) & OF. Then the count feedback circuit may include a NOT gate and an AND gate, the input of the NOT gate receives pulse, the output of the NOT gate is coupled to the second input of the AND gate, the first input of the AND gate receives OF, and the output of the AND gate outputs dlsb_ck. Among them, the NOT gate outputs a positive pulse in response to the pulse having a negative pulse (valid), and the AND gate outputs a positive pulse in response to OF being a high level (invalid) and the NOT gate outputting a positive pulse. The AND gate does not output a pulse in response to OF being a low level (valid).

[0096] In Example 12, compared with Example 10, the counting pulse signal pulse is modified to be high level valid, and the logical expression is: dlsb_ck=pulse&OF. In this configuration, the counting feedback circuit 320 may include an AND gate, the first input of the AND gate receives OF, the second input receives pulse, and the output outputs dlsb_ck. The AND gate is configured as follows: in response to OF being high level (invalid), the counting pulse signal pulse has a positive pulse, and the output counting trigger signal dlsb_ck has a positive pulse; in response to OF being low level (valid), no pulse is output.

[0097] In Example 13, compared with Example 9, the count trigger signal dlsb_ck is modified to be low level valid, and the logical expression is: dlsb_ck=pulse|OF. In this configuration, the count feedback circuit 320 may include an OR gate, the first input terminal of the OR gate receives OF, the second input terminal receives pulse, and the output terminal outputs dlsb_ck. The OR gate is configured as follows: in response to OF being low level (invalid), the count pulse signal pulse has a negative pulse, and the output count trigger signal dlsb_ck has a negative pulse; in response to OF being high level (valid), no pulse is output.

[0098] In Example 16, compared with Example 9, the counting pulse signal pulse is modified to be high level valid, the counting indication signal OF is modified to be low level valid, and the counting trigger signal dlsb_ck is modified to be low level valid, then the logical expression is: dlsb_ck = ~(pulse & OF). In this configuration, the counting feedback circuit 320 may include a NAND gate, the first input terminal of the NAND gate receives OF, the second input terminal receives pulse, and the output terminal outputs dlsb_ck. The NAND gate is configured as follows: in response to OF being high level (invalid), the counting pulse signal pulse has a positive pulse, and the output counting trigger signal dlsb_ck has a negative pulse; in response to OF being low level (valid), no pulse is output.

[0099] Based on similar analysis, it can be known that in Example 11, the counting feedback circuit may include a NOT gate and an AND gate, the input end of the NOT gate receives OF, the output end of the NOT gate is coupled to the first input end of the AND gate, the second input end of the AND gate receives pulse, and the output end of the AND gate outputs dlsb_ck. In Example 14, the counting feedback circuit may include a NOT gate and an OR gate, the input end of the NOT gate receives OF, the output end of the NOT gate is coupled to the first input end of the OR gate, the second input end of the OR gate receives pulse, and the output end of the OR gate outputs dlsb_ck. In Example 15, the counting feedback circuit may include a NOT gate and an OR gate, the input end of the NOT gate receives pulse, the output end of the NOT gate is coupled to the second input end of the OR gate, the first input end of the OR gate receives OF, and the output end of the OR gate outputs dlsb_ck. Examples 9 to 16 of the counting feedback circuit provided above in the present disclosure are only examples and do not constitute a limitation on the overflow feedback circuit of the present disclosure. It should be understood that circuits that can replace the logic gates in Examples 9 to 16 are also within the scope of protection of the present disclosure. For example, the AND gate can be used to replace the NAND gate and the NOT gate.

[0100] The counting feedback circuit in the embodiment of the present disclosure can prohibit the counting pulse signal from entering the first input terminal of the counter when the counter is saturated, so as to reduce the power consumption of the counter.

[0101] Fig.10 Schematic diagram of an image sensor provided in an embodiment of the present disclosure Figure 4 In some embodiments, Fig.10 As shown in Figure (a) of FIG. , a counter (e.g., Figure 5 , Figure 7 and Fig. 9 The counter 120 in the embodiment includes a plurality of cascaded trigger units, and each stage of the trigger unit includes a first selector 210, a second selector 220 and a trigger 230.

[0102] In each level of trigger unit, the clock terminal of the trigger 230 is coupled to the output terminal of the first selector 210, the input terminal D of the trigger 230 is coupled to the output terminal of the second selector 220, and the output terminal Q of the trigger 230 is connected to the second selector 220 of the corresponding trigger unit of the corresponding counter in the next pixel row. The output terminals Q of all the triggers 230 in the counter constitute the first output terminal out1 of the counter, which is used to output the count value. The output terminal Q or the reverse output terminal of the trigger of the last level of trigger unit in the counter It also forms a second output terminal out2 of the counter, which is used to output a counting indication signal OF.

[0103] Fig.10Figure (b) is a partial enlarged view of the first selector 210 and the second selector 220. As shown in Figure (b), the control ends of the first selector 210 and the second selector 220 are connected to the first control signal expo_en, so that expo_en can control the signal input of each trigger 230 in the counter through the first selector 210 and the second selector 220, thereby controlling the counter to switch between the counting mode and the conversion mode.

[0104] In each counter, the first input end of the first selector 210 in all trigger units is used to receive the second control signal clk_shift. The second input end of the first selector 210 of the first-stage trigger unit is used as the first input end in1 of the counter, and is used to receive the counting pulse signal after passing through the counting feedback circuit 320, that is, the counting trigger signal dlsb_clk. The second input end of the first selector 210 of the trigger units of all stages except the first-stage trigger unit is coupled to the output end Q of the trigger of the previous stage trigger unit.

[0105] The first input terminals of the second selectors 220 of all trigger units in the counter constitute the third input terminal in3 of the counter, which is used to receive the count value of the corresponding counter in the previous pixel row to realize the count value transfer. The second input terminals of the second selectors 220 in the trigger units of the other levels except the last level are coupled to the reverse output terminal of the trigger in the trigger unit of the same level. The second input terminal of the second selector 220 of the last stage trigger unit is used to receive a preset value.

[0106] This embodiment is described by taking the output terminal Q of the trigger of the last level trigger unit as the second output terminal out2 of the counter as an example. In the counting mode, in the last level trigger unit of each counter, when the clock terminal of the trigger 230 receives a pulse output from the previous level trigger unit, the preset value received by the second selector 220 is used to flip the signal of the output terminal Q of the trigger, so that the count indication signal OF is switched from the first level state indicating that the count is not saturated to the second level state indicating that the count is saturated. For example, Fig.10 As shown, the preset value is 1, that is, the second input terminal of the second selector 220 receives a fixed high level, so that the output terminal of the trigger flips from 0 to 1, indicating that the count is saturated.

[0107] Here, it should be noted that Figure 6 In the example 3 provided, when the count indication signal is high level valid, the overflow feedback circuit 310 mentioned above includes a NOT gate and an AND gate, and another implementation method is to use the reverse output terminal of the trigger in the last stage trigger unit. The second output terminal out2 of the counter is formed, so that the count indication signal becomes low level effective. Then, as in Example 4, the overflow feedback circuit can only use an AND gate. In other words, the output terminal Q or the reverse output terminal of the trigger in the last stage trigger unit can be selected for the purpose of simplifying the structure of the overflow feedback circuit 310. As the second output terminal out2 of the counter.

[0108] In addition, it should be noted that, in other embodiments, the second input terminal of the second selector 220 of the last stage trigger unit may also be coupled to the reverse output terminal of the trigger in the trigger unit of the current stage. Instead of the preset value, the output terminal Q of the flip-flop can be used. It constitutes the second output terminal out2 of the counter.

[0109] For example, the type of the trigger may be a D flip-flop (D Flip-Flop, DFF). It should be understood that in other embodiments, the trigger may also be an RS trigger, a JK trigger, etc. The present disclosure does not limit the type of the trigger. Any trigger in the art that can be combined to form a counter can be applied to the present disclosure. In practical applications, a suitable trigger can be selected according to design requirements. In addition, the trigger may be a rising edge trigger or a falling edge trigger. The present disclosure does not limit this.

[0110] exist Fig.10 In the example, the trigger is a falling edge triggered D trigger. In another embodiment, if a rising edge triggered D trigger is used, except for the last level trigger unit, the reverse output terminal of the trigger 230 in the other levels of trigger units is is connected to the second input terminal of the first selector 210 in the next stage trigger unit. Fig.11 In the asynchronous counting structure shown in FIG. 1 , the reverse output terminal of the trigger 230 in the other trigger units is The output terminal Q of the trigger 230 is connected to the clock terminal of the trigger 230 in the next stage trigger unit, and the output terminal Q of the trigger 230 is connected to the second input terminal of the second selector 220 of the trigger unit at this stage.

[0111] The counter implements the counting function through multiple triggers 230. Among the multiple triggers 230, the trigger at the lowest position of the counter is DLSB, which is the trigger in the first-level trigger unit. The trigger at the highest position of the counter is DMSB, which is the trigger in the last-level trigger unit.

[0112] Fig.11Schematic diagram of the asynchronous counting structure of the image sensor. When the first control signal expo_en is in the first level state (valid), the counter enters the counting mode: each first selector 210 turns on its second input terminal and output terminal (i.e., turns on the output terminal Q of the previous stage trigger and the clock terminal of the current stage trigger, so that the signal output by the output terminal Q of the previous stage trigger can be used as the clock signal of the current stage trigger), and each second selector 220 turns on its second input terminal and output terminal (i.e., turns on the reverse output terminal of the current stage trigger). With input terminal D, the reverse output terminal of the trigger at this level The output signal can be used as the trigger signal of the trigger at this level), so that the counter has an asynchronous counting structure. Fig.11 As shown, when the counter adopts an asynchronous counting structure, there is no cascade relationship between the counters of different pixels in each column. In the counter of each pixel, multiple triggers DLSB, D1, D2...DMSB are connected to form a traveling wave asynchronous counter circuit.

[0113] During the pixel exposure phase, the SPAD in the pixel unit 110 in the waiting state is excited by light, generating photogenerated electrons and causing an avalanche event. After the avalanche event, the quenching circuit works to extinguish the avalanche, and then the quenching circuit recharges the SPAD to restore it to the waiting state. In this process, the quenching circuit also generates a pulse to the counter 120. The DLSB of the counter 120 receives this pulse, causing the count value of the entire traveling wave counting circuit to increase by 1.

[0114] During the exposure phase, the SPAD repeatedly generates avalanche events, and the count value of the counter 120 continues to increase. The last trigger DMSB of the counter 120 acts as an overflow protection register. When the signal at the output terminal Q of DMSB or the reverse output terminal After the signal of DMSB flips from the default value to the preset value, it means that the count values ​​of all previous triggers have reached the maximum, indicating that the counter counts are saturated. For example, the output terminal Q of DMSB is used to output the count indication signal OF, whose default value is 0 and the preset value is 1. In this embodiment, after DMSB flips from 0 to 1, it means that the count is saturated.

[0115] Continue to see Fig.11 After the signal at the output terminal Q of DMSB flips to 1, as a counting saturation flag, on the one hand, the overflow feedback circuit 310 controls the counting signal qch_en to switch to the second level state, that is, turns off the enable signal of the quenching circuit, so that the SPAD no longer generates an avalanche event, and no longer generates a counting pulse signal; on the other hand, the counting feedback circuit 320 shields the counting pulse signal, so that the counting pulse signal cannot be transmitted to the clock end of DLSB, so that the counter will no longer work.

[0116] After the exposure phase is completed, the counter of each pixel stores the number of pulses detected during the exposure phase, which is a representation of the light intensity of the optical target.

[0117] The working mode of the counter 120 is described in detail below. When the first control signal expo_en is in the first level state (for example, the low level is effective to make the counter enter the counting mode), the first selector 210 and the second selector 220 both turn on their respective second input terminals and output terminals, so that the trigger DFF n The Q end is connected to the next stage DFF n+1 The clock end of DFF n+1 Count clock of DFF n of Connecting DFF n The D end itself.

[0118] In this embodiment, DFF is a falling edge trigger. n Before the first falling edge of the counting clock, the signal at the Q end is 0. The signal at the end is 1; after the first falling edge appears, the Q end flips to 1. The end flips to 0; at this time DFF n The signal at the Q end is used as the DFF n+1 The signal at the clock end has a rising edge transition from 0 to 1, which will not trigger DFF n+1 .

[0119] When DFF n After the second falling edge of the counting clock appears, the Q terminal flips to 0. The end is flipped to 1; at this time DFF n The Q-end signal is used as DFF n+1 The clock signal changes from 1 to 0, triggering the DFF n+1 The Q end and Flip end.

[0120] Similarly, the counting pulse signal emitted by the pixel unit is used as the counting clock of DLSB. As the counting pulses continue to be generated, the Q ends of the three triggers show an incremental change of 000 (DMSB, DFF1, DLSB) → 001 → 010 → 011 → 100 (binary expression) (decimal expression, 0->1->2->3->4).

[0121] When the DMSB in the last-stage trigger unit flips, the counter reaches saturation, the quenching circuit is turned off through the overflow feedback circuit, the count is turned off through the count feedback circuit, and the pixel enters a dormant state to save power consumption.

[0122] Fig.12The figure is a schematic diagram of the synchronous transfer circuit structure of the image sensor. Fig.12 , when the first control signal expo_en is in the second level state (for example, the high level is invalid to make the counter enter the transfer mode), the first selector of each trigger unit in the counter turns on its first input terminal and its output terminal, and the second selector turns on its first input terminal and its output terminal, so that [Row n , Col n ]DFF of the pixel at position n The D end of the connection and the previous row [Row n+1 , Col n ] The corresponding DFF of the pixel n The Q end of all DFFs is connected to a unified transfer clock signal clk_shift, and the counter has a synchronous transfer structure.

[0123] After forming such a cascade relationship between upper and lower pixels, the control transfer clock signal clk_shift is flipped. Since the DFF trigger is a falling edge trigger type, when the falling edge of the transfer clock signal clk_shift arrives, [Row n+1 ,Col n ]Pixel DFF n The trigger transfers the count value to [Row n ,Col n ]Pixel DFF n This transfer process occurs simultaneously in each row, that is, all pixels are connected to the same transfer clock signal, and after N clock pulses, the transfer of N rows of data is completed. n The row count value is completed in N clock pulses. n →Row n-1 →Row n-2 …→Row2→Row1→shift reg. Under these N clock pulses, Row n-1 The row count value completes the Row n-1 →Row n-2 …→Row2→Row1→shift reg. And so on, N rows of data are transferred under N clock pulses.

[0124] Therefore, in the present disclosure, when N pixel rows perform one imaging on an imaging target, the image transfer time is Tclk_shift is the delay of one data transfer between two adjacent pixel rows, that is, the transmission delay of the second selector 220. For a 1080P resolution image, N=1080, the clk_shift frequency is 50MHz (T clk_shift=20ns), the readout time is about 20us. Compared with 300ns in the prior art, the readout time is greatly shortened, so the frame rate of the image can be significantly improved, improving the user's visual experience.

[0125] exist Fig.12 In the embodiment shown, the specific working mode of the counter is: when the transfer clock signal clk_shift flips a cycle and clk_shift has a falling edge, Row n DFF of row n The count value stored in DFF n The Q end of the count value is passed to Row n-1 DFF of row n The D end.

[0126] Each time the transfer clock signal clk_shift flips a cycle, all pixel rows are simultaneously transferred down one row, instead of just one row in the normal way, which greatly improves efficiency. The last pixel row Row1 will be transferred down to the shift register outside the pixel array. Specifically, it is transferred to the shift register of the shift register, and then the subsequent required processing is performed.

[0127] Fig.13 This is a working timing diagram of the image sensor provided in an embodiment of the present disclosure. Fig.13 Shows Fig.10 The timing of the transfer of multiple signals and count values ​​in the corresponding image sensor. Among them, the first control signal is low level effective. Fig.13 As shown, when the first control signal expo_en is set to 0, each selector conducts the corresponding path so that the counter uses an asynchronous counting structure (or asynchronous counting path). In the pixels in each pixel row (such as row N+2, row N+1 and row N in the figure), as shown in ① in the figure, each time the pixel unit responds to a photon, an avalanche event is triggered, triggering the quenching circuit to generate a counting pulse, and the corresponding counter is incremented by 1.

[0128] After a certain period of time, as shown in the figure, the first control signal expo_en is set to 1, the exposure ends, the quenching circuit is turned off, and no counting pulses are generated. At the same time, each selector conducts another path so that the counter selects a synchronous transfer structure (or synchronous transfer path).

[0129] Next, as shown in FIG. ③, the control circuit generates a continuous periodic transfer clock signal clk_shift; FIG. ③ is the falling edge of the first cycle of the transfer clock signal clk_shift, and the count value P of the pixel in the N+2th row is N+2 The count value P of the pixel in the N+1th row is passed to the pixel in the N+1th row. N+1 The count value P of the pixels in the Nth row is passed to the pixels in the Nth row.N The data is transferred to the pixels in the N-1th row; the same is true for the pixels in other rows, whose data is transferred to the next row, and the count value of the previous row is saved; the second cycle and subsequent cycles work in this way; all rows are transferred once in each cycle.

[0130] During the period when expo_en is set to 1, the transfer clock signal clk_shift has multiple cycles (i.e., multiple falling edges). In some embodiments, the number of cycles of the transfer clock signal may be equal to the number of pixel rows N, so that the pixels of the first pixel row can be transferred to the last shift register and the counters of all pixel rows are automatically reset to 0, as shown by the arrows in the figure. In other embodiments, the number of cycles of the transfer clock signal may be equal to the number of pixel rows N plus 1, so that the counters of all pixel rows are automatically reset to 0, and the shift registers may also be automatically reset to 0.

[0131] As shown in Figures ④ and ⑤, the data shifted into the first pixel row (a row of pixels farthest from the shift register) is fixed to 0. In the subsequent transfer cycle, data 0 is transferred to each pixel, thereby resetting all pixel counters.

[0132] Fig.13 Assuming that the Nth row is the last row to be transferred, then as shown in ⑥, the count value P of the pixel in the Nth row is N The data is transferred to the shift register outside the pixel array. The downstream processing module will take the data away for processing in each transfer clock signal clk_shift cycle, and the data in the shift register is updated in each cycle.

[0133] As shown in FIG. 7 , after the transfer is completed, the first control signal expo_en is reset to 0 again, and a new round of exposure counting and transfer process begins.

[0134] In summary, the image sensor provided by the embodiment of the present disclosure completes the exposure of N pixel rows at one time, and then transfers all the data synchronously after the exposure is completed at one time, that is, by exposing once and transferring N times, all the count values ​​of the N pixel rows are transferred out to obtain a digital image corresponding to the image. In addition, the image sensor also includes an overflow feedback circuit, which can prohibit the pixel unit from generating a counting pulse signal after the count is saturated to reduce the power consumption of the pixel unit. The image sensor may also include a counting feedback circuit, which can prohibit the counting pulse signal from entering the counter after the count is saturated, so that the counter stops working and reduces power consumption. It should be understood that only one of the overflow feedback circuit and the counting feedback circuit can be set, or both can be set. Furthermore, the image sensor can realize automatic reset to 0 in the transfer operation without setting an additional reset structure and reset signal, thereby saving circuit area, simplifying the circuit and reducing costs.

[0135] The disclosed embodiment also provides an image sensing circuit, which is applied to an image sensor, wherein the image sensor includes a plurality of pixel rows arranged in a first direction, each pixel row includes a plurality of pixels arranged in a second direction intersecting the first direction; the image sensor has a counting mode and a transfer mode, and the image sensing circuit includes a counting circuit and a transfer circuit. Wherein, when the image sensor is in the counting mode, the plurality of pixel rows count the received photons through the counting circuit to obtain a count value; when the image sensor is in the transfer mode, the plurality of pixel rows perform multiple transfer operations through the transfer circuit, so that the count value of each pixel row is transferred and output row by row; wherein, in each transfer operation, the count values ​​of each pixel row except the last pixel row are transferred to the next pixel row, the count value of the last pixel row is output, and the count values ​​of each pixel row except the first pixel row are replaced by the count value from the previous pixel row.

[0136] The features of the image sensor provided in the embodiments of the present disclosure can be applied to image sensor circuits to achieve the same or similar technical effects, which will not be described in detail in this disclosure.

[0137] The present disclosure provides an image processing method for an image sensor. Fig.14 The flowchart of the image processing method provided by the embodiment of the present disclosure is as follows: the image sensor includes a plurality of pixel rows arranged in a first direction, and each of the pixel rows includes a plurality of pixels arranged in a second direction intersecting the first direction. Fig.14 As shown, the image processing method includes:

[0138] S100: In the counting mode, a plurality of pixel rows count received photons to obtain count values;

[0139] S200: In the transfer mode, multiple pixel rows perform multiple transfer operations, so that the count value of each pixel row is transferred and output row by row; wherein, in each transfer operation, the count value of each pixel row except the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each pixel row except the first pixel row is replaced by the count value from the previous pixel row.

[0140] The image processing method described above on the image sensor side can be applied to the image processing method provided in this embodiment, and has the same or similar technical effects, and will not be described in detail in this disclosure.

[0141] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0142] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. An image sensor, characterized in that: include: A plurality of pixel rows arranged in a first direction, each of the pixel rows comprising a plurality of pixels arranged in a second direction intersecting the first direction; The plurality of pixel rows are configured as follows: In the counting mode, the received photons are counted to obtain the count value; In the transfer mode, multiple transfer operations are performed so that the count value of each pixel row is transferred and output row by row; wherein, in each transfer operation, the count value of each pixel row except the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each pixel row except the first pixel row is replaced by the count value from the previous pixel row.

2. The image sensor according to claim 1, characterized in that The plurality of pixel rows are configured as follows: In response to the first control signal being in a first level state synchronously, the counting mode is entered; and in response to the first control signal being in a second level state synchronously, the transfer mode is entered.

3. The image sensor according to claim 2, characterized in that The plurality of pixel rows are configured as follows: In the transfer mode, the multiple transfer operations are performed in synchronous response to a second control signal; wherein the second control signal is a transfer clock signal including a plurality of periodic clock pulses, and the multiple pixel rows perform the transfer operation once in response to one of the clock pulses.

4. The image sensor according to claim 3, characterized in that: Each of the pixels comprises: a pixel unit and a counter, wherein a first input terminal of the counter is coupled to an output terminal of the pixel unit, and a second input terminal of the counter is used to receive the first control signal; The pixel unit generates a counting pulse signal based on the received photons; The counter enters the counting mode in response to the first control signal being in the first level state, counts the received counting pulse signal to generate the counting value; and enters the transfer mode in response to the first control signal being in the second level state.

5. The image sensor according to claim 4, characterized in that: In each of the other pixel rows except the first pixel row, the third input terminal of the counter is coupled to the first output terminal of the corresponding counter in the previous pixel row; in each of the other pixel rows except the last pixel row, the first output terminal of the counter is coupled to the third input terminal of the corresponding counter in the next pixel row; In the transfer mode, all the counters of the multiple pixel rows perform the transfer operation multiple times; wherein, in each transfer operation, the counters of the pixel rows other than the last pixel row transfer the count value to the corresponding counter in the next pixel row, and the counter of the last pixel row outputs the count value; the count values ​​of the counters of the pixel rows other than the first pixel row are replaced by the count values ​​transferred by the corresponding counters in the previous pixel row.

6. The image sensor according to claim 5, characterized in that When performing the transfer operation, the third input terminal of the counter of the first pixel row is used to receive a reset value.

7. The image sensor according to claim 4, characterized in that: Each of the pixels further comprises: an overflow feedback circuit coupled to the second output terminal of the counter and the control terminal of the pixel unit; the overflow feedback circuit is configured to: generate a control count signal in response to the first control signal and a count indication signal outputted from the second output terminal of the counter, and output the control count signal to the pixel unit; The pixel unit is configured to: generate a counting pulse signal based on the received photons in response to the control counting signal being in a first level state; or stop generating the counting pulse signal in response to the control counting signal being in a second level state.

8. The image sensor according to claim 4, characterized in that: Each of the pixels further comprises: a counting feedback circuit, wherein a first input terminal of the counting feedback circuit is coupled to a second output terminal of the counter, a second input terminal of the counting feedback circuit is coupled to an output terminal of the pixel unit, and an output terminal of the counting feedback circuit is coupled to a first input terminal of the counter; the counting feedback circuit is configured as follows: In response to the count indication signal indicating that the count is not saturated, allowing the count pulse signal to enter the first input terminal of the counter; In response to the count indication signal indicating count saturation, the count pulse signal is prohibited from entering the first input terminal of the counter.

9. The image sensor according to any one of claims 5 to 8, characterized in that: The counter comprises a plurality of cascaded trigger units, and each stage of the trigger unit comprises a first selector, a second selector and a trigger; In each level of the trigger unit, the clock end of the trigger is coupled to the output end of the first selector, the input end of the trigger is coupled to the output end of the second selector, the output end of the trigger is connected to the second selector of the corresponding trigger unit of the corresponding counter in the next pixel row, the output ends of all the triggers in the counter constitute the first output end of the counter, and the output end or the reverse output end of the trigger of the last level of the trigger unit in the counter also constitutes the second output end of the counter; The control ends of the first selector and the second selector are connected to the first control signal; The first input terminal of the first selector is used to receive the second control signal; The second input end of the first selector of the first-stage trigger unit is used as the first input end of the counter, and the second input ends of the first selectors of the trigger units of the other stages except the first-stage trigger unit are coupled to the output end of the trigger of the previous stage trigger unit; The first input ends of all the second selectors in the counter constitute the third input end of the counter; the second input ends of all the second selectors are coupled to the reverse output end of the trigger in the trigger unit at this level, or the second input ends of the second selectors in the trigger units at all levels except the last level are coupled to the reverse output end of the trigger in the trigger unit at this level, and the second input end of the second selector of the last level trigger unit is used to receive a preset value.

10. An image sensing circuit, applied to an image sensor, characterized in that: The image sensor includes a plurality of pixel rows arranged in a first direction, each of the pixel rows including a plurality of pixels arranged in a second direction intersecting the first direction; The image sensor has a counting mode and a transfer mode, and the image sensing circuit includes a counting circuit and a transfer circuit; When the image sensor is in a counting mode, the plurality of pixel rows count received photons through the counting circuit to obtain count values; When the image sensor is in the transfer mode, the multiple pixel rows perform multiple transfer operations through the transfer circuit, so that the count value of each pixel row is transferred and output row by row; wherein, in each transfer operation, the count value of each pixel row except the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each pixel row except the first pixel row is replaced by the count value from the previous pixel row.

11. An image processing method for an image sensor, characterized in that: The image sensor includes a plurality of pixel rows arranged in a first direction, each of the pixel rows including a plurality of pixels arranged in a second direction intersecting the first direction; The image processing method comprises: In the counting mode, the plurality of pixel rows count received photons to obtain count values; In the transfer mode, the multiple pixel rows perform multiple transfer operations so that the count value of each pixel row is transferred and output row by row; wherein, in each transfer operation, the count value of each pixel row except the last pixel row is transferred to the next pixel row, the count value of the last pixel row is output, and the count value of each pixel row except the first pixel row is replaced by the count value from the previous pixel row.

Images