Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a substrate (101) and a plurality of driving units (Dpi). The driving units (Dpi) are located on one side of the substrate (101), orthographic projections of the multiple driving units (Dpi) on the substrate (101) are distributed in an array mode in the row and column direction, each driving unit (Dpi) comprises n rows and m columns of pixel driving circuits (Pix) and a compensation circuit (Cp), n and m are positive integers larger than or equal to 1, and n + m is larger than or equal to 3; the compensation circuit (Cp) is connected with a plurality of pixel driving circuits (Pix) located in the same driving unit (Dpi) with the compensation circuit (Cp), and the compensation circuit (Cp) is used for providing threshold value compensation signals for the pixel driving circuits (Pix) connected with the compensation circuit (Cp). The display panel can realize high pixel density setting.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, in an external compensation pixel driving circuit, since the pixel driving circuit includes a compensation circuit, the structure of the pixel driving circuit is relatively complex, which makes it difficult to achieve a high pixel density setting for the display panel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes: a base substrate, a plurality of driving units, the plurality of driving units being located on one side of the base substrate, and the orthographic projections of the plurality of driving units on the base substrate being distributed in an array along row and column directions, the driving unit including: n rows and m columns of pixel driving circuits, and a compensation circuit, where n and m are both positive integers greater than or equal to 1, and n+m is greater than or equal to 3; the compensation circuit is connected to a plurality of pixel driving circuits located in the same driving unit, and the compensation circuit is used to provide a threshold compensation signal to the pixel driving circuit connected thereto.

[0006] In an exemplary embodiment of the present disclosure, the driving unit includes a first sub-driving unit and a second sub-driving unit, and the orthographic projection of the first sub-driving unit on the substrate and the orthographic projection of the second sub-driving unit on the substrate are spaced apart in a column direction; the first sub-driving unit includes an n1-row and m-column pixel driving circuit, and the second sub-driving unit includes an n2-row and m-column pixel driving circuit, wherein n1 and n2 are positive integers greater than or equal to 1, and n1+n2=n; the orthographic projection of at least part of the structure of the compensation circuit on the substrate is located between the orthographic projection of the first sub-driving unit on the substrate and the orthographic projection of the second sub-driving unit on the substrate.

[0007] In an exemplary embodiment of the present disclosure, n1 is equal to n2.

[0008] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes: a driving circuit, a data writing circuit, and a first storage circuit. The driving circuit includes a first input terminal, a first output terminal, and a first control terminal, wherein the driving circuit is configured to provide a driving current to the first output terminal using the first input terminal based on a voltage at the first control terminal; the data writing circuit is connected to the first control terminal, a data line, and a gate line, and is configured to transmit a signal on the data line to the first control terminal in response to a signal on the gate line; and the first storage circuit is connected between the first control terminal and a first node, and is configured to store a voltage difference between the first control terminal and the first node. The compensation circuit includes: an analog circuit, a compensation control circuit, and a first reset circuit. The analog circuit and the driving circuit have the same or approximately the same threshold voltage. The analog circuit includes a second input terminal, a second output terminal, and a second control terminal. The analog circuit is used to provide a driving current to the second output terminal using the second input terminal according to the voltage of the second control terminal. The second input terminal is connected to the power line, and the second output terminal is connected to the second control terminal; the compensation control circuit is connected to the first node, the second output terminal, and the enable signal line, and is used to respond to the signal of the enable signal line to connect the first node and the second output terminal; the first reset circuit is connected to the first node, the reference signal line, and the reset signal line, and is used to respond to the signal of the reset signal line to transmit the signal of the reference signal line to the first node.

[0009] In an exemplary embodiment of the present disclosure, when the driving unit includes a first sub-driving unit and a second sub-driving unit; the orthographic projections of the analog circuit, the compensation control circuit, and the first reset circuit on the substrate are all located between the orthographic projection of the first sub-driving unit on the substrate and the orthographic projection of the second sub-driving unit on the substrate.

[0010] In an exemplary embodiment of the present disclosure, the orthographic projection of the enable signal line on the base substrate, the orthographic projection of the reference signal line on the base substrate, the orthographic projection of the reset signal line on the base substrate, and the orthographic projection of the power line on the base substrate all extend along the row direction and are located between the orthographic projection of the first sub-driving unit on the base substrate and the orthographic projection of the second sub-driving unit on the base substrate.

[0011] In an exemplary embodiment of the present disclosure, the compensation circuit further includes: a second storage circuit connected between the power line and the first node, and configured to store a voltage difference between the power line and the first node.

[0012] In an exemplary embodiment of the present disclosure, the display panel also includes: a light-emitting control circuit and a second reset circuit, the light-emitting control circuit is connected to the power line, the first input terminal, and the enable signal line, and is used to transmit the signal of the power line to the first input terminal in response to the signal of the enable signal line; the second reset circuit is connected to the first input terminal, the initial signal line, and the reset signal line, and is used to transmit the signal of the initial signal line to the first input terminal in response to the signal of the reset signal line.

[0013] In an exemplary embodiment of the present disclosure, the light emitting control circuit and the second reset circuit form an auxiliary driving circuit, and the pixel driving circuits located in the same row share one or more groups of the auxiliary driving circuits.

[0014] In an exemplary embodiment of the present disclosure, the pixel driving circuits located in the same row share two groups of the auxiliary driving circuits, and the pixel driving circuits located in the same row form a pixel driving circuit row, and the orthographic projections of the two groups of auxiliary driving circuits on the substrate are respectively located on both sides of the orthographic projection of the pixel driving circuit row connected to them on the substrate in the row direction.

[0015] In an exemplary embodiment of the present disclosure, the driving circuit includes: a driving transistor, wherein the first electrode of the driving transistor forms the first input terminal, the second electrode forms the first output terminal, and the gate forms the first control terminal; the data writing circuit includes: a first transistor, wherein the first electrode of the first transistor is connected to the data line, the second electrode is connected to the first control terminal, and the gate is connected to the gate line; the first storage circuit includes: a first capacitor, wherein the first electrode of the first capacitor is connected to the first control terminal, and the second electrode is connected to the first node; the analog circuit includes: an analog transistor, wherein the analog transistor and the driving transistor have the same or substantially the same threshold voltage, the first electrode of the analog transistor forms the second input terminal, and the second electrode forms the second output terminal , the gate forms the second control terminal; the compensation control circuit includes: a second transistor, the first electrode of the second transistor is connected to the second output terminal, the second electrode is connected to the first node, and the gate is connected to the enable signal line; the first reset circuit includes: a third transistor, the first electrode of the third transistor is connected to the reference signal line, the second electrode is connected to the first node, and the gate is connected to the reset signal line; the light-emitting control circuit includes: a fourth transistor, the first electrode of the fourth transistor is connected to the power line, the second electrode is connected to the first input terminal, and the gate is connected to the enable signal line; the second reset circuit includes: a fifth transistor, the first electrode of the fifth transistor is connected to the initial signal line, the second electrode is connected to the first input terminal, and the gate is connected to the reset signal line.

[0016] In an exemplary embodiment of the present disclosure, the second storage capacitor includes: a second capacitor, a first electrode of the second capacitor is connected to the power line, and a second electrode of the second capacitor is connected to the first node.

[0017] In an exemplary embodiment of the present disclosure, the driving circuit includes: a driving transistor, wherein the first electrode of the driving transistor forms the first input terminal, the second electrode forms the first output terminal, and the gate forms the first control terminal; the light-emitting control circuit includes: a fourth transistor, wherein the first electrode of the fourth transistor is connected to the power line, the second electrode is connected to the first input terminal, and the gate is connected to the enable signal line; the second reset circuit includes: a fifth transistor, wherein the first electrode of the fifth transistor is connected to the initial signal line, the second electrode is connected to the first input terminal, and the gate is connected to the reset signal line. The display panel also includes: an active layer, the active layer is located on one side of the base substrate, the active layer includes a fourth active portion, a fifth active portion, a sixth active portion, and an active line; wherein the fourth active portion is used to form a channel region of the fourth transistor, the fifth active portion is used to form a channel region of the fifth transistor, and the sixth active portion is used to form a channel region of the driving transistor; wherein the positive projection of the active line on the base substrate extends along the row direction, the active line is connected to the first electrode of the driving transistor, the sixth active portion in the pixel driving circuit located in the same row is connected to the same active line, and the fifth active portion and the sixth active portion are connected to the same end of the active line in the row direction.

[0018] In an exemplary embodiment of the present disclosure, the driving unit includes a first sub-driving unit, the orthographic projection of the first sub-driving unit on the base substrate is located on one side of the orthographic projection of the auxiliary driving circuit on the base substrate in the column direction, and the first sub-driving unit includes two adjacent rows and m columns of pixel driving circuits; in the same row of the first sub-driving unit, the sixth active portions in the driving circuits in the two rows are connected to the same active line.

[0019] In an exemplary embodiment of the present disclosure, the driving circuit includes: a driving transistor, wherein the first electrode of the driving transistor forms the first input terminal, the second electrode forms the first output terminal, and the gate forms the first control terminal; the first storage circuit includes: a first capacitor, wherein the first electrode of the first capacitor is connected to the first control terminal, and the second electrode is connected to the first node. The display panel also includes: a first conductive layer and a second conductive layer, wherein the first conductive layer is located on one side of the base substrate, the first conductive layer includes a sixth gate portion, at least a portion of the structure of the sixth gate portion is used to form the gate of the driving transistor and the first electrode of the first capacitor; the second conductive layer is located on a side of the first conductive layer facing away from the base substrate, the second conductive layer includes a first conductive portion, the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the sixth gate portion on the base substrate at least partially overlap, and the first conductive portion is used to form the second electrode of the first capacitor; m is a positive integer greater than or equal to 2, and in the same driving unit, the first conductive portions in the same row of pixel driving circuits are connected.

[0020] In an exemplary embodiment of the present disclosure, the compensation control circuit includes: a second transistor, a first electrode of the second transistor being connected to the second output terminal, a second electrode being connected to the first node, and a gate being connected to the enable signal line; the first reset circuit includes: a third transistor, a first electrode of the third transistor being connected to the reference signal line, a second electrode being connected to the first node, and a gate being connected to the reset signal line; the driving unit includes a first sub-driving unit and a second sub-driving unit, wherein an orthographic projection of the first sub-driving unit and an orthographic projection of the second sub-driving unit on the substrate are distributed in a column direction; the first sub-driving unit includes an n1-row and m-column pixel driving circuit, and the second sub-driving unit includes an n2-row and m-column pixel driving circuit, wherein n1 and n2 are positive integers greater than or equal to 1, and n1+n2=n; and the orthographic projections of the analog circuit, the compensation control circuit, and the first reset circuit on the substrate are all located between the orthographic projections of the first sub-driving unit and the second sub-driving unit on the substrate. The display panel also includes: a first bridge portion and a second bridge portion, wherein the orthographic projection of the first bridge portion on the base substrate extends along the column direction, the first bridge portion is connected to the second electrode of the second transistor, and is connected to the first conductive portions respectively located in the first sub-driving unit and the second sub-driving unit; the orthographic projection of the second bridge portion on the base substrate extends along the column direction, the second bridge portion is connected to the second electrode of the third transistor, and is connected to the first conductive portions respectively located in the first sub-driving unit and the second sub-driving unit; the first bridge portion and the second bridge portion are connected to different first conductive portions.

[0021] In an exemplary embodiment of the present disclosure, the orthographic projections of the analog circuit, the compensation control circuit, and the first reset circuit on the base substrate are all located between the orthographic projections of the first bridge portion and the second bridge portion on the base substrate.

[0022] In an exemplary embodiment of the present disclosure, the display panel further includes: a fourth conductive layer and a fifth conductive layer, the fourth conductive layer is located on a side of the second conductive layer away from the base substrate, the fourth conductive layer includes a second shielding line, the second shielding line is connected to a stable power supply terminal, the orthographic projection of the second shielding line on the base substrate extends along a column direction, and the second shielding line includes a first extension portion; the fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate, the fifth conductive layer includes the data line; the overlapping portion of the orthographic projection of the sixth gate portion on the base substrate and the orthographic projection of the data line on the base substrate and the orthographic projection of the first extension portion on the base substrate at least partially overlap, and / or the overlapping portion of the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the data line on the base substrate and the orthographic projection of the first extension portion on the base substrate at least partially overlap.

[0023] In an exemplary embodiment of the present disclosure, the second shielding line further includes a second extending portion, and an orthographic projection of the second extending portion on the base substrate is located between orthographic projections of two adjacent data lines on the base substrate.

[0024] In an exemplary embodiment of the present disclosure, the compensation circuit further includes a second capacitor, wherein a first electrode of the second capacitor is connected to the power line, and a second electrode of the second capacitor is connected to the first node. The display panel further includes: a third conductive layer and a fourth conductive layer, wherein the third conductive layer is located on a side of the second conductive layer facing away from the base substrate, the third conductive layer including the first bridge portion and the second bridge portion; a fourth conductive layer is located on a side of the third conductive layer facing away from the base substrate, the fourth conductive layer including a plurality of second shielding lines, the second shielding lines connected to the power line, and the second shielding lines including a second extension portion; an orthographic projection of the first bridge portion on the base substrate overlaps with an orthographic projection of one of the second extension portions on the base substrate, and an orthographic projection of the second bridge portion on the base substrate overlaps with an orthographic projection of another of the second extension portions on the base substrate; the first bridge portion and the second bridge portion are used to form the second electrode of the second capacitor, and the second extension portion is used to form the first electrode of the second capacitor.

[0025] In an exemplary embodiment of the present disclosure, the display panel further includes: a third conductive layer and a fifth conductive layer, the third conductive layer is located on a side of the second conductive layer away from the base substrate, the third conductive layer includes a power connection line segment, the power connection line segment is connected to the power line, and the orthographic projection of the power connection line segment on the base substrate extends along the column direction; the fifth conductive layer is located on a side of the third conductive layer away from the base substrate, the fifth conductive layer includes the data line; the overlapping part of the orthographic projection of the sixth gate portion on the base substrate and the orthographic projection of the data line on the base substrate and the orthographic projection of the power connection line segment on the base substrate at least partially overlap, and / or the overlapping part of the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the data line on the base substrate and the orthographic projection of the power connection line segment on the base substrate at least partially overlap.

[0026] In an exemplary embodiment of the present disclosure, an orthographic projection of the power connection line segment on the substrate is located between orthographic projections of adjacent reset signal lines and enable signal lines in adjacent driving units in a column direction on the substrate.

[0027] In an exemplary embodiment of the present disclosure, adjacent power connection line segments in a column direction are connected to form a power connection line.

[0028] In an exemplary embodiment of the present disclosure, the display panel also includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The display panel also includes: a fifth conductive layer, an electrode layer, and a pixel definition layer, the fifth conductive layer is located on one side of the base substrate, and the fifth conductive layer includes the data line; the electrode layer is located on the side of the fifth conductive layer away from the base substrate, and the electrode layer includes a plurality of electrode portions, and the electrode portions are used to form the first electrode of the light-emitting unit; a plurality of pixel openings are formed on the pixel definition layer, and the pixel openings are used to form the light-emitting unit, and the orthographic projections of the pixel openings on the base substrate coincide with the effects of the corresponding electrode portions on the base substrate; wherein the orthographic projections of the electrode portions on the base substrate are located between the orthographic projections of adjacent data lines on the base substrate.

[0029] In an exemplary embodiment of the present disclosure, the display panel further includes: a first conductive line, the orthographic projection of the first conductive line on the base substrate extends along a row direction, and the first conductive line is connected to the active line through a plurality of vias distributed in the row direction.

[0030] In an exemplary embodiment of the present disclosure, the compensation circuit further includes: a second capacitor, wherein a first electrode of the second capacitor is connected to the power line, and a second electrode of the second capacitor is connected to the first node. The display panel further includes: a third conductive layer and a fourth conductive layer, wherein the third conductive layer is located on a side of the second conductive layer facing away from the base substrate, the third conductive layer includes a seventh conductive portion, the seventh conductive portion is connected to the first conductive portion, and the seventh conductive portion is used to form the second electrode of the second capacitor; and a fourth conductive layer is located on a side of the third conductive layer facing away from the base substrate, the fourth conductive layer includes a second shielding line, the second shielding line is connected to the power line, the orthographic projection of the second shielding line on the base substrate and the orthographic projection of the seventh conductive portion on the base substrate at least partially overlap, and the second shielding line portion is structured to form the first electrode of the second capacitor.

[0031] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0034] FIG1 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0035] FIG2 is an equivalent circuit diagram of a driving unit in an exemplary embodiment of a display panel disclosed herein;

[0036] FIG3 is a timing diagram of each signal line in a driving method of the display panel shown in FIG2 ;

[0037] FIG4 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0038] FIG5 is a structural diagram of the active layer in FIG4 ;

[0039] FIG6 is a structural diagram of the first conductive layer in FIG4 ;

[0040] FIG7 is a structural diagram of the second conductive layer in FIG4 ;

[0041] FIG8 is a structural diagram of the third conductive layer in FIG4 ;

[0042] FIG9 is a structural diagram of the fourth conductive layer in FIG4 ;

[0043] FIG10 is a structural diagram of the fifth conductive layer in FIG4 ;

[0044] FIG11 is a structural diagram of the electrode layer in FIG4 ;

[0045] FIG12 is a structural layout diagram of the active layer and the first conductive layer in FIG4 ;

[0046] FIG13 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG4 ;

[0047] FIG14 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG4 ;

[0048] FIG15 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in FIG4 ;

[0049] FIG16 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG4 ;

[0050] FIG17 is a partial cross-sectional view of the display panel shown in FIG4 taken along dotted line AA;

[0051] FIG18 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0052] FIG19 is a structural diagram of the active layer in FIG18 ;

[0053] FIG20 is a structural layout diagram of the first conductive layer in FIG18 ;

[0054] FIG21 is a structural diagram of the second conductive layer in FIG18;

[0055] FIG22 is a structural layout diagram of the third conductive layer in FIG18;

[0056] FIG23 is a structural layout diagram of the fifth conductive layer in FIG18;

[0057] FIG24 is a structural diagram of the electrode layer in FIG18;

[0058] FIG25 is a structural layout diagram of the active layer and the first conductive layer in FIG18;

[0059] FIG26 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG18 ;

[0060] FIG27 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG18 ;

[0061] FIG28 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fifth conductive layer in FIG18 ;

[0062] FIG29 is a partial cross-sectional view of the display panel shown in FIG18 taken along dotted line BB;

[0063] FIG30 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0064] FIG31 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0065] FIG32 is a structural diagram of the active layer in FIG31;

[0066] FIG33 is a structural diagram of the first conductive layer in FIG31;

[0067] FIG34 is a structural layout diagram of the second conductive layer in FIG31;

[0068] FIG35 is a structural layout diagram of the third conductive layer in FIG31;

[0069] FIG36 is a structural layout diagram of the active layer and the first conductive layer in FIG31;

[0070] FIG37 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG31;

[0071] FIG38 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0072] FIG39 is a structural layout diagram of the active layer in FIG38;

[0073] FIG40 is a structural layout diagram of the first conductive layer in FIG38;

[0074] FIG41 is a structural layout diagram of the second conductive layer in FIG38;

[0075] FIG42 is a structural layout diagram of the third conductive layer in FIG38;

[0076] FIG43 is a structural layout diagram of the fourth conductive layer in FIG38;

[0077] FIG44 is a structural layout diagram of the fifth conductive layer in FIG38;

[0078] FIG45 is a structural diagram of the electrode layer in FIG38;

[0079] FIG46 is a structural layout diagram of the active layer and the first conductive layer in FIG38;

[0080] FIG47 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG38;

[0081] FIG48 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG38 ;

[0082] FIG49 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in FIG38;

[0083] FIG50 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG38;

[0084] FIG51 is a partial cross-sectional view of the display panel shown in FIG38 taken along the dotted line CC;

[0085] FIG52 is a partial structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0086] FIG53 is a structural diagram of the active layer in FIG52;

[0087] FIG54 is a structural layout diagram of the first conductive layer in FIG52;

[0088] FIG55 is a structural layout diagram of the third conductive layer in FIG52;

[0089] FIG56 is a structural layout diagram of the fourth conductive layer in FIG52;

[0090] FIG57 is a structural layout diagram of the active layer and the first conductive layer in FIG52;

[0091] FIG58 is a structural layout diagram of the active layer, the first conductive layer, and the third conductive layer in FIG52;

[0092] FIG59 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0093] FIG60 is a structural layout diagram of the active layer in FIG59;

[0094] FIG61 is a structural layout diagram of the first conductive layer in FIG59;

[0095] FIG62 is a structural layout diagram of the second conductive layer in FIG59;

[0096] FIG63 is a structural layout diagram of the third conductive layer in FIG59;

[0097] FIG64 is a structural layout diagram of the fourth conductive layer in FIG59;

[0098] FIG65 is a structural layout diagram of the fifth conductive layer in FIG59;

[0099] FIG66 is a structural diagram of the electrode layer in FIG59;

[0100] FIG67 is a structural layout diagram of the active layer and the first conductive layer in FIG59;

[0101] FIG68 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG59;

[0102] FIG69 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG59;

[0103] FIG70 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in FIG59;

[0104] FIG71 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG59;

[0105] FIG72 is a partial cross-sectional view of the display panel shown in FIG59 taken along dotted line DD;

[0106] FIG73 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0107] FIG74 is a structural layout diagram of the second conductive layer in FIG73;

[0108] Figure 75 is a structural layout of the third conductive layer in Figure 73. DETAILED DESCRIPTION

[0109] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0110] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0111] In the related art, a display panel includes a pixel driving circuit and a light-emitting unit. The pixel driving circuit includes a driving transistor. The driving transistor outputs a driving current to the light-emitting unit according to its gate voltage. The driving current output by the driving transistor is I = (μWCox / 2L)(Vgs-Vth)2, where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The magnitude of the driving current output by the driving transistor is related to the threshold voltage of the driving transistor. However, in the related art, due to process errors and other reasons, the threshold voltages of different driving transistors on the display panel vary, resulting in uneven display of the display panel. In the related art, the threshold voltage of the driving transistor can be compensated by external compensation so that the magnitude of the driving current output by the driving transistor is unrelated to the threshold voltage of the driving transistor. In the related art, the display panel usually sets a compensation circuit in the pixel driving circuit, and inputs a threshold compensation signal to the gate of the driving transistor through the compensation circuit so that the driving current output by the driving transistor is unrelated to its threshold voltage. However, since the pixel driving circuit includes a compensation circuit, the layout space of the pixel driving circuit is relatively large, which makes it difficult to achieve high-density pixel arrangement in the display panel.

[0112] Based on this, this exemplary embodiment provides a display panel. FIG1 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein. The display panel may include a base substrate and a plurality of drive units Dpi. The orthographic projections of the plurality of drive units Dpi on the base substrate are arranged in an array along the row direction X and the column direction Y. The drive units Dpi may include: two rows and five columns of pixel drive circuits Pix and a compensation circuit Cp. The compensation circuit Cp may be connected to each pixel drive circuit Pix within the same drive unit, and the compensation circuit Cp is configured to provide a threshold compensation signal to the connected pixel drive circuit Pix.

[0113] The display panel provided in this exemplary embodiment can provide threshold compensation signals to multiple pixel driving circuits Pix via compensation circuit Cp, thereby decoupling the driving current output by the driving transistors in the pixel driving circuits from their threshold voltages. This arrangement can improve the integration of the pixel driving circuits, thereby facilitating the design of high-pixel-density display panels.

[0114] As shown in Figure 1 , the drive unit Dpi may include a first sub-drive unit Dpi1 and a second sub-drive unit Dpi2. The orthographic projections of the first sub-drive unit Dpi1 and the second sub-drive unit Dpi2 on the substrate are spaced apart in the column direction Y. The first sub-drive unit Dpi1 may include a pixel drive circuit in one row and five columns, and the second sub-drive unit Dpi2 may include a pixel drive circuit in one row and five columns. The orthographic projection of at least part of the compensation circuit Cp on the substrate may be located between the orthographic projections of the first sub-drive unit Dpi1 and the second sub-drive unit Dpi2 on the substrate. This arrangement facilitates connection of the compensation circuit Cp with the pixel drive circuit in the same drive unit.

[0115] It should be understood that in other exemplary embodiments, the driving unit Dpi may also include pixel driving circuits with other numbers of rows and columns. For example, the driving unit Dpi may include: n rows and m columns of pixel driving circuits Pix, where n and m are both positive integers greater than or equal to 1, and n+m is greater than or equal to 3, that is, the driving unit Dpi may include multiple rows and columns of pixel driving circuits, or the driving unit Dpi may include one row and multiple columns of pixel driving circuits, or the driving unit Dpi may include multiple rows and one column of pixel driving circuits. In other exemplary embodiments, the first sub-driving unit and the second sub-driving unit may also include pixel driving circuits with other numbers of rows and columns. The first sub-driving unit may include n1 rows and m columns of pixel driving circuits, and the second sub-driving unit may include n2 rows and m columns of pixel driving circuits, where n1 and n2 are positive integers greater than or equal to 1, and n1+n2=n. n1 may be equal to n2, and n1 may not be equal to n2.

[0116] As shown in Figure 2, an equivalent circuit diagram of a driving unit in an exemplary embodiment of the display panel disclosed herein is shown. As shown in Figure 2, this exemplary embodiment is described by taking an example where the driving unit Dpi includes two rows and two columns of pixel driving circuits Pix.

[0117] In this exemplary embodiment, the pixel driving circuit Pix may include a driving circuit 11, a data writing circuit 12, and a first storage circuit 13. The driving circuit 11 includes a first control terminal CN1, a first input terminal IN1, and a first output terminal OT1. The driving circuit 11 is configured to provide a driving current to the first output terminal OT1 using the first input terminal IN1 based on the voltage at the first control terminal CN1. The data writing circuit 12 is connected to the first control terminal CN1, data signal terminals Da1 / Da2, and gate drive signal terminals G1 / G2, and is configured to transmit the signal at the data signal terminals Da1 / Da2 to the first control terminal CN1 in response to the signal at the gate drive signal terminals G1 / G2. The first storage circuit 13 is connected between the first control terminal CN1 and a first node N1 and is configured to store the voltage difference between the first control terminal CN1 and the first node N1. The compensation circuit Cp may include an analog circuit 21, a compensation control circuit 22, a first reset circuit 23, and a second storage circuit 24. The analog circuit 21 has the same or leads to the same threshold voltage as the driving circuit 11. The analog circuit 21 includes a second control terminal CN2, a second input terminal IN2, and a second output terminal OT2. The analog circuit 21 is used to input a driving current to the second output terminal OT2 using the second input terminal IN2 according to the signal of the second control terminal CN2. The second input terminal IN2 is connected to the first power supply terminal VDD, and the second output terminal OT2 is connected to the second control terminal CN2; the compensation control circuit 22 is connected to the first node N1, the second output terminal OT2, and the enable signal terminal EM, and is used to respond to the signal of the enable signal terminal EM to connect the first node N1 and the second output terminal OT2; the first reset circuit 23 is connected to the first node N1, the reference signal line Vref, and the reset signal terminal Re, and is used to transmit the signal of the reference signal line Vref to the first node N1 in response to the signal of the reset signal terminal Re; the second storage circuit 24 is connected between the first power supply terminal VDD and the first node N1, and is used to store the voltage between the first power supply terminal VDD and the first node N1.

[0118] In this exemplary embodiment, the orthographic projections of the analog circuit 21 , the compensation control circuit 22 , and the first reset circuit 23 on the substrate may be located between the orthographic projections of the first sub-driving unit and the second sub-driving unit on the substrate.

[0119] As shown in FIG2 , the display panel may further include a light-emitting control circuit 31 and a second reset circuit 32. The light-emitting control circuit 31 is connected to the first power supply terminal VDD, the first input terminal IN1, and the enable signal terminal EM, and is configured to transmit a signal from the first power supply terminal VDD to the first input terminal IN1 in response to a signal from the enable signal terminal EM. The second reset circuit 32 is connected to the first input terminal IN1, the initial signal terminal Vinit, and the reset signal terminal Re, and is configured to transmit a signal from the initial signal terminal Vinit to the first input terminal IN1 in response to a signal from the reset signal terminal Re. As shown in FIG2 , the light-emitting control circuit 31 and the second reset circuit 32 may form an auxiliary drive circuit 3. The pixel drive circuits Pix in the same row may share a group of auxiliary drive circuits 3.

[0120] As shown in FIG2 , the driving circuit includes a driving transistor DT, wherein a first electrode of the driving transistor DT forms the first input terminal IN1, a second electrode forms the first output terminal OT1, and a gate forms the first control terminal CN1. The data write circuit 12 includes a first transistor T1, wherein a first electrode of the first transistor T1 is connected to the data signal terminals Da1 / Da2, a second electrode is connected to the first control terminal CN1, and a gate is connected to the gate drive signal terminals G1 / G2. The first storage circuit 13 includes a first capacitor C1, wherein a first electrode of the first capacitor C1 is connected to the first control terminal CN1, and a second electrode of the first capacitor C1 is connected to the first node N1. The analog circuit 21 includes an analog transistor DTd, wherein the analog transistor DTd and the driving transistor DT have the same or substantially the same threshold voltage. The first electrode of the analog transistor DTd forms the first power supply terminal VDD, the second electrode forms the second output terminal OT2, and the gate forms the second output terminal OT2. The compensation control circuit 22 may include: a second transistor T2, wherein a first electrode of the second transistor T2 is connected to the second output terminal OT2, a second electrode is connected to the first node N1, and a gate is connected to the enable signal terminal EM; the first reset circuit 23 may include: a third transistor T3, wherein a first electrode of the third transistor T3 is connected to the reference signal line Vref, a second electrode is connected to the first node N1, and a gate is connected to the reset signal terminal Re. The light emitting control circuit 31 may include: a fourth transistor T4, wherein a first electrode of the fourth transistor T4 is connected to the first power supply terminal VDD, a second electrode is connected to the first input terminal IN1, and a gate is connected to the enable signal terminal EM; the second reset circuit 32 may include: a fifth transistor T5, wherein a first electrode of the fifth transistor T5 is connected to the initial signal terminal Vinit, a second electrode is connected to the first input terminal IN1, and a gate is connected to the reset signal terminal Re.

[0121] In this exemplary embodiment, the threshold voltage of the analog transistor DTd can be Vth, and the difference between the threshold voltage of the analog transistor DTd and the threshold voltage of the driving transistor DT can be Vth1. The analog transistor DTd and the driving transistor DT have approximately the same threshold voltage, which can be understood as the absolute value of Vth1 / Vth is less than or equal to 20%. For example, the absolute value of Vth1 / Vth can be 1%, 2%, 3%, 5%, 10%, 20%, etc.

[0122] In this exemplary embodiment, the analog transistor DTd and the driving transistor DT may have the same threshold voltage by having the same channel size, the same channel aspect ratio, and the same channel material. In this exemplary embodiment, the analog transistor DTd and the driving transistor DT may also have the same channel shape. The analog transistor DTd and the driving transistor DT may have substantially the same threshold voltage by having the same channel size and the same channel material having substantially the same carrier mobility.

[0123] In this exemplary embodiment, the display panel may further include a light-emitting unit L. The first output terminal OT1 may be connected to a first electrode of the light-emitting unit L, and a second electrode of the light-emitting unit L may be connected to a second power supply terminal VSS. The first power supply terminal VDD may be used to output a high-level power signal, and the power supply terminal VSS may be used to output a low-level power signal.

[0124] It should be noted that a gate line is provided for pixel drive circuits in the same row, and the gate drive signal terminals in the pixel drive circuits in the same row are provided by the same gate line; a data line is provided for pixel drive circuits in the same column, and the data signal terminals in the pixel drive circuits in the same column are provided by the same data line. For example, in FIG2 , the gate drive signal terminal G1 in the pixel drive circuits in the first row is connected to the same gate line, the gate drive signal terminal G2 in the pixel drive circuits in the second row is connected to the same gate line, the data signal terminal Da1 in the pixel drive circuits in the first column is connected to the same data line, and the data signal terminal Da2 in the pixel drive circuits in the second column is connected to the same data line.

[0125] In this exemplary embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the driving transistor DT, and the analog transistor DTd may all be P-type transistors. It should be understood that in other exemplary embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may also be N-type transistors.

[0126] FIG3 is a timing diagram of each signal line in a driving method of the display panel shown in FIG2. In particular, G1 represents the timing diagram of the gate drive signal terminal G1, G2 represents the timing diagram of the gate drive signal terminal G2, EM represents the timing diagram of the enable signal terminal, and Re represents the timing diagram of the reset signal terminal.

[0127] The driving method of the driving unit in the display panel may include: a first data writing phase t1, a second data writing phase t2, and a light emitting phase t3. In the first data writing phase t1, the reset signal terminal Re outputs a low level, the fifth transistor T5 and the third transistor T3 are turned on, the initial signal terminal Vinit inputs an initial signal to the first input terminal IN1 of each driving transistor DT in the same driving unit, the reference signal terminal Vref inputs a reference signal to the first node N1, and simultaneously, the gate driving signal terminal G1 outputs a low level, the first transistor T1 in the first row pixel driving circuit is turned on, the data signal line inputs a data signal to the first control terminal CN1 in the first row pixel driving circuit, and simultaneously, the first power supply terminal VDD inputs a voltage Vdd+Vth to the second output terminal OT2, where Vdd is the voltage of the first power supply terminal VDD and Vth is the threshold voltage of the analog transistor DTd. During the second data writing phase t2, the reset signal terminal Re outputs a low level, the fifth transistor T5 and the third transistor T3 are turned on, the initial signal terminal Vinit inputs an initial signal to the first input terminal IN1 of each driver transistor DT in the same driver unit, the reference signal terminal Vref inputs a reference signal to the first node N1, and the gate drive signal terminal G2 outputs a low level. The first transistor T1 in the second row pixel driver circuit is turned on, and the data signal line inputs a data signal to the first control terminal CN1 in the second row pixel driver circuit. Furthermore, the first power supply terminal VDD continuously inputs a voltage Vdd+Vth to the second output terminal OT2. During the light-emitting phase t3, the enable signal terminal EM outputs a low level enable signal, the second transistor T2 and the fourth transistor T4 are turned on, and the voltage at the first node N1 changes from Vref to Vdd+Vth. Coupled by the first capacitor C1, the voltage at the first control terminal CN1 changes from Vdata to Vdd+Vth-Vref+Vdata. Vref is the voltage of the reference signal, and Vdata is the voltage of the data signal. Thus, the driving current output by the driving transistor DT is I = (μW Cox / 2L)(Vgs - Vth)² = I = (μW Cox / 2L)(Vdata - Vref)². This driving current formula indicates that the driving current output by the pixel driving circuit in this display panel is independent of the threshold voltage of the driving transistor. Furthermore, the driving current output by the pixel driving circuit in this display panel is also independent of the voltage at the first power supply terminal. This means that this display panel can address display unevenness caused by a signal voltage drop at the first power supply terminal.

[0128] In this exemplary embodiment, the second storage circuit 24 can be used to stabilize the voltage of the first node N1. It should be understood that in other exemplary embodiments, the second storage circuit 24 may not be provided in the compensation circuit Cp. In addition, in other exemplary embodiments, the light emitting control circuit 31 and the second reset circuit 32 may also be integrated into the pixel driving circuit, that is, each pixel driving circuit may include a set of the light emitting control circuit 31 and the second reset circuit 32.

[0129] In this exemplary embodiment, the display panel may include a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and an electrode layer stacked in sequence, wherein an insulating layer may be provided between adjacent layers. As shown in Figures 4-16, Figure 4 is a structural layout of an exemplary embodiment of the display panel disclosed herein, Figure 5 is a structural layout of the active layer in Figure 4, Figure 6 is a structural layout of the first conductive layer in Figure 4, Figure 7 is a structural layout of the second conductive layer in Figure 4, Figure 8 is a structural layout of the third conductive layer in Figure 4, Figure 9 is a structural layout of the fourth conductive layer in Figure 4, Figure 10 is a structural layout of the fifth conductive layer in Figure 4, Figure 11 is a structural layout of the electrode layer in Figure 4, Figure 12 is a structural layout of the active layer and the first conductive layer in Figure 4, Figure 13 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in Figure 4, Figure 14 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figure 4, Figure 15 is a structural layout of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in Figure 4, and Figure 16 is a structural layout of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in Figure 4. The display panel may include a plurality of driving units Dpi distributed along row and column directions. The driving unit in the display panel differs from the driving unit shown in FIG. 2 in that the driving unit in this exemplary embodiment includes 2 rows and 6 columns of pixel driving circuits.

[0130] As shown in Figures 4, 5, and 12, the active layer may include a first active portion 41, a second active portion 42, a third active portion 43, a sixth active portion 46, a seventh active portion 47, an eighth active portion 48, a ninth active portion 49, a tenth active portion 410, an eleventh active portion 411, a twelfth active portion 412, a thirteenth active portion 413, a fourteenth active portion 414, a fifteenth active portion 415, and an active line 416. The first active portion 41 is used to form the channel region of the first transistor T1; the second active portion 42 is used to form the channel region of the second transistor T2; the third active portion 43 is used to form the channel region of the third transistor, wherein the third active portion 43 includes a first sub-active portion 431 and a second sub-active portion 432 connected to each other; the sixth active portion 46 is used to form the channel region of the driving transistor DT; the seventh active portion 47 is used to form the channel region of the analog transistor DTd; the eighth active portion 48 and the ninth active portion 49 are connected to both ends of the first active portion 41; the tenth active portion 410 and the active line 411 are connected to each other. The active line 416 is connected to both ends of the sixth active portion 46. The orthographic projection of the active line 416 on the substrate can extend along the row direction X. The sixth active portions 46 in the same row are connected to the same active line 416. The thirteenth active portion 413 is connected between the seventh active portion 47 and the second active portion 42. The eleventh active portion 411 is connected to the end of the seventh active portion 47 away from the second active portion 42. The twelfth active portion 412 is connected to the end of the second active portion 42 away from the seventh active portion 47. The fourteenth active portion 414 and the fifteenth active portion 415 are connected to both ends of the third active portion 43. The active layer can be formed of polycrystalline silicon material. Accordingly, the first transistor T1, the second transistor T2, the third transistor T3, the driving transistor DT, and the analog transistor DTd can be P-type low-temperature polycrystalline silicon thin film transistors.

[0131] As shown in Figures 4, 6, and 12, the first conductive layer may include a gate line 5G, a second gate portion 52, a third gate portion 53, a sixth gate portion 56, and a seventh gate portion 57. The orthographic projection of the gate line 5G on the substrate extends along the row direction X and covers the orthographic projection of the first active portion 41 on the substrate. Part of the structure of the gate line 5G is used to form the gate of the first transistor T1, and the gate line 5G can also provide a gate drive signal terminal. The orthographic projection of the sixth gate portion 56 on the substrate covers the orthographic projection of the sixth active portion 46 on the substrate. Part of the structure of the sixth gate portion 56 is used to form the gate of the driving transistor DT and the first electrode of the first capacitor C1. The orthographic projection of the second gate portion 52 on the substrate covers the orthographic projection of the second active portion 42 on the substrate. Part of the structure of the second gate portion 52 is used to form the gate of the second transistor T2. The orthographic projection of the third gate portion 53 on the substrate can overlap the orthographic projection of the third active portion 43 on the substrate. Part of the structure of the third gate portion 53 can be used to form the gate of the third transistor T3, wherein the third transistor T3 has a dual-gate structure and has a low off-leakage current. The orthographic projection of the seventh gate portion 57 on the substrate can overlap the orthographic projection of the seventh active portion 47 on the substrate. Part of the structure of the seventh gate portion 57 can be used to form the gate of the analog transistor DTd. Furthermore, the display panel can use the first conductive layer as a mask to perform a conductor process on the active layer, i.e., the area of ​​the active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first conductive layer forms a conductor structure.

[0132] As shown in Figures 4, 7, and 13, the second conductive layer may include: a first conductive portion 61, a second conductive portion 62, a third conductive portion 63, a fourth conductive portion 64, a power line VDD, an enable signal line EM, a reference signal line Vref, and a reset signal line Re. The orthographic projections of the power line VDD, the enable signal line EM, the reference signal line Vref, and the reset signal line Re on the substrate may all extend along the row direction X. The power line VDD is used to provide a first power supply terminal and can be connected to the eleventh active portion 411 through a via H to connect to the first electrode of the analog transistor DTd. In this exemplary embodiment, the black squares indicate the locations of the vias. The enable signal line EM is used to provide an enable signal terminal and can be connected to the second gate portion 52 through a via to connect to the gate of the second transistor T2. The reference signal line Vref is used to provide a reference signal terminal and can be connected to the fourteenth active portion 414 through a via to connect to the first electrode of the third transistor T3. The reset signal line Re is used to provide a reset signal terminal. The reset signal line Re can be connected to the third gate portion 53 through a via to connect the gate of the third transistor T3. The orthographic projection of the first conductive portion 61 on the base substrate intersects with the orthographic projection of the sixth gate portion 56 on the base substrate. The first conductive portion 61 can be used to form the second electrode of the first capacitor C1. The first conductive portions 61 in the same row of pixel driving circuits in the same driving unit can be connected to each other, and adjacent first conductive portions 61 in adjacent driving units in the row direction X are arranged at intervals. The second conductive portion 62 can be connected to the eighth active portion through a via to connect the first electrode of the first transistor. The third conductive portion 63 can be connected to the ninth active portion 49 and the sixth gate portion 56 through vias, respectively, to connect the second electrode of the first transistor T1 and the gate of the driving transistor. The fourth conductive portion 64 is connected to the seventh gate portion 57 and the thirteenth active portion 413 through vias, respectively, to connect the second electrode and the gate of the analog transistor DTd.

[0133] As shown in Figures 4, 8, and 14, the third conductive layer may include a first bridge portion 71, a second bridge portion 72, a third bridge portion 73, and a fourth bridge portion 74. The first bridge portion 71 may be connected to the twelfth active portion 412 and the first conductive portion 61 located in the two rows of pixel driving circuits through vias, respectively, to connect the second electrode of the second transistor T2 and the second electrode of the first capacitor C1. The second bridge portion 72 may be connected to the fifteenth active portion 415 and the first conductive portion 61 located in the two rows of pixel driving circuits through vias, respectively, to connect the second electrode of the third transistor T3 and the second electrode of the first capacitor C1. The third bridge portion 73 may be connected to the tenth active portion 410 through a via to connect the second electrode of the driving transistor DT. The fourth bridge portion 74 may be connected to the first conductive portion 61 that is not connected to the first bridge portion 71 or the second bridge portion 72 through vias. The fourth bridge portion 74 may enable the first conductive portions 61 at different positions to have the same or similar parasitic capacitances. It should be understood that in other exemplary embodiments, the third conductive layer may not be provided with the fourth bridge portion 74. The orthographic projections of the analog transistor DTd, the second transistor T2, and the third transistor T3 on the substrate may be located between the orthographic projections of the first bridge portion 71 and the orthographic projections of the second bridge portion 72 on the substrate.

[0134] As shown in Figures 4, 9, and 15, the fourth conductive layer may include a first shielding line 81 and a second shielding line 82, wherein the orthographic projection of the first shielding line 81 on the substrate extends along the row direction X, and the orthographic projection of the second shielding line 82 on the substrate extends along the column direction Y. The orthographic projection of the first shielding line 81 on the substrate and the orthographic projection of the second shielding line 82 on the substrate intersect. Each column of pixel driving circuits may be provided with a corresponding second shielding line 82, and each row of pixel driving circuits may be provided with a corresponding first shielding line 81. Multiple first shielding lines 81 and multiple second shielding lines 82 may form a grid structure, and the first shielding lines 81 and the second shielding lines 82 may be connected to the power line VDD. The first shielding lines 81 and the second shielding lines 82 of the grid structure may reduce the resistance of the power line itself. The first shielding line 81 and the second shielding line 82 may be connected to the power line VDD through vias located in a frame area outside the display area or at the edge of the display area. The orthographic projections of the first shielding line 81 and the second shielding line 82 on the substrate substrate may at least partially overlap with the orthographic projections of the equipotential structure of the second electrode of the first capacitor C1 on the substrate substrate. Portions of the first shielding line 81 and the second shielding line 82 may be used to form the first electrode of the second capacitor C2, and the second electrode of the first capacitor C1 may be reused as the second electrode of the second capacitor C2. For example, the orthographic projection of the second shielding line 82 on the substrate substrate may overlap with the orthographic projections of the first bridging portion 71 and the second bridging portion 72 on the substrate substrate. The orthographic projection of the first shielding line 81 on the substrate substrate may overlap with the orthographic projection of the first conductive portion 61 on the substrate substrate.

[0135] As shown in Figures 4, 10, and 16, the fifth conductive layer may include a data line Da and a fifth bridge portion 95. The orthographic projection of the data line Da on the substrate may extend along the column direction Y. The data line Da may be used to provide a data signal terminal. The data line Da may be connected to the second conductive portion 62 via a via to connect to the first electrode of the first transistor T1. The fifth bridge portion 95 may be connected to the third bridge portion 73 via a via to connect to the second electrode of the driving transistor.

[0136] As shown in Figures 4, 9, 10, and 16, the second shielding line 82 may include a first extension portion 821 and a second extension portion 822. The overlapping portion of the orthographic projection of the sixth gate portion 56 on the substrate and the orthographic projection of the data line Da on the substrate may overlap with the orthographic projection of the first extension portion 821 on the substrate, i.e., the first extension portion 821 shields the sixth gate portion 56 and the data line Da. Furthermore, the overlapping portion of the orthographic projection of the first conductive portion 61 on the substrate and the orthographic projection of the data line Da on the substrate may overlap with the orthographic projection of the first extension portion 821 on the substrate, i.e., the first extension portion 821 shields the first conductive portion 61 and the data line Da. The first extension portion 821 can shield the sixth gate portion 56 and the first conductive portion 61 from noise caused by the data line Da, thereby improving the stability of the gate voltage of the driving transistor. The orthographic projection of the second extension portion 822 on the substrate can be located between the orthographic projections of adjacent data lines Da on the substrate, that is, the orthographic projection of the second extension portion 822 on the substrate does not overlap with the orthographic projection of the data line Da on the substrate. This arrangement can reduce the parasitic capacitance of the data line Da, thereby improving the efficiency of writing data signals to the data line. In addition, the orthographic projection of the first bridge portion 71 on the substrate can overlap with the orthographic projection of one second extension portion 822 on the substrate, and the orthographic projection of the second bridge portion 72 on the substrate can overlap with the orthographic projection of another second extension portion 822 on the substrate. The second extension portion 822 can be used to form the first electrode of the second capacitor C.

[0137] As shown in Figures 4 and 11, the electrode layer may include multiple electrode portions: a first electrode portion R, a second electrode portion B, and a third electrode portion G. Each electrode portion may be connected to a fifth bridge portion 95 through a via to connect to the second electrode of the driving transistor DT. The first electrode portion R may be used to form the first electrode of a red light-emitting unit, the second electrode portion B may be used to form the first electrode of a blue light-emitting unit, and the third electrode portion G may be used to form the first electrode of a green light-emitting unit. In this exemplary embodiment, the light-emitting unit L may be a Real RGB distribution. For example, the first electrode portion R, the third electrode portion G, and the second electrode portion B may be alternately distributed in the row direction, and electrode portions of the same color may be located in the same column. As shown in Figure 4, the orthographic projection of the electrode portion on the base substrate is located between the orthographic projections of two adjacent data lines Da on the base substrate. On the one hand, this arrangement can avoid the influence of the data line Da on the flatness of the electrode portion, and on the other hand, this arrangement can reduce the noise influence of the data line Da on the electrode portion. The display panel may further include a pixel definition layer located on the side of the electrode layer facing away from the base substrate, wherein a pixel opening for forming a light-emitting unit is formed on the pixel definition layer, wherein the orthographic projection of the first electrode portion R on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate, the orthographic projection of the second electrode portion B on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate, and the orthographic projection of the third electrode portion G on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate.

[0138] FIG17 is a partial cross-sectional view of the display panel shown in FIG4 taken along dotted line AA. The display panel may further include a first insulating layer 102, a second insulating layer 103, a first dielectric layer 104, a passivation layer 105, a second dielectric layer 106, and a planarization layer 107. The substrate 101, active layer, first insulating layer 102, first conductive layer, second insulating layer 103, second conductive layer, first dielectric layer 104, third conductive layer, passivation layer 105, fourth conductive layer, second dielectric layer 106, fifth conductive layer, planarization layer 107, and electrode layer are stacked in sequence. The first insulating layer 102 and the second insulating layer 103 may be single-layer or multi-layer structures, and the material of the first insulating layer 102 and the second insulating layer 103 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 104 and the second dielectric layer 106 may be silicon nitride layers. The material of the planar layer 107 may be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The material of the passivation layer 105 may be silicon oxide. The base substrate 101 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer may be an inorganic material. The material of the first conductive layer and the second conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked layer. The third and fifth conductive layers may be made of metal materials, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate, or a titanium / aluminum / titanium laminate. The electrode layer may include an indium tin oxide layer or a silver layer. The sheet resistance of either the first or second conductive layer may be greater than the sheet resistance of either the fourth or third conductive layer.

[0139] This exemplary embodiment also provides another display panel, which may include: a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a fifth conductive layer, and an electrode layer stacked in sequence, wherein an insulating layer may be provided between adjacent layers. As shown in Figures 18-28, Figure 18 is a structural layout of an exemplary embodiment of the display panel disclosed herein, Figure 19 is a structural layout of the active layer in Figure 18, Figure 20 is a structural layout of the first conductive layer in Figure 18, Figure 21 is a structural layout of the second conductive layer in Figure 18, Figure 22 is a structural layout of the third conductive layer in Figure 18, Figure 23 is a structural layout of the fifth conductive layer in Figure 18, Figure 24 is a structural layout of the electrode layer in Figure 18, Figure 25 is a structural layout of the active layer and the first conductive layer in Figure 18, Figure 26 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in Figure 18, Figure 27 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figure 18, and Figure 28 is a structural layout of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fifth conductive layer in Figure 18. The display panel may include a plurality of driving units Dpi distributed along row and column directions. The driving unit in the display panel differs from the driving unit shown in FIG. 2 in that the driving unit in this exemplary embodiment includes 2 rows and 6 columns of pixel driving circuits.

[0140] As shown in Figures 18, 19, and 25, the active layer in this exemplary embodiment may have the same structure as the active layer in the display panel shown in Figure 4. The active layer may include a first active portion 41, a second active portion 42, a third active portion 43, a sixth active portion 46, a seventh active portion 47, an eighth active portion 48, a ninth active portion 49, a tenth active portion 410, an eleventh active portion 411, a twelfth active portion 412, a thirteenth active portion 413, a fourteenth active portion 414, a fifteenth active portion 415, and an active line 416. The active layer may be formed of polycrystalline silicon material. Accordingly, the first transistor T1, the second transistor T2, the third transistor T3, the driving transistor DT, and the analog transistor DTd may be P-type low-temperature polycrystalline silicon thin film transistors.

[0141] As shown in Figures 18, 20, and 25, the first conductive layer in this exemplary embodiment can have the same structure as the first conductive layer in the display panel shown in Figure 4. The first conductive layer can include gate lines 5G, a sixth gate portion 56, a second gate portion 52, a third gate portion 53, and a seventh gate portion 57. In this exemplary embodiment, the display panel can also use the first conductive layer as a mask to perform a conductor process on the active layer. That is, the area of ​​the active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first conductive layer forms a conductor structure.

[0142] As shown in Figures 18, 21, and 26, in this exemplary embodiment, the second conductive layer may include a first conductive portion 61, a second conductive portion 62, a third conductive portion 63, a power line VDD, an enable signal line EM, a reference signal line Vref, and a reset signal line Re. The second conductive layer in this exemplary embodiment differs from the second conductive layer in the display panel shown in Figure 4 only in that, in this exemplary embodiment, the orthographic projection of the power line VDD on the substrate has a uniform size in the column direction Y.

[0143] As shown in Figures 18, 22, and 27, the third conductive layer may include a first bridge portion 71, a second bridge portion 72, a third bridge portion 73, and a power connection line segment 7VDD1. The first bridge portion 71 may be connected to the twelfth active portion 412 and the first conductive portion 61 located in the two rows of pixel driving circuits through vias, respectively, to connect the second electrode of the second transistor T2 and the second electrode of the first capacitor C1. The second bridge portion 72 may be connected to the fifteenth active portion 415 and the first conductive portion 61 located in the two rows of pixel driving circuits through vias, respectively, to connect the second electrode of the third transistor T3 and the second electrode of the first capacitor C1. The third bridge portion 73 may be connected to the tenth active portion 410 through a via to connect the second electrode of the driving transistor DT. The orthographic projection of the power connection line segment 7VDD1 on the substrate may extend along the column direction Y, and the power connection line segment 7VDD1 may be connected to a power line VDD through a via. The orthographic projection of the same power connection line segment 7VDD1 on the substrate can overlap with the orthographic projections of the first conductive portions 61 in two adjacent rows of pixel drive circuits on the substrate, and these two adjacent rows of pixel drive circuits are respectively located in adjacent drive units in the column direction. Figure 22 only shows a partial structure of the complete power connection line segment 7VDD1. The power connection line segment 7VDD1 in the upper row of pixel drive circuits in Figure 22 only shows the lower half of the complete power connection line segment 7VDD1, and the power connection line segment 7VDD1 in the lower row of pixel drive circuits in Figure 22 only shows the upper half of the complete power connection line segment 7VDD1. The structure and connection relationship of the upper half of the power connection line segment 7VDD1 in the pixel driving circuit of the previous row in FIG22 can be the same as the upper half of the power connection line segment 7VDD1 in the pixel driving circuit of the next row in FIG22. Similarly, the structure and connection relationship of the lower half of the power connection line segment 7VDD1 in the pixel driving circuit of the next row in FIG22 can be the same as the lower half of the power connection line segment 7VDD1 in the pixel driving circuit of the previous row in FIG22. In addition, the orthographic projection of the power connection line segment 7VDD1 on the base substrate can overlap with the orthographic projection of the first conductive portion 61 on the base substrate. The power connection line segment 7VDD1 can be used to form the first electrode of the second capacitor.

[0144] As shown in Figures 18, 22, and 27, in a drive unit, the orthographic projection of the reference signal line Vref on the substrate is located between the orthographic projections of the enable signal line EM and the reset signal line Re on the substrate. The orthographic projection of the power connection line segment 7VDD1 on the substrate can be located between the orthographic projections of the reset signal line Re and the enable signal line EM in adjacent drive units in the column direction. Adjacent reset signal lines Re and enable signal lines EM may refer to reset signal lines Re and enable signal lines EM that are not interposed with other reset signal lines Re or enable signal lines EM. That is, the orthographic projection of the power connection line segment 7VDD1 on the substrate does not overlap with the orthographic projections of EM, the reset signal line Re, or the reference signal line Vref on the substrate. This arrangement reduces the parasitic capacitance of the enable signal line EM, the reset signal line Re, and the reference signal line Vref, thereby improving the charging efficiency of the enable signal line EM, the reset signal line Re, and the reference signal line Vref.

[0145] As shown in Figures 18, 23, and 28, the fifth conductive layer may include: a data line Da and a fifth bridge portion 95. The orthographic projection of the data line Da on the base substrate may extend along the column direction Y, and the data line Da may be used to provide a data signal terminal. The data line Da may be connected to the second conductive portion 62 via a via, thereby connecting to the first electrode of the first transistor T1. The overlapping portion of the orthographic projection of the sixth gate portion 56 on the base substrate and the orthographic projection of the data line Da on the base substrate may overlap with the orthographic projection of the power connection line segment 7VDD1 on the base substrate, i.e., the power connection line segment 7VDD1 is shielded between the sixth gate portion 56 and the data line Da, and / or the overlapping portion of the orthographic projection of the first conductive portion 61 on the base substrate and the orthographic projection of the data line Da on the base substrate may overlap with the orthographic projection of the power connection line segment 7VDD1 on the base substrate, i.e., the power connection line segment 7VDD1 is shielded between the first conductive portion 61 and the data line Da. The power connection line segment 7VDD1 can shield the noise influence of the data line Da on the sixth gate portion 56 and the first conductive portion 61 , thereby improving the stability of the gate voltage of the driving transistor.

[0146] As shown in Figures 18 and 24, the electrode layer may include multiple electrode portions: a first electrode portion R, a second electrode portion B, and a third electrode portion G. Each electrode portion may be connected to a fifth bridge portion 95 via a via to connect to the second electrode of the driving transistor DT. The first electrode portion R may be used to form the first electrode of a red light-emitting unit, the second electrode portion B may be used to form the first electrode of a blue light-emitting unit, and the third electrode portion G may be used to form the first electrode of a green light-emitting unit. In this exemplary embodiment, the light-emitting unit L may have a Real RGB distribution. For example, the first electrode portion R, the third electrode portion G, and the second electrode portion B may be alternately distributed in the row direction, and electrode portions of the same color may be located in the same column. As shown in Figure 18, the orthographic projection of the electrode portion on the base substrate is located between the orthographic projections of two adjacent data lines Da on the base substrate. On the one hand, this arrangement can avoid the influence of the data line Da on the flatness of the electrode portion, and on the other hand, this arrangement can reduce the noise impact of the data line Da on the electrode portion. The display panel may further include a pixel definition layer located on the side of the electrode layer facing away from the base substrate, wherein a pixel opening for forming a light-emitting unit is formed on the pixel definition layer, wherein the orthographic projection of the first electrode portion R on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate, the orthographic projection of the second electrode portion B on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate, and the orthographic projection of the third electrode portion G on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate.

[0147] FIG29 is a partial cross-sectional view of the display panel shown in FIG18 taken along dotted line BB. The display panel may further include a first insulating layer 102, a second insulating layer 103, a first dielectric layer 104, a second dielectric layer 106, and a planar layer 107. The substrate 101, active layer, first insulating layer 102, first conductive layer, second insulating layer 103, second conductive layer, first dielectric layer 104, third conductive layer, second dielectric layer 106, fifth conductive layer, planar layer 107, and electrode layer are stacked in sequence. The first insulating layer 102 and the second insulating layer 103 may be a single-layer structure or a multi-layer structure, and the material of the first insulating layer 102 and the second insulating layer 103 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 104 and the second dielectric layer 106 may be silicon nitride layers. The material of the planar layer 107 may be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The base substrate 101 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer may be an inorganic material. The material of the first and second conductive layers may be molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate, etc. The material of the third and fifth conductive layers may be a metal material, such as molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate, etc., or a titanium / aluminum / titanium laminate. The electrode layer may include an indium tin oxide layer and a silver layer. The square resistance of any one of the first conductive layer and the second conductive layer may be greater than the square resistance of any one of the fourth conductive layer and the third conductive layer.

[0148] Figure 30 shows the structural layout of another exemplary embodiment of a display panel according to the present disclosure. Unlike the display panel shown in Figure 18 , the power connection line segments 7VDD1 distributed along the column direction Y in the display panel shown in Figure 30 are interconnected to form power connection lines 7VDD. Power connection lines 7VDD can form a grid structure with power line VDD to reduce the power line's inherent resistance.

[0149] As shown in Figures 31-37, Figure 31 is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein. Figure 31 shows a schematic structural diagram of the fourth transistor T4 and the fifth transistor T5 in Figure 2. The structure of the fourth transistor and the fifth transistor shown in Figure 31 can be applied to the display panels shown in Figures 4, 18, and 30. In particular, two groups of fourth transistors and fifth transistors can be provided for each row of pixel driving circuits, and the two groups of fourth transistors and fifth transistors can be respectively located on both sides of the pixel driving circuit row in the row direction X. Figure 31 only shows the structure of the fourth transistor and the fifth transistor on one side of the pixel driving circuit row in the row direction X. Figure 32 is a structural layout diagram of the active layer in Figure 31, Figure 33 is a structural layout diagram of the first conductive layer in Figure 31, Figure 34 is a structural layout diagram of the second conductive layer in Figure 31, Figure 35 is a structural layout diagram of the third conductive layer in Figure 31, Figure 36 is a structural layout diagram of the active layer and the first conductive layer in Figure 31, and Figure 37 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in Figure 31.

[0150] As shown in Figures 31, 32, and 36, the active layer may further include a fourth active portion 44, a fifth active portion 45, an eighteenth active portion 418, and a nineteenth active portion 419. The two active lines 416 in Figure 32 are two active lines in the same row of drive units. The fourth active portion 44 may be used to form the channel region of the fourth transistor. The fifth active portion 45 may be used to form the channel region of the fifth transistor T5. The fifth active portion 45 may include a third sub-active portion 451 and a fourth sub-active portion 452. The fifth active portion 45 on the same side of two rows of pixel drive circuits in the same row of drive units may share the third sub-active portion. The eighteenth active portion 418 is connected to the side of the fourth active portion 44 away from the fifth active portion 45, and the nineteenth active portion 419 is connected to the side of the fifth active portion 45 away from the fourth active portion 44.

[0151] As shown in Figures 31, 33, and 36, the first conductive layer may further include a fifth gate portion 5Re, a first transition portion 521, and a fourth gate portion 5EM. The orthographic projection of the fourth gate portion 5EM on the base substrate overlaps the orthographic projection of the fourth active portion 44 on the base substrate, and at least a portion of the fourth gate portion 5EM forms the gate of the fourth transistor T4. The orthographic projection of the fifth gate portion 5Re on the base substrate overlaps the orthographic projection of the fifth active portion 45 on the base substrate, and at least a portion of the fifth gate portion 5Re forms the gate of the fifth transistor T5. The first transition portion 521 is used to provide an enable signal required to enable the signal line.

[0152] As shown in Figures 31, 34, and 37, the second conductive layer may further include a first connection portion EM1, a second connection portion Vref2, and a third connection portion Re3. The enable signal line EM, reference signal line Vref, and reset signal line Re shown in Figure 34 are the enable signal line EM, reference signal line Vref, and reset signal line Re in the same row drive unit. The first connection portion EM1 connects to the enable signal line EM, and the first connection portion EM1 may be connected to the fourth gate portion 5EM via a via. The second connection portion Vref2 connects to the reference signal line Vref. The third connection portion Re3 connects to the reset signal line Re, and the third connection portion Re3 is connected to the fifth gate portion 5Re via a via.

[0153] As shown in Figures 31 and 35, the third conductive layer can include a seventh bridge portion 77, an initial signal line Vinit, a first power extension line VDDx, and a reference signal extension line Vrefx. The seventh bridge portion 77 can be connected to the first transfer portion 521 and the fourth gate portion 5EM via vias. The orthographic projections of the initial signal line Vinit, the first power extension line VDDx, and the reference signal extension line Vrefx on the base substrate can all extend along the column direction Y. The initial signal line Vinit can provide an initial signal terminal. The initial signal line Vinit can be connected to the nineteenth active portion 419 via a via to connect the first electrode of the fifth transistor to the initial signal terminal. The first power extension line VDDx can be connected to the power line VDD, and the first power extension line VDDx can be connected to the eighteenth active portion 418 via a via to connect the first electrode of the fourth transistor to the first power terminal. The reference signal extension line Vrefx can be connected to the second connection portion Vref2 via a via to connect to the reference signal line Vref.

[0154] This exemplary embodiment also provides another display panel, as shown in Figures 38-50, Figure 38 is a structural layout of an exemplary embodiment of the display panel disclosed in the present invention, Figure 39 is a structural layout of the active layer in Figure 38, Figure 40 is a structural layout of the first conductive layer in Figure 38, Figure 41 is a structural layout of the second conductive layer in Figure 38, Figure 42 is a structural layout of the third conductive layer in Figure 38, Figure 43 is a structural layout of the fourth conductive layer in Figure 38, Figure 44 is a structural layout of the fifth conductive layer in Figure 38, and Figure 45 is a structural layout of the electrode layer in Figure 38. FIG46 is a structural layout diagram of the active layer and the first conductive layer in FIG38 , FIG47 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG38 , FIG48 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG38 , FIG49 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in FIG38 , and FIG50 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG38 . The display panel may include a plurality of drive units Dpi distributed along row and column directions. The drive unit in the display panel differs from the drive unit shown in FIG2 only in that the drive unit in this exemplary embodiment includes 2 rows and 6 columns of pixel drive circuits.

[0155] As shown in Figures 38, 39, and 46, the active layer may include a first active portion 41, a second active portion 42, a third active portion 43, a sixth active portion 46, a seventh active portion 47, an eighth active portion 48, a ninth active portion 49, a tenth active portion 410, an eleventh active portion 411, a twelfth active portion 412, a thirteenth active portion 413, a fourteenth active portion 414, a fifteenth active portion 415, and an active line 416. The first active portion 41 is used to form the channel region of the first transistor T1; the second active portion 42 is used to form the channel region of the second transistor T2; the third active portion 43 is used to form the channel region of the third transistor, wherein the third active portion 43 includes a first sub-active portion 431 and a second sub-active portion 432 connected to each other; the sixth active portion 46 is used to form the channel region of the driving transistor DT; the seventh active portion 47 is used to form the channel region of the analog transistor DTd; the eighth active portion 48 and the ninth active portion 49 are connected to both ends of the first active portion 41; the tenth active portion 410 and the active line 411 are connected to each other. The active line 416 is connected to both ends of the sixth active portion 46. The orthographic projection of the active line 416 on the substrate can extend along the row direction X. The sixth active portions 46 in the same row are connected to the same active line 416. The thirteenth active portion 413 is connected between the seventh active portion 47 and the second active portion 42. The eleventh active portion 411 is connected to the end of the seventh active portion 47 away from the second active portion 42. The twelfth active portion 412 is connected to the end of the second active portion 42 away from the seventh active portion 47. The fourteenth active portion 414 and the fifteenth active portion 415 are connected to both ends of the third active portion 43. The active layer can be formed of polycrystalline silicon material. Accordingly, the first transistor T1, the second transistor T2, the third transistor T3, the driving transistor DT, and the analog transistor DTd can be P-type low-temperature polycrystalline silicon thin film transistors.

[0156] As shown in Figures 38, 40, and 46, the first conductive layer may include a gate line 5G, a second gate portion 52, a third gate portion 53, a sixth gate portion 56, and a seventh gate portion 57. The orthographic projection of the gate line 5G on the substrate extends along the row direction X and covers the orthographic projection of the first active portion 41 on the substrate. A portion of the gate line 5G is used to form the gate of the first transistor T1, and the gate line 5G may also be used to provide a gate drive signal terminal. The orthographic projection of the sixth gate portion 56 on the substrate covers the orthographic projection of the sixth active portion 46 on the substrate. A portion of the sixth gate portion 56 is used to form the gate of the drive transistor DT and the first electrode of the first capacitor C1. The orthographic projection of the second gate portion 52 on the substrate covers the orthographic projection of the second active portion 42 on the substrate. A portion of the second gate portion 52 is used to form the gate of the second transistor T2. The orthographic projection of the third gate portion 53 on the substrate can overlap the orthographic projection of the third active portion 43 on the substrate. Part of the structure of the third gate portion 53 can be used to form the gate of the third transistor T3, wherein the third transistor T3 has a dual-gate structure and has a low off-leakage current. The orthographic projection of the seventh gate portion 57 on the substrate can overlap the orthographic projection of the seventh active portion 47 on the substrate. Part of the structure of the seventh gate portion 57 can be used to form the gate of the analog transistor DTd. Furthermore, the display panel can use the first conductive layer as a mask to perform a conductor process on the active layer, i.e., the area of ​​the active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first conductive layer forms a conductor structure.

[0157] As shown in Figures 38, 41, and 47, the second conductive layer may include: a first conductive portion 61, a second conductive portion 62, a third conductive portion 63, a fourth conductive portion 64, a fifth conductive portion 65, a sixth conductive portion 66, a first bridge portion 611, and a second bridge portion 612. The orthographic projection of the first conductive portion 61 on the substrate intersects with the orthographic projection of the sixth gate portion 56 on the substrate, and the first conductive portion 61 may be used to form the second electrode of the first capacitor C1. The first conductive portions 61 in the same row of pixel driving circuits in the same driving unit may be connected to each other, and adjacent first conductive portions 61 in adjacent driving units in the row direction X may be spaced apart. The second conductive portion 62 may be connected to the eighth active portion through a via to connect the first electrode of the first transistor. The third conductive portion 63 may be connected to the ninth active portion 49 and the sixth gate portion 56 through vias, respectively, to connect the second electrode of the first transistor T1 and the gate of the driving transistor. The fourth conductive portion 64 is connected to the seventh gate portion 57 and the thirteenth active portion 413 through vias, respectively, to connect the second electrode and the gate of the analog transistor DTd. The fifth conductive portion 65 can be connected to the fourteenth active portion 414 through a via to connect the first electrode of the third transistor T3. The sixth conductive portion 66 can be connected to the eleventh active portion 411 through a via to connect the first electrode of the analog transistor DTd. The first bridge portion 611 can be connected to the twelfth active portion 412 through a via, and connects the first conductive portion 61 located in the two rows of pixel driving circuits to connect the second electrode of the second transistor T2 and the second electrode of the first capacitor C1. The second bridge portion 612 can be connected to the fifteenth active portion 415 through a via, and connects the first conductive portion 61 located in the two rows of pixel driving circuits to connect the second electrode of the third transistor T3 and the second electrode of the first capacitor C1.

[0158] As shown in Figures 38, 42, and 48, the third conductive layer may include a third bridge portion 73, a sixth bridge portion 76, a seventh conductive portion 79, an enable signal line EM, a reference signal line Vref, and a reset signal line Re. The third bridge portion 73 may be connected to the tenth active portion 410 via a via to connect to the second electrode of the driving transistor DT. The sixth bridge portion 76 may be connected to the sixth conductive portion 66 via a via to connect to the first electrode of the analog transistor DTd. The orthographic projections of the enable signal line EM, the reference signal line Vref, and the reset signal line Re on the substrate may all extend along the row direction X. The enable signal line EM is used to provide an enable signal terminal and may be connected to the second gate portion 52 via a via to connect to the gate of the second transistor T2. The reference signal line Vref is used to provide a reference signal terminal and may be connected to the fifth conductive portion 65 via a via to connect to the first electrode of the third transistor T3. The reset signal line Re is used to provide a reset signal terminal. The reset signal line Re can be connected to the third gate portion 53 through a via to connect to the gate of the third transistor T3. The first conductive line 75 can be connected to the active line 416 through a plurality of vias distributed in the row direction X to connect to the first electrode of the driving transistor DT. The first conductive line 75 can reduce the resistance of the active line 416, thereby reducing the voltage drop of the signal on the active line 416. The seventh conductive portion 79 can be connected to the first conductive portion 61 through a via. In this exemplary embodiment, the square resistance of the second conductive layer is greater than the square resistance of the third conductive layer. In this exemplary embodiment, the enable signal line EM, the reference signal line Vref, and the reset signal line Re are arranged in the third conductive layer to reduce the resistance of the above-mentioned signal lines, thereby improving the efficiency of the above-mentioned signal lines in transmitting signals.

[0159] As shown in Figures 38, 43, and 49, the fourth conductive layer may include a first shielding line 81, a second shielding line 82, and a power line VDD, wherein the orthographic projection of the power line VDD on the substrate and the orthographic projection of the first shielding line 81 on the substrate may extend along the row direction X, and the orthographic projection of the second shielding line 82 on the substrate may extend along the column direction Y. The orthographic projections of the first shielding line 81, the power line VDD, and the orthographic projections of the second shielding line 82 on the substrate intersect. Each column of pixel drive circuits may be provided with a corresponding second shielding line 82, each row of pixel drive circuits may be provided with a corresponding first shielding line 81, and each row of drive units may be provided with a corresponding power line VDD. Multiple first shielding lines 81, multiple power lines VDD, and multiple second shielding lines 82 may form a grid structure. The power lines in the grid structure have a relatively low resistance, thereby reducing the voltage drop of the power signal on the power lines. The orthographic projections of the first shielding line 81 and the second shielding line 82 on the substrate substrate can at least partially overlap with the orthographic projections of the equipotential structure of the second electrode of the first capacitor C1 on the substrate substrate. Partial structures of the first shielding line 81 and the second shielding line 82 can be used to form the first electrode of the second capacitor C2, and the second electrode of the first capacitor C1 can be reused as the second electrode of the second capacitor C2. For example, the orthographic projection of the second shielding line 82 on the substrate substrate can overlap with the orthographic projection of the seventh conductive portion 79 on the substrate substrate, and the orthographic projection of the first shielding line 81 on the substrate substrate can overlap with the orthographic projection of the first conductive portion 61 on the substrate substrate. The power line VDD can be used to provide a first power supply terminal. The power line VDD can be connected to the sixth bridge portion 76 through a via to connect the first electrode of the analog transistor DTd and the first power supply terminal.

[0160] As shown in Figures 38, 44, and 50, the fifth conductive layer may include a data line Da and a fifth bridge portion 95. The orthographic projection of the data line Da on the substrate may extend along the column direction Y. The data line Da may be used to provide a data signal terminal. The data line Da may be connected to the second conductive portion 62 via a via to connect to the first electrode of the first transistor T1. The fifth bridge portion 95 may be connected to the third bridge portion 73 via a via to connect to the second electrode of the driving transistor.

[0161] As shown in Figures 38, 43, 44, and 50, the second shielding line 82 may include a first extension 821 and a second extension 822. The overlapping portion of the orthographic projection of the seventh conductive portion 79 on the substrate and the orthographic projection of the data line Da on the substrate overlaps with the orthographic projection of the first extension 821 on the substrate. That is, the first extension 821 shields between the seventh conductive portion 79 and the data line Da to shield the noise impact of the data line Da on the seventh conductive portion 79, thereby improving the stability of the gate voltage of the driving transistor. The orthographic projection of the second extension 822 on the substrate can be located between the orthographic projections of adjacent data lines Da on the substrate, that is, the orthographic projection of the second extension 822 on the substrate does not overlap with the orthographic projection of the data line Da on the substrate. This arrangement can reduce the parasitic capacitance of the data line Da, thereby improving the efficiency of writing data signals to the data line.

[0162] As shown in Figures 38 and 45, the electrode layer may include multiple electrode portions: a first electrode portion R, a second electrode portion B, and a third electrode portion G. Each electrode portion may be connected to a fifth bridge portion 95 via a via to connect to the second electrode of the driving transistor DT. The first electrode portion R may be used to form the first electrode of a red light-emitting unit, the second electrode portion B may be used to form the first electrode of a blue light-emitting unit, and the third electrode portion G may be used to form the first electrode of a green light-emitting unit. In this exemplary embodiment, the light-emitting units L may have a Real RGB distribution. For example, the first electrode portion R, the third electrode portion G, and the second electrode portion B may be alternately distributed in the row direction, with electrode portions of the same color located in the same column. As shown in Figure 38, the orthographic projection of the electrode portion on the base substrate is located between the orthographic projections of two adjacent data lines Da on the base substrate. On the one hand, this arrangement can prevent the data lines Da from affecting the flatness of the electrode portion, and on the other hand, this arrangement can reduce the noise impact of the data lines Da on the electrode portion. The display panel may further include a pixel definition layer located on the side of the electrode layer facing away from the base substrate, wherein a pixel opening for forming a light-emitting unit is formed on the pixel definition layer, wherein the orthographic projection of the first electrode portion R on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate, the orthographic projection of the second electrode portion B on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate, and the orthographic projection of the third electrode portion G on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate.

[0163] FIG51 is a partial cross-sectional view of the display panel shown in FIG38 taken along dotted line CC. The display panel may further include a first insulating layer 102, a second insulating layer 103, a first dielectric layer 104, a passivation layer 105, a second dielectric layer 106, and a planarization layer 107. The substrate 101, active layer, first insulating layer 102, first conductive layer, second insulating layer 103, second conductive layer, first dielectric layer 104, third conductive layer, passivation layer 105, fourth conductive layer, second dielectric layer 106, fifth conductive layer, planarization layer 107, and electrode layer are stacked in sequence. The first insulating layer 102 and the second insulating layer 103 may be single-layer or multi-layer structures, and the material of the first insulating layer 102 and the second insulating layer 103 may be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 104 and the second dielectric layer 106 may be silicon nitride layers. The material of the planar layer 107 may be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The material of the passivation layer 105 may be silicon oxide. The base substrate 101 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer may be an inorganic material. The material of the first conductive layer and the second conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked layer. The third and fifth conductive layers may be made of metal materials, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate, or a titanium / aluminum / titanium laminate. The electrode layer may include an indium tin oxide layer or a silver layer. The sheet resistance of either the first or second conductive layer may be greater than the sheet resistance of either the fourth or third conductive layer.

[0164] As shown in Figures 52-58, Figure 52 is a partial structural layout diagram of an exemplary embodiment of the display panel disclosed herein. Figure 52 shows a schematic structural diagram of the fourth transistor T4 and the fifth transistor T5 in Figure 2. The structure of the fourth transistor and the fifth transistor shown in Figure 52 can be a partial structure of the display panel shown in Figure 38. In particular, two groups of fourth transistors and fifth transistors can be provided for each row of pixel drive circuits, and the two groups of fourth transistors and fifth transistors can be respectively located on both sides of the pixel drive circuit row in the row direction X. Figure 52 only shows the structure of the fourth transistor and the fifth transistor on one side of the pixel drive circuit row in the row direction X. Figure 53 is a structural layout diagram of the active layer in Figure 52, Figure 54 is a structural layout diagram of the first conductive layer in Figure 52, Figure 55 is a structural layout diagram of the third conductive layer in Figure 52, Figure 56 is a structural layout diagram of the fourth conductive layer in Figure 52, Figure 57 is a structural layout diagram of the active layer and the first conductive layer in Figure 52, and Figure 58 is a structural layout diagram of the active layer, the first conductive layer, and the third conductive layer in Figure 52.

[0165] As shown in Figures 52, 53, and 57, the active layer may include a fourth active portion 44, a fifth active portion 45, an eighteenth active portion 418, and a nineteenth active portion 419. The two active lines 416 in Figure 52 are two active lines in the same row of drive units. The fourth active portion 44 may be used to form the channel region of the fourth transistor. The fifth active portion 45 may be used to form the channel region of the fifth transistor T5. The fifth active portion 45 may include a third sub-active portion 451 and a fourth sub-active portion 452. The fifth active portions 45 on the same side of two rows of pixel drive circuits in the same row of drive units share the third sub-active portion. The eighteenth active portion 418 is connected to the side of the fourth active portion 44 away from the fifth active portion 45, and the nineteenth active portion 419 is connected to the side of the fifth active portion 45 away from the fourth active portion 44.

[0166] As shown in Figures 52, 54, and 57, the first conductive layer may further include a fifth gate portion 5Re, a first transition portion 521, and a fourth gate portion 5EM. The orthographic projection of the fourth gate portion 5EM on the base substrate overlaps the orthographic projection of the fourth active portion 44 on the base substrate, and at least a portion of the fourth gate portion 5EM forms the gate of the fourth transistor T4. The orthographic projection of the fifth gate portion 5Re on the base substrate overlaps the orthographic projection of the fifth active portion 45 on the base substrate, and at least a portion of the fifth gate portion 5Re forms the gate of the fifth transistor T5. The first transition portion 521 is used to provide an enable signal required to enable the signal line.

[0167] As shown in Figures 52, 55, and 58, the third conductive layer can include a seventh bridge portion 77, an initial signal line Vinit, a first power extension line VDDx, a reference signal extension line Vrefx, a first connection portion EM1, a second connection portion Vref2, and a third connection portion Re3. The enable signal line EM, reference signal line Vref, and reset signal line Re shown in Figure 55 are the enable signal line EM, reference signal line Vref, and reset signal line Re in the same row driver unit. The first connection portion EM1 is connected to the enable signal line EM and is connected to the fourth gate portion 5EM through a via to connect the gate of the fourth transistor to the enable signal terminal. The second connection portion Vref2 is connected between the reference signal line Vref and the reference signal extension line Vrefx. The third connection portion Re3 is connected to the reset signal line Re and is connected to the fifth gate portion 5Re through a via to connect the gate of the fifth transistor to the reset signal terminal. The seventh bridge portion 77 can be connected to the first transfer portion 521 and the fourth gate portion 5EM through vias, respectively. The orthographic projection of the initial signal line Vinit on the substrate, the orthographic projection of the first power extension line VDDx on the substrate, and the orthographic projection of the reference signal extension line Vrefx on the substrate can all extend along the column direction Y. The initial signal line Vinit can provide an initial signal terminal. The initial signal line Vinit can be connected to the nineteenth active portion 419 via a via to connect the first electrode of the fifth transistor to the initial signal terminal. The first power extension line VDDx can be connected to the eighteenth active portion 418 via a via to connect the first electrode of the fourth transistor to the first power terminal.

[0168] As shown in Figures 52 and 56, the fourth conductive layer may include a second power extension line VDDy. The two first shielding lines 81 in Figure 52 are two first shielding lines in the same driving unit. The second power extension line VDDy can connect the two first shielding lines 81. The second power extension line VDDy can be connected to the first power extension line VDDx through a via so that the analog transistor DTd and the fourth transistor T4 are connected to the first power end.

[0169] This exemplary embodiment also provides another display panel, which may include a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and an electrode layer stacked in sequence. An insulating layer may be provided between the adjacent layers. As shown in Figures 59-71, Figure 59 is a structural layout of an exemplary embodiment of the display panel disclosed herein, Figure 60 is a structural layout of the active layer in Figure 59, Figure 61 is a structural layout of the first conductive layer in Figure 59, Figure 62 is a structural layout of the second conductive layer in Figure 59, Figure 63 is a structural layout of the third conductive layer in Figure 59, Figure 64 is a structural layout of the fourth conductive layer in Figure 59, Figure 65 is a structural layout of the fifth conductive layer in Figure 59, Figure 66 is a structural layout of the electrode layer in Figure 59, and Figure 67 is a structural layout of the electrode layer in Figure 59. FIG59 is a structural layout diagram of the active layer and the first conductive layer in FIG59 ; FIG68 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG59 ; FIG69 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG59 ; FIG70 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in FIG59 ; and FIG71 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG59 . The display panel may include a plurality of drive units Dpi distributed along the row and column directions. The drive unit in this display panel differs from the drive unit shown in FIG2 in that the drive unit in this exemplary embodiment includes 12 columns and 4 rows of pixel drive circuits. As shown in FIG71 , the same drive unit includes two sub-drive units: a first sub-drive unit Dpi1 and a second sub-drive unit Dpi2. The two sub-drive units are distributed in the column direction Y, and the first sub-drive unit Dpi1 and the second sub-drive unit Dpi2 each include two adjacent rows and 12 columns of pixel drive circuits. Each row of sub-driving units Dpix may be provided with two sets of fourth transistors T4 and fifth transistors T5, and the two sets of fourth transistors T4 and fifth transistors T5 are respectively provided on both sides of a row of sub-driving units Dpix in the row direction X. In this exemplary embodiment, FIG. 59 only shows a set of fourth transistors and fifth transistors on one side of a row of sub-driving units Dpix in the row direction X.

[0170] As shown in Figures 59, 60, and 67, the active layer may include a first active portion 41, a second active portion 42, a third active portion 43, a sixth active portion 46, a seventh active portion 47, an eighth active portion 48, a ninth active portion 49, a tenth active portion 410, an eleventh active portion 411, a twelfth active portion 412, a thirteenth active portion 413, a fourteenth active portion 414, a fifteenth active portion 415, and an active line 416. The first active portion 41 is used to form the channel region of the first transistor T1; the second active portion 42 is used to form the channel region of the second transistor T2, wherein the second active portion 42 includes a first sub-active portion 421 and a second sub-active portion 422 connected to each other; the third active portion 43 is used to form the channel region of the third transistor; the sixth active portion 46 is used to form the channel region of the driving transistor DT; the seventh active portion 47 is used to form the channel region of the analog transistor DTd; the eighth active portion 48 and the ninth active portion 49 are used to form the channel region of the analog transistor DTd. The active layer 410 and the active line 416 are connected to both ends of the sixth active portion 46. The orthographic projection of the active line 416 on the substrate can extend along the row direction X. Sixth active portions 46 located in two rows in the same sub-driving unit can be connected to the same active line 416. The thirteenth active portion 413 is connected between the seventh active portion 47 and the second active portion 42. The eleventh active portion 411 is connected to the end of the seventh active portion 47 away from the second active portion 42. The twelfth active portion 412 is connected to the end of the second active portion 42 away from the seventh active portion 47. The fourteenth active portion 414 and the fifteenth active portion 415 are connected to both ends of the third active portion 43. The active layer may further include a fourth active portion 44, a fifth active portion 45, an eighteenth active portion 418, and a nineteenth active portion 419. The fourth active portion 44 and the fifth active portion 45 may be connected to the active line 416. The fourth active portion 44 may be used to form the channel region of the fourth transistor. The fifth active portion 45 may be used to form the channel region of the fifth transistor T5. The fifth active portion 45 may include a third sub-active portion 451 and a fourth sub-active portion 452. The eighteenth active portion 418 is connected to a side of the fourth active portion 44 away from the fifth active portion 45, and the nineteenth active portion 419 is connected to a side of the fifth active portion 45 away from the fourth active portion 44. The active layer may be formed of polycrystalline silicon material. Accordingly, the first transistor T1, the second transistor T2, the third transistor T3, the driving transistor DT, the analog transistor DTd, the fourth transistor T4, and the fifth transistor T5 may be P-type low-temperature polycrystalline silicon thin film transistors.

[0171] As shown in Figures 59, 61, and 67, the first conductive layer may include a gate line 5G, a second gate portion 52, a third gate portion 53, a sixth gate portion 56, and a seventh gate portion 57. The orthographic projection of the gate line 5G on the substrate extends along the row direction X and covers the orthographic projection of the first active portion 41 on the substrate. A portion of the gate line 5G is used to form the gate of the first transistor T1, and the gate line 5G may also be used to provide a gate drive signal terminal. The orthographic projection of the sixth gate portion 56 on the substrate covers the orthographic projection of the sixth active portion 46 on the substrate. A portion of the sixth gate portion 56 is used to form the gate of the drive transistor DT and the first electrode of the first capacitor C1. The orthographic projection of the second gate portion 52 on the substrate covers the orthographic projection of the second active portion 42 on the substrate. A portion of the second gate portion 52 is used to form the gate of the second transistor T2. The orthographic projection of the third gate portion 53 on the substrate can overlap the orthographic projection of the third active portion 43 on the substrate. Part of the structure of the third gate portion 53 can be used to form the gate of the third transistor T3. The third transistor T3 has a dual-gate structure, and the dual-gate structure of the third transistor T3 has a low off-leakage current. The orthographic projection of the seventh gate portion 57 on the substrate can overlap the orthographic projection of the seventh active portion 47 on the substrate. Part of the structure of the seventh gate portion 57 can be used to form the gate of the analog transistor DTd. The first conductive layer may further include a fourth gate portion 5EM and a fifth gate portion 5Re. The orthographic projection of the fourth gate portion 5EM on the substrate overlaps the orthographic projection of the fourth active portion 44 on the substrate. At least a portion of the structure of the fourth gate portion 5EM forms the gate of the fourth transistor T4. The orthographic projection of the fifth gate portion 5Re on the substrate overlaps the orthographic projection of the fifth active portion 45 on the substrate. At least a portion of the structure of the fifth gate portion 5Re forms the gate of the fifth transistor T5. In addition, the display panel can use the first conductive layer as a mask to conduct conductor processing on the active layer, that is, the area of ​​the active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first conductive layer forms a conductor structure.

[0172] As shown in Figures 59, 62, and 68, the second conductive layer may include: a first conductive portion 61, a second conductive portion 62, a third conductive portion 63, a fourth conductive portion 64, an enable signal line EM, a reference signal line Vref, and a reset signal line Re. The orthographic projections of the enable signal line EM, the reference signal line Vref, and the reset signal line Re on the substrate can all extend along the row direction X. The enable signal line EM is used to provide an enable signal terminal. The enable signal line EM can be connected to the second gate portion 52 through a via to connect to the gate of the second transistor T2. The reference signal line Vref is used to provide a reference signal terminal. The reference signal line Vref can be connected to the fourteenth active portion 414 through a via to connect to the first electrode of the third transistor T3. The reset signal line Re is used to provide a reset signal terminal. The reset signal line Re can be connected to the third gate portion 53 through a via to connect to the gate of the third transistor T3. The orthographic projection of the first conductive portion 61 on the substrate intersects the orthographic projection of the sixth gate portion 56 on the substrate, and the first conductive portion 61 can be used to form the second electrode of the first capacitor C1. The first conductive portions 61 in the same row of pixel drive circuits in the same drive unit can be interconnected, and adjacent first conductive portions 61 in adjacent drive units in the row direction X are spaced apart. The first conductive portions 61 in different rows of pixel drive circuits in the same sub-drive unit can also be interconnected. The second conductive portion 62 can be connected to the eighth active portion via a via to connect the first electrode of the first transistor. The third conductive portion 63 can be connected to the ninth active portion 49 and the sixth gate portion 56 via vias to connect the second electrode of the first transistor T1 and the gate of the drive transistor. The fourth conductive portion 64 can be connected to the seventh gate portion 57 and the thirteenth active portion 413 via vias to connect the second electrode and gate of the analog transistor DTd. The second conductive layer may further include a first connecting portion EM1, a second connecting portion Vref2, a third connecting portion Re3, and a second transition portion 622. The first connection part EM1 is connected to the enable signal line EM, the second connection part Vref2 is connected to the reference signal line Vref, the third connection part Re3 is connected to the reset signal line Re, and the second transfer part 622 can be connected to the fifth gate part 5Re through a via hole. The second transfer part 622 can be used to provide the reset signal required by the reset signal line.

[0173] As shown in Figures 59, 63, and 69, the third conductive layer may include a first bridge portion 71, a second bridge portion 72, a third bridge portion 73, a first conductive line 75, a seventh conductive portion 79, and a sixth bridge portion 76. The seventh conductive portion 79 may be connected to the first conductive portion 61 via a via. The first bridge portion 71 may be connected to the twelfth active portion 412 and the seventh conductive portion 79 located in different sub-drive units within the same drive unit via vias, thereby connecting the second electrode of the second transistor T2 and the second electrode of the first capacitor C1. The second bridge portion 72 may be connected to the fifteenth active portion 415 and the seventh conductive portion 79 located in different sub-drive units within the same drive unit via vias, thereby connecting the second electrode of the third transistor T3 and the second electrode of the first capacitor C1. The third bridge portion 73 may be connected to the tenth active portion 410 via a via, thereby connecting the second electrode of the driving transistor DT. The sixth bridge portion 76 may be connected to the eleventh active portion 411 via a via, thereby connecting the first electrode of the analog transistor DTd. The first conductive line 75 can be connected to the active line 416 via multiple vias distributed in the row direction X to reduce the voltage drop of the signal on the active line 416. The third conductive layer may also include a seventh bridge portion 77, an eighth bridge portion 78, an initial signal line Vinit, a first power extension line VDDx, and a reference signal extension line Vrefx. The seventh bridge portion 77 can be connected to the fourth gate portion 5EM and the first connection portion EM1 via vias, respectively. The orthographic projection of the initial signal line Vinit on the substrate, the orthographic projection of the first power extension line VDDx on the substrate, and the orthographic projection of the reference signal extension line Vrefx on the substrate can all extend along the column direction Y. The initial signal line Vinit can provide an initial signal terminal. The initial signal line Vinit can be connected to the nineteenth active portion 419 via a via to connect the first electrode of the fifth transistor to the initial signal terminal. The first power extension line VDDx can be connected to the power line VDD, and the first power extension line VDDx can be connected to the eighteenth active portion 418 via a via to connect the first electrode of the fourth transistor to the first power terminal. The reference signal extension line Vrefx may be connected to the second connection portion Vref2 through a via hole to be connected to the reference signal line Vref.

[0174] As shown in Figures 59, 64, and 70, the fourth conductive layer may include a first shielding line 81, a second shielding line 82, and a power line VDD, wherein the orthographic projection of the power line VDD on the substrate and the orthographic projection of the first shielding line 81 on the substrate extend along the row direction X, and the orthographic projection of the second shielding line 82 on the substrate extends along the column direction Y. The orthographic projections of the first shielding line 81, the power line VDD, and the second shielding line 82 on the substrate intersect. Each column of pixel driving circuits may be provided with a corresponding second shielding line 82, each row of pixel driving circuits may be provided with a corresponding first shielding line 81, and each row of driving units may be provided with a corresponding power line VDD. Multiple power lines VDD, multiple first shielding lines 81, and multiple second shielding lines 82 may form a grid structure. The orthographic projections of the first shielding line 81 and the second shielding line 82 on the substrate can at least partially overlap with the orthographic projections of the equipotential structure of the second electrode of the first capacitor C1 on the substrate. Partial structures of the first shielding line 81 and the second shielding line 82 can be used to form the first electrode of the second capacitor C2, and the second electrode of the first capacitor C1 can be reused as the second electrode of the second capacitor C2. For example, the orthographic projection of the second shielding line 82 on the substrate can overlap with the orthographic projection of the seventh conductive portion 79 on the substrate, and the orthographic projection of the first shielding line 81 on the substrate can overlap with the orthographic projection of the first conductive portion 61 on the substrate. The power line VDD can be used to provide a first power supply terminal. The power line VDD can be connected to the sixth bridge portion 76 through a via to connect the first electrode of the analog transistor DTd and the first power supply terminal. The fourth conductive layer can also include a second power extension line VDDy. The second power extension line VDDy can be connected to the first power extension line VDDx through a via to connect the analog transistor DTd and the fourth transistor T4 to the first power supply terminal.

[0175] As shown in Figures 59, 65, and 71, the fifth conductive layer may include a data line Da and a fifth bridge portion 95. The orthographic projection of the data line Da on the substrate may extend along the column direction Y. The data line Da may be used to provide a data signal terminal. The data line Da may be connected to the second conductive portion 62 via a via to connect to the first electrode of the first transistor T1. The fifth bridge portion 95 may be connected to the third bridge portion 73 via a via to connect to the second electrode of the driving transistor.

[0176] As shown in Figures 59, 64, 65, and 71, the second shielding line 82 may include a first extension 821 and a second extension 822. The overlapping portion of the orthographic projection of the seventh conductive portion 79 on the substrate and the orthographic projection of the data line Da on the substrate overlaps with the orthographic projection of the first extension 821 on the substrate. The overlapping portion of the orthographic projection of the first conductive portion 61 on the substrate and the orthographic projection of the data line Da on the substrate overlaps with the orthographic projection of the first extension 821 on the substrate. In other words, the first extension 821 shields the seventh conductive portion 79 from the data line Da, and the first conductive portion 61 from the data line Da. The first extension 821 can shield the first conductive portion 61 from noise from the data line Da, thereby improving the stability of the gate voltage of the driving transistor. The orthographic projection of the second extension 822 on the substrate can be located between the orthographic projections of adjacent data lines Da on the substrate, meaning that the orthographic projections of the second extension 822 on the substrate do not overlap with the orthographic projections of the data line Da on the substrate. This configuration can reduce the parasitic capacitance of the data line Da, thereby improving the efficiency of writing data signals to the data line Da.

[0177] As shown in Figures 59 and 66, the electrode layer may include multiple electrode portions: a first electrode portion R, a second electrode portion B, and a third electrode portion G. Each electrode portion may be connected to a fifth bridge portion 95 via a via to connect to the second electrode of the driving transistor DT. The first electrode portion R may be used to form the first electrode of a red light-emitting unit, the second electrode portion B may be used to form the first electrode of a blue light-emitting unit, and the third electrode portion G may be used to form the first electrode of a green light-emitting unit. In this exemplary embodiment, the light-emitting units L may have a Real RGB distribution. For example, the first electrode portion R, the third electrode portion G, and the second electrode portion B may be alternately distributed in the row direction, with electrode portions of the same color located in the same column. As shown in Figure 59, the orthographic projection of the electrode portion on the base substrate is located between the orthographic projections of two adjacent data lines Da on the base substrate. On the one hand, this arrangement can prevent the data lines Da from affecting the flatness of the electrode portion, and on the other hand, this arrangement can reduce the noise impact of the data lines Da on the electrode portion. The display panel may further include a pixel definition layer located on the side of the electrode layer facing away from the base substrate, wherein a pixel opening for forming a light-emitting unit is formed on the pixel definition layer, wherein the orthographic projection of the first electrode portion R on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate, the orthographic projection of the second electrode portion B on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate, and the orthographic projection of the third electrode portion G on the base substrate coincides with the orthographic projection of the corresponding pixel opening on the pixel definition layer on the base substrate.

[0178] FIG72 is a partial cross-sectional view of the display panel shown in FIG59 taken along dotted line DD. The display panel may further include a first insulating layer 102, a second insulating layer 103, a first dielectric layer 104, a passivation layer 105, a second dielectric layer 106, and a planarization layer 107. The substrate 101, active layer, first insulating layer 102, first conductive layer, second insulating layer 103, second conductive layer, first dielectric layer 104, third conductive layer, passivation layer 105, fourth conductive layer, second dielectric layer 106, fifth conductive layer, planarization layer 107, and electrode layer are stacked in sequence. The first insulating layer 102 and the second insulating layer 103 can be single-layer or multi-layer structures, and the material of the first insulating layer 102 and the second insulating layer 103 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 104 and the second dielectric layer 106 can be silicon nitride layers. The material of the planarization layer 107 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The material of the passivation layer 105 can be silicon oxide. The base substrate 101 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The material of the first conductive layer and the second conductive layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked layer. The third and fifth conductive layers may be made of metal materials, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate, or a titanium / aluminum / titanium laminate. The electrode layer may include an indium tin oxide layer or a silver layer. The sheet resistance of either the first or second conductive layer may be greater than the sheet resistance of either the fourth or third conductive layer.

[0179] This exemplary embodiment also provides another display panel, as shown in Figures 73-75, where Figure 73 is a structural layout of another exemplary embodiment of the display panel disclosed herein, Figure 74 is a structural layout of the second conductive layer in Figure 73, and Figure 75 is a structural layout of the third conductive layer in Figure 73.

[0180] The display panel provided by this exemplary embodiment differs from the display panel shown in FIG59 only in the second and third conductive layers. As shown in FIG73-75 , in this exemplary embodiment, first conductive portions 61 located in different rows within the same sub-drive unit are not connected. The third conductive layer lacks first conductive lines 75, and within the same sub-drive unit, adjacent seventh conductive portions 79 in the column direction are connected.

[0181] It should be noted that in each of the above exemplary embodiments, the black squares drawn on the side of the second conductive layer facing away from the substrate represent vias connecting the second conductive layer to other layers facing the substrate; the black squares drawn on the side of the third conductive layer facing away from the substrate represent vias connecting the third conductive layer to other layers facing the substrate; the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. The black squares merely indicate the locations of the vias; different vias represented by black squares in different locations may penetrate different insulating layers.

[0182] The scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to define different structure names and do not have a specific order of meaning. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending straight or bent along the direction. A transistor refers to an element that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this exemplary embodiment, the channel region refers to the region where current mainly flows. In this exemplary embodiment, the first electrode can be a drain and the second electrode can be a source, or the first electrode can be a source and the second electrode can be a drain. When using transistors with opposite polarity or when the direction of current changes during circuit operation, the functions of "source" and "drain" are sometimes reversed. Therefore, in this exemplary embodiment, "source" and "drain" can be reversed. Furthermore, the gate electrode can also be referred to as a control electrode.

[0183] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0184] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0185] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

[0186] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes: substrate; A plurality of driving units are located on one side of the substrate, and the orthographic projections of the plurality of driving units on the substrate are distributed in an array along row and column directions, and the driving units include: A pixel driving circuit having n rows and m columns, where n and m are both positive integers greater than or equal to 1, and n+m is greater than or equal to 3; A compensation circuit is connected to a plurality of pixel driving circuits in the same driving unit, and is used to provide a threshold compensation signal to the pixel driving circuits connected thereto.

2. The display panel according to claim 1, wherein The driving unit includes a first sub-driving unit and a second sub-driving unit, wherein an orthographic projection of the first sub-driving unit on the base substrate and an orthographic projection of the second sub-driving unit on the base substrate are alternately distributed in a column direction; The first sub-driving unit includes n1 rows and m columns of pixel driving circuits, and the second sub-driving unit includes n2 rows and m columns of pixel driving circuits, wherein n1 and n2 are positive integers greater than or equal to 1, and n1+n2=n; An orthographic projection of at least a portion of the structure of the compensation circuit on the base substrate is located between an orthographic projection of the first sub-driving unit on the base substrate and an orthographic projection of the second sub-driving unit on the base substrate.

3. The display panel according to claim 2, wherein: n1 equals n2.

4. The display panel according to any one of claims 1 to 3, wherein: The pixel driving circuit includes: a driving circuit comprising a first input terminal, a first output terminal, and a first control terminal, wherein the driving circuit is configured to provide a driving current to the first output terminal via the first input terminal according to a voltage at the first control terminal; a data writing circuit connected to the first control terminal, the data line, and the gate line, and configured to transmit the signal on the data line to the first control terminal in response to the signal on the gate line; a first storage circuit connected between the first control terminal and the first node, and configured to store a voltage difference between the first control terminal and the first node; The compensation circuit comprises: an analog circuit having the same or substantially the same threshold voltage as the driving circuit, the analog circuit comprising a second input terminal, a second output terminal, and a second control terminal, the analog circuit being configured to provide a driving current to the second output terminal using the second input terminal according to a voltage at the second control terminal, the second input terminal being connected to a power line, and the second output terminal being connected to the second control terminal; a compensation control circuit connected to the first node, the second output terminal, and an enable signal line, and configured to connect the first node and the second output terminal in response to a signal on the enable signal line; The first reset circuit is connected to the first node, the reference signal line, and the reset signal line, and is configured to transmit the signal of the reference signal line to the first node in response to the signal of the reset signal line.

5. The display panel according to claim 4, wherein: When the driving unit includes a first sub-driving unit and a second sub-driving unit; The orthographic projections of the analog circuit, the compensation control circuit, and the first reset circuit on the base substrate are all located between the orthographic projections of the first sub-driving unit on the base substrate and the orthographic projections of the second sub-driving unit on the base substrate. The display panel according to claim 5 , wherein: The orthographic projection of the enable signal line on the base substrate, the orthographic projection of the reference signal line on the base substrate, the orthographic projection of the reset signal line on the base substrate, and the orthographic projection of the power line on the base substrate all extend along the row direction and are located between the orthographic projection of the first sub-driving unit on the base substrate and the orthographic projection of the second sub-driving unit on the base substrate.

7. The display panel according to claim 4, wherein: The compensation circuit further includes: The second storage circuit is connected between the power line and the first node, and is used to store the voltage difference between the power line and the first node.

8. The display panel according to claim 4, wherein: The display panel further includes: a light emitting control circuit connected to the power line, the first input terminal, and the enable signal line, and configured to transmit the signal of the power line to the first input terminal in response to the signal of the enable signal line; The second reset circuit is connected to the first input terminal, the initial signal line, and the reset signal line, and is used for transmitting the signal of the initial signal line to the first input terminal in response to the signal of the reset signal line.

9. The display panel according to claim 8, wherein: The light emitting control circuit and the second reset circuit form an auxiliary driving circuit, and the pixel driving circuits located in the same row share one or more groups of the auxiliary driving circuits.

10. The display panel according to claim 9, wherein: The pixel driving circuits located in the same row share two groups of auxiliary driving circuits, and the pixel driving circuits located in the same row form a pixel driving circuit row. The orthographic projections of the two groups of auxiliary driving circuits on the substrate are respectively located on both sides of the orthographic projection of the pixel driving circuit row connected to them on the substrate in the row direction.

11. The display panel according to claim 8, wherein: The driving circuit includes: a driving transistor, wherein the first electrode forms the first input terminal, the second electrode forms the first output terminal, and the gate forms the first control terminal; The data writing circuit includes: a first transistor, having a first electrode connected to the data line, a second electrode connected to the first control terminal, and a gate connected to the gate line; The first storage circuit includes: a first capacitor, a first electrode of which is connected to the first control terminal, and a second electrode of which is connected to the first node; The analog circuit comprises: an analog transistor, wherein the analog transistor and the driving transistor have the same or substantially the same threshold voltage, a first electrode of the analog transistor forms the second input terminal, a second electrode forms the second output terminal, and a gate forms the second control terminal; The compensation control circuit includes: a second transistor, having a first electrode connected to the second output terminal, a second electrode connected to the first node, and a gate connected to the enable signal line; The first reset circuit includes: a third transistor, having a first electrode connected to the reference signal line, a second electrode connected to the first node, and a gate connected to the reset signal line; The light emitting control circuit includes: a fourth transistor, a first electrode connected to the power line, a second electrode connected to the first input terminal, and a gate connected to the enable signal line; The second reset circuit includes: A fifth transistor has a first electrode connected to the initial signal line, a second electrode connected to the first input terminal, and a gate connected to the reset signal line.

12. The display panel according to claim 7, wherein: The second storage capacitor includes: A second capacitor, wherein a first electrode of the second capacitor is connected to the power line, and a second electrode of the second capacitor is connected to the first node.

13. The display panel according to claim 9, wherein: The driving circuit includes: a driving transistor, wherein the first electrode forms the first input terminal, the second electrode forms the first output terminal, and the gate forms the first control terminal; The light emitting control circuit includes: a fourth transistor, a first electrode connected to the power line, a second electrode connected to the first input terminal, and a gate connected to the enable signal line; The second reset circuit includes: a fifth transistor, a first electrode connected to the initial signal line, a second electrode connected to the first input terminal, and a gate connected to the reset signal line; The display panel further includes: an active layer located on one side of the base substrate, the active layer comprising a fourth active portion, a fifth active portion, a sixth active portion, and an active line; The fourth active portion is used to form a channel region of the fourth transistor, the fifth active portion is used to form a channel region of the fifth transistor, and the sixth active portion is used to form a channel region of the driving transistor; The orthographic projection of the active line on the substrate extends along the row direction, the active line is connected to the first electrode of the driving transistor, the sixth active portion in the pixel driving circuit located in the same row is connected to the same active line, and the fifth active portion and the sixth active portion are connected to the same end of the active line in the row direction.

14. The display panel according to claim 13, wherein: The driving unit includes a first sub-driving unit, the orthographic projection of the first sub-driving unit on the base substrate is located on one side of the orthographic projection of the auxiliary driving circuit on the base substrate in the column direction, and the first sub-driving unit includes two adjacent rows and m columns of pixel driving circuits; In the first sub-driving units in the same row, the sixth active portion in the driving circuit is connected to the same active line.

15. The display panel according to claim 4, wherein: The driving circuit includes: a driving transistor, wherein the first electrode forms the first input terminal, the second electrode forms the first output terminal, and the gate forms the first control terminal; The first storage circuit includes: a first capacitor, a first electrode of which is connected to the first control terminal, and a second electrode of which is connected to the first node; The display panel further includes: a first conductive layer, located on one side of the base substrate, the first conductive layer including a sixth gate portion, at least a portion of which is used to form a gate of the driving transistor and a first electrode of the first capacitor; a second conductive layer, located on a side of the first conductive layer facing away from the base substrate, the second conductive layer comprising a first conductive portion, an orthographic projection of the first conductive portion on the base substrate and an orthographic projection of the sixth gate portion on the base substrate at least partially overlapping, the first conductive portion being configured to form a second electrode of the first capacitor; m is a positive integer greater than or equal to 2. In the same driving unit, the first conductive parts in the pixel driving circuits in the same row are connected.

16. The display panel according to claim 15, wherein: The compensation control circuit includes: a second transistor, having a first electrode connected to the second output terminal, a second electrode connected to the first node, and a gate connected to the enable signal line; The first reset circuit includes: a third transistor, having a first electrode connected to the reference signal line, a second electrode connected to the first node, and a gate connected to the reset signal line; The driving unit includes a first sub-driving unit and a second sub-driving unit, wherein an orthographic projection of the first sub-driving unit on the substrate and an orthographic projection of the second sub-driving unit on the substrate are distributed in a column direction; The first sub-driving unit includes n1 rows and m columns of pixel driving circuits, and the second sub-driving unit includes n2 rows and m columns of pixel driving circuits, wherein n1 and n2 are positive integers greater than or equal to 1, and n1+n2=n; The orthographic projections of the analog circuit, the compensation control circuit, and the first reset circuit on the base substrate are all located between the orthographic projections of the first sub-driving unit on the base substrate and the orthographic projections of the second sub-driving unit on the base substrate; The display panel further includes: a first bridge portion, wherein an orthographic projection of the first bridge portion on the base substrate extends along a column direction, the first bridge portion being connected to the second electrode of the second transistor and to the first conductive portions respectively located in the first sub-driving unit and the second sub-driving unit; a second bridge portion, wherein an orthographic projection of the second bridge portion on the base substrate extends along a column direction, the second bridge portion being connected to the second electrode of the third transistor and to the first conductive portions respectively located in the first sub-driving unit and the second sub-driving unit; The first bridge portion and the second bridge portion are connected to different first conductive portions.

17. The display panel according to claim 16, wherein: The orthographic projections of the analog circuit, the compensation control circuit, and the first reset circuit on the base substrate are all located between the orthographic projection of the first bridge portion on the base substrate and the orthographic projection of the second bridge portion on the base substrate.

18. The display panel according to claim 15, wherein: The display panel further includes: a fourth conductive layer, located on a side of the second conductive layer facing away from the base substrate, the fourth conductive layer comprising a second shielding line, the second shielding line being connected to a stable power supply terminal, an orthographic projection of the second shielding line on the base substrate extending along a column direction, and the second shielding line comprising a first extension portion; a fifth conductive layer, located on a side of the fourth conductive layer away from the base substrate, the fifth conductive layer including the data line; The overlapping portion of the orthographic projection of the sixth gate portion on the base substrate and the orthographic projection of the data line on the base substrate and the orthographic projection of the first extension portion on the base substrate at least partially overlap, and / or the overlapping portion of the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the data line on the base substrate and the orthographic projection of the first extension portion on the base substrate at least partially overlap.

19. The display panel according to claim 18, wherein: The second shielding line further includes a second extending portion, and an orthographic projection of the second extending portion on the base substrate is located between orthographic projections of two adjacent data lines on the base substrate.

20. The display panel according to claim 16, wherein The compensation circuit further includes a second capacitor, a first electrode of the second capacitor is connected to the power line, and a second electrode of the second capacitor is connected to the first node; The display panel further includes: a third conductive layer, the third conductive layer being located on a side of the second conductive layer facing away from the substrate, the third conductive layer comprising the first bridge portion and the second bridge portion; a fourth conductive layer, located on a side of the third conductive layer away from the base substrate, the fourth conductive layer comprising a plurality of second shielding lines, the second shielding lines being connected to the power lines, and the second shielding lines comprising second extension portions; The orthographic projection of the first bridge portion on the base substrate overlaps with the orthographic projection of one of the second extension portions on the base substrate, and the orthographic projection of the second bridge portion on the base substrate overlaps with the orthographic projection of another of the second extension portions on the base substrate; The first bridge portion and the second bridge portion are used to form a second electrode of the second capacitor, and the second extension portion is used to form a first electrode of the second capacitor.

21. The display panel according to claim 15, wherein The display panel further includes: a third conductive layer, located on a side of the second conductive layer facing away from the base substrate, the third conductive layer comprising a power connection line segment connected to the power line, and an orthographic projection of the power connection line segment on the base substrate extending along a column direction; a fifth conductive layer, located on a side of the third conductive layer away from the base substrate, the fifth conductive layer including the data line; The overlapping portion of the orthographic projection of the sixth gate portion on the base substrate and the orthographic projection of the data line on the base substrate and the orthographic projection of the power connection line segment on the base substrate at least partially overlap, and / or the overlapping portion of the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the data line on the base substrate and the orthographic projection of the power connection line segment on the base substrate at least partially overlap.

22. The display panel according to claim 21, wherein: The orthographic projection of the power connection line segment on the base substrate is located between the orthographic projections of adjacent reset signal lines and enable signal lines in adjacent driving units in the column direction on the base substrate.

23. The display panel according to claim 21, wherein The power connection line segments adjacent to each other in the column direction are connected to form a power connection line.

24. The display panel according to claim 4, wherein: The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The display panel further includes: a fifth conductive layer, located on one side of the base substrate, wherein the fifth conductive layer includes the data line; an electrode layer, located on a side of the fifth conductive layer facing away from the base substrate, the electrode layer comprising a plurality of electrode portions, the electrode portions being used to form a first electrode of the light-emitting unit; a pixel definition layer, wherein a plurality of pixel openings are formed on the pixel definition layer, the pixel openings are used to form the light-emitting units, and the orthographic projections of the pixel openings on the base substrate overlap with the effects of the corresponding electrode portions on the base substrate; The orthographic projection of the electrode portion on the base substrate is located between orthographic projections of adjacent data lines on the base substrate.

25. The display panel according to claim 13, wherein: The display panel further includes: A first conductive line, wherein an orthographic projection of the first conductive line on the substrate extends along a row direction, and the first conductive line is connected to the active line through a plurality of vias distributed in the row direction.

26. The display panel according to claim 15, wherein: The compensation circuit further includes: a second capacitor, wherein a first electrode of the second capacitor is connected to the power line, and a second electrode of the second capacitor is connected to the first node; The display panel further includes: a third conductive layer, located on a side of the second conductive layer facing away from the base substrate, the third conductive layer comprising a seventh conductive portion connected to the first conductive portion, the seventh conductive portion being used to form a second electrode of the second capacitor; A fourth conductive layer is located on the side of the third conductive layer away from the base substrate, the fourth conductive layer includes a second shielding line, the second shielding line is connected to the power line, the orthographic projection of the second shielding line on the base substrate and the orthographic projection of the seventh conductive part on the base substrate at least partially overlap, and the second shielding line portion is structured to form a first electrode of the second capacitor.

27. A display device, wherein: A display panel comprising any one of claims 1-26.

Images